processed review comments

libraries/io/fpga_sense/src/vhdl/fpga_sense.vhd

@@ -105,6 +105,8 @@ BEGIN
       tempout => temp_data --: OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
     );
 
+--  The eoc signal goes high for one clock cycle of the 1-MHz internal oscillator clock,
+--  indicating end of conversion. You can latch the data on tempout at the falling edge of eoc.
     PROCESS(eoc, mm_rst)
     BEGIN
       IF mm_rst = '1' THEN
@@ -117,8 +119,8 @@ BEGIN
   END GENERATE;
 
   no_tech_fpga_temp_sens: IF g_sim=TRUE GENERATE                                                                              
-    -- temp = (708 * adc)/1024 - 273 => adc = (temp + 273)*1024/708                                                             
-    temp_data <= TO_UVEC(460, temp_data'LENGTH);   -- choose temp = 45 degrees so adc temp_data = 460
+    -- temp = (693 * adc)/1024 - 265 => adc = (temp + 265)*1024/693                                                             
+    temp_data <= TO_UVEC(458, temp_data'LENGTH);   -- choose temp = 45 degrees so adc temp_data = 458
     mm_reg_temp_data <= RESIZE_UVEC(temp_data,c_mem_reg_temp_dat_w);
   END GENERATE;
 
@@ -190,7 +192,7 @@ BEGIN
           start_sense_mm_d2 <= start_sense_mm_d1;
           if start_sense_mm_d1 = '1' and start_sense_mm_d2 = '0' then
             controller_csr_write <= '1';
-	        else 
+          else 
             controller_csr_write <= '0';
           end if;
         END IF;