Reinier van der Walle
--- a/libraries/io/fpga_sense/src/vhdl/fpga_sense.vhd
+++ b/libraries/io/fpga_sense/src/vhdl/fpga_sense.vhd
  CONSTANT c_mem_reg_temp_nof_data  : NATURAL := 1;
  CONSTANT c_mem_reg_temp_data : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_temp_adr_w , c_mem_reg_temp_dat_w , c_mem_reg_temp_nof_data, 'X');

+  -- temp = (693 * adc)/1024 - 265 => adc = (temp + 265)*1024/693                                                             
--- a/libraries/io/fpga_sense/src/vhdl/fpga_sense.vhd
+++ b/libraries/io/fpga_sense/src/vhdl/fpga_sense.vhd
      BEGIN
        IF mm_rst = '1' THEN
          controller_csr_write <= '0';
+          start_sense_mm       <= '0';
+          start_sense_mm_d1    <= '0';
+          start_sense_mm_d2    <= '0';
        ELSIF rising_edge(mm_clk) THEN
          start_sense_mm <= start_sense;
          start_sense_mm_d1 <= start_sense_mm;
          start_sense_mm_d2 <= start_sense_mm_d1;
          if start_sense_mm_d1 = '1' and start_sense_mm_d2 = '0' then
            controller_csr_write <= '1';
-	  else 
+	        else 
--- a/libraries/io/fpga_sense/src/vhdl/fpga_sense.vhd
+++ b/libraries/io/fpga_sense/src/vhdl/fpga_sense.vhd
    )
    PORT MAP (
      corectl => start_sense,
      eoc     => eoc,      --: OUT STD_LOGIC;
--- a/libraries/io/fpga_sense/src/vhdl/fpga_sense.vhd
+++ b/libraries/io/fpga_sense/src/vhdl/fpga_sense.vhd
 BEGIN

  -- temperature sensor
-
+  temp_alarm <= '1' WHEN (UNSIGNED(temp_data) > UNSIGNED(c_temp_high_raw)) ELSE '0';