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Commit df0a9106 authored by Reinier van der Walle's avatar Reinier van der Walle
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processed review comments

parent 7f50c364
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1 merge request!177Resolve L2SDP-532
Pipeline #22355 passed
...@@ -105,6 +105,8 @@ BEGIN ...@@ -105,6 +105,8 @@ BEGIN
tempout => temp_data --: OUT STD_LOGIC_VECTOR(9 DOWNTO 0) tempout => temp_data --: OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
); );
-- The eoc signal goes high for one clock cycle of the 1-MHz internal oscillator clock,
-- indicating end of conversion. You can latch the data on tempout at the falling edge of eoc.
PROCESS(eoc, mm_rst) PROCESS(eoc, mm_rst)
BEGIN BEGIN
IF mm_rst = '1' THEN IF mm_rst = '1' THEN
...@@ -117,8 +119,8 @@ BEGIN ...@@ -117,8 +119,8 @@ BEGIN
END GENERATE; END GENERATE;
no_tech_fpga_temp_sens: IF g_sim=TRUE GENERATE no_tech_fpga_temp_sens: IF g_sim=TRUE GENERATE
-- temp = (708 * adc)/1024 - 273 => adc = (temp + 273)*1024/708 -- temp = (693 * adc)/1024 - 265 => adc = (temp + 265)*1024/693
temp_data <= TO_UVEC(460, temp_data'LENGTH); -- choose temp = 45 degrees so adc temp_data = 460 temp_data <= TO_UVEC(458, temp_data'LENGTH); -- choose temp = 45 degrees so adc temp_data = 458
mm_reg_temp_data <= RESIZE_UVEC(temp_data,c_mem_reg_temp_dat_w); mm_reg_temp_data <= RESIZE_UVEC(temp_data,c_mem_reg_temp_dat_w);
END GENERATE; END GENERATE;
......
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