Export jesd clock, reset and sysref signals from IP

libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd

@@ -50,7 +50,9 @@ ENTITY ip_arria10_e1sg_jesd204b IS
     
     -- Data to fabric
     rx_src_out_arr        : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0);    -- Parallel data out to fabric
-    jesd204b_frame_clk    : OUT  STD_LOGIC := '0';                           -- Regenerated data clock to fabric
+    rx_clk                : OUT  STD_LOGIC := '0';                           -- Exported data clock (frame clock) to fabric
+    rx_rst                : OUT  STD_LOGIC := '0';                           -- Exported reset on rx_clk domain
+    rx_sysref             : OUT  STD_LOGIC := '0';                           -- Exported copy of sysref
 
     -- MM Control
     mm_clk                : IN  STD_LOGIC;
@@ -109,6 +111,8 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
   SIGNAL core_pll_locked_reg        : STD_LOGIC;               
   SIGNAL jesd204b_sysref_1          : STD_LOGIC;               
   SIGNAL jesd204b_sysref_2          : STD_LOGIC;               
+  SIGNAL jesd204b_sysref_frameclk_1 : STD_LOGIC;               
+  SIGNAL jesd204b_sysref_frameclk_2 : STD_LOGIC;               
 
   -- Data path
   SIGNAL jesd204b_rx_link_data_arr  : STD_LOGIC_VECTOR(c_jesd204b_rx_data_w*g_nof_channels-1 DOWNTO 0);               
@@ -221,7 +225,8 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
 
 BEGIN
 
-  jesd204b_frame_clk <= rxframe_clk;
+  rx_clk <= rxframe_clk;
+  rx_rst <= not core_pll_locked;
 
   -- The avs clock is driven by the rxlink_clk for simulation. This is a workaround for a bug 
   -- in the Q18.0 IP where the jesd receiver fails to recognize the SYSREF pulse
@@ -260,7 +265,7 @@ BEGIN
         csr_s                      => OPEN, 
         dev_lane_aligned           => dev_lane_aligned_arr(i),           
         dev_sync_n                 => jesd204b_sync_n_arr(i),
-        jesd204_rx_avs_chipselect         => '0', --jesd204b_mosi_arr(i).chipselect,
+        jesd204_rx_avs_chipselect         => '1', --jesd204b_mosi_arr(i).chipselect,
         jesd204_rx_avs_address            => jesd204b_mosi_arr(i).address(c_jesd204b_mm_addr_w-1 downto 0),
         jesd204_rx_avs_read               => jesd204b_mosi_arr(i).rd,
         jesd204_rx_avs_readdata           => jesd204b_miso_arr(i).rddata(31 downto 0),
@@ -377,6 +382,28 @@ BEGIN
       END IF;
     END PROCESS;
 
+    -----------------------------------------------------------------------------
+    -- Capture sysref on the frame clock for export
+    -----------------------------------------------------------------------------
+    p_rx_sysref : PROCESS (rxframe_clk, core_pll_locked)
+    BEGIN
+      IF core_pll_locked = '0' THEN
+        jesd204b_sysref_frameclk_1 <= '0';
+        jesd204b_sysref_frameclk_2 <= '0';
+        rx_sysref <= '0';
+      ELSE
+        IF rising_edge(rxframe_clk) THEN
+          jesd204b_sysref_frameclk_1 <= jesd204b_sysref;
+          jesd204b_sysref_frameclk_2 <= jesd204b_sysref_frameclk_1;
+          IF jesd204b_sysref_frameclk_1 = '1' and jesd204b_sysref_frameclk_2 = '0' THEN
+            rx_sysref <= '1';
+          ELSE
+            rx_sysref <= '0';
+          END IF;
+        END IF;
+      END IF;
+    END PROCESS;
+
   
     -- IOPLL in source synchronous or normal mode. (Intel JESD204B-UG p66)
     u_ip_arria10_e1sg_jesd204b_rx_corepll : ip_arria10_e1sg_jesd204b_rx_core_pll

libraries/technology/jesd204b/tech_jesd204b.vhd

@@ -58,6 +58,7 @@ ENTITY tech_jesd204b IS
     g_sim                 : BOOLEAN := FALSE;
     g_technology          : NATURAL := c_tech_arria10_e1sg;
     g_nof_channels        : NATURAL := 12;
+    g_nof_syncs           : NATURAL := 12;
     g_direction           : STRING := "RX_ONLY"  -- "TX_RX", "TX_ONLY", "RX_ONLY"
   );
   PORT (
@@ -68,7 +69,9 @@ ENTITY tech_jesd204b IS
     
     -- Data to fabric
     rx_src_out_arr        : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0);    -- Parallel data out to fabric
-    jesd204b_frame_clk    : OUT  STD_LOGIC := '0';                           -- Regenerated data clock to fabric
+    rx_clk                : OUT  STD_LOGIC := '0';                           -- Exported data clock (frame clock) to fabric
+    rx_rst                : OUT  STD_LOGIC := '0';                           -- Exported reset on rx_clk domain
+    rx_sysref             : OUT  STD_LOGIC := '0';                           -- Exported copy of sysref
 
     -- MM Control
     mm_clk                : IN  STD_LOGIC;
@@ -100,7 +103,9 @@ BEGIN
       jesd204b_sync_n_arr  => jesd204b_sync_n_arr,   
   
       rx_src_out_arr       => rx_src_out_arr,          
-      jesd204b_frame_clk   => jesd204b_frame_clk,          
+      rx_clk               => rx_clk,          
+      rx_rst               => rx_rst,          
+      rx_sysref            => rx_sysref,          
   
       -- MM
       mm_clk               => mm_clk,           
@@ -128,7 +133,9 @@ BEGIN
       jesd204b_sync_n_arr  => jesd204b_sync_n_arr,   
   
       rx_src_out_arr       => rx_src_out_arr,          
-      jesd204b_frame_clk   => jesd204b_frame_clk,          
+      rx_clk               => rx_clk,          
+      rx_rst               => rx_rst,          
+      rx_sysref            => rx_sysref,          
   
       -- MM
       mm_clk               => mm_clk,           

libraries/technology/jesd204b/tech_jesd204b_arria10_e1sg.vhd

@@ -49,7 +49,9 @@ ENTITY tech_jesd204b_arria10_e1sg IS
     
     -- Data to fabric
     rx_src_out_arr        : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0);    -- Parallel data out to fabric
-    jesd204b_frame_clk    : OUT  STD_LOGIC := '0';                           -- Regenerated data clock to fabric
+    rx_clk                : OUT  STD_LOGIC := '0';                           -- Exported data clock (frame clock) to fabric
+    rx_rst                : OUT  STD_LOGIC := '0';                           -- Exported reset on rx_clk domain
+    rx_sysref             : OUT  STD_LOGIC := '0';                           -- Exported copy of sysref
 
     -- MM Control
     mm_clk                : IN  STD_LOGIC;
@@ -80,7 +82,9 @@ BEGIN
     jesd204b_sync_n_arr  => jesd204b_sync_n_arr,   
 
     rx_src_out_arr       => rx_src_out_arr,          
-    jesd204b_frame_clk   => jesd204b_frame_clk,          
+    rx_clk               => rx_clk,          
+    rx_rst               => rx_rst,          
+    rx_sysref            => rx_sysref,          
 
     -- MM
     mm_clk               => mm_clk,           

libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd

@@ -49,7 +49,9 @@ ENTITY tech_jesd204b_arria10_e2sg IS
     
     -- Data to fabric
     rx_src_out_arr        : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0);    -- Parallel data out to fabric
-    jesd204b_frame_clk    : OUT  STD_LOGIC := '0';                           -- Regenerated data clock to fabric
+    rx_clk                : OUT  STD_LOGIC := '0';                           -- Exported data clock (frame clock) to fabric
+    rx_rst                : OUT  STD_LOGIC := '0';                           -- Exported reset on rx_clk domain
+    rx_sysref             : OUT  STD_LOGIC := '0';                           -- Exported copy of sysref
 
     -- MM Control
     mm_clk                : IN  STD_LOGIC;
@@ -80,7 +82,9 @@ BEGIN
     jesd204b_sync_n_arr  => jesd204b_sync_n_arr,   
 
     rx_src_out_arr       => rx_src_out_arr,          
-    jesd204b_frame_clk   => jesd204b_frame_clk,          
+    rx_clk               => rx_clk,          
+    rx_rst               => rx_rst,          
+    rx_sysref            => rx_sysref,          
 
     -- MM
     mm_clk               => mm_clk,           

libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd

@@ -49,7 +49,9 @@ PACKAGE tech_jesd204b_component_pkg IS
     
     -- Data to fabric
     rx_src_out_arr        : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0);    -- Parallel data out to fabric
-    jesd204b_frame_clk    : OUT  STD_LOGIC := '0';               -- Regenerated data clock to fabric
+    rx_clk                : OUT  STD_LOGIC := '0';                           -- Exported data clock (frame clock) to fabric
+    rx_rst                : OUT  STD_LOGIC := '0';                           -- Exported reset on rx_clk domain
+    rx_sysref             : OUT  STD_LOGIC := '0';                           -- Exported copy of sysref
 
     -- MM Control
     mm_clk                : IN  STD_LOGIC;
@@ -82,7 +84,9 @@ PACKAGE tech_jesd204b_component_pkg IS
     
     -- Data to fabric
     rx_src_out_arr        : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0);    -- Parallel data out to fabric
-    jesd204b_frame_clk    : OUT  STD_LOGIC := '0';               -- Regenerated data clock to fabric
+    rx_clk                : OUT  STD_LOGIC := '0';                           -- Exported data clock (frame clock) to fabric
+    rx_rst                : OUT  STD_LOGIC := '0';                           -- Exported reset on rx_clk domain
+    rx_sysref             : OUT  STD_LOGIC := '0';                           -- Exported copy of sysref
 
     -- MM Control
     mm_clk                : IN  STD_LOGIC;