Resolve L2SDP-48
Closes L2SDP-48
Merge request reports
Activity
assigned to @kooistra
564 wg_sosi_arr(I).data(c_wg_buf_dat_w-1 downto 0) <= wg_out_data((I+1)*c_wg_buf_dat_w-1 downto I*c_wg_buf_dat_w); 565 wg_sosi_arr(I).sync <= wg_out_sync(I); 566 567 END GENERATE; 568 569 570 571 ----------------------------------------------------------------------------- 572 -- ADC/WG Mux (Input Select) 573 ----------------------------------------------------------------------------- 453 -- clocks and resets 454 mm_clk => mm_clk, 455 mm_rst => mm_rst, 456 dp_clk => dp_clk, 457 dp_rst => dp_rst, 458 -- dp_pps => dp_pps, changed this line in version 2 of the diff
7 -- 8 -- This program is free software: you can redistribute it and/or modify 9 -- it under the terms of the GNU General Public License as published by 10 -- the Free Software Foundation, either version 3 of the License, or 11 -- (at your option) any later version. 12 -- 13 -- This program is distributed in the hope that it will be useful, 14 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 15 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 -- GNU General Public License for more details. 17 -- 18 -- You should have received a copy of the GNU General Public License 19 -- along with this program. If not, see <http://www.gnu.org/licenses/>. 20 -- 21 ------------------------------------------------------------------------------- 22 -
Add author, purpose and description. Description can be as short as adding link to the L5 AIT document in confluence. Same for other files.
Edited by Eric Kooistra
24 USE IEEE.STD_LOGIC_1164.ALL; 25 USE IEEE.NUMERIC_STD.ALL; 26 USE common_lib.common_pkg.ALL; 27 USE common_lib.common_mem_pkg.ALL; 28 USE technology_lib.technology_pkg.ALL; 29 USE unb2b_board_lib.unb2b_board_pkg.ALL; 30 USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL; 31 USE diag_lib.diag_pkg.ALL; 32 USE dp_lib.dp_stream_pkg.ALL; 33 USE work.lofar2_unb2b_adc_pkg.ALL; 34 35 ENTITY node_adc_input_and_timing IS 36 GENERIC ( 37 g_technology : NATURAL := c_tech_arria10_e1sg; 38 g_buf_nof_data : NATURAL := 1024; 39 g_nof_streams_jesd204b : NATURAL := 12; -- Fixed in IP changed this line in version 2 of the diff
35 ENTITY node_adc_input_and_timing IS 36 GENERIC ( 37 g_technology : NATURAL := c_tech_arria10_e1sg; 38 g_buf_nof_data : NATURAL := 1024; 39 g_nof_streams_jesd204b : NATURAL := 12; -- Fixed in IP 40 g_nof_streams_db : NATURAL := 2; -- Only applied to input (raw jesd) data buffer 41 g_nof_streams_input : NATURAL := 12; 42 g_sim : BOOLEAN := FALSE --Overridden by TB 43 ); 44 PORT ( 45 -- clocks and resets 46 mm_clk : IN STD_LOGIC; 47 mm_rst : IN STD_LOGIC; 48 dp_clk : IN STD_LOGIC; 49 dp_rst : IN STD_LOGIC; 50 -- dp_pps : IN STD_LOGIC; changed this line in version 2 of the diff
497 ram_data_buf_miso => ram_diag_data_buf_bsn_miso, 498 reg_data_buf_mosi => reg_diag_data_buf_bsn_mosi, 499 reg_data_buf_miso => reg_diag_data_buf_bsn_miso, 500 501 in_sosi_arr => rx_sosi_arr, 502 in_sync => rx_sosi_arr(0).sync 503 ); 504 505 506 ----------------------------------------------------------------------------- 507 -- Output Stage 508 -- . Thin dual clock fifo to cross from jesd frame clock (rx_clk) to dp_clk domain 509 ----------------------------------------------------------------------------- 510 511 gen_fifo_dc : FOR I IN 0 TO g_nof_streams_input-1 GENERATE 512 u_dp_fifo_dc : ENTITY dp_lib.dp_fifo_dc changed this line in version 2 of the diff
512 u_dp_fifo_dc : ENTITY dp_lib.dp_fifo_dc 513 GENERIC MAP ( 514 g_data_w => c_data_w, 515 g_use_empty => FALSE, --TRUE, 516 g_use_ctrl => TRUE, 517 g_use_sync => TRUE, 518 g_use_bsn => TRUE, 519 g_fifo_size => c_dp_fifo_dc_size 520 ) 521 PORT MAP ( 522 wr_rst => rx_rst, 523 wr_clk => rx_clk, 524 rd_rst => dp_rst, 525 rd_clk => dp_clk, 526 snk_in => rx_sosi_arr(I), 527 src_in => c_dp_siso_rdy, changed this line in version 2 of the diff
408 END PROCESS; 409 END GENERATE; 410 411 412 --------------------------------------------------------------------------------------- 413 -- Diagnostics on the bsn-framed data 414 -- . BSN Monitor (ToDo: can be removed as not part of the spec) 415 -- . Aduh monitor 416 -- . Data Buffer (variable depth from 1k-128k) 417 --------------------------------------------------------------------------------------- 418 419 420 --------------------------------------------------------------------------------------- 421 -- BSN monitor (Block Checker) 422 --------------------------------------------------------------------------------------- 423 u_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor 169 ----------------------------------------------------------------------------- 170 -- JESD204B IP (ADC Handler) 171 ----------------------------------------------------------------------------- 172 173 u_jesd204b: ENTITY tech_jesd204b_lib.tech_jesd204b 174 GENERIC MAP( 175 g_sim => g_sim, 176 g_nof_channels => g_nof_streams_jesd204b, 177 g_nof_syncs => g_nof_streams_jesd204b/3 -- Three ADCs per RCU share a sync 178 ) 179 PORT MAP( 180 jesd204b_refclk => JESD204B_REFCLK, 181 jesd204b_sysref => JESD204B_SYSREF, 182 jesd204b_sync_n_arr => JESD204B_SYNC, 183 184 rx_src_out_arr => jesd204b_rx_src_out_arr, changed this line in version 2 of the diff
197 serial_tx_arr => open, 198 serial_rx_arr => JESD204B_SERIAL_DATA(g_nof_streams_jesd204b-1 downto 0) 199 ); 200 201 202 gen_jesd_mon_in : FOR i IN 0 TO g_nof_streams_db-1 GENERATE 203 diag_data_buf_snk_in_arr(i).data(c_data_w-1 downto 0) <= jesd204b_rx_src_out_arr(i).data(c_data_w-1 downto 0); 204 diag_data_buf_snk_in_arr(i).valid <= jesd204b_rx_src_out_arr(i).valid; 205 diag_data_buf_snk_in_arr(i).sop <= '0'; 206 diag_data_buf_snk_in_arr(i).eop <= '0'; 207 diag_data_buf_snk_in_arr(i).err <= (OTHERS=>'0'); 208 END GENERATE; 209 210 211 ----------------------------------------------------------------------------- 212 -- Diagnostic Data Buffer (Records 8192 raw ADC samples after the PPS) 245 246 u_dp_shiftram : ENTITY dp_lib.dp_shiftram 247 GENERIC MAP ( 248 g_nof_streams => g_nof_streams_jesd204b, 249 g_nof_words => c_dp_shiftram_nof_samples, 250 g_data_w => c_data_w, 251 g_use_sync_in => TRUE 252 ) 253 PORT MAP ( 254 dp_rst => rx_rst, 255 dp_clk => rx_clk, 256 257 mm_rst => mm_rst, 258 mm_clk => mm_clk, 259 260 sync_in => bs_sosi.sync, 168 mm_wrdata => buf_mosi_arr(I).wrdata(g_buf_dat_w-1 DOWNTO 0), 169 mm_address => buf_mosi_arr(I).address(g_buf_addr_w-1 DOWNTO 0), 170 mm_wr => buf_mosi_arr(I).wr, 171 mm_rd => buf_mosi_arr(I).rd, 172 mm_rdval => buf_miso_arr(I).rdval, 173 mm_rddata => buf_miso_arr(I).rddata(g_buf_dat_w-1 DOWNTO 0), 174 175 -- Streaming clock domain 176 st_rst => st_rst, 177 st_clk => st_clk, 178 st_restart => st_restart, 179 180 st_ctrl => st_wg_ctrl_arr(I) 181 182 -- out_ovr => wg_ovr( (I+1)*g_wideband_factor -1 DOWNTO I*g_wideband_factor ), 183 -- out_dat => wg_dat( (I+1)*g_wideband_factor*g_buf_dat_w-1 DOWNTO I*g_wideband_factor*g_buf_dat_w), -
The out_dat is not connected to wg_dat, that is why WG does not work I think. Same for out_val and out_sync.
Edited by Eric Kooistra changed this line in version 2 of the diff
61 ); 62 END mms_aduh_monitor_arr; 63 64 65 ARCHITECTURE str OF mms_aduh_monitor_arr IS 66 67 CONSTANT c_reg_adr_w : NATURAL := ceil_log2(2); 68 CONSTANT c_buf_adr_w : NATURAL := ceil_log2(8); 69 70 SIGNAL reg_mosi_arr : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0); 71 SIGNAL reg_miso_arr : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0); 72 SIGNAL buf_mosi_arr : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0); 73 SIGNAL buf_miso_arr : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0); 74 75 -- Monitor outputs 76 --SIGNAL mon_mean_sum : STD_LOGIC_VECTOR(c_longword_w-1 DOWNTO 0); -- use fixed 64 bit sum width changed this line in version 2 of the diff
149 SIGNAL wg_sosi_arr : t_dp_sosi_arr(g_nof_streams_input-1 DOWNTO 0); 150 SIGNAL mux_sosi_arr : t_dp_sosi_arr(g_nof_streams_input-1 DOWNTO 0); 151 SIGNAL rx_sosi_arr : t_dp_sosi_arr(g_nof_streams_input-1 DOWNTO 0); 152 SIGNAL nxt_mux_sosi_arr : t_dp_sosi_arr(g_nof_streams_input-1 DOWNTO 0); 153 SIGNAL ant_sosi_arr : t_dp_sosi_arr(g_nof_streams_jesd204b-1 DOWNTO 0); 154 155 156 ------------------------------------------------------------------------------- 157 -- DP sync checker / insert 158 ------------------------------------------------------------------------------- 159 CONSTANT c_nof_clk_per_blk : NATURAL := 1024; 160 CONSTANT c_nof_blk_per_sync : NATURAL := 800000; 161 CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_blk_per_sync * 256; -- = 800000 * 256 162 CONSTANT c_bsn_sync_timeout : NATURAL := (c_nof_clk_per_sync * 10)/8; -- *10/8 as margin 163 164 changed this line in version 2 of the diff
309 -- Streaming clock domain 310 dp_rst => rx_rst, 311 dp_clk => rx_clk, 312 313 snk_in => bs_sosi, -- only uses eop (= block sync), bsn[] 314 trigger_out => trigger_wg 315 ); 316 317 318 ----------------------------------------------------------------------------- 319 -- WG (Test Signal Generator) 320 ----------------------------------------------------------------------------- 321 322 -- TODO: remove commented lines once the array version is working 323 324 u_sp : ENTITY diag_lib.mms_diag_wg_wideband_arr changed this line in version 2 of the diff
370 371 ----------------------------------------------------------------------------- 372 -- ADC/WG Mux (Input Select) 373 ----------------------------------------------------------------------------- 374 375 gen_mux : FOR I IN 0 TO g_nof_streams_input-1 GENERATE 376 p_sosi : PROCESS(ant_sosi_arr(I), wg_sosi_arr(I)) 377 BEGIN 378 -- Valid is forced to '1' here for dp_shiftram. 379 -- nxt_mux_sosi_arr(I).valid <= '1'; 380 381 -- Default use the ADC data 382 nxt_mux_sosi_arr(I).data <= ant_sosi_arr(I).data; 383 IF wg_sosi_arr(I).valid='1' THEN 384 -- Valid WG data overrules ADC data 385 -- nxt_mux_sosi_arr(I).data <= wg_sosi_arr(I).data; changed this line in version 2 of the diff
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