RTSD-156: apply vhdl_style_fix, delete space before semicolon

d4a911bf · Pieter Donker · 1dc76b73 · d4a911bf · d4a911bf · d4a911bf
Commit d4a911bf authored 1 year ago by Pieter Donker
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(stratix).vhd
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(stratix).vhd
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf(stratix).vhd
--- a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
--- a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd
@@ -76,8 +76,8 @@ architecture tb of tb_lofar2_unb2b_adc_wg is
  constant c_pps_period          : natural := 1000;

  constant c_tb_clk_period       : time := 100 ps;  -- use fast tb_clk to speed up M&C
-  constant c_cable_delay         : time := 12 ns
-;
+  constant c_cable_delay         : time := 12 ns;
+
  constant c_sample_freq         : natural := c_unb2b_board_ext_clk_freq_200M / 10**6;  -- 200 MSps
  constant c_sample_period       : time := (10**6 / c_sample_freq) * 1 ps;


--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd
+++ b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
--- a/boards/uniboard2/designs/unb2_led/tb/vhdl/tb_unb2_led.vhd
+++ b/boards/uniboard2/designs/unb2_led/tb/vhdl/tb_unb2_led.vhd
@@ -38,7 +38,7 @@
 --
 --

-library IEEE, common_lib, unb2_board_lib, ;
+library IEEE, common_lib, unb2_board_lib;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 use common_lib.common_pkg.all;

--- a/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
+++ b/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
--- a/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd
--- a/libraries/base/common/src/vhdl/common_evt.vhd
+++ b/libraries/base/common/src/vhdl/common_evt.vhd
--- a/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd
--- a/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
--- a/libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd
--- a/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd
--- a/libraries/base/reorder/tb/vhdl/tb_reorder_col_select_all.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_reorder_col_select_all.vhd
@@ -357,7 +357,7 @@ begin
      v := c_reorder_transpose_rst;
    end if;
    -- Synchronous reset
-    if rst = '1' THEN
+    if rst = '1' then
      v := c_reorder_transpose_rst;
    end if;
    d_transpose <= v;
@@ -379,7 +379,7 @@ begin
      v := c_reorder_transpose_rst;
    end if;
    -- Synchronous reset
-    if rst = '1' THEN
+    if rst = '1' then
      v := c_reorder_transpose_rst;
    end if;
    d_undo_transpose <= v;

--- a/libraries/base/tst/src/vhdl/tst_input.vhd
+++ b/libraries/base/tst/src/vhdl/tst_input.vhd