From d4a911bf2b4adfbc6f0da7d163fbf7c024a6bd9d Mon Sep 17 00:00:00 2001
From: donker <donker@astron.nl>
Date: Wed, 16 Aug 2023 13:45:03 +0200
Subject: [PATCH] RTSD-156: apply vhdl_style_fix, delete space before semicolon
---
.../pfs/src/vhdl/pfs_coefsbuf(stratix).vhd | 4 +-
.../RSP/pfs/src/vhdl/pfs_filter(stratix).vhd | 120 +++++------
.../src/vhdl/pfs_fir_coefsbuf(stratix).vhd | 4 +-
.../vhdl/tb_lofar2_unb2b_adc_multichannel.vhd | 4 +-
.../tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd | 4 +-
.../sdp/tb/vhdl/tb_sdp_statistics_offload.vhd | 2 +-
.../ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd | 2 +-
.../tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd | 2 +-
.../mmm_unb1_minimal_qsys_wo_pll.vhd | 6 +-
.../src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd | 6 +-
.../designs/unb2_led/tb/vhdl/tb_unb2_led.vhd | 2 +-
.../unb2_pinning/src/vhdl/unb2_pinning.vhd | 2 +-
.../axi4/src/vhdl/axi4_stream_dp_bridge.vhd | 2 +-
libraries/base/common/src/vhdl/common_evt.vhd | 2 +-
.../src/vhdl/common_network_layers_pkg.vhd | 8 +-
libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd | 2 +-
.../vhdl/dp_block_validate_bsn_at_sync.vhd | 2 +-
.../dp/src/vhdl/dp_block_validate_err.vhd | 2 +-
.../tb/vhdl/tb_reorder_col_select_all.vhd | 4 +-
libraries/base/tst/src/vhdl/tst_input.vhd | 2 +-
libraries/base/uth/src/vhdl/uth_pkg.vhd | 4 +-
libraries/base/util/src/vhdl/util_heater.vhd | 2 +-
.../correlator/src/vhdl/corr_accumulator.vhd | 2 +-
.../tb/vhdl/tb_corr_accumulator.vhd | 2 +-
.../correlator/tb/vhdl/tb_correlator_dev.vhd | 4 +-
.../tb/vhdl/tb_fringe_stop_unit.vhd | 2 +-
.../ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd | 4 +-
.../src/vhdl/mmm_unb1_eth_10g.vhd | 6 +-
libraries/io/eth/src/vhdl/eth_hdr.vhd | 2 +-
.../eth/src/vhdl/eth_ip_header_checksum.vhd | 26 +--
libraries/io/eth/src/vhdl/eth_tester_tx.vhd | 10 +-
.../eth/tb/vhdl/tb_eth_ip_header_checksum.vhd | 16 +-
.../tb/vhdl/tb_tb_eth_ip_header_checksum.vhd | 2 +-
libraries/io/i2c/src/vhdl/i2c_smbus.vhd | 2 +-
.../tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd | 2 +-
.../fifo/tech_fifo_component_pkg.vhd | 190 +++++++++---------
.../flash/tech_flash_asmi_parallel.vhd | 22 +-
.../flash/tech_flash_component_pkg.vhd | 34 ++--
.../tech_fractional_pll_clk125.vhd | 8 +-
.../tech_fractional_pll_clk200.vhd | 6 +-
.../ip_arria10/fifo/ip_arria10_fifo_dc.vhd | 12 +-
.../fifo/ip_arria10_fifo_dc_mixed_widths.vhd | 12 +-
.../ip_arria10/fifo/ip_arria10_fifo_sc.vhd | 14 +-
.../ip_arria10/ram/ip_arria10_ram_cr_cw.vhd | 2 +-
.../ip_arria10/ram/ip_arria10_ram_crw_crw.vhd | 2 +-
.../ram/ip_arria10_ram_crwk_crw.vhd | 2 +-
.../fifo/ip_arria10_e1sg_fifo_dc.vhd | 12 +-
.../ip_arria10_e1sg_fifo_dc_mixed_widths.vhd | 12 +-
.../fifo/ip_arria10_e1sg_fifo_sc.vhd | 14 +-
.../ram/ip_arria10_e1sg_ram_cr_cw.vhd | 2 +-
.../ram/ip_arria10_e1sg_ram_crw_crw.vhd | 2 +-
.../ram/ip_arria10_e1sg_ram_crwk_crw.vhd | 2 +-
.../fifo/ip_arria10_e2sg_fifo_dc.vhd | 12 +-
.../ip_arria10_e2sg_fifo_dc_mixed_widths.vhd | 12 +-
.../fifo/ip_arria10_e2sg_fifo_sc.vhd | 14 +-
.../ram/ip_arria10_e2sg_ram_cr_cw.vhd | 2 +-
.../ram/ip_arria10_e2sg_ram_crw_crw.vhd | 2 +-
.../ram/ip_arria10_e2sg_ram_crwk_crw.vhd | 2 +-
.../fifo/ip_arria10_e3sge3_fifo_dc.vhd | 12 +-
...ip_arria10_e3sge3_fifo_dc_mixed_widths.vhd | 12 +-
.../fifo/ip_arria10_e3sge3_fifo_sc.vhd | 14 +-
.../ram/ip_arria10_e3sge3_ram_cr_cw.vhd | 2 +-
.../ram/ip_arria10_e3sge3_ram_crw_crw.vhd | 2 +-
.../ram/ip_arria10_e3sge3_ram_crwk_crw.vhd | 2 +-
.../fifo/ip_ultrascale_fifo_dc.vhd | 12 +-
.../ip_ultrascale_fifo_dc_mixed_widths.vhd | 12 +-
.../fifo/ip_ultrascale_fifo_sc.vhd | 14 +-
.../ram/ip_ultrascale_ram_cr_cw.vhd | 2 +-
.../ram/ip_ultrascale_ram_crw_crw.vhd | 2 +-
.../technology/jesd204b/tb_tech_jesd204b.vhd | 4 +-
.../memory/tech_memory_component_pkg.vhd | 34 ++--
.../memory/tech_memory_ram_cr_cw.vhd | 2 +-
.../memory/tech_memory_ram_crw_crw.vhd | 2 +-
.../memory/tech_memory_ram_crwk_crw.vhd | 2 +-
.../mult/tech_mult_component_pkg.vhd | 6 +-
libraries/technology/pll/tech_pll_clk125.vhd | 8 +-
libraries/technology/pll/tech_pll_clk200.vhd | 6 +-
.../technology/pll/tech_pll_clk200_p6.vhd | 14 +-
libraries/technology/pll/tech_pll_clk25.vhd | 10 +-
.../technology/pll/tech_pll_component_pkg.vhd | 118 +++++------
.../sim_transceiver_deserializer.vhd | 2 +-
.../tech_transceiver_component_pkg.vhd | 28 +--
82 files changed, 491 insertions(+), 491 deletions(-)
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(stratix).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(stratix).vhd
index 9d7c70a8a7..8a18fea17a 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(stratix).vhd
@@ -22,8 +22,8 @@ architecture stratix of pfs_coefsbuf is
intended_device_family : string
);
port (
- aclr0 : in std_logic ;
- clock0 : in std_logic ;
+ aclr0 : in std_logic;
+ clock0 : in std_logic;
address_a : in std_logic_vector(g_addr_w - 1 downto 0);
q_a : out std_logic_vector(g_data_w - 1 downto 0)
);
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(stratix).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(stratix).vhd
index 9cde479324..eb483ea066 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(stratix).vhd
@@ -8,73 +8,73 @@ architecture stratix of pfs_filter is
component altmult_add
generic (
- input_register_b2 : string := "CLOCK0" ;
- input_register_a1 : string := "CLOCK0" ;
- multiplier_register0 : string := "CLOCK0" ;
- signed_pipeline_aclr_b : string := "ACLR3" ;
- input_register_b3 : string := "CLOCK0" ;
- input_register_a2 : string := "CLOCK0" ;
- multiplier_register1 : string := "CLOCK0" ;
- addnsub_multiplier_pipeline_aclr1 : string := "ACLR3" ;
- input_register_a3 : string := "CLOCK0" ;
- multiplier_register2 : string := "CLOCK0" ;
- signed_aclr_a : string := "ACLR3" ;
- signed_register_a : string := "CLOCK0" ;
- number_of_multipliers : natural := 4 ;
- multiplier_register3 : string := "CLOCK0" ;
- multiplier_aclr0 : string := "ACLR3" ;
- addnsub_multiplier_pipeline_aclr3 : string := "ACLR3" ;
- signed_aclr_b : string := "ACLR3" ;
- signed_register_b : string := "CLOCK0" ;
+ input_register_b2 : string := "CLOCK0";
+ input_register_a1 : string := "CLOCK0";
+ multiplier_register0 : string := "CLOCK0";
+ signed_pipeline_aclr_b : string := "ACLR3";
+ input_register_b3 : string := "CLOCK0";
+ input_register_a2 : string := "CLOCK0";
+ multiplier_register1 : string := "CLOCK0";
+ addnsub_multiplier_pipeline_aclr1 : string := "ACLR3";
+ input_register_a3 : string := "CLOCK0";
+ multiplier_register2 : string := "CLOCK0";
+ signed_aclr_a : string := "ACLR3";
+ signed_register_a : string := "CLOCK0";
+ number_of_multipliers : natural := 4;
+ multiplier_register3 : string := "CLOCK0";
+ multiplier_aclr0 : string := "ACLR3";
+ addnsub_multiplier_pipeline_aclr3 : string := "ACLR3";
+ signed_aclr_b : string := "ACLR3";
+ signed_register_b : string := "CLOCK0";
lpm_type : string := "altmult_add";
- multiplier_aclr1 : string := "ACLR3" ;
- input_aclr_b0 : string := "ACLR3" ;
- output_register : string := "CLOCK0" ;
+ multiplier_aclr1 : string := "ACLR3";
+ input_aclr_b0 : string := "ACLR3";
+ output_register : string := "CLOCK0";
width_result : natural := g_taps_w + g_coef_w + 2;
- representation_a : string := "SIGNED" ;
- signed_pipeline_register_a : string := "CLOCK0" ;
- input_source_b0 : string := "DATAB" ;
- multiplier_aclr2 : string := "ACLR3" ;
- input_aclr_b1 : string := "ACLR3" ;
- input_aclr_a0 : string := "ACLR3" ;
- multiplier3_direction : string := "ADD" ;
- addnsub_multiplier_register1 : string := "CLOCK0" ;
- representation_b : string := "SIGNED" ;
- signed_pipeline_register_b : string := "CLOCK0" ;
- input_source_b1 : string := "DATAB" ;
- input_source_a0 : string := "DATAA" ;
- multiplier_aclr3 : string := "ACLR3" ;
- input_aclr_b2 : string := "ACLR3" ;
- input_aclr_a1 : string := "ACLR3" ;
- dedicated_multiplier_circuitry : string := "YES" ;
- input_source_b2 : string := "DATAB" ;
- input_source_a1 : string := "DATAA" ;
- input_aclr_b3 : string := "ACLR3" ;
- input_aclr_a2 : string := "ACLR3" ;
- addnsub_multiplier_register3 : string := "CLOCK0" ;
- addnsub_multiplier_aclr1 : string := "ACLR3" ;
- output_aclr : string := "ACLR3" ;
- input_source_b3 : string := "DATAB" ;
- input_source_a2 : string := "DATAA" ;
- input_aclr_a3 : string := "ACLR3" ;
- input_source_a3 : string := "DATAA" ;
- addnsub_multiplier_aclr3 : string := "ACLR3" ;
- intended_device_family : string := "Stratix II" ;
- addnsub_multiplier_pipeline_register1 : string := "CLOCK0" ;
- width_a : natural := g_taps_w ;
- input_register_b0 : string := "CLOCK0" ;
- width_b : natural := g_coef_w ;
- input_register_b1 : string := "CLOCK0" ;
- input_register_a0 : string := "CLOCK0" ;
- addnsub_multiplier_pipeline_register3 : string := "CLOCK0" ;
- multiplier1_direction : string := "ADD" ;
+ representation_a : string := "SIGNED";
+ signed_pipeline_register_a : string := "CLOCK0";
+ input_source_b0 : string := "DATAB";
+ multiplier_aclr2 : string := "ACLR3";
+ input_aclr_b1 : string := "ACLR3";
+ input_aclr_a0 : string := "ACLR3";
+ multiplier3_direction : string := "ADD";
+ addnsub_multiplier_register1 : string := "CLOCK0";
+ representation_b : string := "SIGNED";
+ signed_pipeline_register_b : string := "CLOCK0";
+ input_source_b1 : string := "DATAB";
+ input_source_a0 : string := "DATAA";
+ multiplier_aclr3 : string := "ACLR3";
+ input_aclr_b2 : string := "ACLR3";
+ input_aclr_a1 : string := "ACLR3";
+ dedicated_multiplier_circuitry : string := "YES";
+ input_source_b2 : string := "DATAB";
+ input_source_a1 : string := "DATAA";
+ input_aclr_b3 : string := "ACLR3";
+ input_aclr_a2 : string := "ACLR3";
+ addnsub_multiplier_register3 : string := "CLOCK0";
+ addnsub_multiplier_aclr1 : string := "ACLR3";
+ output_aclr : string := "ACLR3";
+ input_source_b3 : string := "DATAB";
+ input_source_a2 : string := "DATAA";
+ input_aclr_a3 : string := "ACLR3";
+ input_source_a3 : string := "DATAA";
+ addnsub_multiplier_aclr3 : string := "ACLR3";
+ intended_device_family : string := "Stratix II";
+ addnsub_multiplier_pipeline_register1 : string := "CLOCK0";
+ width_a : natural := g_taps_w;
+ input_register_b0 : string := "CLOCK0";
+ width_b : natural := g_coef_w;
+ input_register_b1 : string := "CLOCK0";
+ input_register_a0 : string := "CLOCK0";
+ addnsub_multiplier_pipeline_register3 : string := "CLOCK0";
+ multiplier1_direction : string := "ADD";
signed_pipeline_aclr_a : string := "ACLR3"
);
port (
dataa : in std_logic_vector(g_taps_w * 4 - 1 downto 0);
datab : in std_logic_vector(g_coef_w * 4 - 1 downto 0);
- clock0 : in std_logic ;
- aclr3 : in std_logic ;
+ clock0 : in std_logic;
+ aclr3 : in std_logic;
result : out std_logic_vector(g_coef_w + g_taps_w + 2 - 1 downto 0)
);
end component;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf(stratix).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf(stratix).vhd
index 9569e84d0b..57b0f46def 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf(stratix).vhd
@@ -22,8 +22,8 @@ architecture stratix of pfs_fir_coefsbuf is
intended_device_family : string
);
port (
- aclr0 : in std_logic ;
- clock0 : in std_logic ;
+ aclr0 : in std_logic;
+ clock0 : in std_logic;
address_a : in std_logic_vector(g_coefs_w - 1 downto 0);
q_a : out std_logic_vector(g_data_w - 1 downto 0)
);
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
index 061f75cf7b..6fe9a16e9b 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
@@ -71,7 +71,7 @@ architecture tb of tb_lofar2_unb2b_adc_multichannel is
5000 ps,
5000 ps,
5000 ps,
- 5000 ps) ; -- transport delays tx to rx data
+ 5000 ps); -- transport delays tx to rx data
constant c_delay_sysreftoadc_arr : t_time_arr := (4000 ps,
5000 ps,
6000 ps,
@@ -83,7 +83,7 @@ architecture tb of tb_lofar2_unb2b_adc_multichannel is
1000 ps,
1000 ps,
1000 ps,
- 1000 ps) ; -- transport delays clock source to adc(tx)
+ 1000 ps); -- transport delays clock source to adc(tx)
constant c_delay_sysreftofpga : time := 10200 ps;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd
index f3791a4aef..c1689b31e3 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd
@@ -76,8 +76,8 @@ architecture tb of tb_lofar2_unb2b_adc_wg is
constant c_pps_period : natural := 1000;
constant c_tb_clk_period : time := 100 ps; -- use fast tb_clk to speed up M&C
- constant c_cable_delay : time := 12 ns
-;
+ constant c_cable_delay : time := 12 ns;
+
constant c_sample_freq : natural := c_unb2b_board_ext_clk_freq_200M / 10**6; -- 200 MSps
constant c_sample_period : time := (10**6 / c_sample_freq) * 1 ps;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
index 5dccef4959..eafe4669a3 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
@@ -249,7 +249,7 @@ architecture tb of tb_sdp_statistics_offload is
signal dbg_c_crosslets_info_slv : std_logic_vector(c_sdp_crosslets_info_reg_w - 1 downto 0) := c_crosslets_info_slv;
signal dbg_c_nof_block_per_sync : natural := c_nof_block_per_sync;
signal dbg_c_nof_clk_per_block : natural := c_nof_clk_per_block;
- signal dbg_c_nof_clk_per_sync : natural := c_nof_clk_per_sync ;
+ signal dbg_c_nof_clk_per_sync : natural := c_nof_clk_per_sync;
begin
diff --git a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd
index f747878245..b80bc1c49f 100644
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd
+++ b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd
@@ -31,7 +31,7 @@
-- . M&C
-- --------------------------------------------------------------------------
-library IEEE, common_lib, unb2b_board_lib, technology_lib, dp_lib, tech_ddr_lib, ta2_unb2b_40GbE_lib, ta2_unb2b_10gbe_lib, ta2_unb2b_1gbe_lib, ta2_unb2b_mm_io_lib, ta2_unb2b_jesd204b_lib ;
+library IEEE, common_lib, unb2b_board_lib, technology_lib, dp_lib, tech_ddr_lib, ta2_unb2b_40GbE_lib, ta2_unb2b_10gbe_lib, ta2_unb2b_1gbe_lib, ta2_unb2b_mm_io_lib, ta2_unb2b_jesd204b_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd b/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd
index fc2e86fa11..7dc0e26872 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd
@@ -79,7 +79,7 @@ entity tb_node_unb1_bn_terminal_bg is
-- Mesh serial interface (tr_nonbonded)
mesh_tx_serial_2arr : out t_unb1_board_mesh_sl_2arr; -- Tx
- mesh_rx_serial_2arr : in t_unb1_board_mesh_sl_2arr := (others => (others => '0')) ; -- Rx support for diagnostics
+ mesh_rx_serial_2arr : in t_unb1_board_mesh_sl_2arr := (others => (others => '0')); -- Rx support for diagnostics
-- Back serial interface (tr_nonbonded)
back_tx_serial_2arr : out t_unb1_board_back_sl_2arr; -- Tx
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
index b0b46e9cec..980363e3dd 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
@@ -110,11 +110,11 @@ architecture str of mmm_unb1_minimal_qsys_wo_pll is
constant c_sim_eth_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
constant c_sim_eth_control_rx_en : natural := 2**c_eth_mm_reg_control_bi.rx_en;
- signal sim_eth_mm_bus_switch : std_logic ;
- signal sim_eth_psc_access : std_logic ;
+ signal sim_eth_mm_bus_switch : std_logic;
+ signal sim_eth_psc_access : std_logic;
signal i_eth1g_reg_mosi : t_mem_mosi;
signal i_eth1g_reg_miso : t_mem_miso;
- signal mm_rst_n : std_logic ;
+ signal mm_rst_n : std_logic;
signal sim_eth1g_reg_mosi : t_mem_mosi;
constant c_mm_clk_period : time := 1000 ms / g_mm_clk_freq;
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
index 794e9af242..6f2d2143cc 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
@@ -138,11 +138,11 @@ architecture str of mmm_unb1_terminal_bg_mesh_db is
constant c_sim_eth_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
constant c_sim_eth_control_rx_en : natural := 2**c_eth_mm_reg_control_bi.rx_en;
- signal sim_eth_mm_bus_switch : std_logic ;
- signal sim_eth_psc_access : std_logic ;
+ signal sim_eth_mm_bus_switch : std_logic;
+ signal sim_eth_psc_access : std_logic;
signal i_eth1g_reg_mosi : t_mem_mosi;
signal i_eth1g_reg_miso : t_mem_miso;
- signal mm_rst_n : std_logic ;
+ signal mm_rst_n : std_logic;
signal sim_eth1g_reg_mosi : t_mem_mosi;
component qsys_unb1_terminal_bg_mesh_db is
diff --git a/boards/uniboard2/designs/unb2_led/tb/vhdl/tb_unb2_led.vhd b/boards/uniboard2/designs/unb2_led/tb/vhdl/tb_unb2_led.vhd
index 26d6ca1ef6..63962939ea 100644
--- a/boards/uniboard2/designs/unb2_led/tb/vhdl/tb_unb2_led.vhd
+++ b/boards/uniboard2/designs/unb2_led/tb/vhdl/tb_unb2_led.vhd
@@ -38,7 +38,7 @@
--
--
-library IEEE, common_lib, unb2_board_lib, ;
+library IEEE, common_lib, unb2_board_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd b/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
index 9fa20f22f2..0890ad356b 100644
--- a/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
+++ b/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
@@ -649,7 +649,7 @@ begin
rx_serial_data_front <= RING_0_RX
& QSFP_0_RX & QSFP_1_RX & QSFP_2_RX & QSFP_3_RX & QSFP_4_RX & QSFP_5_RX
- & RING_1_RX ;
+ & RING_1_RX;
transceiver_phy_front : transceiver_phy
diff --git a/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd b/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd
index f554bfe7fe..670f3ac26a 100644
--- a/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd
@@ -95,7 +95,7 @@ architecture str of axi4_stream_dp_bridge is
dp_from_axi4_sosi : t_dp_sosi;
end record;
- constant c_reg_init : t_reg := ('1', c_dp_sosi_rst) ;
+ constant c_reg_init : t_reg := ('1', c_dp_sosi_rst);
-- Registers
signal d_reg : t_reg := c_reg_init;
diff --git a/libraries/base/common/src/vhdl/common_evt.vhd b/libraries/base/common/src/vhdl/common_evt.vhd
index 69706e8b87..ea7fef958b 100644
--- a/libraries/base/common/src/vhdl/common_evt.vhd
+++ b/libraries/base/common/src/vhdl/common_evt.vhd
@@ -76,7 +76,7 @@ begin
p_clk : process(rst, clk)
begin
if rst = '1' then
- out_evt <= sel_a_b(g_out_invert, '1', '0') ;
+ out_evt <= sel_a_b(g_out_invert, '1', '0');
elsif rising_edge(clk) then
if clken = '1' then
out_evt <= sel_a_b(g_out_invert, sig_evt_n, sig_evt);
diff --git a/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd b/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd
index 520d585be9..d713e18b3d 100644
--- a/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd
@@ -374,15 +374,15 @@ package body common_network_layers_pkg is
variable vec : std_logic_vector(c_halfword_w * c_nof_halfword - 1 downto 0);
begin
-- vec = whole ip header excluding ip_header_checksum.
- vec :=
- hdr_fields_slv(field_hi(field_arr, "ip_version" ) downto field_lo(field_arr, "ip_protocol" ))
+ vec :=
+ hdr_fields_slv(field_hi(field_arr, "ip_version" ) downto field_lo(field_arr, "ip_protocol" ))
& hdr_fields_slv(field_hi(field_arr, "ip_src_addr" ) downto field_lo(field_arr, "ip_dst_addr" ));
-- sum up vec in halfwords
for i in 0 to c_nof_halfword - 1 loop
sum := sum + unsigned(vec(( i + 1 ) * c_halfword_w - 1 downto i * c_halfword_w));
- end loop;
-
+ end loop;
+
-- checksum = inverted (sum + carry)
crc := not(std_logic_vector(sum(c_halfword_w - 1 downto 0) + sum(sum'high downto c_halfword_w)));
return crc;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd b/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
index 4990dd0672..c9fbf5bb56 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
@@ -174,7 +174,7 @@ package tb_diag_pkg is
signal cw_dat : out integer; -- estimated CW
signal cw_noise : out real; -- estimated CW quantization noise
signal accum_noise_power : inout real; -- store noise power accumulator in signal
- signal measured_noise_power : out real) ; -- measured noise power in in_dat
+ signal measured_noise_power : out real); -- measured noise power in in_dat
procedure proc_diag_measure_cw_noise_power(constant c_fft_size : in natural; -- number of points of FFT = number of samples per in_start interval
constant c_sub : in real;
diff --git a/libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd b/libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd
index 983aba1db1..545d9c06bf 100644
--- a/libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd
@@ -121,7 +121,7 @@ architecture rtl of dp_block_validate_bsn_at_sync is
begin
- mm_cnt_clr <= (reg_mosi.rd or reg_mosi.wr) when TO_UINT(reg_mosi.address(c_mm_reg.adr_w - 1 downto 0)) = c_clear_adr else '0' ;
+ mm_cnt_clr <= (reg_mosi.rd or reg_mosi.wr) when TO_UINT(reg_mosi.address(c_mm_reg.adr_w - 1 downto 0)) = c_clear_adr else '0';
u_common_spulse : entity common_lib.common_spulse
port map (
in_rst => mm_rst,
diff --git a/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd b/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd
index e56d4b1444..c44962c7f7 100644
--- a/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd
@@ -167,7 +167,7 @@ architecture rtl of dp_block_validate_err is
begin
- mm_cnt_clr <= (reg_mosi.rd or reg_mosi.wr) when TO_UINT(reg_mosi.address(c_mm_reg.adr_w - 1 downto 0)) = c_clear_adr else '0' ;
+ mm_cnt_clr <= (reg_mosi.rd or reg_mosi.wr) when TO_UINT(reg_mosi.address(c_mm_reg.adr_w - 1 downto 0)) = c_clear_adr else '0';
u_common_spulse : entity common_lib.common_spulse
port map (
in_rst => mm_rst,
diff --git a/libraries/base/reorder/tb/vhdl/tb_reorder_col_select_all.vhd b/libraries/base/reorder/tb/vhdl/tb_reorder_col_select_all.vhd
index 8b4640ebd3..955c7a7184 100644
--- a/libraries/base/reorder/tb/vhdl/tb_reorder_col_select_all.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_reorder_col_select_all.vhd
@@ -357,7 +357,7 @@ begin
v := c_reorder_transpose_rst;
end if;
-- Synchronous reset
- if rst = '1' THEN
+ if rst = '1' then
v := c_reorder_transpose_rst;
end if;
d_transpose <= v;
@@ -379,7 +379,7 @@ begin
v := c_reorder_transpose_rst;
end if;
-- Synchronous reset
- if rst = '1' THEN
+ if rst = '1' then
v := c_reorder_transpose_rst;
end if;
d_undo_transpose <= v;
diff --git a/libraries/base/tst/src/vhdl/tst_input.vhd b/libraries/base/tst/src/vhdl/tst_input.vhd
index d56f662cf2..e6076abfd1 100644
--- a/libraries/base/tst/src/vhdl/tst_input.vhd
+++ b/libraries/base/tst/src/vhdl/tst_input.vhd
@@ -126,7 +126,7 @@ begin
process (rst, state, eof, sync, en, gap_count, msg, lno, rep)
variable file_status : FILE_OPEN_STATUS;
- file in_file : TEXT ;
+ file in_file : TEXT;
variable in_line : LINE;
variable num : integer;
variable cycle_lno : integer; -- file line number
diff --git a/libraries/base/uth/src/vhdl/uth_pkg.vhd b/libraries/base/uth/src/vhdl/uth_pkg.vhd
index f29b48bd53..b66e634936 100644
--- a/libraries/base/uth/src/vhdl/uth_pkg.vhd
+++ b/libraries/base/uth/src/vhdl/uth_pkg.vhd
@@ -35,8 +35,8 @@ package uth_pkg is
constant c_uth_crc64 : natural := 64; -- internally use CRC-8, 16, 32 or 64, use CRC-64 for data wider than 32 bits
constant c_uth_nof_overhead : natural := 4; -- header: idle, sfd, tlen and tail: crc, so total 4 words frame overhead
constant c_uth_gap_min : natural := c_uth_nof_overhead; -- minimal gap between valid data blocks (to be able to insert the frame overhead into the stream)
- constant c_uth_idle : std_logic_vector(c_uth_data_max_w - 1 downto 0) := c_slv1( c_uth_data_max_w - 1 downto 0) ; -- = 0xF..FFFF
- constant c_uth_preamble : std_logic_vector(c_uth_data_max_w - 1 downto 0) := c_slv10(c_uth_data_max_w - 1 downto 0) ; -- = 0xA..AAAA
+ constant c_uth_idle : std_logic_vector(c_uth_data_max_w - 1 downto 0) := c_slv1( c_uth_data_max_w - 1 downto 0); -- = 0xF..FFFF
+ constant c_uth_preamble : std_logic_vector(c_uth_data_max_w - 1 downto 0) := c_slv10(c_uth_data_max_w - 1 downto 0); -- = 0xA..AAAA
constant c_uth_sfd : std_logic_vector(c_uth_data_max_w - 1 downto 0) := c_slv10(c_uth_data_max_w - 1 downto 1) & '1'; -- = 0xA..AAAB
constant c_uth_payload_min : natural := 1; -- an empty payload is not allowed because we need at least one data to signal sop and eop
diff --git a/libraries/base/util/src/vhdl/util_heater.vhd b/libraries/base/util/src/vhdl/util_heater.vhd
index 4f5c3265af..93ea856dfb 100644
--- a/libraries/base/util/src/vhdl/util_heater.vhd
+++ b/libraries/base/util/src/vhdl/util_heater.vhd
@@ -94,7 +94,7 @@ architecture rtl of util_heater is
-- Random input generators
constant c_in_dat_w : natural := 18; -- fixed multiplier input data width
- constant c_prsg_0_w : natural := c_in_dat_w ; -- generate sufficiently large random range
+ constant c_prsg_0_w : natural := c_in_dat_w; -- generate sufficiently large random range
constant c_prsg_1_w : natural := c_in_dat_w + 1; -- generate different range
constant c_prsg_2_w : natural := c_in_dat_w + 2; -- generate different range
constant c_prsg_3_w : natural := c_in_dat_w + 3; -- generate different range
diff --git a/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd b/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd
index 08315cb2b7..3ae04fca64 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd
@@ -1,6 +1,6 @@
--------------------------------------------------------------------------------
--
--- Author: Daniel van der Schuur
+-- Author: Daniel van der Schuur
--
-- Copyright (C) 2016
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
diff --git a/libraries/dsp/correlator/tb/vhdl/tb_corr_accumulator.vhd b/libraries/dsp/correlator/tb/vhdl/tb_corr_accumulator.vhd
index 41cc6863b2..6e849f6c02 100644
--- a/libraries/dsp/correlator/tb/vhdl/tb_corr_accumulator.vhd
+++ b/libraries/dsp/correlator/tb/vhdl/tb_corr_accumulator.vhd
@@ -119,7 +119,7 @@ begin
nxt_in_valid_count <= in_valid_count;
nxt_int_period_cnt <= int_period_cnt;
if dp_gen_data_src_out_arr(0).valid = '1' then
- nxt_in_valid_count <= in_valid_count + 1 ;
+ nxt_in_valid_count <= in_valid_count + 1;
if in_valid_count > 0 and (in_valid_count mod (g_nof_channels * g_nof_channel_accs)) = 0 then
nxt_int_period_cnt <= int_period_cnt + 1;
end if;
diff --git a/libraries/dsp/correlator/tb/vhdl/tb_correlator_dev.vhd b/libraries/dsp/correlator/tb/vhdl/tb_correlator_dev.vhd
index 286003b00e..b9042998fb 100644
--- a/libraries/dsp/correlator/tb/vhdl/tb_correlator_dev.vhd
+++ b/libraries/dsp/correlator/tb/vhdl/tb_correlator_dev.vhd
@@ -1,6 +1,6 @@
--------------------------------------------------------------------------------
--
--- Author: Daniel van der Schuur
+-- Author: Daniel van der Schuur
--
-- Copyright (C) 2016
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
@@ -126,7 +126,7 @@ begin
nxt_in_valid_count <= in_valid_count;
nxt_int_period_cnt <= int_period_cnt;
if dp_gen_data_src_out_arr(0).valid = '1' then
- nxt_in_valid_count <= in_valid_count + 1 ;
+ nxt_in_valid_count <= in_valid_count + 1;
if in_valid_count > 0 and (in_valid_count mod (g_nof_channels * g_nof_channel_accs)) = 0 then
nxt_int_period_cnt <= int_period_cnt + 1;
end if;
diff --git a/libraries/dsp/fringe_stop/tb/vhdl/tb_fringe_stop_unit.vhd b/libraries/dsp/fringe_stop/tb/vhdl/tb_fringe_stop_unit.vhd
index 477a78ead4..505a615c77 100644
--- a/libraries/dsp/fringe_stop/tb/vhdl/tb_fringe_stop_unit.vhd
+++ b/libraries/dsp/fringe_stop/tb/vhdl/tb_fringe_stop_unit.vhd
@@ -147,7 +147,7 @@ architecture tb of tb_fringe_stop_unit is
ref_im : integer;
end record;
- constant c_reg_type_rst : reg_type := ((others => c_dp_sosi_rst), (others => 0), 0, 0, 0, 0, 0, true, true, true, 0, 0, 0) ;
+ constant c_reg_type_rst : reg_type := ((others => c_dp_sosi_rst), (others => 0), 0, 0, 0, 0, 0, true, true, true, 0, 0, 0);
signal r : reg_type := c_reg_type_rst;
signal rin : reg_type := c_reg_type_rst;
diff --git a/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd b/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd
index 76a064d7b0..3012e51ac8 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd
@@ -86,8 +86,8 @@ begin
-- Flush disable control
no_channel: if g_use_channel = false generate
gen_valid : if g_mode = "VAL" generate flush_dis <= ctlr_wr_sosi.valid; end generate;
- gen_sop : if g_mode = "SOP" generate flush_dis <= ctlr_wr_sosi.sop ; end generate;
- gen_sync : if g_mode = "SYN" generate flush_dis <= ctlr_wr_sosi.sync ; end generate;
+ gen_sop : if g_mode = "SOP" generate flush_dis <= ctlr_wr_sosi.sop; end generate;
+ gen_sync : if g_mode = "SYN" generate flush_dis <= ctlr_wr_sosi.sync; end generate;
end generate;
use_channel: if g_use_channel = true generate
diff --git a/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd b/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd
index 4b679a931f..45e5c26c4a 100644
--- a/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd
+++ b/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd
@@ -231,11 +231,11 @@ architecture str of mmm_unb1_eth_10g is
constant c_sim_eth_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
constant c_sim_eth_control_rx_en : natural := 2**c_eth_mm_reg_control_bi.rx_en;
- signal sim_eth_mm_bus_switch : std_logic ;
- signal sim_eth_psc_access : std_logic ;
+ signal sim_eth_mm_bus_switch : std_logic;
+ signal sim_eth_psc_access : std_logic;
signal i_eth1g_reg_mosi : t_mem_mosi;
signal i_eth1g_reg_miso : t_mem_miso;
- signal mm_rst_n : std_logic ;
+ signal mm_rst_n : std_logic;
signal sim_eth1g_reg_mosi : t_mem_mosi;
component qsys_unb1_eth_10g is
diff --git a/libraries/io/eth/src/vhdl/eth_hdr.vhd b/libraries/io/eth/src/vhdl/eth_hdr.vhd
index 981d34d3b9..e183e1a050 100644
--- a/libraries/io/eth/src/vhdl/eth_hdr.vhd
+++ b/libraries/io/eth/src/vhdl/eth_hdr.vhd
@@ -92,7 +92,7 @@ begin
-- Make all header info available
hdr_words_arr <= i_hdr_words_arr;
- hdr_words_arr_val <= i_hdr_words_arr_val ;
+ hdr_words_arr_val <= i_hdr_words_arr_val;
hdr_fields <= i_hdr_fields;
hdr_fields_val <= i_hdr_fields_val;
hdr_data <= i_hdr_data;
diff --git a/libraries/io/eth/src/vhdl/eth_ip_header_checksum.vhd b/libraries/io/eth/src/vhdl/eth_ip_header_checksum.vhd
index 5f5067f952..14013f5dbe 100644
--- a/libraries/io/eth/src/vhdl/eth_ip_header_checksum.vhd
+++ b/libraries/io/eth/src/vhdl/eth_ip_header_checksum.vhd
@@ -17,18 +17,18 @@
-- --------------------------------------------------------------------------
--
-- Author: R. van der Walle
--- Purpose:
--- Can be used to calculate and insert the checksum for the IP header
--- in a network package, if the correct hdr_fields_slv_in is provided.
--- Description:
--- Determine the 16 bit 1-complement checksum according IPv4 to for the
--- hdr_fields_slv_in.
+-- Purpose:
+-- Can be used to calculate and insert the checksum for the IP header
+-- in a network package, if the correct hdr_fields_slv_in is provided.
+-- Description:
+-- Determine the 16 bit 1-complement checksum according IPv4 to for the
+-- hdr_fields_slv_in.
-- After calculation, the checksum is inserted in the outgoing stream at
-- corresponding position based on g_hdr_field_arr and g_data_w.
-- Remarks:
-- The hdr_fields_slv_in should be valid on the snk_in.sop
-
+
library IEEE, common_lib, dp_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -63,9 +63,9 @@ architecture rtl of eth_ip_header_checksum is
constant c_hdr_crc_bit_lo : natural := field_lo(g_hdr_field_arr, "ip_header_checksum");
-- calculate which word(s) of the incoming snk_in stream should contain the checksum.
- constant c_hdr_crc_word_hi : natural := sel_a_b((c_hdr_crc_bit_hi / g_data_w) > 0, c_hdr_crc_bit_hi / g_data_w,
+ constant c_hdr_crc_word_hi : natural := sel_a_b((c_hdr_crc_bit_hi / g_data_w) > 0, c_hdr_crc_bit_hi / g_data_w,
sel_a_b( c_hdr_crc_bit_hi > (c_hdr_len mod g_data_w), 1, 0)); --special case as the last hdr word can be < g_data_w.
- constant c_hdr_crc_word_lo : natural := sel_a_b((c_hdr_crc_bit_lo / g_data_w) > 0, c_hdr_crc_bit_lo / g_data_w,
+ constant c_hdr_crc_word_lo : natural := sel_a_b((c_hdr_crc_bit_lo / g_data_w) > 0, c_hdr_crc_bit_lo / g_data_w,
sel_a_b( c_hdr_crc_bit_lo > (c_hdr_len mod g_data_w), 1, 0)); --special case as the last hdr word can be < g_data_w.
-- calculate in which bit range of the selected word(s) the checksum should go.
@@ -86,9 +86,9 @@ begin
-- calculate checksum
checksum <= func_network_ip_header_checksum(g_hdr_field_arr, hdr_fields_slv_in) when rising_edge(clk);
-
+
-- register to know when crc has been inserted.
- reg_done <= nxt_reg_done when rising_edge(clk);
+ reg_done <= nxt_reg_done when rising_edge(clk);
---------------------------------------------------
-- process to insert checksum in outgoing stream --
@@ -121,7 +121,7 @@ begin
src_out <= dp_pipeline_src_out;
nxt_reg_done <= reg_done;
if reg_done = '0' and dp_pipeline_src_out.valid = '1' then
- if v_count = c_hdr_crc_word_hi then
+ if v_count = c_hdr_crc_word_hi then
src_out.data(c_crc_hi_bit_in_word downto 0) <= checksum(c_network_ip_header_checksum_w - 1 downto c_network_ip_header_checksum_w - c_crc_hi_bit_in_word - 1);
elsif v_count = c_hdr_crc_word_lo then
src_out.data(g_data_w - 1 downto c_crc_lo_bit_in_word) <= checksum(g_data_w - c_crc_lo_bit_in_word - 1 downto 0);
@@ -132,7 +132,7 @@ begin
src_out.data(g_data_w - 1 downto 0) <= checksum(v_hi downto v_lo);
end if;
end if;
-
+
if reg_done = '1' and dp_pipeline_src_out.eop = '1' then
nxt_reg_done <= '0';
end if;
diff --git a/libraries/io/eth/src/vhdl/eth_tester_tx.vhd b/libraries/io/eth/src/vhdl/eth_tester_tx.vhd
index 43d049dcd8..265db1b7e9 100644
--- a/libraries/io/eth/src/vhdl/eth_tester_tx.vhd
+++ b/libraries/io/eth/src/vhdl/eth_tester_tx.vhd
@@ -407,13 +407,13 @@ begin
port map (
rst => st_rst,
clk => st_clk,
-
+
snk_in => tx_offload_sosi,
- snk_out => tx_offload_siso,
-
+ snk_out => tx_offload_siso,
+
src_out => tx_offload_frame_sosi,
- src_in => tx_offload_frame_siso,
-
+ src_in => tx_offload_frame_siso,
+
hdr_fields_slv_in => hdr_fields_slv_tx
);
end generate;
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_ip_header_checksum.vhd b/libraries/io/eth/tb/vhdl/tb_eth_ip_header_checksum.vhd
index 58c8d41dfe..0f7ddc33da 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_ip_header_checksum.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_ip_header_checksum.vhd
@@ -270,7 +270,7 @@ architecture tb of tb_eth_ip_header_checksum is
X"214368AC", -- 23 = eth_dst_mac[31:0]
X"0000001B"); -- 24 = eth_dst_mac[47:32]
- -- Override ('1') only the Ethernet fields so we can use MM defaults there
+ -- Override ('1') only the Ethernet fields so we can use MM defaults there
constant c_hdr_field_ovr_init : std_logic_vector(c_udp_offload_nof_hdr_fields - 1 downto 0) := "101" & "111111111111" & "1111" & "100";
constant c_NODE_ID : std_logic_vector(7 downto 0) := TO_UVEC(0, 8);
@@ -521,7 +521,7 @@ begin
);
------------------------------------------------------------------------------
- -- DUT: IP header CRC checksum
+ -- DUT: IP header CRC checksum
------------------------------------------------------------------------------
u_dut : entity work.eth_ip_header_checksum
generic map (
@@ -529,14 +529,14 @@ begin
g_hdr_field_arr => c_udp_offload_hdr_field_arr
)
port map (
- rst => dp_rst,
- clk => dp_clk,
+ rst => dp_rst,
+ clk => dp_clk,
- src_out => link_offload_sosi_arr(0),
- snk_in => tx_offload_sosi_arr(0),
+ src_out => link_offload_sosi_arr(0),
+ snk_in => tx_offload_sosi_arr(0),
- src_in => link_offload_siso_arr(0),
- snk_out => tx_offload_siso_arr(0),
+ src_in => link_offload_siso_arr(0),
+ snk_out => tx_offload_siso_arr(0),
hdr_fields_slv_in => tx_hdr_fields_out_arr(0)
);
diff --git a/libraries/io/eth/tb/vhdl/tb_tb_eth_ip_header_checksum.vhd b/libraries/io/eth/tb/vhdl/tb_tb_eth_ip_header_checksum.vhd
index fe15112818..5193171673 100644
--- a/libraries/io/eth/tb/vhdl/tb_tb_eth_ip_header_checksum.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_tb_eth_ip_header_checksum.vhd
@@ -49,7 +49,7 @@ begin
-- g_pkt_gap : NATURAL := 16
u_pls_act_data_w_256 : entity work.tb_eth_ip_header_checksum generic map (e_pulse, e_active, false, 256, 64, 0, 240, 16);
- u_act_act_data_w_512_no_gap : entity work.tb_eth_ip_header_checksum generic map (e_active, e_active, false, 512, 8, 0, 240, 0);
+ u_act_act_data_w_512_no_gap : entity work.tb_eth_ip_header_checksum generic map (e_active, e_active, false, 512, 8, 0, 240, 0);
u_pls_act_data_w_64_no_gap : entity work.tb_eth_ip_header_checksum generic map (e_pulse, e_active, false, 64, 64, 0, 240, 0);
u_rnd_act_data_w_32 : entity work.tb_eth_ip_header_checksum generic map (e_random, e_active, false, 32, 8, 0, 240, 16);
u_rnd_act_data_w_8 : entity work.tb_eth_ip_header_checksum generic map (e_random, e_active, false, 8, 8, 0, 240, 16);
diff --git a/libraries/io/i2c/src/vhdl/i2c_smbus.vhd b/libraries/io/i2c/src/vhdl/i2c_smbus.vhd
index d6a3be33eb..2b6d0908c5 100644
--- a/libraries/io/i2c/src/vhdl/i2c_smbus.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_smbus.vhd
@@ -420,7 +420,7 @@ begin
else
i2c_start <= '1';
i2c_write <= '1';
- i2c_dat_in <= adr & '0' ;
+ i2c_dat_in <= adr & '0';
end if;
when OP_WR_ADR_RD =>
diff --git a/libraries/io/tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd b/libraries/io/tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd
index 007d637ff2..a2db82ef49 100644
--- a/libraries/io/tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd
+++ b/libraries/io/tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd
@@ -138,7 +138,7 @@ begin
begin
bn_clk_en <= '0';
if g_sim_level = 0 then
- wait for 1.6 ns ; -- with PHY use bn_tr_clk 1/4 cycle behind fn_tr_clk, with sim model the all tr_clk must have the same phase
+ wait for 1.6 ns; -- with PHY use bn_tr_clk 1/4 cycle behind fn_tr_clk, with sim model the all tr_clk must have the same phase
end if;
bn_clk_en <= '1';
wait;
diff --git a/libraries/technology/fifo/tech_fifo_component_pkg.vhd b/libraries/technology/fifo/tech_fifo_component_pkg.vhd
index 27b875cd8f..4c46bf4f7c 100644
--- a/libraries/technology/fifo/tech_fifo_component_pkg.vhd
+++ b/libraries/technology/fifo/tech_fifo_component_pkg.vhd
@@ -103,14 +103,14 @@ package tech_fifo_component_pkg is
g_nof_words : natural := 1024
);
port (
- aclr : in std_logic ;
- clock : in std_logic ;
+ aclr : in std_logic;
+ clock : in std_logic;
data : in std_logic_vector(g_dat_w - 1 downto 0);
- rdreq : in std_logic ;
- wrreq : in std_logic ;
- empty : out std_logic ;
- full : out std_logic ;
- q : out std_logic_vector(g_dat_w - 1 downto 0) ;
+ rdreq : in std_logic;
+ wrreq : in std_logic;
+ empty : out std_logic;
+ full : out std_logic;
+ q : out std_logic_vector(g_dat_w - 1 downto 0);
usedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end component;
@@ -124,14 +124,14 @@ package tech_fifo_component_pkg is
port (
aclr : in std_logic := '0';
data : in std_logic_vector(g_dat_w - 1 downto 0);
- rdclk : in std_logic ;
- rdreq : in std_logic ;
- wrclk : in std_logic ;
- wrreq : in std_logic ;
+ rdclk : in std_logic;
+ rdreq : in std_logic;
+ wrclk : in std_logic;
+ wrreq : in std_logic;
q : out std_logic_vector(g_dat_w - 1 downto 0);
- rdempty : out std_logic ;
+ rdempty : out std_logic;
rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0);
- wrfull : out std_logic ;
+ wrfull : out std_logic;
wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end component;
@@ -145,14 +145,14 @@ package tech_fifo_component_pkg is
port (
aclr : in std_logic := '0';
data : in std_logic_vector(g_wrdat_w - 1 downto 0);
- rdclk : in std_logic ;
- rdreq : in std_logic ;
- wrclk : in std_logic ;
- wrreq : in std_logic ;
+ rdclk : in std_logic;
+ rdreq : in std_logic;
+ wrclk : in std_logic;
+ wrreq : in std_logic;
q : out std_logic_vector(g_rddat_w - 1 downto 0);
- rdempty : out std_logic ;
+ rdempty : out std_logic;
rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words * g_wrdat_w / g_rddat_w) - 1 downto 0);
- wrfull : out std_logic ;
+ wrfull : out std_logic;
wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end component;
@@ -168,14 +168,14 @@ package tech_fifo_component_pkg is
g_nof_words : natural := 1024
);
port (
- aclr : in std_logic ;
- clock : in std_logic ;
+ aclr : in std_logic;
+ clock : in std_logic;
data : in std_logic_vector(g_dat_w - 1 downto 0);
- rdreq : in std_logic ;
- wrreq : in std_logic ;
- empty : out std_logic ;
- full : out std_logic ;
- q : out std_logic_vector(g_dat_w - 1 downto 0) ;
+ rdreq : in std_logic;
+ wrreq : in std_logic;
+ empty : out std_logic;
+ full : out std_logic;
+ q : out std_logic_vector(g_dat_w - 1 downto 0);
usedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end component;
@@ -189,14 +189,14 @@ package tech_fifo_component_pkg is
port (
aclr : in std_logic := '0';
data : in std_logic_vector(g_dat_w - 1 downto 0);
- rdclk : in std_logic ;
- rdreq : in std_logic ;
- wrclk : in std_logic ;
- wrreq : in std_logic ;
+ rdclk : in std_logic;
+ rdreq : in std_logic;
+ wrclk : in std_logic;
+ wrreq : in std_logic;
q : out std_logic_vector(g_dat_w - 1 downto 0);
- rdempty : out std_logic ;
+ rdempty : out std_logic;
rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0);
- wrfull : out std_logic ;
+ wrfull : out std_logic;
wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end component;
@@ -210,14 +210,14 @@ package tech_fifo_component_pkg is
port (
aclr : in std_logic := '0';
data : in std_logic_vector(g_wrdat_w - 1 downto 0);
- rdclk : in std_logic ;
- rdreq : in std_logic ;
- wrclk : in std_logic ;
- wrreq : in std_logic ;
+ rdclk : in std_logic;
+ rdreq : in std_logic;
+ wrclk : in std_logic;
+ wrreq : in std_logic;
q : out std_logic_vector(g_rddat_w - 1 downto 0);
- rdempty : out std_logic ;
+ rdempty : out std_logic;
rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words * g_wrdat_w / g_rddat_w) - 1 downto 0);
- wrfull : out std_logic ;
+ wrfull : out std_logic;
wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end component;
@@ -233,14 +233,14 @@ package tech_fifo_component_pkg is
g_nof_words : natural := 1024
);
port (
- aclr : in std_logic ;
- clock : in std_logic ;
+ aclr : in std_logic;
+ clock : in std_logic;
data : in std_logic_vector(g_dat_w - 1 downto 0);
- rdreq : in std_logic ;
- wrreq : in std_logic ;
- empty : out std_logic ;
- full : out std_logic ;
- q : out std_logic_vector(g_dat_w - 1 downto 0) ;
+ rdreq : in std_logic;
+ wrreq : in std_logic;
+ empty : out std_logic;
+ full : out std_logic;
+ q : out std_logic_vector(g_dat_w - 1 downto 0);
usedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end component;
@@ -254,14 +254,14 @@ package tech_fifo_component_pkg is
port (
aclr : in std_logic := '0';
data : in std_logic_vector(g_dat_w - 1 downto 0);
- rdclk : in std_logic ;
- rdreq : in std_logic ;
- wrclk : in std_logic ;
- wrreq : in std_logic ;
+ rdclk : in std_logic;
+ rdreq : in std_logic;
+ wrclk : in std_logic;
+ wrreq : in std_logic;
q : out std_logic_vector(g_dat_w - 1 downto 0);
- rdempty : out std_logic ;
+ rdempty : out std_logic;
rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0);
- wrfull : out std_logic ;
+ wrfull : out std_logic;
wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end component;
@@ -275,14 +275,14 @@ package tech_fifo_component_pkg is
port (
aclr : in std_logic := '0';
data : in std_logic_vector(g_wrdat_w - 1 downto 0);
- rdclk : in std_logic ;
- rdreq : in std_logic ;
- wrclk : in std_logic ;
- wrreq : in std_logic ;
+ rdclk : in std_logic;
+ rdreq : in std_logic;
+ wrclk : in std_logic;
+ wrreq : in std_logic;
q : out std_logic_vector(g_rddat_w - 1 downto 0);
- rdempty : out std_logic ;
+ rdempty : out std_logic;
rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words * g_wrdat_w / g_rddat_w) - 1 downto 0);
- wrfull : out std_logic ;
+ wrfull : out std_logic;
wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end component;
@@ -298,14 +298,14 @@ package tech_fifo_component_pkg is
g_nof_words : natural := 1024
);
port (
- aclr : in std_logic ;
- clock : in std_logic ;
+ aclr : in std_logic;
+ clock : in std_logic;
data : in std_logic_vector(g_dat_w - 1 downto 0);
- rdreq : in std_logic ;
- wrreq : in std_logic ;
- empty : out std_logic ;
- full : out std_logic ;
- q : out std_logic_vector(g_dat_w - 1 downto 0) ;
+ rdreq : in std_logic;
+ wrreq : in std_logic;
+ empty : out std_logic;
+ full : out std_logic;
+ q : out std_logic_vector(g_dat_w - 1 downto 0);
usedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end component;
@@ -319,14 +319,14 @@ package tech_fifo_component_pkg is
port (
aclr : in std_logic := '0';
data : in std_logic_vector(g_dat_w - 1 downto 0);
- rdclk : in std_logic ;
- rdreq : in std_logic ;
- wrclk : in std_logic ;
- wrreq : in std_logic ;
+ rdclk : in std_logic;
+ rdreq : in std_logic;
+ wrclk : in std_logic;
+ wrreq : in std_logic;
q : out std_logic_vector(g_dat_w - 1 downto 0);
- rdempty : out std_logic ;
+ rdempty : out std_logic;
rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0);
- wrfull : out std_logic ;
+ wrfull : out std_logic;
wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end component;
@@ -340,14 +340,14 @@ package tech_fifo_component_pkg is
port (
aclr : in std_logic := '0';
data : in std_logic_vector(g_wrdat_w - 1 downto 0);
- rdclk : in std_logic ;
- rdreq : in std_logic ;
- wrclk : in std_logic ;
- wrreq : in std_logic ;
+ rdclk : in std_logic;
+ rdreq : in std_logic;
+ wrclk : in std_logic;
+ wrreq : in std_logic;
q : out std_logic_vector(g_rddat_w - 1 downto 0);
- rdempty : out std_logic ;
+ rdempty : out std_logic;
rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words * g_wrdat_w / g_rddat_w) - 1 downto 0);
- wrfull : out std_logic ;
+ wrfull : out std_logic;
wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end component;
@@ -362,14 +362,14 @@ package tech_fifo_component_pkg is
g_nof_words : natural := 1024
);
port (
- aclr : in std_logic ;
- clock : in std_logic ;
+ aclr : in std_logic;
+ clock : in std_logic;
data : in std_logic_vector(g_dat_w - 1 downto 0);
- rdreq : in std_logic ;
- wrreq : in std_logic ;
- empty : out std_logic ;
- full : out std_logic ;
- q : out std_logic_vector(g_dat_w - 1 downto 0) ;
+ rdreq : in std_logic;
+ wrreq : in std_logic;
+ empty : out std_logic;
+ full : out std_logic;
+ q : out std_logic_vector(g_dat_w - 1 downto 0);
usedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end component;
@@ -382,14 +382,14 @@ package tech_fifo_component_pkg is
port (
aclr : in std_logic := '0';
data : in std_logic_vector(g_dat_w - 1 downto 0);
- rdclk : in std_logic ;
- rdreq : in std_logic ;
- wrclk : in std_logic ;
- wrreq : in std_logic ;
+ rdclk : in std_logic;
+ rdreq : in std_logic;
+ wrclk : in std_logic;
+ wrreq : in std_logic;
q : out std_logic_vector(g_dat_w - 1 downto 0);
- rdempty : out std_logic ;
+ rdempty : out std_logic;
rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0);
- wrfull : out std_logic ;
+ wrfull : out std_logic;
wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end component;
@@ -403,14 +403,14 @@ package tech_fifo_component_pkg is
port (
aclr : in std_logic := '0';
data : in std_logic_vector(g_wrdat_w - 1 downto 0);
- rdclk : in std_logic ;
- rdreq : in std_logic ;
- wrclk : in std_logic ;
- wrreq : in std_logic ;
+ rdclk : in std_logic;
+ rdreq : in std_logic;
+ wrclk : in std_logic;
+ wrreq : in std_logic;
q : out std_logic_vector(g_rddat_w - 1 downto 0);
- rdempty : out std_logic ;
+ rdempty : out std_logic;
rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words * g_wrdat_w / g_rddat_w) - 1 downto 0);
- wrfull : out std_logic ;
+ wrfull : out std_logic;
wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end component;
diff --git a/libraries/technology/flash/tech_flash_asmi_parallel.vhd b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
index 61e250d943..aa8214345c 100644
--- a/libraries/technology/flash/tech_flash_asmi_parallel.vhd
+++ b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
@@ -41,19 +41,19 @@ entity tech_flash_asmi_parallel is
);
port (
addr : in std_logic_vector(tech_flash_addr_w(g_technology) - 1 downto 0);
- clkin : in std_logic ;
+ clkin : in std_logic;
datain : in std_logic_vector(7 downto 0);
- rden : in std_logic ;
- read : in std_logic ;
- sector_erase : in std_logic ;
- shift_bytes : in std_logic ;
- wren : in std_logic ;
- write : in std_logic ;
- busy : out std_logic ;
- data_valid : out std_logic ;
+ rden : in std_logic;
+ read : in std_logic;
+ sector_erase : in std_logic;
+ shift_bytes : in std_logic;
+ wren : in std_logic;
+ write : in std_logic;
+ busy : out std_logic;
+ data_valid : out std_logic;
dataout : out std_logic_vector(7 downto 0);
- illegal_erase : out std_logic ;
- illegal_write : out std_logic ;
+ illegal_erase : out std_logic;
+ illegal_write : out std_logic;
reset : in std_logic := '0';
sce : in std_logic_vector(2 downto 0) := (others => '0');
en4b_addr : in std_logic := '0'
diff --git a/libraries/technology/flash/tech_flash_component_pkg.vhd b/libraries/technology/flash/tech_flash_component_pkg.vhd
index 73f80b086d..ebedb81c75 100644
--- a/libraries/technology/flash/tech_flash_component_pkg.vhd
+++ b/libraries/technology/flash/tech_flash_component_pkg.vhd
@@ -37,33 +37,33 @@ package tech_flash_component_pkg is
);
port (
addr : in std_logic_vector(23 downto 0);
- clkin : in std_logic ;
+ clkin : in std_logic;
datain : in std_logic_vector(7 downto 0);
- rden : in std_logic ;
- read : in std_logic ;
- sector_erase : in std_logic ;
- shift_bytes : in std_logic ;
- wren : in std_logic ;
- write : in std_logic ;
- busy : out std_logic ;
- data_valid : out std_logic ;
+ rden : in std_logic;
+ read : in std_logic;
+ sector_erase : in std_logic;
+ shift_bytes : in std_logic;
+ wren : in std_logic;
+ write : in std_logic;
+ busy : out std_logic;
+ data_valid : out std_logic;
dataout : out std_logic_vector(7 downto 0);
- illegal_erase : out std_logic ;
+ illegal_erase : out std_logic;
illegal_write : out std_logic
);
end component;
component ip_stratixiv_remote_update is
port (
- clock : in std_logic ;
+ clock : in std_logic;
data_in : in std_logic_vector(23 downto 0);
param : in std_logic_vector(2 downto 0);
- read_param : in std_logic ;
- reconfig : in std_logic ;
- reset : in std_logic ;
- reset_timer : in std_logic ;
- write_param : in std_logic ;
- busy : out std_logic ;
+ read_param : in std_logic;
+ reconfig : in std_logic;
+ reset : in std_logic;
+ reset_timer : in std_logic;
+ write_param : in std_logic;
+ busy : out std_logic;
data_out : out std_logic_vector(23 downto 0)
);
end component;
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
index ebbcfee8b4..b88b4653d2 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
@@ -38,10 +38,10 @@ entity tech_fractional_pll_clk125 is
port (
areset : in std_logic := '0';
inclk0 : in std_logic := '0'; -- 125 MHz
- c0 : out std_logic ; -- 20 MHz
- c1 : out std_logic ; -- 50 MHz
- c2 : out std_logic ; -- 100 MHz
- c3 : out std_logic ; -- 125 MHz
+ c0 : out std_logic; -- 20 MHz
+ c1 : out std_logic; -- 50 MHz
+ c2 : out std_logic; -- 100 MHz
+ c3 : out std_logic; -- 125 MHz
locked : out std_logic
);
end tech_fractional_pll_clk125;
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
index 9aa1d74f84..5b69f99ecd 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
@@ -38,9 +38,9 @@ entity tech_fractional_pll_clk200 is
port (
areset : in std_logic := '0';
inclk0 : in std_logic := '0'; -- 200 MHz
- c0 : out std_logic ; -- 200 MHz
- c1 : out std_logic ; -- 200 MHz shifted 90 degrees
- c2 : out std_logic ; -- 400 MHz
+ c0 : out std_logic; -- 200 MHz
+ c1 : out std_logic; -- 200 MHz shifted 90 degrees
+ c2 : out std_logic; -- 400 MHz
locked : out std_logic
);
end tech_fractional_pll_clk200;
diff --git a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc.vhd b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc.vhd
index 185c63eaea..9122cd0333 100644
--- a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc.vhd
+++ b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc.vhd
@@ -41,14 +41,14 @@ entity ip_arria10_fifo_dc is
port (
aclr : in std_logic := '0';
data : in std_logic_vector(g_dat_w - 1 downto 0);
- rdclk : in std_logic ;
- rdreq : in std_logic ;
- wrclk : in std_logic ;
- wrreq : in std_logic ;
+ rdclk : in std_logic;
+ rdreq : in std_logic;
+ wrclk : in std_logic;
+ wrreq : in std_logic;
q : out std_logic_vector(g_dat_w - 1 downto 0);
- rdempty : out std_logic ;
+ rdempty : out std_logic;
rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0);
- wrfull : out std_logic ;
+ wrfull : out std_logic;
wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end ip_arria10_fifo_dc;
diff --git a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc_mixed_widths.vhd b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc_mixed_widths.vhd
index c1fb41b79c..ef461ee1e1 100644
--- a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc_mixed_widths.vhd
@@ -41,14 +41,14 @@ entity ip_arria10_fifo_dc_mixed_widths is
port (
aclr : in std_logic := '0';
data : in std_logic_vector(g_wrdat_w - 1 downto 0);
- rdclk : in std_logic ;
- rdreq : in std_logic ;
- wrclk : in std_logic ;
- wrreq : in std_logic ;
+ rdclk : in std_logic;
+ rdreq : in std_logic;
+ wrclk : in std_logic;
+ wrreq : in std_logic;
q : out std_logic_vector(g_rddat_w - 1 downto 0);
- rdempty : out std_logic ;
+ rdempty : out std_logic;
rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words * g_wrdat_w / g_rddat_w) - 1 downto 0);
- wrfull : out std_logic ;
+ wrfull : out std_logic;
wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end ip_arria10_fifo_dc_mixed_widths;
diff --git a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_sc.vhd b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_sc.vhd
index a35839805e..8cce1d7ec7 100644
--- a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_sc.vhd
+++ b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_sc.vhd
@@ -39,14 +39,14 @@ entity ip_arria10_fifo_sc is
g_nof_words : natural := 1024
);
port (
- aclr : in std_logic ;
- clock : in std_logic ;
+ aclr : in std_logic;
+ clock : in std_logic;
data : in std_logic_vector(g_dat_w - 1 downto 0);
- rdreq : in std_logic ;
- wrreq : in std_logic ;
- empty : out std_logic ;
- full : out std_logic ;
- q : out std_logic_vector(g_dat_w - 1 downto 0) ;
+ rdreq : in std_logic;
+ wrreq : in std_logic;
+ empty : out std_logic;
+ full : out std_logic;
+ q : out std_logic_vector(g_dat_w - 1 downto 0);
usedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end ip_arria10_fifo_sc;
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd b/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd
index d52451712a..bab5e8d17f 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd
@@ -42,7 +42,7 @@ entity ip_arria10_ram_cr_cw is
(
data : in std_logic_vector(g_dat_w - 1 downto 0);
rdaddress : in std_logic_vector(g_adr_w - 1 downto 0);
- rdclk : in std_logic ;
+ rdclk : in std_logic;
wraddress : in std_logic_vector(g_adr_w - 1 downto 0);
wrclk : in std_logic := '1';
wren : in std_logic := '0';
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.vhd b/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.vhd
index aff4502d6b..a101a09dbf 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.vhd
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.vhd
@@ -43,7 +43,7 @@ entity ip_arria10_ram_crw_crw is
address_a : in std_logic_vector(g_adr_w - 1 downto 0);
address_b : in std_logic_vector(g_adr_w - 1 downto 0);
clk_a : in std_logic := '1';
- clk_b : in std_logic ;
+ clk_b : in std_logic;
data_a : in std_logic_vector(g_dat_w - 1 downto 0);
data_b : in std_logic_vector(g_dat_w - 1 downto 0);
wren_a : in std_logic := '0';
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_ram_crwk_crw.vhd b/libraries/technology/ip_arria10/ram/ip_arria10_ram_crwk_crw.vhd
index 921a67c881..ec4a9e6a1b 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_ram_crwk_crw.vhd
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_ram_crwk_crw.vhd
@@ -34,7 +34,7 @@ entity ip_arria10_ram_crwk_crw is
address_a : in std_logic_vector(g_adr_a_w - 1 downto 0);
address_b : in std_logic_vector(g_adr_b_w - 1 downto 0);
clk_a : in std_logic := '1';
- clk_b : in std_logic ;
+ clk_b : in std_logic;
data_a : in std_logic_vector(g_dat_a_w - 1 downto 0);
data_b : in std_logic_vector(g_dat_b_w - 1 downto 0);
wren_a : in std_logic := '0';
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc.vhd b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc.vhd
index b51643da4f..2a91090a95 100644
--- a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc.vhd
+++ b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc.vhd
@@ -41,14 +41,14 @@ entity ip_arria10_e1sg_fifo_dc is
port (
aclr : in std_logic := '0';
data : in std_logic_vector(g_dat_w - 1 downto 0);
- rdclk : in std_logic ;
- rdreq : in std_logic ;
- wrclk : in std_logic ;
- wrreq : in std_logic ;
+ rdclk : in std_logic;
+ rdreq : in std_logic;
+ wrclk : in std_logic;
+ wrreq : in std_logic;
q : out std_logic_vector(g_dat_w - 1 downto 0);
- rdempty : out std_logic ;
+ rdempty : out std_logic;
rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0);
- wrfull : out std_logic ;
+ wrfull : out std_logic;
wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end ip_arria10_e1sg_fifo_dc;
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc_mixed_widths.vhd b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc_mixed_widths.vhd
index c616af4aad..b5ff1184fd 100644
--- a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc_mixed_widths.vhd
@@ -41,14 +41,14 @@ entity ip_arria10_e1sg_fifo_dc_mixed_widths is
port (
aclr : in std_logic := '0';
data : in std_logic_vector(g_wrdat_w - 1 downto 0);
- rdclk : in std_logic ;
- rdreq : in std_logic ;
- wrclk : in std_logic ;
- wrreq : in std_logic ;
+ rdclk : in std_logic;
+ rdreq : in std_logic;
+ wrclk : in std_logic;
+ wrreq : in std_logic;
q : out std_logic_vector(g_rddat_w - 1 downto 0);
- rdempty : out std_logic ;
+ rdempty : out std_logic;
rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words * g_wrdat_w / g_rddat_w) - 1 downto 0);
- wrfull : out std_logic ;
+ wrfull : out std_logic;
wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end ip_arria10_e1sg_fifo_dc_mixed_widths;
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_sc.vhd b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_sc.vhd
index 2b9f9562c7..79fd98df70 100644
--- a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_sc.vhd
+++ b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_sc.vhd
@@ -39,14 +39,14 @@ entity ip_arria10_e1sg_fifo_sc is
g_nof_words : natural := 1024
);
port (
- aclr : in std_logic ;
- clock : in std_logic ;
+ aclr : in std_logic;
+ clock : in std_logic;
data : in std_logic_vector(g_dat_w - 1 downto 0);
- rdreq : in std_logic ;
- wrreq : in std_logic ;
- empty : out std_logic ;
- full : out std_logic ;
- q : out std_logic_vector(g_dat_w - 1 downto 0) ;
+ rdreq : in std_logic;
+ wrreq : in std_logic;
+ empty : out std_logic;
+ full : out std_logic;
+ q : out std_logic_vector(g_dat_w - 1 downto 0);
usedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end ip_arria10_e1sg_fifo_sc;
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.vhd
index 7ebebc0d6c..dd02bff6f8 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.vhd
@@ -42,7 +42,7 @@ entity ip_arria10_e1sg_ram_cr_cw is
(
data : in std_logic_vector(g_dat_w - 1 downto 0);
rdaddress : in std_logic_vector(g_adr_w - 1 downto 0);
- rdclk : in std_logic ;
+ rdclk : in std_logic;
wraddress : in std_logic_vector(g_adr_w - 1 downto 0);
wrclk : in std_logic := '1';
wren : in std_logic := '0';
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.vhd
index ffcb8cfb22..f1ee7e7f67 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.vhd
@@ -43,7 +43,7 @@ entity ip_arria10_e1sg_ram_crw_crw is
address_a : in std_logic_vector(g_adr_w - 1 downto 0);
address_b : in std_logic_vector(g_adr_w - 1 downto 0);
clk_a : in std_logic := '1';
- clk_b : in std_logic ;
+ clk_b : in std_logic;
data_a : in std_logic_vector(g_dat_w - 1 downto 0);
data_b : in std_logic_vector(g_dat_w - 1 downto 0);
wren_a : in std_logic := '0';
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.vhd
index 56da39e2ee..76e942f71d 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.vhd
@@ -34,7 +34,7 @@ entity ip_arria10_e1sg_ram_crwk_crw is
address_a : in std_logic_vector(g_adr_a_w - 1 downto 0);
address_b : in std_logic_vector(g_adr_b_w - 1 downto 0);
clk_a : in std_logic := '1';
- clk_b : in std_logic ;
+ clk_b : in std_logic;
data_a : in std_logic_vector(g_dat_a_w - 1 downto 0);
data_b : in std_logic_vector(g_dat_b_w - 1 downto 0);
wren_a : in std_logic := '0';
diff --git a/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc.vhd b/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc.vhd
index 3fbe2d25a8..887841ab6d 100644
--- a/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc.vhd
+++ b/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc.vhd
@@ -41,14 +41,14 @@ entity ip_arria10_e2sg_fifo_dc is
port (
aclr : in std_logic := '0';
data : in std_logic_vector(g_dat_w - 1 downto 0);
- rdclk : in std_logic ;
- rdreq : in std_logic ;
- wrclk : in std_logic ;
- wrreq : in std_logic ;
+ rdclk : in std_logic;
+ rdreq : in std_logic;
+ wrclk : in std_logic;
+ wrreq : in std_logic;
q : out std_logic_vector(g_dat_w - 1 downto 0);
- rdempty : out std_logic ;
+ rdempty : out std_logic;
rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0);
- wrfull : out std_logic ;
+ wrfull : out std_logic;
wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end ip_arria10_e2sg_fifo_dc;
diff --git a/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc_mixed_widths.vhd b/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc_mixed_widths.vhd
index 0f22e32d2a..49fbe8a0b6 100644
--- a/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc_mixed_widths.vhd
@@ -41,14 +41,14 @@ entity ip_arria10_e2sg_fifo_dc_mixed_widths is
port (
aclr : in std_logic := '0';
data : in std_logic_vector(g_wrdat_w - 1 downto 0);
- rdclk : in std_logic ;
- rdreq : in std_logic ;
- wrclk : in std_logic ;
- wrreq : in std_logic ;
+ rdclk : in std_logic;
+ rdreq : in std_logic;
+ wrclk : in std_logic;
+ wrreq : in std_logic;
q : out std_logic_vector(g_rddat_w - 1 downto 0);
- rdempty : out std_logic ;
+ rdempty : out std_logic;
rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words * g_wrdat_w / g_rddat_w) - 1 downto 0);
- wrfull : out std_logic ;
+ wrfull : out std_logic;
wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end ip_arria10_e2sg_fifo_dc_mixed_widths;
diff --git a/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_sc.vhd b/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_sc.vhd
index 078217dd5f..f5dffa5e60 100644
--- a/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_sc.vhd
+++ b/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_sc.vhd
@@ -39,14 +39,14 @@ entity ip_arria10_e2sg_fifo_sc is
g_nof_words : natural := 1024
);
port (
- aclr : in std_logic ;
- clock : in std_logic ;
+ aclr : in std_logic;
+ clock : in std_logic;
data : in std_logic_vector(g_dat_w - 1 downto 0);
- rdreq : in std_logic ;
- wrreq : in std_logic ;
- empty : out std_logic ;
- full : out std_logic ;
- q : out std_logic_vector(g_dat_w - 1 downto 0) ;
+ rdreq : in std_logic;
+ wrreq : in std_logic;
+ empty : out std_logic;
+ full : out std_logic;
+ q : out std_logic_vector(g_dat_w - 1 downto 0);
usedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end ip_arria10_e2sg_fifo_sc;
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_cr_cw.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_cr_cw.vhd
index c59b73a969..3c87928c11 100644
--- a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_cr_cw.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_cr_cw.vhd
@@ -42,7 +42,7 @@ entity ip_arria10_e2sg_ram_cr_cw is
(
data : in std_logic_vector(g_dat_w - 1 downto 0);
rdaddress : in std_logic_vector(g_adr_w - 1 downto 0);
- rdclk : in std_logic ;
+ rdclk : in std_logic;
wraddress : in std_logic_vector(g_adr_w - 1 downto 0);
wrclk : in std_logic := '1';
wren : in std_logic := '0';
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.vhd
index 36d9eebd4f..e1fcb23652 100644
--- a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.vhd
@@ -43,7 +43,7 @@ entity ip_arria10_e2sg_ram_crw_crw is
address_a : in std_logic_vector(g_adr_w - 1 downto 0);
address_b : in std_logic_vector(g_adr_w - 1 downto 0);
clk_a : in std_logic := '1';
- clk_b : in std_logic ;
+ clk_b : in std_logic;
data_a : in std_logic_vector(g_dat_w - 1 downto 0);
data_b : in std_logic_vector(g_dat_w - 1 downto 0);
wren_a : in std_logic := '0';
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crwk_crw.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crwk_crw.vhd
index ad121c31b4..26326f34b0 100644
--- a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crwk_crw.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crwk_crw.vhd
@@ -34,7 +34,7 @@ entity ip_arria10_e2sg_ram_crwk_crw is
address_a : in std_logic_vector(g_adr_a_w - 1 downto 0);
address_b : in std_logic_vector(g_adr_b_w - 1 downto 0);
clk_a : in std_logic := '1';
- clk_b : in std_logic ;
+ clk_b : in std_logic;
data_a : in std_logic_vector(g_dat_a_w - 1 downto 0);
data_b : in std_logic_vector(g_dat_b_w - 1 downto 0);
wren_a : in std_logic := '0';
diff --git a/libraries/technology/ip_arria10_e3sge3/fifo/ip_arria10_e3sge3_fifo_dc.vhd b/libraries/technology/ip_arria10_e3sge3/fifo/ip_arria10_e3sge3_fifo_dc.vhd
index 4a4710ad4a..7231923dd6 100644
--- a/libraries/technology/ip_arria10_e3sge3/fifo/ip_arria10_e3sge3_fifo_dc.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/fifo/ip_arria10_e3sge3_fifo_dc.vhd
@@ -41,14 +41,14 @@ entity ip_arria10_e3sge3_fifo_dc is
port (
aclr : in std_logic := '0';
data : in std_logic_vector(g_dat_w - 1 downto 0);
- rdclk : in std_logic ;
- rdreq : in std_logic ;
- wrclk : in std_logic ;
- wrreq : in std_logic ;
+ rdclk : in std_logic;
+ rdreq : in std_logic;
+ wrclk : in std_logic;
+ wrreq : in std_logic;
q : out std_logic_vector(g_dat_w - 1 downto 0);
- rdempty : out std_logic ;
+ rdempty : out std_logic;
rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0);
- wrfull : out std_logic ;
+ wrfull : out std_logic;
wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end ip_arria10_e3sge3_fifo_dc;
diff --git a/libraries/technology/ip_arria10_e3sge3/fifo/ip_arria10_e3sge3_fifo_dc_mixed_widths.vhd b/libraries/technology/ip_arria10_e3sge3/fifo/ip_arria10_e3sge3_fifo_dc_mixed_widths.vhd
index 4e30a8c81a..8eaf5ceb56 100644
--- a/libraries/technology/ip_arria10_e3sge3/fifo/ip_arria10_e3sge3_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/fifo/ip_arria10_e3sge3_fifo_dc_mixed_widths.vhd
@@ -41,14 +41,14 @@ entity ip_arria10_e3sge3_fifo_dc_mixed_widths is
port (
aclr : in std_logic := '0';
data : in std_logic_vector(g_wrdat_w - 1 downto 0);
- rdclk : in std_logic ;
- rdreq : in std_logic ;
- wrclk : in std_logic ;
- wrreq : in std_logic ;
+ rdclk : in std_logic;
+ rdreq : in std_logic;
+ wrclk : in std_logic;
+ wrreq : in std_logic;
q : out std_logic_vector(g_rddat_w - 1 downto 0);
- rdempty : out std_logic ;
+ rdempty : out std_logic;
rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words * g_wrdat_w / g_rddat_w) - 1 downto 0);
- wrfull : out std_logic ;
+ wrfull : out std_logic;
wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end ip_arria10_e3sge3_fifo_dc_mixed_widths;
diff --git a/libraries/technology/ip_arria10_e3sge3/fifo/ip_arria10_e3sge3_fifo_sc.vhd b/libraries/technology/ip_arria10_e3sge3/fifo/ip_arria10_e3sge3_fifo_sc.vhd
index 69173e5b42..4e233325fe 100644
--- a/libraries/technology/ip_arria10_e3sge3/fifo/ip_arria10_e3sge3_fifo_sc.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/fifo/ip_arria10_e3sge3_fifo_sc.vhd
@@ -39,14 +39,14 @@ entity ip_arria10_e3sge3_fifo_sc is
g_nof_words : natural := 1024
);
port (
- aclr : in std_logic ;
- clock : in std_logic ;
+ aclr : in std_logic;
+ clock : in std_logic;
data : in std_logic_vector(g_dat_w - 1 downto 0);
- rdreq : in std_logic ;
- wrreq : in std_logic ;
- empty : out std_logic ;
- full : out std_logic ;
- q : out std_logic_vector(g_dat_w - 1 downto 0) ;
+ rdreq : in std_logic;
+ wrreq : in std_logic;
+ empty : out std_logic;
+ full : out std_logic;
+ q : out std_logic_vector(g_dat_w - 1 downto 0);
usedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end ip_arria10_e3sge3_fifo_sc;
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_cr_cw.vhd b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_cr_cw.vhd
index b688b46615..51682fa2f8 100644
--- a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_cr_cw.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_cr_cw.vhd
@@ -42,7 +42,7 @@ entity ip_arria10_e3sge3_ram_cr_cw is
(
data : in std_logic_vector(g_dat_w - 1 downto 0);
rdaddress : in std_logic_vector(g_adr_w - 1 downto 0);
- rdclk : in std_logic ;
+ rdclk : in std_logic;
wraddress : in std_logic_vector(g_adr_w - 1 downto 0);
wrclk : in std_logic := '1';
wren : in std_logic := '0';
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crw_crw.vhd b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crw_crw.vhd
index bcd5864593..013e8f634c 100644
--- a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crw_crw.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crw_crw.vhd
@@ -43,7 +43,7 @@ entity ip_arria10_e3sge3_ram_crw_crw is
address_a : in std_logic_vector(g_adr_w - 1 downto 0);
address_b : in std_logic_vector(g_adr_w - 1 downto 0);
clk_a : in std_logic := '1';
- clk_b : in std_logic ;
+ clk_b : in std_logic;
data_a : in std_logic_vector(g_dat_w - 1 downto 0);
data_b : in std_logic_vector(g_dat_w - 1 downto 0);
wren_a : in std_logic := '0';
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crwk_crw.vhd b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crwk_crw.vhd
index 184c263210..c9f32b64aa 100644
--- a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crwk_crw.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crwk_crw.vhd
@@ -34,7 +34,7 @@ entity ip_arria10_e3sge3_ram_crwk_crw is
address_a : in std_logic_vector(g_adr_a_w - 1 downto 0);
address_b : in std_logic_vector(g_adr_b_w - 1 downto 0);
clk_a : in std_logic := '1';
- clk_b : in std_logic ;
+ clk_b : in std_logic;
data_a : in std_logic_vector(g_dat_a_w - 1 downto 0);
data_b : in std_logic_vector(g_dat_b_w - 1 downto 0);
wren_a : in std_logic := '0';
diff --git a/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_dc.vhd b/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_dc.vhd
index bf1f8336e2..4ce755cacd 100644
--- a/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_dc.vhd
+++ b/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_dc.vhd
@@ -38,14 +38,14 @@ entity ip_ultrascale_fifo_dc is
port (
aclr : in std_logic := '0';
data : in std_logic_vector(g_dat_w - 1 downto 0);
- rdclk : in std_logic ;
- rdreq : in std_logic ;
- wrclk : in std_logic ;
- wrreq : in std_logic ;
+ rdclk : in std_logic;
+ rdreq : in std_logic;
+ wrclk : in std_logic;
+ wrreq : in std_logic;
q : out std_logic_vector(g_dat_w - 1 downto 0);
- rdempty : out std_logic ;
+ rdempty : out std_logic;
rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0);
- wrfull : out std_logic ;
+ wrfull : out std_logic;
wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end ip_ultrascale_fifo_dc;
diff --git a/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_dc_mixed_widths.vhd b/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_dc_mixed_widths.vhd
index aeceea9c34..bb3116ad98 100644
--- a/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_dc_mixed_widths.vhd
@@ -39,14 +39,14 @@ entity ip_ultrascale_fifo_dc_mixed_widths is
port (
aclr : in std_logic := '0';
data : in std_logic_vector(g_wrdat_w - 1 downto 0);
- rdclk : in std_logic ;
- rdreq : in std_logic ;
- wrclk : in std_logic ;
- wrreq : in std_logic ;
+ rdclk : in std_logic;
+ rdreq : in std_logic;
+ wrclk : in std_logic;
+ wrreq : in std_logic;
q : out std_logic_vector(g_rddat_w - 1 downto 0);
- rdempty : out std_logic ;
+ rdempty : out std_logic;
rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words * g_wrdat_w / g_rddat_w) - 1 downto 0);
- wrfull : out std_logic ;
+ wrfull : out std_logic;
wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end ip_ultrascale_fifo_dc_mixed_widths;
diff --git a/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_sc.vhd b/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_sc.vhd
index 5480175cca..5dc9078227 100644
--- a/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_sc.vhd
+++ b/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_sc.vhd
@@ -36,14 +36,14 @@ entity ip_ultrascale_fifo_sc is
g_nof_words : natural := 1024
);
port (
- aclr : in std_logic ;
- clock : in std_logic ;
+ aclr : in std_logic;
+ clock : in std_logic;
data : in std_logic_vector(g_dat_w - 1 downto 0);
- rdreq : in std_logic ;
- wrreq : in std_logic ;
- empty : out std_logic ;
- full : out std_logic ;
- q : out std_logic_vector(g_dat_w - 1 downto 0) ;
+ rdreq : in std_logic;
+ wrreq : in std_logic;
+ empty : out std_logic;
+ full : out std_logic;
+ q : out std_logic_vector(g_dat_w - 1 downto 0);
usedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end ip_ultrascale_fifo_sc;
diff --git a/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd b/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd
index 10697d372c..76a9db04b2 100644
--- a/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd
+++ b/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd
@@ -41,7 +41,7 @@ entity ip_ultrascale_ram_cr_cw is
(
data : in std_logic_vector(g_dat_w - 1 downto 0);
rdaddress : in std_logic_vector(g_adr_w - 1 downto 0);
- rdclk : in std_logic ;
+ rdclk : in std_logic;
wraddress : in std_logic_vector(g_adr_w - 1 downto 0);
wrclk : in std_logic := '1';
wren : in std_logic := '0';
diff --git a/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_crw_crw.vhd b/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_crw_crw.vhd
index f80e90e2e6..f1cbab189c 100644
--- a/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_crw_crw.vhd
+++ b/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_crw_crw.vhd
@@ -42,7 +42,7 @@ entity ip_ultrascale_ram_crw_crw is
address_a : in std_logic_vector(g_adr_w - 1 downto 0);
address_b : in std_logic_vector(g_adr_w - 1 downto 0);
clk_a : in std_logic := '1';
- clk_b : in std_logic ;
+ clk_b : in std_logic;
data_a : in std_logic_vector(g_dat_w - 1 downto 0);
data_b : in std_logic_vector(g_dat_w - 1 downto 0);
wren_a : in std_logic := '0';
diff --git a/libraries/technology/jesd204b/tb_tech_jesd204b.vhd b/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
index 10698a5902..a9c7b306ee 100644
--- a/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
+++ b/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
@@ -78,7 +78,7 @@ architecture tb of tb_tech_jesd204b is
5000 ps,
5000 ps,
5000 ps,
- 5000 ps) ; -- transport delays tx to rx data
+ 5000 ps); -- transport delays tx to rx data
constant c_delay_sysreftoadc_arr : t_time_arr := (4000 ps,
5000 ps,
6000 ps,
@@ -90,7 +90,7 @@ architecture tb of tb_tech_jesd204b is
1000 ps,
1000 ps,
1000 ps,
- 1000 ps) ; -- transport delays clock source to adc(tx)
+ 1000 ps); -- transport delays clock source to adc(tx)
constant c_delay_sysreftofpga : time := 10200 ps;
-- clocks and resets for the jesd204b tx
diff --git a/libraries/technology/memory/tech_memory_component_pkg.vhd b/libraries/technology/memory/tech_memory_component_pkg.vhd
index 7fd446d98c..15a6bcc7e4 100644
--- a/libraries/technology/memory/tech_memory_component_pkg.vhd
+++ b/libraries/technology/memory/tech_memory_component_pkg.vhd
@@ -45,7 +45,7 @@ package tech_memory_component_pkg is
address_a : in std_logic_vector(g_adr_a_w - 1 downto 0);
address_b : in std_logic_vector(g_adr_b_w - 1 downto 0);
clock_a : in std_logic := '1';
- clock_b : in std_logic ;
+ clock_b : in std_logic;
data_a : in std_logic_vector(g_dat_a_w - 1 downto 0);
data_b : in std_logic_vector(g_dat_b_w - 1 downto 0);
enable_a : in std_logic := '1';
@@ -71,7 +71,7 @@ package tech_memory_component_pkg is
address_a : in std_logic_vector(g_adr_w - 1 downto 0);
address_b : in std_logic_vector(g_adr_w - 1 downto 0);
clock_a : in std_logic := '1';
- clock_b : in std_logic ;
+ clock_b : in std_logic;
data_a : in std_logic_vector(g_dat_w - 1 downto 0);
data_b : in std_logic_vector(g_dat_w - 1 downto 0);
enable_a : in std_logic := '1';
@@ -96,7 +96,7 @@ package tech_memory_component_pkg is
port (
data : in std_logic_vector(g_dat_w - 1 downto 0);
rdaddress : in std_logic_vector(g_adr_w - 1 downto 0);
- rdclock : in std_logic ;
+ rdclock : in std_logic;
rdclocken : in std_logic := '1';
wraddress : in std_logic_vector(g_adr_w - 1 downto 0);
wrclock : in std_logic := '1';
@@ -160,7 +160,7 @@ package tech_memory_component_pkg is
address_a : in std_logic_vector(g_adr_a_w - 1 downto 0);
address_b : in std_logic_vector(g_adr_b_w - 1 downto 0);
clk_a : in std_logic := '1';
- clk_b : in std_logic ;
+ clk_b : in std_logic;
data_a : in std_logic_vector(g_dat_a_w - 1 downto 0);
data_b : in std_logic_vector(g_dat_b_w - 1 downto 0);
wren_a : in std_logic := '0';
@@ -184,7 +184,7 @@ package tech_memory_component_pkg is
address_a : in std_logic_vector(g_adr_w - 1 downto 0);
address_b : in std_logic_vector(g_adr_w - 1 downto 0);
clk_a : in std_logic := '1';
- clk_b : in std_logic ;
+ clk_b : in std_logic;
data_a : in std_logic_vector(g_dat_w - 1 downto 0);
data_b : in std_logic_vector(g_dat_w - 1 downto 0);
wren_a : in std_logic := '0';
@@ -207,7 +207,7 @@ package tech_memory_component_pkg is
(
data : in std_logic_vector(g_dat_w - 1 downto 0);
rdaddress : in std_logic_vector(g_adr_w - 1 downto 0);
- rdclk : in std_logic ;
+ rdclk : in std_logic;
wraddress : in std_logic_vector(g_adr_w - 1 downto 0);
wrclk : in std_logic := '1';
wren : in std_logic := '0';
@@ -254,7 +254,7 @@ package tech_memory_component_pkg is
address_a : in std_logic_vector(g_adr_a_w - 1 downto 0);
address_b : in std_logic_vector(g_adr_b_w - 1 downto 0);
clk_a : in std_logic := '1';
- clk_b : in std_logic ;
+ clk_b : in std_logic;
data_a : in std_logic_vector(g_dat_a_w - 1 downto 0);
data_b : in std_logic_vector(g_dat_b_w - 1 downto 0);
wren_a : in std_logic := '0';
@@ -278,7 +278,7 @@ package tech_memory_component_pkg is
address_a : in std_logic_vector(g_adr_w - 1 downto 0);
address_b : in std_logic_vector(g_adr_w - 1 downto 0);
clk_a : in std_logic := '1';
- clk_b : in std_logic ;
+ clk_b : in std_logic;
data_a : in std_logic_vector(g_dat_w - 1 downto 0);
data_b : in std_logic_vector(g_dat_w - 1 downto 0);
wren_a : in std_logic := '0';
@@ -301,7 +301,7 @@ package tech_memory_component_pkg is
(
data : in std_logic_vector(g_dat_w - 1 downto 0);
rdaddress : in std_logic_vector(g_adr_w - 1 downto 0);
- rdclk : in std_logic ;
+ rdclk : in std_logic;
wraddress : in std_logic_vector(g_adr_w - 1 downto 0);
wrclk : in std_logic := '1';
wren : in std_logic := '0';
@@ -348,7 +348,7 @@ package tech_memory_component_pkg is
address_a : in std_logic_vector(g_adr_a_w - 1 downto 0);
address_b : in std_logic_vector(g_adr_b_w - 1 downto 0);
clk_a : in std_logic := '1';
- clk_b : in std_logic ;
+ clk_b : in std_logic;
data_a : in std_logic_vector(g_dat_a_w - 1 downto 0);
data_b : in std_logic_vector(g_dat_b_w - 1 downto 0);
wren_a : in std_logic := '0';
@@ -372,7 +372,7 @@ package tech_memory_component_pkg is
address_a : in std_logic_vector(g_adr_w - 1 downto 0);
address_b : in std_logic_vector(g_adr_w - 1 downto 0);
clk_a : in std_logic := '1';
- clk_b : in std_logic ;
+ clk_b : in std_logic;
data_a : in std_logic_vector(g_dat_w - 1 downto 0);
data_b : in std_logic_vector(g_dat_w - 1 downto 0);
wren_a : in std_logic := '0';
@@ -395,7 +395,7 @@ package tech_memory_component_pkg is
(
data : in std_logic_vector(g_dat_w - 1 downto 0);
rdaddress : in std_logic_vector(g_adr_w - 1 downto 0);
- rdclk : in std_logic ;
+ rdclk : in std_logic;
wraddress : in std_logic_vector(g_adr_w - 1 downto 0);
wrclk : in std_logic := '1';
wren : in std_logic := '0';
@@ -442,7 +442,7 @@ package tech_memory_component_pkg is
address_a : in std_logic_vector(g_adr_a_w - 1 downto 0);
address_b : in std_logic_vector(g_adr_b_w - 1 downto 0);
clk_a : in std_logic := '1';
- clk_b : in std_logic ;
+ clk_b : in std_logic;
data_a : in std_logic_vector(g_dat_a_w - 1 downto 0);
data_b : in std_logic_vector(g_dat_b_w - 1 downto 0);
wren_a : in std_logic := '0';
@@ -466,7 +466,7 @@ package tech_memory_component_pkg is
address_a : in std_logic_vector(g_adr_w - 1 downto 0);
address_b : in std_logic_vector(g_adr_w - 1 downto 0);
clk_a : in std_logic := '1';
- clk_b : in std_logic ;
+ clk_b : in std_logic;
data_a : in std_logic_vector(g_dat_w - 1 downto 0);
data_b : in std_logic_vector(g_dat_w - 1 downto 0);
wren_a : in std_logic := '0';
@@ -489,7 +489,7 @@ package tech_memory_component_pkg is
(
data : in std_logic_vector(g_dat_w - 1 downto 0);
rdaddress : in std_logic_vector(g_adr_w - 1 downto 0);
- rdclk : in std_logic ;
+ rdclk : in std_logic;
wraddress : in std_logic_vector(g_adr_w - 1 downto 0);
wrclk : in std_logic := '1';
wren : in std_logic := '0';
@@ -533,7 +533,7 @@ package tech_memory_component_pkg is
address_a : in std_logic_vector(g_adr_w - 1 downto 0);
address_b : in std_logic_vector(g_adr_w - 1 downto 0);
clk_a : in std_logic := '1';
- clk_b : in std_logic ;
+ clk_b : in std_logic;
data_a : in std_logic_vector(g_dat_w - 1 downto 0);
data_b : in std_logic_vector(g_dat_w - 1 downto 0);
wren_a : in std_logic := '0';
@@ -556,7 +556,7 @@ package tech_memory_component_pkg is
(
data : in std_logic_vector(g_dat_w - 1 downto 0);
rdaddress : in std_logic_vector(g_adr_w - 1 downto 0);
- rdclk : in std_logic ;
+ rdclk : in std_logic;
wraddress : in std_logic_vector(g_adr_w - 1 downto 0);
wrclk : in std_logic := '1';
wren : in std_logic := '0';
diff --git a/libraries/technology/memory/tech_memory_ram_cr_cw.vhd b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
index 49f47054dc..6028d8a490 100644
--- a/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
@@ -46,7 +46,7 @@ entity tech_memory_ram_cr_cw is
(
data : in std_logic_vector(g_dat_w - 1 downto 0);
rdaddress : in std_logic_vector(g_adr_w - 1 downto 0);
- rdclock : in std_logic ;
+ rdclock : in std_logic;
rdclocken : in std_logic := '1';
wraddress : in std_logic_vector(g_adr_w - 1 downto 0);
wrclock : in std_logic := '1';
diff --git a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
index efb7a13ef3..defe84f9ee 100644
--- a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
@@ -47,7 +47,7 @@ entity tech_memory_ram_crw_crw is
address_a : in std_logic_vector(g_adr_w - 1 downto 0);
address_b : in std_logic_vector(g_adr_w - 1 downto 0);
clock_a : in std_logic := '1';
- clock_b : in std_logic ;
+ clock_b : in std_logic;
data_a : in std_logic_vector(g_dat_w - 1 downto 0);
data_b : in std_logic_vector(g_dat_w - 1 downto 0);
enable_a : in std_logic := '1';
diff --git a/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
index 26a60c37be..ae952e2d30 100644
--- a/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
@@ -49,7 +49,7 @@ entity tech_memory_ram_crwk_crw is -- support different port data widths and co
address_a : in std_logic_vector(g_adr_a_w - 1 downto 0);
address_b : in std_logic_vector(g_adr_b_w - 1 downto 0);
clock_a : in std_logic := '1';
- clock_b : in std_logic ;
+ clock_b : in std_logic;
data_a : in std_logic_vector(g_dat_a_w - 1 downto 0);
data_b : in std_logic_vector(g_dat_b_w - 1 downto 0);
enable_a : in std_logic := '1';
diff --git a/libraries/technology/mult/tech_mult_component_pkg.vhd b/libraries/technology/mult/tech_mult_component_pkg.vhd
index da86bb1ffb..448746885e 100644
--- a/libraries/technology/mult/tech_mult_component_pkg.vhd
+++ b/libraries/technology/mult/tech_mult_component_pkg.vhd
@@ -33,13 +33,13 @@ package tech_mult_component_pkg is
component ip_stratixiv_complex_mult is
port
(
- aclr : in std_logic ;
- clock : in std_logic ;
+ aclr : in std_logic;
+ clock : in std_logic;
dataa_imag : in std_logic_vector(17 downto 0);
dataa_real : in std_logic_vector(17 downto 0);
datab_imag : in std_logic_vector(17 downto 0);
datab_real : in std_logic_vector(17 downto 0);
- ena : in std_logic ;
+ ena : in std_logic;
result_imag : out std_logic_vector(35 downto 0);
result_real : out std_logic_vector(35 downto 0)
);
diff --git a/libraries/technology/pll/tech_pll_clk125.vhd b/libraries/technology/pll/tech_pll_clk125.vhd
index 88111c2eb9..53b683d3ef 100644
--- a/libraries/technology/pll/tech_pll_clk125.vhd
+++ b/libraries/technology/pll/tech_pll_clk125.vhd
@@ -38,10 +38,10 @@ entity tech_pll_clk125 is
port (
areset : in std_logic := '0';
inclk0 : in std_logic := '0';
- c0 : out std_logic ;
- c1 : out std_logic ;
- c2 : out std_logic ;
- c3 : out std_logic ;
+ c0 : out std_logic;
+ c1 : out std_logic;
+ c2 : out std_logic;
+ c3 : out std_logic;
locked : out std_logic
);
end tech_pll_clk125;
diff --git a/libraries/technology/pll/tech_pll_clk200.vhd b/libraries/technology/pll/tech_pll_clk200.vhd
index e375a6a6bc..9c12384460 100644
--- a/libraries/technology/pll/tech_pll_clk200.vhd
+++ b/libraries/technology/pll/tech_pll_clk200.vhd
@@ -42,9 +42,9 @@ entity tech_pll_clk200 is
port (
areset : in std_logic := '0';
inclk0 : in std_logic := '0';
- c0 : out std_logic ;
- c1 : out std_logic ;
- c2 : out std_logic ;
+ c0 : out std_logic;
+ c1 : out std_logic;
+ c2 : out std_logic;
locked : out std_logic
);
end tech_pll_clk200;
diff --git a/libraries/technology/pll/tech_pll_clk200_p6.vhd b/libraries/technology/pll/tech_pll_clk200_p6.vhd
index 175a8d3ea4..c61ee97b77 100644
--- a/libraries/technology/pll/tech_pll_clk200_p6.vhd
+++ b/libraries/technology/pll/tech_pll_clk200_p6.vhd
@@ -59,13 +59,13 @@ entity tech_pll_clk200_p6 is
(
areset : in std_logic := '0';
inclk0 : in std_logic := '0';
- c0 : out std_logic ;
- c1 : out std_logic ;
- c2 : out std_logic ;
- c3 : out std_logic ;
- c4 : out std_logic ;
- c5 : out std_logic ;
- c6 : out std_logic ;
+ c0 : out std_logic;
+ c1 : out std_logic;
+ c2 : out std_logic;
+ c3 : out std_logic;
+ c4 : out std_logic;
+ c5 : out std_logic;
+ c6 : out std_logic;
locked : out std_logic
);
end tech_pll_clk200_p6;
diff --git a/libraries/technology/pll/tech_pll_clk25.vhd b/libraries/technology/pll/tech_pll_clk25.vhd
index f3aa6ee6fc..cb34290234 100644
--- a/libraries/technology/pll/tech_pll_clk25.vhd
+++ b/libraries/technology/pll/tech_pll_clk25.vhd
@@ -39,11 +39,11 @@ entity tech_pll_clk25 is
port (
areset : in std_logic := '0';
inclk0 : in std_logic := '0';
- c0 : out std_logic ;
- c1 : out std_logic ;
- c2 : out std_logic ;
- c3 : out std_logic ;
- c4 : out std_logic ;
+ c0 : out std_logic;
+ c1 : out std_logic;
+ c2 : out std_logic;
+ c3 : out std_logic;
+ c4 : out std_logic;
locked : out std_logic
);
end tech_pll_clk25;
diff --git a/libraries/technology/pll/tech_pll_component_pkg.vhd b/libraries/technology/pll/tech_pll_component_pkg.vhd
index 91a3d8b44a..9ed0139407 100644
--- a/libraries/technology/pll/tech_pll_component_pkg.vhd
+++ b/libraries/technology/pll/tech_pll_component_pkg.vhd
@@ -48,9 +48,9 @@ package tech_pll_component_pkg is
(
areset : in std_logic := '0';
inclk0 : in std_logic := '0';
- c0 : out std_logic ;
- c1 : out std_logic ;
- c2 : out std_logic ;
+ c0 : out std_logic;
+ c1 : out std_logic;
+ c2 : out std_logic;
locked : out std_logic
);
end component;
@@ -85,13 +85,13 @@ package tech_pll_component_pkg is
(
areset : in std_logic := '0';
inclk0 : in std_logic := '0';
- c0 : out std_logic ;
- c1 : out std_logic ;
- c2 : out std_logic ;
- c3 : out std_logic ;
- c4 : out std_logic ;
- c5 : out std_logic ;
- c6 : out std_logic ;
+ c0 : out std_logic;
+ c1 : out std_logic;
+ c2 : out std_logic;
+ c3 : out std_logic;
+ c4 : out std_logic;
+ c5 : out std_logic;
+ c6 : out std_logic;
locked : out std_logic
);
end component;
@@ -101,11 +101,11 @@ package tech_pll_component_pkg is
(
areset : in std_logic := '0';
inclk0 : in std_logic := '0';
- c0 : out std_logic ;
- c1 : out std_logic ;
- c2 : out std_logic ;
- c3 : out std_logic ;
- c4 : out std_logic ;
+ c0 : out std_logic;
+ c1 : out std_logic;
+ c2 : out std_logic;
+ c3 : out std_logic;
+ c4 : out std_logic;
locked : out std_logic
);
end component;
@@ -130,9 +130,9 @@ package tech_pll_component_pkg is
(
rst : in std_logic := '0';
refclk : in std_logic := '0';
- outclk_0 : out std_logic ;
- outclk_1 : out std_logic ;
- outclk_2 : out std_logic ;
+ outclk_0 : out std_logic;
+ outclk_1 : out std_logic;
+ outclk_2 : out std_logic;
locked : out std_logic
);
end component;
@@ -142,10 +142,10 @@ package tech_pll_component_pkg is
(
rst : in std_logic := '0';
refclk : in std_logic := '0';
- outclk_0 : out std_logic ;
- outclk_1 : out std_logic ;
- outclk_2 : out std_logic ;
- outclk_3 : out std_logic ;
+ outclk_0 : out std_logic;
+ outclk_1 : out std_logic;
+ outclk_2 : out std_logic;
+ outclk_3 : out std_logic;
locked : out std_logic
);
end component;
@@ -155,10 +155,10 @@ package tech_pll_component_pkg is
(
rst : in std_logic := '0';
refclk : in std_logic := '0';
- outclk_0 : out std_logic ;
- outclk_1 : out std_logic ;
- outclk_2 : out std_logic ;
- outclk_3 : out std_logic ;
+ outclk_0 : out std_logic;
+ outclk_1 : out std_logic;
+ outclk_2 : out std_logic;
+ outclk_3 : out std_logic;
locked : out std_logic
);
end component;
@@ -197,9 +197,9 @@ package tech_pll_component_pkg is
(
rst : in std_logic := '0';
refclk : in std_logic := '0';
- outclk_0 : out std_logic ;
- outclk_1 : out std_logic ;
- outclk_2 : out std_logic ;
+ outclk_0 : out std_logic;
+ outclk_1 : out std_logic;
+ outclk_2 : out std_logic;
locked : out std_logic
);
end component;
@@ -209,10 +209,10 @@ package tech_pll_component_pkg is
(
rst : in std_logic := '0';
refclk : in std_logic := '0';
- outclk_0 : out std_logic ;
- outclk_1 : out std_logic ;
- outclk_2 : out std_logic ;
- outclk_3 : out std_logic ;
+ outclk_0 : out std_logic;
+ outclk_1 : out std_logic;
+ outclk_2 : out std_logic;
+ outclk_3 : out std_logic;
locked : out std_logic
);
end component;
@@ -222,10 +222,10 @@ package tech_pll_component_pkg is
(
rst : in std_logic := '0';
refclk : in std_logic := '0';
- outclk_0 : out std_logic ;
- outclk_1 : out std_logic ;
- outclk_2 : out std_logic ;
- outclk_3 : out std_logic ;
+ outclk_0 : out std_logic;
+ outclk_1 : out std_logic;
+ outclk_2 : out std_logic;
+ outclk_3 : out std_logic;
locked : out std_logic
);
end component;
@@ -250,9 +250,9 @@ package tech_pll_component_pkg is
(
rst : in std_logic := '0';
refclk : in std_logic := '0';
- outclk_0 : out std_logic ;
- outclk_1 : out std_logic ;
- outclk_2 : out std_logic ;
+ outclk_0 : out std_logic;
+ outclk_1 : out std_logic;
+ outclk_2 : out std_logic;
locked : out std_logic
);
end component;
@@ -262,10 +262,10 @@ package tech_pll_component_pkg is
(
rst : in std_logic := '0';
refclk : in std_logic := '0';
- outclk_0 : out std_logic ;
- outclk_1 : out std_logic ;
- outclk_2 : out std_logic ;
- outclk_3 : out std_logic ;
+ outclk_0 : out std_logic;
+ outclk_1 : out std_logic;
+ outclk_2 : out std_logic;
+ outclk_3 : out std_logic;
locked : out std_logic
);
end component;
@@ -275,10 +275,10 @@ package tech_pll_component_pkg is
(
rst : in std_logic := '0';
refclk : in std_logic := '0';
- outclk_0 : out std_logic ;
- outclk_1 : out std_logic ;
- outclk_2 : out std_logic ;
- outclk_3 : out std_logic ;
+ outclk_0 : out std_logic;
+ outclk_1 : out std_logic;
+ outclk_2 : out std_logic;
+ outclk_3 : out std_logic;
locked : out std_logic
);
end component;
@@ -303,9 +303,9 @@ package tech_pll_component_pkg is
(
rst : in std_logic := '0';
refclk : in std_logic := '0';
- outclk_0 : out std_logic ;
- outclk_1 : out std_logic ;
- outclk_2 : out std_logic ;
+ outclk_0 : out std_logic;
+ outclk_1 : out std_logic;
+ outclk_2 : out std_logic;
locked : out std_logic
);
end component;
@@ -315,10 +315,10 @@ package tech_pll_component_pkg is
(
rst : in std_logic := '0';
refclk : in std_logic := '0';
- outclk_0 : out std_logic ;
- outclk_1 : out std_logic ;
- outclk_2 : out std_logic ;
- outclk_3 : out std_logic ;
+ outclk_0 : out std_logic;
+ outclk_1 : out std_logic;
+ outclk_2 : out std_logic;
+ outclk_3 : out std_logic;
locked : out std_logic
);
end component;
@@ -328,10 +328,10 @@ package tech_pll_component_pkg is
(
rst : in std_logic := '0';
refclk : in std_logic := '0';
- outclk_0 : out std_logic ;
- outclk_1 : out std_logic ;
- outclk_2 : out std_logic ;
- outclk_3 : out std_logic ;
+ outclk_0 : out std_logic;
+ outclk_1 : out std_logic;
+ outclk_2 : out std_logic;
+ outclk_3 : out std_logic;
locked : out std_logic
);
end component;
diff --git a/libraries/technology/transceiver/sim_transceiver_deserializer.vhd b/libraries/technology/transceiver/sim_transceiver_deserializer.vhd
index 81baf459b5..ad928b3a80 100644
--- a/libraries/technology/transceiver/sim_transceiver_deserializer.vhd
+++ b/libraries/technology/transceiver/sim_transceiver_deserializer.vhd
@@ -73,7 +73,7 @@ begin
rx_out_sop <= (others => '0');
rx_out_eop <= (others => '0');
- wait until tr_rst = '0' ;
+ wait until tr_rst = '0';
-- Align to tr_clk
wait until rising_edge(tr_clk);
diff --git a/libraries/technology/transceiver/tech_transceiver_component_pkg.vhd b/libraries/technology/transceiver/tech_transceiver_component_pkg.vhd
index f68f590374..184d46bb49 100644
--- a/libraries/technology/transceiver/tech_transceiver_component_pkg.vhd
+++ b/libraries/technology/transceiver/tech_transceiver_component_pkg.vhd
@@ -37,11 +37,11 @@ package tech_transceiver_component_pkg is
starting_channel_number : natural := 0
);
port (
- cal_blk_clk : in std_logic ;
+ cal_blk_clk : in std_logic;
gxb_powerdown : in std_logic_vector(0 downto 0);
- pll_inclk : in std_logic ;
+ pll_inclk : in std_logic;
pll_powerdown : in std_logic_vector(0 downto 0);
- reconfig_clk : in std_logic ;
+ reconfig_clk : in std_logic;
reconfig_togxb : in std_logic_vector(3 downto 0);
rx_analogreset : in std_logic_vector(0 downto 0);
rx_datain : in std_logic_vector(0 downto 0);
@@ -71,9 +71,9 @@ package tech_transceiver_component_pkg is
g_mbps : natural
);
port (
- cal_blk_clk : in std_logic ;
+ cal_blk_clk : in std_logic;
gxb_powerdown : in std_logic_vector(0 downto 0);
- pll_inclk : in std_logic ;
+ pll_inclk : in std_logic;
pll_powerdown : in std_logic_vector(0 downto 0);
tx_ctrlenable : in std_logic_vector(3 downto 0);
tx_datain : in std_logic_vector(31 downto 0);
@@ -90,9 +90,9 @@ package tech_transceiver_component_pkg is
starting_channel_number : natural := 0
);
port (
- cal_blk_clk : in std_logic ;
+ cal_blk_clk : in std_logic;
gxb_powerdown : in std_logic_vector(0 downto 0);
- reconfig_clk : in std_logic ;
+ reconfig_clk : in std_logic;
reconfig_togxb : in std_logic_vector(3 downto 0);
rx_analogreset : in std_logic_vector(0 downto 0);
rx_cruclk : in std_logic_vector(0 downto 0) := (others => '0');
@@ -118,10 +118,10 @@ package tech_transceiver_component_pkg is
);
port
(
- cal_blk_clk : in std_logic ;
- pll_inclk : in std_logic ;
+ cal_blk_clk : in std_logic;
+ pll_inclk : in std_logic;
pll_powerdown : in std_logic_vector(0 downto 0);
- reconfig_clk : in std_logic ;
+ reconfig_clk : in std_logic;
reconfig_togxb : in std_logic_vector(3 downto 0);
rx_analogreset : in std_logic_vector(0 downto 0);
rx_datain : in std_logic_vector(0 downto 0);
@@ -143,8 +143,8 @@ package tech_transceiver_component_pkg is
component ip_stratixiv_hssi_tx_16b is
port
(
- cal_blk_clk : in std_logic ;
- pll_inclk : in std_logic ;
+ cal_blk_clk : in std_logic;
+ pll_inclk : in std_logic;
pll_powerdown : in std_logic_vector(0 downto 0);
tx_ctrlenable : in std_logic_vector(1 downto 0);
tx_datain : in std_logic_vector(15 downto 0);
@@ -162,8 +162,8 @@ package tech_transceiver_component_pkg is
);
port
(
- cal_blk_clk : in std_logic ;
- reconfig_clk : in std_logic ;
+ cal_blk_clk : in std_logic;
+ reconfig_clk : in std_logic;
reconfig_togxb : in std_logic_vector(3 downto 0);
rx_analogreset : in std_logic_vector(0 downto 0);
rx_cruclk : in std_logic_vector(0 downto 0) := (others => '0');
--
GitLab