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Commit c3575bc3 authored by Eric Kooistra's avatar Eric Kooistra
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Added MAC 10GbE IP generated with Quartus 11.1 SP2.

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libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g.qip 0 → 100644
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set_global_assignment -entity "ip_stratixiv_mac_10g" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_10g_mac"
set_global_assignment -entity "ip_stratixiv_mac_10g" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1sp2"
set_global_assignment -entity "ip_stratixiv_mac_10g" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VHDL_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g.vhd]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_0002.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_avalon_st_handshake_clock_crosser.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_avalon_st_clock_crosser.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_avalon_st_pipeline_base.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_merlin_arbitrator.sv]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rsp_xbar_mux_002.sv]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rsp_xbar_demux_010.sv]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_cmd_xbar_demux_002.sv]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rsp_xbar_mux_001.sv]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rsp_xbar_demux_002.sv]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_cmd_xbar_demux_001.sv]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rsp_xbar_mux.sv]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rsp_xbar_demux.sv]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_cmd_xbar_demux.sv]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_reset_controller.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_reset_synchronizer.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SDC_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_reset_controller.sdc]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_merlin_traffic_limiter.sv]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_id_router_010.sv]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_addr_router_002.sv]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_id_router_002.sv]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_addr_router_001.sv]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_id_router.sv]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_addr_router.sv]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_merlin_master_agent.sv]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_avalon_sc_fifo.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_merlin_slave_agent.sv]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_merlin_burst_uncompressor.sv]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_merlin_slave_translator.sv]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_tx.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_rx.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_avalon_dc_fifo.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_dcfifo_synchronizer_bundle.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SDC_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_avalon_dc_fifo.sdc]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_export.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_rx.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rx_st_error_adapter_stat.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_avalon_st_delay.sv]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_packet_overflow_control.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_packet_overflow_control.ocp]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_crc_pad_rem.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_crc_pad_rem.ocp]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_crc_rem.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_packet_stripper.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_avalon_st_pipeline_stage.sv]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_frame_status_merger.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rx_timing_adapter_frame_status_out_frame_decoder.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rx_st_timing_adapter_frame_status_in.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_lane_decoder.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_lane_decoder.ocp]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_link_fault_detection.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_link_fault_detection.ocp]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rx_st_timing_adapter_lane_decoder.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rx_st_timing_adapter_interface_conversion.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_link_fault_generation.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_link_fault_generation.ocp]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_xgmii_termination.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_xgmii_termination.ocp]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_packet_formatter.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_packet_formatter.ocp]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_10gmem_statistics_collector.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_10gmem_statistics_collector.ocp]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_output.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_in.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_tx_st_error_adapter_stat.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_frame_decoder.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_frame_decoder.ocp]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_tx_st_timing_adapter_frame_decoder.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_avalon_st_splitter.sv]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_crc.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_crc.ocp]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/crc32.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/gf_mult32_kc.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_address_inserter.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_address_inserter.ocp]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_tx_st_mux_flow_control_user_frame.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_tx_st_pause_ctrl_error_adapter.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_pause_controller.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_pause_ctrl_gen.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_pause_ctrl_gen.ocp]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_pause_gen.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_pause_beat_conversion.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_pkt_backpressure_control.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_pkt_backpressure_control.ocp]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_pad_inserter.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_pad_inserter.ocp]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_packet_underflow_control.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_packet_underflow_control.ocp]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_avalon_mm_bridge.v]
set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_merlin_master_translator.sv]
set_global_assignment -entity "ip_stratixiv_mac_10g_0002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_10g_mac"
set_global_assignment -entity "ip_stratixiv_mac_10g_0002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_0002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "altera_avalon_st_handshake_clock_crosser" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_avalon_st_handshake_clock_crosser"
set_global_assignment -entity "altera_avalon_st_handshake_clock_crosser" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "altera_avalon_st_handshake_clock_crosser" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_mux_002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_multiplexer"
set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_mux_002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_mux_002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_demux_010" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_demux_010" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_demux_010" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "ip_stratixiv_mac_10g_cmd_xbar_demux_002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
set_global_assignment -entity "ip_stratixiv_mac_10g_cmd_xbar_demux_002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_cmd_xbar_demux_002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_mux_001" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_multiplexer"
set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_mux_001" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_mux_001" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_demux_002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_demux_002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_demux_002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "ip_stratixiv_mac_10g_cmd_xbar_demux_001" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
set_global_assignment -entity "ip_stratixiv_mac_10g_cmd_xbar_demux_001" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_cmd_xbar_demux_001" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_mux" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_multiplexer"
set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_mux" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_mux" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_demux" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_demux" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_demux" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "ip_stratixiv_mac_10g_cmd_xbar_demux" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
set_global_assignment -entity "ip_stratixiv_mac_10g_cmd_xbar_demux" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_cmd_xbar_demux" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "altera_reset_controller" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_reset_controller"
set_global_assignment -entity "altera_reset_controller" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "altera_reset_controller" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_traffic_limiter"
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "ip_stratixiv_mac_10g_id_router_010" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_router"
set_global_assignment -entity "ip_stratixiv_mac_10g_id_router_010" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_id_router_010" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "ip_stratixiv_mac_10g_addr_router_002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_router"
set_global_assignment -entity "ip_stratixiv_mac_10g_addr_router_002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_addr_router_002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "ip_stratixiv_mac_10g_id_router_002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_router"
set_global_assignment -entity "ip_stratixiv_mac_10g_id_router_002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_id_router_002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "ip_stratixiv_mac_10g_addr_router_001" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_router"
set_global_assignment -entity "ip_stratixiv_mac_10g_addr_router_001" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_addr_router_001" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "ip_stratixiv_mac_10g_id_router" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_router"
set_global_assignment -entity "ip_stratixiv_mac_10g_id_router" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_id_router" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "ip_stratixiv_mac_10g_addr_router" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_router"
set_global_assignment -entity "ip_stratixiv_mac_10g_addr_router" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_addr_router" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "altera_merlin_master_agent" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_master_agent"
set_global_assignment -entity "altera_merlin_master_agent" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "altera_merlin_master_agent" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "altera_avalon_sc_fifo" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_avalon_sc_fifo"
set_global_assignment -entity "altera_avalon_sc_fifo" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "altera_avalon_sc_fifo" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "altera_merlin_slave_agent" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_slave_agent"
set_global_assignment -entity "altera_merlin_slave_agent" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "altera_merlin_slave_agent" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "altera_merlin_slave_translator" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_slave_translator"
set_global_assignment -entity "altera_merlin_slave_translator" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "altera_merlin_slave_translator" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_tx" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "timing_adapter"
set_global_assignment -entity "ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_tx" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_tx" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_rx" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "timing_adapter"
set_global_assignment -entity "ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_rx" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_rx" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "altera_avalon_dc_fifo" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_avalon_dc_fifo"
set_global_assignment -entity "altera_avalon_dc_fifo" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "altera_avalon_dc_fifo" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_export" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "timing_adapter"
set_global_assignment -entity "ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_export" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_export" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_rx" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "timing_adapter"
set_global_assignment -entity "ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_rx" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_rx" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "ip_stratixiv_mac_10g_rx_st_error_adapter_stat" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "error_adapter"
set_global_assignment -entity "ip_stratixiv_mac_10g_rx_st_error_adapter_stat" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_rx_st_error_adapter_stat" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "altera_avalon_st_delay" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_avalon_st_delay"
set_global_assignment -entity "altera_avalon_st_delay" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "altera_avalon_st_delay" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "altera_eth_packet_overflow_control" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_packet_overflow_control"
set_global_assignment -entity "altera_eth_packet_overflow_control" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "altera_eth_packet_overflow_control" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "altera_eth_crc_pad_rem" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_crc_pad_rem"
set_global_assignment -entity "altera_eth_crc_pad_rem" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "altera_eth_crc_pad_rem" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "altera_eth_frame_status_merger" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_frame_status_merger"
set_global_assignment -entity "altera_eth_frame_status_merger" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "altera_eth_frame_status_merger" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "ip_stratixiv_mac_10g_rx_timing_adapter_frame_status_out_frame_decoder" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "timing_adapter"
set_global_assignment -entity "ip_stratixiv_mac_10g_rx_timing_adapter_frame_status_out_frame_decoder" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_rx_timing_adapter_frame_status_out_frame_decoder" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "ip_stratixiv_mac_10g_rx_st_timing_adapter_frame_status_in" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "timing_adapter"
set_global_assignment -entity "ip_stratixiv_mac_10g_rx_st_timing_adapter_frame_status_in" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_rx_st_timing_adapter_frame_status_in" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "altera_eth_lane_decoder" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_lane_decoder"
set_global_assignment -entity "altera_eth_lane_decoder" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "altera_eth_lane_decoder" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "altera_eth_link_fault_detection" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_link_fault_detection"
set_global_assignment -entity "altera_eth_link_fault_detection" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "altera_eth_link_fault_detection" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "ip_stratixiv_mac_10g_rx_st_timing_adapter_lane_decoder" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "timing_adapter"
set_global_assignment -entity "ip_stratixiv_mac_10g_rx_st_timing_adapter_lane_decoder" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_rx_st_timing_adapter_lane_decoder" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "ip_stratixiv_mac_10g_rx_st_timing_adapter_interface_conversion" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "timing_adapter"
set_global_assignment -entity "ip_stratixiv_mac_10g_rx_st_timing_adapter_interface_conversion" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_rx_st_timing_adapter_interface_conversion" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "altera_eth_link_fault_generation" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_link_fault_generation"
set_global_assignment -entity "altera_eth_link_fault_generation" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "altera_eth_link_fault_generation" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "altera_eth_xgmii_termination" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_xgmii_termination"
set_global_assignment -entity "altera_eth_xgmii_termination" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "altera_eth_xgmii_termination" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "altera_eth_packet_formatter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_packet_formatter"
set_global_assignment -entity "altera_eth_packet_formatter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "altera_eth_packet_formatter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "altera_eth_10gmem_statistics_collector" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_10gmem_statistics_collector"
set_global_assignment -entity "altera_eth_10gmem_statistics_collector" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "altera_eth_10gmem_statistics_collector" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_output" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "timing_adapter"
set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_output" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_output" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_in" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "timing_adapter"
set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_in" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_in" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_error_adapter_stat" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "error_adapter"
set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_error_adapter_stat" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_error_adapter_stat" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "altera_eth_frame_decoder" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_frame_decoder"
set_global_assignment -entity "altera_eth_frame_decoder" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "altera_eth_frame_decoder" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_timing_adapter_frame_decoder" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "timing_adapter"
set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_timing_adapter_frame_decoder" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_timing_adapter_frame_decoder" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "altera_avalon_st_splitter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_avalon_st_splitter"
set_global_assignment -entity "altera_avalon_st_splitter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "altera_avalon_st_splitter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "altera_avalon_st_pipeline_stage" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_avalon_st_pipeline_stage"
set_global_assignment -entity "altera_avalon_st_pipeline_stage" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "altera_avalon_st_pipeline_stage" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "altera_eth_crc" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_crc"
set_global_assignment -entity "altera_eth_crc" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "altera_eth_crc" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "altera_eth_address_inserter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_address_inserter"
set_global_assignment -entity "altera_eth_address_inserter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "altera_eth_address_inserter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_mux_flow_control_user_frame" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "multiplexer"
set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_mux_flow_control_user_frame" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_mux_flow_control_user_frame" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_pause_ctrl_error_adapter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "error_adapter"
set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_pause_ctrl_error_adapter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_pause_ctrl_error_adapter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "altera_eth_pause_ctrl_gen" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_pause_ctrl_gen"
set_global_assignment -entity "altera_eth_pause_ctrl_gen" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "altera_eth_pause_ctrl_gen" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "altera_eth_pause_beat_conversion" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_pause_beat_conversion"
set_global_assignment -entity "altera_eth_pause_beat_conversion" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "altera_eth_pause_beat_conversion" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "altera_eth_pkt_backpressure_control" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_pkt_backpressure_control"
set_global_assignment -entity "altera_eth_pkt_backpressure_control" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "altera_eth_pkt_backpressure_control" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "altera_eth_pad_inserter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_pad_inserter"
set_global_assignment -entity "altera_eth_pad_inserter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "altera_eth_pad_inserter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "altera_eth_packet_underflow_control" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_packet_underflow_control"
set_global_assignment -entity "altera_eth_packet_underflow_control" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "altera_eth_packet_underflow_control" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "altera_avalon_mm_bridge" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_avalon_mm_bridge"
set_global_assignment -entity "altera_avalon_mm_bridge" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "altera_avalon_mm_bridge" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "altera_merlin_master_translator" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_master_translator"
set_global_assignment -entity "altera_merlin_master_translator" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
set_global_assignment -entity "altera_merlin_master_translator" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_dc_fifo.sdc 0 → 100644
+ 12
− 0
View file @ c3575bc3
# $Id: //acds/rel/11.1sp2/ip/sopc/components/altera_avalon_dc_fifo/altera_avalon_dc_fifo.sdc#1 $
# $Revision: #1 $
# $Date: 2011/11/10 $
#-------------------------------------------------------------------------------
# TimeQuest constraints to cut all false timing paths across asynchronous
# clock domains. The paths are from the Gray Code read and write pointers to
# their respective synchronizer banks.
set_false_path -from [get_registers {*|in_wr_ptr_gray[*]}] -to [get_registers {*|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[*].u|din_s1}]
set_false_path -from [get_registers {*|out_rd_ptr_gray[*]}] -to [get_registers {*|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[*].u|din_s1}]
libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_mm_bridge.v 0 → 100644
+ 291
− 0
View file @ c3575bc3
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/11.1sp2/ip/merlin/altera_avalon_mm_bridge/altera_avalon_mm_bridge.v#1 $
// $Revision: #1 $
// $Date: 2011/11/10 $
// $Author: max $
// --------------------------------------
// Avalon-MM pipeline bridge
//
// Optionally registers Avalon-MM command and response signals
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_avalon_mm_bridge
#(
parameter DATA_WIDTH = 32,
parameter SYMBOL_WIDTH = 8,
parameter ADDRESS_WIDTH = 10,
parameter BURSTCOUNT_WIDTH = 1,
parameter PIPELINE_COMMAND = 1,
parameter PIPELINE_RESPONSE = 1,
// --------------------------------------
// Derived parameters
// --------------------------------------
parameter BYTEEN_WIDTH = DATA_WIDTH / SYMBOL_WIDTH
)
(
input clk,
input reset,
output s0_waitrequest,
output [DATA_WIDTH-1:0] s0_readdata,
output s0_readdatavalid,
input [BURSTCOUNT_WIDTH-1:0] s0_burstcount,
input [DATA_WIDTH-1:0] s0_writedata,
input [ADDRESS_WIDTH-1:0] s0_address,
input s0_write,
input s0_read,
input [BYTEEN_WIDTH-1:0] s0_byteenable,
input s0_debugaccess,
input m0_waitrequest,
input [DATA_WIDTH-1:0] m0_readdata,
input m0_readdatavalid,
output [BURSTCOUNT_WIDTH-1:0] m0_burstcount,
output [DATA_WIDTH-1:0] m0_writedata,
output [ADDRESS_WIDTH-1:0] m0_address,
output m0_write,
output m0_read,
output [BYTEEN_WIDTH-1:0] m0_byteenable,
output m0_debugaccess
);
// --------------------------------------
// Registers & signals
// --------------------------------------
reg [BURSTCOUNT_WIDTH-1:0] cmd_burstcount;
reg [DATA_WIDTH-1:0] cmd_writedata;
reg [ADDRESS_WIDTH-1:0] cmd_address;
reg cmd_write;
reg cmd_read;
reg [BYTEEN_WIDTH-1:0] cmd_byteenable;
wire cmd_waitrequest;
reg cmd_debugaccess;
reg [BURSTCOUNT_WIDTH-1:0] wr_burstcount;
reg [DATA_WIDTH-1:0] wr_writedata;
reg [ADDRESS_WIDTH-1:0] wr_address;
reg wr_write;
reg wr_read;
reg [BYTEEN_WIDTH-1:0] wr_byteenable;
reg wr_debugaccess;
reg [BURSTCOUNT_WIDTH-1:0] wr_reg_burstcount;
reg [DATA_WIDTH-1:0] wr_reg_writedata;
reg [ADDRESS_WIDTH-1:0] wr_reg_address;
reg wr_reg_write;
reg wr_reg_read;
reg [BYTEEN_WIDTH-1:0] wr_reg_byteenable;
reg wr_reg_waitrequest;
reg wr_reg_debugaccess;
reg use_reg;
wire wait_rise;
reg [DATA_WIDTH-1:0] rsp_readdata;
reg rsp_readdatavalid;
// --------------------------------------
// Command pipeline
//
// Registers all command signals, including waitrequest
// --------------------------------------
generate if (PIPELINE_COMMAND == 1) begin
// --------------------------------------
// Waitrequest Pipeline Stage
//
// Output waitrequest is delayed by one cycle, which means
// that a master will see waitrequest assertions one cycle
// too late.
//
// Solution: buffer the command when waitrequest transitions
// from low->high. As an optimization, we can safely assume
// waitrequest is low by default because downstream logic
// in the bridge ensures this.
//
// Note: this implementation buffers idle cycles should
// waitrequest transition on such cycles. This is a potential
// cause for throughput loss, but ye olde pipeline bridge did
// the same for years and no one complained. Not buffering idle
// cycles costs logic on the waitrequest path.
// --------------------------------------
assign s0_waitrequest = wr_reg_waitrequest;
assign wait_rise = ~wr_reg_waitrequest & cmd_waitrequest;
always @(posedge clk, posedge reset) begin
if (reset) begin
wr_reg_waitrequest <= 1'b1;
// --------------------------------------
// Bit of trickiness here, deserving of a long comment.
//
// On the first cycle after reset, the pass-through
// must not be used or downstream logic may sample
// the same command twice because of the delay in
// transmitting a falling waitrequest.
//
// Using the registered command works on the condition
// that downstream logic deasserts waitrequest
// immediately after reset, which is true of the
// next stage in this bridge.
// --------------------------------------
use_reg <= 1'b1;
wr_reg_burstcount <= 1'b1;
wr_reg_writedata <= 0;
wr_reg_byteenable <= {BYTEEN_WIDTH{1'b1}};
wr_reg_address <= 0;
wr_reg_write <= 1'b0;
wr_reg_read <= 1'b0;
wr_reg_debugaccess <= 1'b0;
end else begin
wr_reg_waitrequest <= cmd_waitrequest;
if (wait_rise) begin
use_reg <= 1'b1;
wr_reg_writedata <= s0_writedata;
wr_reg_byteenable <= s0_byteenable;
wr_reg_address <= s0_address;
wr_reg_write <= s0_write;
wr_reg_read <= s0_read;
wr_reg_burstcount <= s0_burstcount;
wr_reg_debugaccess <= s0_debugaccess;
end
// stop using the buffer when waitrequest is low
if (~cmd_waitrequest)
use_reg <= 1'b0;
end
end
always @* begin
wr_burstcount = s0_burstcount;
wr_writedata = s0_writedata;
wr_address = s0_address;
wr_write = s0_write;
wr_read = s0_read;
wr_byteenable = s0_byteenable;
wr_debugaccess = s0_debugaccess;
if (use_reg) begin
wr_burstcount = wr_reg_burstcount;
wr_writedata = wr_reg_writedata;
wr_address = wr_reg_address;
wr_write = wr_reg_write;
wr_read = wr_reg_read;
wr_byteenable = wr_reg_byteenable;
wr_debugaccess = wr_reg_debugaccess;
end
end
// --------------------------------------
// Master-Slave Signal Pipeline Stage
//
// One notable detail is that cmd_waitrequest is deasserted
// when this stage is idle. This allows us to make logic
// optimizations in the waitrequest pipeline stage.
//
// Also note that cmd_waitrequest is deasserted during reset,
// which is not spec-compliant, but is ok for an internal
// signal.
// --------------------------------------
wire no_command;
assign no_command = ~(cmd_read || cmd_write);
assign cmd_waitrequest = m0_waitrequest & ~no_command;
always @(posedge clk, posedge reset) begin
if (reset) begin
cmd_burstcount <= 1'b1;
cmd_writedata <= 0;
cmd_byteenable <= {BYTEEN_WIDTH{1'b1}};
cmd_address <= 0;
cmd_write <= 1'b0;
cmd_read <= 1'b0;
cmd_debugaccess <= 1'b0;
end
else begin
if (~cmd_waitrequest) begin
cmd_writedata <= wr_writedata;
cmd_byteenable <= wr_byteenable;
cmd_address <= wr_address;
cmd_write <= wr_write;
cmd_read <= wr_read;
cmd_burstcount <= wr_burstcount;
cmd_debugaccess <= wr_debugaccess;
end
end
end
end // conditional command pipeline
else begin
assign s0_waitrequest = m0_waitrequest;
always @* begin
cmd_burstcount = s0_burstcount;
cmd_writedata = s0_writedata;
cmd_address = s0_address;
cmd_write = s0_write;
cmd_read = s0_read;
cmd_byteenable = s0_byteenable;
cmd_debugaccess = s0_debugaccess;
end
end
endgenerate
assign m0_burstcount = cmd_burstcount;
assign m0_writedata = cmd_writedata;
assign m0_address = cmd_address;
assign m0_write = cmd_write;
assign m0_read = cmd_read;
assign m0_byteenable = cmd_byteenable;
assign m0_debugaccess = cmd_debugaccess;
// --------------------------------------
// Response pipeline
//
// Registers all response signals
// --------------------------------------
generate if (PIPELINE_RESPONSE == 1) begin
always @(posedge clk, posedge reset) begin
if (reset) begin
rsp_readdatavalid <= 1'b0;
rsp_readdata <= 0;
end
else begin
rsp_readdatavalid <= m0_readdatavalid;
rsp_readdata <= m0_readdata;
end
end
end // conditional response pipeline
else begin
always @* begin
rsp_readdatavalid = m0_readdatavalid;
rsp_readdata = m0_readdata;
end
end
endgenerate
assign s0_readdatavalid = rsp_readdatavalid;
assign s0_readdata = rsp_readdata;
endmodule
libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_st_clock_crosser.v 0 → 100644
+ 135
− 0
View file @ c3575bc3
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1ns / 1ns
module altera_avalon_st_clock_crosser(
in_clk,
in_reset,
in_ready,
in_valid,
in_data,
out_clk,
out_reset,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FORWARD_SYNC_DEPTH = 2;
parameter BACKWARD_SYNC_DEPTH = 2;
parameter USE_OUTPUT_PIPELINE = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input in_clk;
input in_reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_clk;
input out_reset;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
// Data is guaranteed valid by control signal clock crossing. Cut data
// buffer false path.
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\" ; -name SDC_STATEMENT \"set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
reg [DATA_WIDTH-1:0] out_data_buffer;
reg in_data_toggle;
wire in_data_toggle_returned;
wire out_data_toggle;
reg out_data_toggle_flopped;
wire take_in_data;
wire out_data_taken;
wire out_valid_internal;
wire out_ready_internal;
assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
assign take_in_data = in_valid & in_ready;
assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
assign out_data_taken = out_ready_internal & out_valid_internal;
always @(posedge in_clk or posedge in_reset) begin
if (in_reset) begin
in_data_buffer <= 'b0;
in_data_toggle <= 1'b0;
end else begin
if (take_in_data) begin
in_data_toggle <= ~in_data_toggle;
in_data_buffer <= in_data;
end
end //in_reset
end //in_clk always block
always @(posedge out_clk or posedge out_reset) begin
if (out_reset) begin
out_data_toggle_flopped <= 1'b0;
out_data_buffer <= 'b0;
end else begin
out_data_buffer <= in_data_buffer;
if (out_data_taken) begin
out_data_toggle_flopped <= out_data_toggle;
end
end //end if
end //out_clk always block
altera_std_synchronizer #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
.clk(out_clk),
.reset_n(~out_reset),
.din(in_data_toggle),
.dout(out_data_toggle)
);
altera_std_synchronizer #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
.clk(in_clk),
.reset_n(~in_reset),
.din(out_data_toggle_flopped),
.dout(in_data_toggle_returned)
);
generate if (USE_OUTPUT_PIPELINE == 1) begin
altera_avalon_st_pipeline_base
#(
.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
) output_stage (
.clk(out_clk),
.reset(out_reset),
.in_ready(out_ready_internal),
.in_valid(out_valid_internal),
.in_data(out_data_buffer),
.out_ready(out_ready),
.out_valid(out_valid),
.out_data(out_data)
);
end else begin
assign out_valid = out_valid_internal;
assign out_ready_internal = out_ready;
assign out_data = out_data_buffer;
end
endgenerate
endmodule
libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_st_delay.sv 0 → 100644
+ 174
− 0
View file @ c3575bc3
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1ns / 1ns
module altera_avalon_st_delay #(
parameter
NUMBER_OF_DELAY_CLOCKS = 1,
DATA_WIDTH = 8,
BITS_PER_SYMBOL = 8,
USE_PACKETS = 0,
USE_CHANNEL = 0,
CHANNEL_WIDTH = 1,
USE_ERROR = 0,
ERROR_WIDTH = 1,
// Derived parameters
SYMBOLS_PER_BEAT = DATA_WIDTH / BITS_PER_SYMBOL,
EMPTY_WV = USE_PACKETS ? (
(SYMBOLS_PER_BEAT > 128) ? 8 :
(SYMBOLS_PER_BEAT > 64) ? 7 :
(SYMBOLS_PER_BEAT > 32) ? 6 :
(SYMBOLS_PER_BEAT > 16) ? 5 :
(SYMBOLS_PER_BEAT > 8) ? 4 :
(SYMBOLS_PER_BEAT > 4) ? 3 :
(SYMBOLS_PER_BEAT > 2) ? 2 :
(SYMBOLS_PER_BEAT > 1) ? 1 :
1) : 1,
CHANNEL_WV = USE_CHANNEL ? CHANNEL_WIDTH : 1,
ERROR_WV = USE_ERROR ? ERROR_WIDTH : 1
)
(
input wire in0_valid,
input wire [DATA_WIDTH-1 :0] in0_data,
input wire [CHANNEL_WV-1 :0] in0_channel,
input wire [ERROR_WV-1 :0] in0_error,
input wire in0_startofpacket,
input wire in0_endofpacket,
input wire [EMPTY_WV-1 :0] in0_empty,
output wire out0_valid,
output wire [DATA_WIDTH-1 :0] out0_data,
output wire [CHANNEL_WV-1 :0] out0_channel,
output wire [ERROR_WV-1 :0] out0_error,
output wire out0_startofpacket,
output wire out0_endofpacket,
output wire [EMPTY_WV-1 :0] out0_empty,
input wire reset_n,
input wire clk
);
// ********************************************************************
// Module Wiring
wire [16:0] OutValid;
wire [DATA_WIDTH-1 :0] OutData [16:0];
wire [CHANNEL_WV-1 :0] OutChannel [16:0];
wire [ERROR_WV-1 :0] OutError [16:0];
wire [16:0] OutSOP;
wire [16:0] OutEOP;
wire [EMPTY_WV-1 :0] OutEmpty [16:0];
genvar i;
// ********************************************************************
// Module Logic
assign OutValid[0] = in0_valid;
assign OutData[0] = in0_data;
assign OutChannel[0] = in0_channel;
assign OutError[0] = in0_error;
assign OutSOP[0] = in0_startofpacket;
assign OutEOP[0] = in0_endofpacket;
assign OutEmpty[0] = in0_empty;
generate
for (i=0; i < NUMBER_OF_DELAY_CLOCKS; i=i+1) begin : DELAY_PORT
altera_st_delay_reg #(DATA_WIDTH, CHANNEL_WV, ERROR_WV, EMPTY_WV) U
(OutValid[i],
OutData[i],
OutChannel[i],
OutError[i],
OutSOP[i],
OutEOP[i],
OutEmpty[i],
OutValid[i+1],
OutData[i+1],
OutChannel[i+1],
OutError[i+1],
OutSOP[i+1],
OutEOP[i+1],
OutEmpty[i+1],
reset_n,
clk);
end
endgenerate
assign out0_valid = OutValid[NUMBER_OF_DELAY_CLOCKS];
assign out0_data = OutData[NUMBER_OF_DELAY_CLOCKS];
assign out0_channel = OutChannel[NUMBER_OF_DELAY_CLOCKS];
assign out0_error = OutError[NUMBER_OF_DELAY_CLOCKS];
assign out0_startofpacket = OutSOP[NUMBER_OF_DELAY_CLOCKS];
assign out0_endofpacket = OutEOP[NUMBER_OF_DELAY_CLOCKS];
assign out0_empty = OutEmpty[NUMBER_OF_DELAY_CLOCKS];
endmodule
module altera_st_delay_reg #(
parameter DATA_WIDTH = 8, CHANNEL_WV = 1, ERROR_WV = 1, EMPTY_WV = 1)
(
input wire in_valid,
input wire [DATA_WIDTH-1 :0] in_data,
input wire [CHANNEL_WV-1 :0] in_channel,
input wire [ERROR_WV-1 :0] in_error,
input wire in_startofpacket,
input wire in_endofpacket,
input wire [EMPTY_WV-1 :0] in_empty,
output reg out_valid,
output reg [DATA_WIDTH-1 :0] out_data,
output reg [CHANNEL_WV-1 :0] out_channel,
output reg [ERROR_WV-1 :0] out_error,
output reg out_startofpacket,
output reg out_endofpacket,
output reg [EMPTY_WV-1 :0] out_empty,
input wire reset_n,
input wire clk
);
always @(posedge clk) begin
if (!reset_n)
out_valid <= 1'b0;
else
out_valid <= in_valid;
end
always @(posedge clk) begin
out_data <= in_data;
out_channel <= in_channel;
out_error <= in_error;
out_startofpacket <= in_startofpacket;
out_endofpacket <= in_endofpacket;
out_empty <= in_empty;
end
endmodule
libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_st_handshake_clock_crosser.v 0 → 100644
+ 212
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View file @ c3575bc3
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// -----------------------------------------------
// Clock crosser module with handshaking mechanism
// -----------------------------------------------
module altera_avalon_st_handshake_clock_crosser
#(
parameter DATA_WIDTH = 8,
BITS_PER_SYMBOL = 8,
USE_PACKETS = 0,
// ------------------------------
// Optional signal widths
// ------------------------------
USE_CHANNEL = 0,
CHANNEL_WIDTH = 1,
USE_ERROR = 0,
ERROR_WIDTH = 1,
VALID_SYNC_DEPTH = 2,
READY_SYNC_DEPTH = 2,
USE_OUTPUT_PIPELINE = 1,
// ------------------------------
// Derived parameters
// ------------------------------
SYMBOLS_PER_BEAT = DATA_WIDTH / BITS_PER_SYMBOL,
EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
input in_clk,
input in_reset,
input out_clk,
input out_reset,
output in_ready,
input in_valid,
input [DATA_WIDTH - 1 : 0] in_data,
input [CHANNEL_WIDTH - 1 : 0] in_channel,
input [ERROR_WIDTH - 1 : 0] in_error,
input in_startofpacket,
input in_endofpacket,
input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
input out_ready,
output out_valid,
output [DATA_WIDTH - 1 : 0] out_data,
output [CHANNEL_WIDTH - 1 : 0] out_channel,
output [ERROR_WIDTH - 1 : 0] out_error,
output out_startofpacket,
output out_endofpacket,
output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
);
// ------------------------------
// Payload-specific widths
// ------------------------------
localparam PACKET_WIDTH = (USE_PACKETS) ? 2 + EMPTY_WIDTH : 0;
localparam PCHANNEL_W = (USE_CHANNEL) ? CHANNEL_WIDTH : 0;
localparam PERROR_W = (USE_ERROR) ? ERROR_WIDTH : 0;
localparam PAYLOAD_WIDTH = DATA_WIDTH +
PACKET_WIDTH +
PCHANNEL_W +
EMPTY_WIDTH +
PERROR_W;
wire [PAYLOAD_WIDTH - 1: 0] in_payload;
wire [PAYLOAD_WIDTH - 1: 0] out_payload;
// ------------------------------
// Assign in_data and other optional sink interface
// signals to in_payload.
// ------------------------------
assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
generate
// optional packet inputs
if (PACKET_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH - 1 :
DATA_WIDTH
] = {in_startofpacket, in_endofpacket};
end
// optional channel input
if (USE_CHANNEL) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
] = in_channel;
end
// optional empty input
if (EMPTY_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
] = in_empty;
end
// optional error input
if (USE_ERROR) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
] = in_error;
end
endgenerate
// --------------------------------------------------
// Pipe the input payload to our inner module which handles the
// actual clock crossing
// --------------------------------------------------
altera_avalon_st_clock_crosser
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (PAYLOAD_WIDTH),
.FORWARD_SYNC_DEPTH (VALID_SYNC_DEPTH),
.BACKWARD_SYNC_DEPTH (READY_SYNC_DEPTH),
.USE_OUTPUT_PIPELINE (USE_OUTPUT_PIPELINE)
) clock_xer (
.in_clk (in_clk ),
.in_reset (in_reset ),
.in_ready (in_ready ),
.in_valid (in_valid ),
.in_data (in_payload ),
.out_clk (out_clk ),
.out_reset (out_reset ),
.out_ready (out_ready ),
.out_valid (out_valid ),
.out_data (out_payload )
);
// --------------------------------------------------
// Split out_payload into the output signals.
// --------------------------------------------------
assign out_data = out_payload[DATA_WIDTH - 1 : 0];
generate
// optional packet outputs
if (USE_PACKETS) begin
assign {out_startofpacket, out_endofpacket} =
out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
end else begin
// avoid a "has no driver" warning.
assign {out_startofpacket, out_endofpacket} = 2'b0;
end
// optional channel output
if (USE_CHANNEL) begin
assign out_channel = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_channel = 1'b0;
end
// optional empty output
if (EMPTY_WIDTH) begin
assign out_empty = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
];
end else begin
// avoid a "has no driver" warning.
assign out_empty = 1'b0;
end
// optional error output
if (USE_ERROR) begin
assign out_error = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_error = 1'b0;
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value.
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_st_pipeline_base.v 0 → 100644
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View file @ c3575bc3
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1ns / 1ns
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter PIPELINE_READY = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input clk;
input reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
reg full0;
reg full1;
reg [DATA_WIDTH-1:0] data0;
reg [DATA_WIDTH-1:0] data1;
assign out_valid = full1;
assign out_data = data1;
generate if (PIPELINE_READY == 1)
begin : REGISTERED_READY_PLINE
assign in_ready = !full0;
always @(posedge clk, posedge reset) begin
if (reset) begin
data0 <= 1'b0;
data1 <= 1'b0;
end else begin
// ----------------------------
// always load the second slot if we can
// ----------------------------
if (~full0)
data0 <= in_data;
// ----------------------------
// first slot is loaded either from the second,
// or with new data
// ----------------------------
if (~full1 || (out_ready && out_valid)) begin
if (full0)
data1 <= data0;
else
data1 <= in_data;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
full0 <= 1'b0;
full1 <= 1'b0;
end else begin
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end
else
begin : UNREGISTERED_READY_PLINE
// in_ready will be a pass through of the out_ready signal as it is not registered
assign in_ready = (~full1) | out_ready;
always @(posedge clk or posedge reset) begin
if (reset) begin
data1 <= 'b0;
full1 <= 1'b0;
end
else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end
endgenerate
endmodule
libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_st_pipeline_stage.sv 0 → 100644
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− 0
View file @ c3575bc3
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1ns / 1ns
module altera_avalon_st_pipeline_stage #(
parameter
SYMBOLS_PER_BEAT = 1,
BITS_PER_SYMBOL = 8,
USE_PACKETS = 0,
USE_EMPTY = 0,
PIPELINE_READY = 1,
// Optional ST signal widths. Value "0" means no such port.
CHANNEL_WIDTH = 0,
ERROR_WIDTH = 0,
// Derived parameters
DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
PACKET_WIDTH = 0,
EMPTY_WIDTH = 0
)
(
input clk,
input reset,
output in_ready,
input in_valid,
input [DATA_WIDTH - 1 : 0] in_data,
input [(CHANNEL_WIDTH ? (CHANNEL_WIDTH - 1) : 0) : 0] in_channel,
input [(ERROR_WIDTH ? (ERROR_WIDTH - 1) : 0) : 0] in_error,
input in_startofpacket,
input in_endofpacket,
input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
input out_ready,
output out_valid,
output [DATA_WIDTH - 1 : 0] out_data,
output [(CHANNEL_WIDTH ? (CHANNEL_WIDTH - 1) : 0) : 0] out_channel,
output [(ERROR_WIDTH ? (ERROR_WIDTH - 1) : 0) : 0] out_error,
output out_startofpacket,
output out_endofpacket,
output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
);
localparam
PAYLOAD_WIDTH =
DATA_WIDTH +
PACKET_WIDTH +
CHANNEL_WIDTH +
EMPTY_WIDTH +
ERROR_WIDTH;
wire [PAYLOAD_WIDTH - 1: 0] in_payload;
wire [PAYLOAD_WIDTH - 1: 0] out_payload;
// Assign in_data and other optional in_* interface signals to in_payload.
assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
generate
// optional packet inputs
if (PACKET_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH - 1 :
DATA_WIDTH
] = {in_startofpacket, in_endofpacket};
end
// optional channel input
if (CHANNEL_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH
] = in_channel;
end
// optional empty input
if (EMPTY_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH
] = in_empty;
end
// optional error input
if (ERROR_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ERROR_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH
] = in_error;
end
endgenerate
altera_avalon_st_pipeline_base #(
.SYMBOLS_PER_BEAT (PAYLOAD_WIDTH),
.BITS_PER_SYMBOL (1),
.PIPELINE_READY (PIPELINE_READY)
) core (
.clk (clk),
.reset (reset),
.in_ready (in_ready),
.in_valid (in_valid),
.in_data (in_payload),
.out_ready (out_ready),
.out_valid (out_valid),
.out_data (out_payload)
);
// Assign out_data and other optional out_* interface signals from out_payload.
assign out_data = out_payload[DATA_WIDTH - 1 : 0];
generate
// optional packet outputs
if (PACKET_WIDTH) begin
assign {out_startofpacket, out_endofpacket} =
out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
end else begin
// Avoid a "has no driver" warning.
assign {out_startofpacket, out_endofpacket} = '0;
end
// optional channel output
if (CHANNEL_WIDTH) begin
assign out_channel = out_payload[
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH
];
end else begin
// Avoid a "has no driver" warning.
assign out_channel = '0;
end
// optional empty output
if (EMPTY_WIDTH) begin
assign out_empty = out_payload[
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH
];
end else begin
// Avoid a "has no driver" warning.
assign out_empty = '0;
end
// optional error output
if (ERROR_WIDTH) begin
assign out_error = out_payload[
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ERROR_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH
];
end else begin
// Avoid a "has no driver" warning.
assign out_error = '0;
end
endgenerate
endmodule
libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_st_splitter.sv 0 → 100644
+ 415
− 0
View file @ c3575bc3
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1ns / 1ns
module altera_avalon_st_splitter #(
parameter
NUMBER_OF_OUTPUTS = 2,
QUALIFY_VALID_OUT = 1,
DATA_WIDTH = 8,
BITS_PER_SYMBOL = 8,
USE_PACKETS = 0,
CHANNEL_WIDTH = 1,
ERROR_WIDTH = 1,
EMPTY_WIDTH = 1
)
(
output wire in0_ready,
input wire in0_valid,
input wire [DATA_WIDTH-1 :0] in0_data,
input wire [CHANNEL_WIDTH-1 :0] in0_channel,
input wire [ERROR_WIDTH-1 :0] in0_error,
input wire in0_startofpacket,
input wire in0_endofpacket,
input wire [EMPTY_WIDTH-1 :0] in0_empty,
input wire out0_ready,
output wire out0_valid,
output wire [DATA_WIDTH-1 :0] out0_data,
output wire [CHANNEL_WIDTH-1 :0] out0_channel,
output wire [ERROR_WIDTH-1 :0] out0_error,
output wire out0_startofpacket,
output wire out0_endofpacket,
output wire [EMPTY_WIDTH-1 :0] out0_empty,
input wire out1_ready,
output wire out1_valid,
output wire [DATA_WIDTH-1 :0] out1_data,
output wire [CHANNEL_WIDTH-1 :0] out1_channel,
output wire [ERROR_WIDTH-1 :0] out1_error,
output wire out1_startofpacket,
output wire out1_endofpacket,
output wire [EMPTY_WIDTH-1 :0] out1_empty,
input wire out2_ready,
output wire out2_valid,
output wire [DATA_WIDTH-1 :0] out2_data,
output wire [CHANNEL_WIDTH-1 :0] out2_channel,
output wire [ERROR_WIDTH-1 :0] out2_error,
output wire out2_startofpacket,
output wire out2_endofpacket,
output wire [EMPTY_WIDTH-1 :0] out2_empty,
input wire out3_ready,
output wire out3_valid,
output wire [DATA_WIDTH-1 :0] out3_data,
output wire [CHANNEL_WIDTH-1 :0] out3_channel,
output wire [ERROR_WIDTH-1 :0] out3_error,
output wire out3_startofpacket,
output wire out3_endofpacket,
output wire [EMPTY_WIDTH-1 :0] out3_empty,
input wire out4_ready,
output wire out4_valid,
output wire [DATA_WIDTH-1 :0] out4_data,
output wire [CHANNEL_WIDTH-1 :0] out4_channel,
output wire [ERROR_WIDTH-1 :0] out4_error,
output wire out4_startofpacket,
output wire out4_endofpacket,
output wire [EMPTY_WIDTH-1 :0] out4_empty,
input wire out5_ready,
output wire out5_valid,
output wire [DATA_WIDTH-1 :0] out5_data,
output wire [CHANNEL_WIDTH-1 :0] out5_channel,
output wire [ERROR_WIDTH-1 :0] out5_error,
output wire out5_startofpacket,
output wire out5_endofpacket,
output wire [EMPTY_WIDTH-1 :0] out5_empty,
input wire out6_ready,
output wire out6_valid,
output wire [DATA_WIDTH-1 :0] out6_data,
output wire [CHANNEL_WIDTH-1 :0] out6_channel,
output wire [ERROR_WIDTH-1 :0] out6_error,
output wire out6_startofpacket,
output wire out6_endofpacket,
output wire [EMPTY_WIDTH-1 :0] out6_empty,
input wire out7_ready,
output wire out7_valid,
output wire [DATA_WIDTH-1 :0] out7_data,
output wire [CHANNEL_WIDTH-1 :0] out7_channel,
output wire [ERROR_WIDTH-1 :0] out7_error,
output wire out7_startofpacket,
output wire out7_endofpacket,
output wire [EMPTY_WIDTH-1 :0] out7_empty,
input wire out8_ready,
output wire out8_valid,
output wire [DATA_WIDTH-1 :0] out8_data,
output wire [CHANNEL_WIDTH-1 :0] out8_channel,
output wire [ERROR_WIDTH-1 :0] out8_error,
output wire out8_startofpacket,
output wire out8_endofpacket,
output wire [EMPTY_WIDTH-1 :0] out8_empty,
input wire out9_ready,
output wire out9_valid,
output wire [DATA_WIDTH-1 :0] out9_data,
output wire [CHANNEL_WIDTH-1 :0] out9_channel,
output wire [ERROR_WIDTH-1 :0] out9_error,
output wire out9_startofpacket,
output wire out9_endofpacket,
output wire [EMPTY_WIDTH-1 :0] out9_empty,
input wire out10_ready,
output wire out10_valid,
output wire [DATA_WIDTH-1 :0] out10_data,
output wire [CHANNEL_WIDTH-1 :0] out10_channel,
output wire [ERROR_WIDTH-1 :0] out10_error,
output wire out10_startofpacket,
output wire out10_endofpacket,
output wire [EMPTY_WIDTH-1 :0] out10_empty,
input wire out11_ready,
output wire out11_valid,
output wire [DATA_WIDTH-1 :0] out11_data,
output wire [CHANNEL_WIDTH-1 :0] out11_channel,
output wire [ERROR_WIDTH-1 :0] out11_error,
output wire out11_startofpacket,
output wire out11_endofpacket,
output wire [EMPTY_WIDTH-1 :0] out11_empty,
input wire out12_ready,
output wire out12_valid,
output wire [DATA_WIDTH-1 :0] out12_data,
output wire [CHANNEL_WIDTH-1 :0] out12_channel,
output wire [ERROR_WIDTH-1 :0] out12_error,
output wire out12_startofpacket,
output wire out12_endofpacket,
output wire [EMPTY_WIDTH-1 :0] out12_empty,
input wire out13_ready,
output wire out13_valid,
output wire [DATA_WIDTH-1 :0] out13_data,
output wire [CHANNEL_WIDTH-1 :0] out13_channel,
output wire [ERROR_WIDTH-1 :0] out13_error,
output wire out13_startofpacket,
output wire out13_endofpacket,
output wire [EMPTY_WIDTH-1 :0] out13_empty,
input wire out14_ready,
output wire out14_valid,
output wire [DATA_WIDTH-1 :0] out14_data,
output wire [CHANNEL_WIDTH-1 :0] out14_channel,
output wire [ERROR_WIDTH-1 :0] out14_error,
output wire out14_startofpacket,
output wire out14_endofpacket,
output wire [EMPTY_WIDTH-1 :0] out14_empty,
input wire out15_ready,
output wire out15_valid,
output wire [DATA_WIDTH-1 :0] out15_data,
output wire [CHANNEL_WIDTH-1 :0] out15_channel,
output wire [ERROR_WIDTH-1 :0] out15_error,
output wire out15_startofpacket,
output wire out15_endofpacket,
output wire [EMPTY_WIDTH-1 :0] out15_empty,
input wire clk
);
// ********************************************************************
// Module Wiring
wire [15:0] OutReady;
wire [15:0] OutValid;
wire [DATA_WIDTH-1 :0] OutData [15:0];
wire [CHANNEL_WIDTH-1 :0] OutChannel [15:0];
wire [ERROR_WIDTH-1 :0] OutError [15:0];
wire [15:0] OutSOP;
wire [15:0] OutEOP;
wire [EMPTY_WIDTH-1 :0] OutEmpty [15:0];
genvar i, j;
// ********************************************************************
// Module Logic
assign in0_ready = &(OutReady[NUMBER_OF_OUTPUTS-1:0]);
generate
for (i=0; i < NUMBER_OF_OUTPUTS; i=i+1) begin : SPLIT_PORT
assign OutData[i] = in0_data;
assign OutChannel[i] = in0_channel;
assign OutError[i] = in0_error;
assign OutSOP[i] = in0_startofpacket;
assign OutEOP[i] = in0_endofpacket;
assign OutEmpty[i] = in0_empty;
end
endgenerate
generate
for (j=NUMBER_OF_OUTPUTS; j <16; j=j+1) begin : NULL_PORT
assign OutData[j] = {DATA_WIDTH{1'b0}};
assign OutChannel[j] = {CHANNEL_WIDTH{1'b0}};
assign OutError[j] = {ERROR_WIDTH{1'b0}};
assign OutSOP[j] = 1'b0;
assign OutEOP[j] = 1'b0;
assign OutEmpty[j] = {EMPTY_WIDTH{1'b0}};
end
endgenerate
generate
if (QUALIFY_VALID_OUT) begin
assign OutValid[0] = &{in0_valid, OutReady[15:1]};
assign OutValid[1] = &{in0_valid, OutReady[15:2], OutReady[0]};
assign OutValid[2] = &{in0_valid, OutReady[15:3], OutReady[1:0]};
assign OutValid[3] = &{in0_valid, OutReady[15:4], OutReady[2:0]};
assign OutValid[4] = &{in0_valid, OutReady[15:5], OutReady[3:0]};
assign OutValid[5] = &{in0_valid, OutReady[15:6], OutReady[4:0]};
assign OutValid[6] = &{in0_valid, OutReady[15:7], OutReady[5:0]};
assign OutValid[7] = &{in0_valid, OutReady[15:8], OutReady[6:0]};
assign OutValid[8] = &{in0_valid, OutReady[15:9], OutReady[7:0]};
assign OutValid[9] = &{in0_valid, OutReady[15:10], OutReady[8:0]};
assign OutValid[10] = &{in0_valid, OutReady[15:11], OutReady[9:0]};
assign OutValid[11] = &{in0_valid, OutReady[15:12], OutReady[10:0]};
assign OutValid[12] = &{in0_valid, OutReady[15:13], OutReady[11:0]};
assign OutValid[13] = &{in0_valid, OutReady[15:14], OutReady[12:0]};
assign OutValid[14] = &{in0_valid, OutReady[15], OutReady[13:0]};
assign OutValid[15] = &{in0_valid, OutReady[14:0]};
end
else begin
assign OutValid[0] = in0_valid;
assign OutValid[1] = in0_valid;
assign OutValid[2] = in0_valid;
assign OutValid[3] = in0_valid;
assign OutValid[4] = in0_valid;
assign OutValid[5] = in0_valid;
assign OutValid[6] = in0_valid;
assign OutValid[7] = in0_valid;
assign OutValid[8] = in0_valid;
assign OutValid[9] = in0_valid;
assign OutValid[10] = in0_valid;
assign OutValid[11] = in0_valid;
assign OutValid[12] = in0_valid;
assign OutValid[13] = in0_valid;
assign OutValid[14] = in0_valid;
assign OutValid[15] = in0_valid;
end
endgenerate
assign OutReady[0] = out0_ready;
assign out0_valid = OutValid[0];
assign out0_data = OutData[0];
assign out0_channel = OutChannel[0];
assign out0_error = OutError[0];
assign out0_startofpacket = OutSOP[0];
assign out0_endofpacket = OutEOP[0];
assign out0_empty = OutEmpty[0];
assign OutReady[1] = out1_ready;
assign out1_valid = OutValid[1];
assign out1_data = OutData[1];
assign out1_channel = OutChannel[1];
assign out1_error = OutError[1];
assign out1_startofpacket = OutSOP[1];
assign out1_endofpacket = OutEOP[1];
assign out1_empty = OutEmpty[1];
assign OutReady[2] = out2_ready;
assign out2_valid = OutValid[2];
assign out2_data = OutData[2];
assign out2_channel = OutChannel[2];
assign out2_error = OutError[2];
assign out2_startofpacket = OutSOP[2];
assign out2_endofpacket = OutEOP[2];
assign out2_empty = OutEmpty[2];
assign OutReady[3] = out3_ready;
assign out3_valid = OutValid[3];
assign out3_data = OutData[3];
assign out3_channel = OutChannel[3];
assign out3_error = OutError[3];
assign out3_startofpacket = OutSOP[3];
assign out3_endofpacket = OutEOP[3];
assign out3_empty = OutEmpty[3];
assign OutReady[4] = out4_ready;
assign out4_valid = OutValid[4];
assign out4_data = OutData[4];
assign out4_channel = OutChannel[4];
assign out4_error = OutError[4];
assign out4_startofpacket = OutSOP[4];
assign out4_endofpacket = OutEOP[4];
assign out4_empty = OutEmpty[4];
assign OutReady[5] = out5_ready;
assign out5_valid = OutValid[5];
assign out5_data = OutData[5];
assign out5_channel = OutChannel[5];
assign out5_error = OutError[5];
assign out5_startofpacket = OutSOP[5];
assign out5_endofpacket = OutEOP[5];
assign out5_empty = OutEmpty[5];
assign OutReady[6] = out6_ready;
assign out6_valid = OutValid[6];
assign out6_data = OutData[6];
assign out6_channel = OutChannel[6];
assign out6_error = OutError[6];
assign out6_startofpacket = OutSOP[6];
assign out6_endofpacket = OutEOP[6];
assign out6_empty = OutEmpty[6];
assign OutReady[7] = out7_ready;
assign out7_valid = OutValid[7];
assign out7_data = OutData[7];
assign out7_channel = OutChannel[7];
assign out7_error = OutError[7];
assign out7_startofpacket = OutSOP[7];
assign out7_endofpacket = OutEOP[7];
assign out7_empty = OutEmpty[7];
assign OutReady[8] = out8_ready;
assign out8_valid = OutValid[8];
assign out8_data = OutData[8];
assign out8_channel = OutChannel[8];
assign out8_error = OutError[8];
assign out8_startofpacket = OutSOP[8];
assign out8_endofpacket = OutEOP[8];
assign out8_empty = OutEmpty[8];
assign OutReady[9] = out9_ready;
assign out9_valid = OutValid[9];
assign out9_data = OutData[9];
assign out9_channel = OutChannel[9];
assign out9_error = OutError[9];
assign out9_startofpacket = OutSOP[9];
assign out9_endofpacket = OutEOP[9];
assign out9_empty = OutEmpty[9];
assign OutReady[10] = out10_ready;
assign out10_valid = OutValid[10];
assign out10_data = OutData[10];
assign out10_channel = OutChannel[10];
assign out10_error = OutError[10];
assign out10_startofpacket = OutSOP[10];
assign out10_endofpacket = OutEOP[10];
assign out10_empty = OutEmpty[10];
assign OutReady[11] = out11_ready;
assign out11_valid = OutValid[11];
assign out11_data = OutData[11];
assign out11_channel = OutChannel[11];
assign out11_error = OutError[11];
assign out11_startofpacket = OutSOP[11];
assign out11_endofpacket = OutEOP[11];
assign out11_empty = OutEmpty[11];
assign OutReady[12] = out12_ready;
assign out12_valid = OutValid[12];
assign out12_data = OutData[12];
assign out12_channel = OutChannel[12];
assign out12_error = OutError[12];
assign out12_startofpacket = OutSOP[12];
assign out12_endofpacket = OutEOP[12];
assign out12_empty = OutEmpty[12];
assign OutReady[13] = out13_ready;
assign out13_valid = OutValid[13];
assign out13_data = OutData[13];
assign out13_channel = OutChannel[13];
assign out13_error = OutError[13];
assign out13_startofpacket = OutSOP[13];
assign out13_endofpacket = OutEOP[13];
assign out13_empty = OutEmpty[13];
assign OutReady[14] = out14_ready;
assign out14_valid = OutValid[14];
assign out14_data = OutData[14];
assign out14_channel = OutChannel[14];
assign out14_error = OutError[14];
assign out14_startofpacket = OutSOP[14];
assign out14_endofpacket = OutEOP[14];
assign out14_empty = OutEmpty[14];
assign OutReady[15] = out15_ready;
assign out15_valid = OutValid[15];
assign out15_data = OutData[15];
assign out15_channel = OutChannel[15];
assign out15_error = OutError[15];
assign out15_startofpacket = OutSOP[15];
assign out15_endofpacket = OutEOP[15];
assign out15_empty = OutEmpty[15];
endmodule
libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_dcfifo_synchronizer_bundle.v 0 → 100644
+ 50
− 0
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// $Id: //acds/main/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer_bundle.v#1 $
// $Revision: #1 $
// $Date: 2008/09/23 $
//----------------------------------------------------------------
//
// File: altera_dcfifo_synchronizer_bundle.v
//
// Abstract: Bundle of bit synchronizers.
// WARNING: only use this to synchronize a bundle of
// *independent* single bit signals or a Gray encoded
// bus of signals. Also remember that pulses entering
// the synchronizer will be swallowed upon a metastable
// condition if the pulse width is shorter than twice
// the synchronizing clock period.
//
// Copyright (C) Altera Corporation 2008, All Rights Reserved
//----------------------------------------------------------------
`timescale 1 ns / 1 ns
module altera_dcfifo_synchronizer_bundle(
clk,
reset_n,
din,
dout
);
parameter WIDTH = 1;
parameter DEPTH = 3;
input clk;
input reset_n;
input [WIDTH-1:0] din;
output [WIDTH-1:0] dout;
genvar i;
generate
for (i=0; i<WIDTH; i=i+1)
begin : sync
altera_std_synchronizer #(.depth(DEPTH))
u (
.clk(clk),
.reset_n(reset_n),
.din(din[i]),
.dout(dout[i])
);
end
endgenerate
endmodule
libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_eth_crc.ocp 0 → 100644
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File added
libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_eth_crc.v 0 → 100644
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File added
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