diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g.qip b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g.qip
new file mode 100644
index 0000000000000000000000000000000000000000..ae289bf47185a44865b37dcaab2182ec637a607a
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g.qip
@@ -0,0 +1,279 @@
+set_global_assignment -entity "ip_stratixiv_mac_10g" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_10g_mac"
+set_global_assignment -entity "ip_stratixiv_mac_10g" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1sp2"
+set_global_assignment -entity "ip_stratixiv_mac_10g" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VHDL_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g.vhd]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_0002.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_avalon_st_handshake_clock_crosser.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_avalon_st_clock_crosser.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_avalon_st_pipeline_base.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_merlin_arbitrator.sv]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rsp_xbar_mux_002.sv]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rsp_xbar_demux_010.sv]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_cmd_xbar_demux_002.sv]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rsp_xbar_mux_001.sv]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rsp_xbar_demux_002.sv]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_cmd_xbar_demux_001.sv]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rsp_xbar_mux.sv]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rsp_xbar_demux.sv]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_cmd_xbar_demux.sv]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_reset_controller.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_reset_synchronizer.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SDC_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_reset_controller.sdc]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_merlin_traffic_limiter.sv]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_id_router_010.sv]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_addr_router_002.sv]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_id_router_002.sv]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_addr_router_001.sv]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_id_router.sv]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_addr_router.sv]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_merlin_master_agent.sv]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_avalon_sc_fifo.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_merlin_slave_agent.sv]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_merlin_burst_uncompressor.sv]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_merlin_slave_translator.sv]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_tx.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_rx.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_avalon_dc_fifo.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_dcfifo_synchronizer_bundle.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SDC_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_avalon_dc_fifo.sdc]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_export.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_rx.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rx_st_error_adapter_stat.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_avalon_st_delay.sv]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_packet_overflow_control.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_packet_overflow_control.ocp]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_crc_pad_rem.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_crc_pad_rem.ocp]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_crc_rem.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_packet_stripper.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_avalon_st_pipeline_stage.sv]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_frame_status_merger.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rx_timing_adapter_frame_status_out_frame_decoder.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rx_st_timing_adapter_frame_status_in.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_lane_decoder.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_lane_decoder.ocp]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_link_fault_detection.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_link_fault_detection.ocp]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rx_st_timing_adapter_lane_decoder.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rx_st_timing_adapter_interface_conversion.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_link_fault_generation.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_link_fault_generation.ocp]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_xgmii_termination.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_xgmii_termination.ocp]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_packet_formatter.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_packet_formatter.ocp]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_10gmem_statistics_collector.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_10gmem_statistics_collector.ocp]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_output.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_in.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_tx_st_error_adapter_stat.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_frame_decoder.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_frame_decoder.ocp]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_tx_st_timing_adapter_frame_decoder.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_avalon_st_splitter.sv]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_crc.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_crc.ocp]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/crc32.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/gf_mult32_kc.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_address_inserter.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_address_inserter.ocp]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_tx_st_mux_flow_control_user_frame.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_tx_st_pause_ctrl_error_adapter.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_pause_controller.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_pause_ctrl_gen.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_pause_ctrl_gen.ocp]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_pause_gen.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_pause_beat_conversion.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_pkt_backpressure_control.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_pkt_backpressure_control.ocp]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_pad_inserter.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_pad_inserter.ocp]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_packet_underflow_control.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_eth_packet_underflow_control.ocp]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_avalon_mm_bridge.v]
+set_global_assignment -library "lib_ip_stratixiv_mac_10g" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_mac_10g/altera_merlin_master_translator.sv]
+
+set_global_assignment -entity "ip_stratixiv_mac_10g_0002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_10g_mac"
+set_global_assignment -entity "ip_stratixiv_mac_10g_0002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_0002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_avalon_st_handshake_clock_crosser" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_avalon_st_handshake_clock_crosser"
+set_global_assignment -entity "altera_avalon_st_handshake_clock_crosser" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_avalon_st_handshake_clock_crosser" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_mux_002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_multiplexer"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_mux_002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_mux_002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_demux_010" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_demux_010" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_demux_010" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "ip_stratixiv_mac_10g_cmd_xbar_demux_002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
+set_global_assignment -entity "ip_stratixiv_mac_10g_cmd_xbar_demux_002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_cmd_xbar_demux_002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_mux_001" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_multiplexer"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_mux_001" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_mux_001" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_demux_002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_demux_002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_demux_002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "ip_stratixiv_mac_10g_cmd_xbar_demux_001" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
+set_global_assignment -entity "ip_stratixiv_mac_10g_cmd_xbar_demux_001" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_cmd_xbar_demux_001" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_mux" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_multiplexer"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_mux" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_mux" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_demux" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_demux" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rsp_xbar_demux" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "ip_stratixiv_mac_10g_cmd_xbar_demux" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
+set_global_assignment -entity "ip_stratixiv_mac_10g_cmd_xbar_demux" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_cmd_xbar_demux" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_reset_controller" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_reset_controller"
+set_global_assignment -entity "altera_reset_controller" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_reset_controller" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_traffic_limiter"
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "ip_stratixiv_mac_10g_id_router_010" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_router"
+set_global_assignment -entity "ip_stratixiv_mac_10g_id_router_010" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_id_router_010" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "ip_stratixiv_mac_10g_addr_router_002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_router"
+set_global_assignment -entity "ip_stratixiv_mac_10g_addr_router_002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_addr_router_002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "ip_stratixiv_mac_10g_id_router_002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_router"
+set_global_assignment -entity "ip_stratixiv_mac_10g_id_router_002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_id_router_002" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "ip_stratixiv_mac_10g_addr_router_001" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_router"
+set_global_assignment -entity "ip_stratixiv_mac_10g_addr_router_001" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_addr_router_001" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "ip_stratixiv_mac_10g_id_router" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_router"
+set_global_assignment -entity "ip_stratixiv_mac_10g_id_router" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_id_router" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "ip_stratixiv_mac_10g_addr_router" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_router"
+set_global_assignment -entity "ip_stratixiv_mac_10g_addr_router" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_addr_router" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_merlin_master_agent" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_master_agent"
+set_global_assignment -entity "altera_merlin_master_agent" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_merlin_master_agent" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_avalon_sc_fifo" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_avalon_sc_fifo"
+set_global_assignment -entity "altera_avalon_sc_fifo" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_avalon_sc_fifo" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_merlin_slave_agent" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_slave_agent"
+set_global_assignment -entity "altera_merlin_slave_agent" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_merlin_slave_agent" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_merlin_slave_translator" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_slave_translator"
+set_global_assignment -entity "altera_merlin_slave_translator" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_merlin_slave_translator" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_tx" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "timing_adapter"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_tx" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_tx" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_rx" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "timing_adapter"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_rx" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_rx" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_avalon_dc_fifo" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_avalon_dc_fifo"
+set_global_assignment -entity "altera_avalon_dc_fifo" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_avalon_dc_fifo" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_export" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "timing_adapter"
+set_global_assignment -entity "ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_export" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_export" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_rx" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "timing_adapter"
+set_global_assignment -entity "ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_rx" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_rx" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rx_st_error_adapter_stat" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "error_adapter"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rx_st_error_adapter_stat" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rx_st_error_adapter_stat" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_avalon_st_delay" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_avalon_st_delay"
+set_global_assignment -entity "altera_avalon_st_delay" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_avalon_st_delay" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_eth_packet_overflow_control" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_packet_overflow_control"
+set_global_assignment -entity "altera_eth_packet_overflow_control" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_eth_packet_overflow_control" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_eth_crc_pad_rem" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_crc_pad_rem"
+set_global_assignment -entity "altera_eth_crc_pad_rem" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_eth_crc_pad_rem" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_eth_frame_status_merger" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_frame_status_merger"
+set_global_assignment -entity "altera_eth_frame_status_merger" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_eth_frame_status_merger" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rx_timing_adapter_frame_status_out_frame_decoder" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "timing_adapter"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rx_timing_adapter_frame_status_out_frame_decoder" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rx_timing_adapter_frame_status_out_frame_decoder" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rx_st_timing_adapter_frame_status_in" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "timing_adapter"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rx_st_timing_adapter_frame_status_in" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rx_st_timing_adapter_frame_status_in" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_eth_lane_decoder" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_lane_decoder"
+set_global_assignment -entity "altera_eth_lane_decoder" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_eth_lane_decoder" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_eth_link_fault_detection" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_link_fault_detection"
+set_global_assignment -entity "altera_eth_link_fault_detection" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_eth_link_fault_detection" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rx_st_timing_adapter_lane_decoder" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "timing_adapter"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rx_st_timing_adapter_lane_decoder" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rx_st_timing_adapter_lane_decoder" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rx_st_timing_adapter_interface_conversion" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "timing_adapter"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rx_st_timing_adapter_interface_conversion" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_rx_st_timing_adapter_interface_conversion" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_eth_link_fault_generation" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_link_fault_generation"
+set_global_assignment -entity "altera_eth_link_fault_generation" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_eth_link_fault_generation" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_eth_xgmii_termination" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_xgmii_termination"
+set_global_assignment -entity "altera_eth_xgmii_termination" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_eth_xgmii_termination" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_eth_packet_formatter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_packet_formatter"
+set_global_assignment -entity "altera_eth_packet_formatter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_eth_packet_formatter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_eth_10gmem_statistics_collector" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_10gmem_statistics_collector"
+set_global_assignment -entity "altera_eth_10gmem_statistics_collector" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_eth_10gmem_statistics_collector" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_output" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "timing_adapter"
+set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_output" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_output" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_in" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "timing_adapter"
+set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_in" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_in" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_error_adapter_stat" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "error_adapter"
+set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_error_adapter_stat" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_error_adapter_stat" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_eth_frame_decoder" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_frame_decoder"
+set_global_assignment -entity "altera_eth_frame_decoder" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_eth_frame_decoder" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_timing_adapter_frame_decoder" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "timing_adapter"
+set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_timing_adapter_frame_decoder" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_timing_adapter_frame_decoder" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_avalon_st_splitter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_avalon_st_splitter"
+set_global_assignment -entity "altera_avalon_st_splitter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_avalon_st_splitter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_avalon_st_pipeline_stage" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_avalon_st_pipeline_stage"
+set_global_assignment -entity "altera_avalon_st_pipeline_stage" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_avalon_st_pipeline_stage" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_eth_crc" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_crc"
+set_global_assignment -entity "altera_eth_crc" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_eth_crc" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_eth_address_inserter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_address_inserter"
+set_global_assignment -entity "altera_eth_address_inserter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_eth_address_inserter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_mux_flow_control_user_frame" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "multiplexer"
+set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_mux_flow_control_user_frame" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_mux_flow_control_user_frame" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_pause_ctrl_error_adapter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "error_adapter"
+set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_pause_ctrl_error_adapter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "ip_stratixiv_mac_10g_tx_st_pause_ctrl_error_adapter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_eth_pause_ctrl_gen" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_pause_ctrl_gen"
+set_global_assignment -entity "altera_eth_pause_ctrl_gen" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_eth_pause_ctrl_gen" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_eth_pause_beat_conversion" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_pause_beat_conversion"
+set_global_assignment -entity "altera_eth_pause_beat_conversion" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_eth_pause_beat_conversion" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_eth_pkt_backpressure_control" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_pkt_backpressure_control"
+set_global_assignment -entity "altera_eth_pkt_backpressure_control" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_eth_pkt_backpressure_control" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_eth_pad_inserter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_pad_inserter"
+set_global_assignment -entity "altera_eth_pad_inserter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_eth_pad_inserter" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_eth_packet_underflow_control" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_eth_packet_underflow_control"
+set_global_assignment -entity "altera_eth_packet_underflow_control" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_eth_packet_underflow_control" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_avalon_mm_bridge" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_avalon_mm_bridge"
+set_global_assignment -entity "altera_avalon_mm_bridge" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_avalon_mm_bridge" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_merlin_master_translator" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_NAME "altera_merlin_master_translator"
+set_global_assignment -entity "altera_merlin_master_translator" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_merlin_master_translator" -library "lib_ip_stratixiv_mac_10g" -name IP_TOOL_ENV "mwpim"
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g.vhd b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a3731cccfbdd83c0211c3e39efb4fb81786fe136
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g.vhd
@@ -0,0 +1,175 @@
+-- megafunction wizard: %Ethernet 10G MAC v11.1%
+-- GENERATION: XML
+-- ip_stratixiv_mac_10g.vhd
+
+-- Generated using ACDS version 11.1sp2 259 at 2014.10.02.11:39:42
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity ip_stratixiv_mac_10g is
+ port (
+ csr_clk_clk : in std_logic := '0'; -- csr_clk.clk
+ csr_reset_reset_n : in std_logic := '0'; -- csr_reset.reset_n
+ csr_address : in std_logic_vector(12 downto 0) := (others => '0'); -- csr.address
+ csr_waitrequest : out std_logic; -- .waitrequest
+ csr_read : in std_logic := '0'; -- .read
+ csr_readdata : out std_logic_vector(31 downto 0); -- .readdata
+ csr_write : in std_logic := '0'; -- .write
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ tx_clk_clk : in std_logic := '0'; -- tx_clk.clk
+ tx_reset_reset_n : in std_logic := '0'; -- tx_reset.reset_n
+ avalon_st_tx_startofpacket : in std_logic := '0'; -- avalon_st_tx.startofpacket
+ avalon_st_tx_valid : in std_logic := '0'; -- .valid
+ avalon_st_tx_data : in std_logic_vector(63 downto 0) := (others => '0'); -- .data
+ avalon_st_tx_empty : in std_logic_vector(2 downto 0) := (others => '0'); -- .empty
+ avalon_st_tx_ready : out std_logic; -- .ready
+ avalon_st_tx_error : in std_logic_vector(0 downto 0) := (others => '0'); -- .error
+ avalon_st_tx_endofpacket : in std_logic := '0'; -- .endofpacket
+ avalon_st_pause_data : in std_logic_vector(1 downto 0) := (others => '0'); -- avalon_st_pause.data
+ xgmii_tx_data : out std_logic_vector(71 downto 0); -- xgmii_tx.data
+ avalon_st_txstatus_valid : out std_logic; -- avalon_st_txstatus.valid
+ avalon_st_txstatus_data : out std_logic_vector(39 downto 0); -- .data
+ avalon_st_txstatus_error : out std_logic_vector(6 downto 0); -- .error
+ rx_clk_clk : in std_logic := '0'; -- rx_clk.clk
+ rx_reset_reset_n : in std_logic := '0'; -- rx_reset.reset_n
+ xgmii_rx_data : in std_logic_vector(71 downto 0) := (others => '0'); -- xgmii_rx.data
+ avalon_st_rx_startofpacket : out std_logic; -- avalon_st_rx.startofpacket
+ avalon_st_rx_endofpacket : out std_logic; -- .endofpacket
+ avalon_st_rx_valid : out std_logic; -- .valid
+ avalon_st_rx_ready : in std_logic := '0'; -- .ready
+ avalon_st_rx_data : out std_logic_vector(63 downto 0); -- .data
+ avalon_st_rx_empty : out std_logic_vector(2 downto 0); -- .empty
+ avalon_st_rx_error : out std_logic_vector(5 downto 0); -- .error
+ avalon_st_rxstatus_valid : out std_logic; -- avalon_st_rxstatus.valid
+ avalon_st_rxstatus_data : out std_logic_vector(39 downto 0); -- .data
+ avalon_st_rxstatus_error : out std_logic_vector(6 downto 0); -- .error
+ link_fault_status_xgmii_rx_data : out std_logic_vector(1 downto 0) -- link_fault_status_xgmii_rx.data
+ );
+end entity ip_stratixiv_mac_10g;
+
+architecture rtl of ip_stratixiv_mac_10g is
+ component ip_stratixiv_mac_10g_0002 is
+ port (
+ csr_clk_clk : in std_logic := 'X'; -- clk
+ csr_reset_reset_n : in std_logic := 'X'; -- reset_n
+ csr_address : in std_logic_vector(12 downto 0) := (others => 'X'); -- address
+ csr_waitrequest : out std_logic; -- waitrequest
+ csr_read : in std_logic := 'X'; -- read
+ csr_readdata : out std_logic_vector(31 downto 0); -- readdata
+ csr_write : in std_logic := 'X'; -- write
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ tx_clk_clk : in std_logic := 'X'; -- clk
+ tx_reset_reset_n : in std_logic := 'X'; -- reset_n
+ avalon_st_tx_startofpacket : in std_logic := 'X'; -- startofpacket
+ avalon_st_tx_valid : in std_logic := 'X'; -- valid
+ avalon_st_tx_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ avalon_st_tx_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ avalon_st_tx_ready : out std_logic; -- ready
+ avalon_st_tx_error : in std_logic_vector(0 downto 0) := (others => 'X'); -- error
+ avalon_st_tx_endofpacket : in std_logic := 'X'; -- endofpacket
+ avalon_st_pause_data : in std_logic_vector(1 downto 0) := (others => 'X'); -- data
+ xgmii_tx_data : out std_logic_vector(71 downto 0); -- data
+ avalon_st_txstatus_valid : out std_logic; -- valid
+ avalon_st_txstatus_data : out std_logic_vector(39 downto 0); -- data
+ avalon_st_txstatus_error : out std_logic_vector(6 downto 0); -- error
+ rx_clk_clk : in std_logic := 'X'; -- clk
+ rx_reset_reset_n : in std_logic := 'X'; -- reset_n
+ xgmii_rx_data : in std_logic_vector(71 downto 0) := (others => 'X'); -- data
+ avalon_st_rx_startofpacket : out std_logic; -- startofpacket
+ avalon_st_rx_endofpacket : out std_logic; -- endofpacket
+ avalon_st_rx_valid : out std_logic; -- valid
+ avalon_st_rx_ready : in std_logic := 'X'; -- ready
+ avalon_st_rx_data : out std_logic_vector(63 downto 0); -- data
+ avalon_st_rx_empty : out std_logic_vector(2 downto 0); -- empty
+ avalon_st_rx_error : out std_logic_vector(5 downto 0); -- error
+ avalon_st_rxstatus_valid : out std_logic; -- valid
+ avalon_st_rxstatus_data : out std_logic_vector(39 downto 0); -- data
+ avalon_st_rxstatus_error : out std_logic_vector(6 downto 0); -- error
+ link_fault_status_xgmii_rx_data : out std_logic_vector(1 downto 0) -- data
+ );
+ end component ip_stratixiv_mac_10g_0002;
+
+begin
+
+ ip_stratixiv_mac_10g_inst : component ip_stratixiv_mac_10g_0002
+ port map (
+ csr_clk_clk => csr_clk_clk, -- csr_clk.clk
+ csr_reset_reset_n => csr_reset_reset_n, -- csr_reset.reset_n
+ csr_address => csr_address, -- csr.address
+ csr_waitrequest => csr_waitrequest, -- .waitrequest
+ csr_read => csr_read, -- .read
+ csr_readdata => csr_readdata, -- .readdata
+ csr_write => csr_write, -- .write
+ csr_writedata => csr_writedata, -- .writedata
+ tx_clk_clk => tx_clk_clk, -- tx_clk.clk
+ tx_reset_reset_n => tx_reset_reset_n, -- tx_reset.reset_n
+ avalon_st_tx_startofpacket => avalon_st_tx_startofpacket, -- avalon_st_tx.startofpacket
+ avalon_st_tx_valid => avalon_st_tx_valid, -- .valid
+ avalon_st_tx_data => avalon_st_tx_data, -- .data
+ avalon_st_tx_empty => avalon_st_tx_empty, -- .empty
+ avalon_st_tx_ready => avalon_st_tx_ready, -- .ready
+ avalon_st_tx_error => avalon_st_tx_error, -- .error
+ avalon_st_tx_endofpacket => avalon_st_tx_endofpacket, -- .endofpacket
+ avalon_st_pause_data => avalon_st_pause_data, -- avalon_st_pause.data
+ xgmii_tx_data => xgmii_tx_data, -- xgmii_tx.data
+ avalon_st_txstatus_valid => avalon_st_txstatus_valid, -- avalon_st_txstatus.valid
+ avalon_st_txstatus_data => avalon_st_txstatus_data, -- .data
+ avalon_st_txstatus_error => avalon_st_txstatus_error, -- .error
+ rx_clk_clk => rx_clk_clk, -- rx_clk.clk
+ rx_reset_reset_n => rx_reset_reset_n, -- rx_reset.reset_n
+ xgmii_rx_data => xgmii_rx_data, -- xgmii_rx.data
+ avalon_st_rx_startofpacket => avalon_st_rx_startofpacket, -- avalon_st_rx.startofpacket
+ avalon_st_rx_endofpacket => avalon_st_rx_endofpacket, -- .endofpacket
+ avalon_st_rx_valid => avalon_st_rx_valid, -- .valid
+ avalon_st_rx_ready => avalon_st_rx_ready, -- .ready
+ avalon_st_rx_data => avalon_st_rx_data, -- .data
+ avalon_st_rx_empty => avalon_st_rx_empty, -- .empty
+ avalon_st_rx_error => avalon_st_rx_error, -- .error
+ avalon_st_rxstatus_valid => avalon_st_rxstatus_valid, -- avalon_st_rxstatus.valid
+ avalon_st_rxstatus_data => avalon_st_rxstatus_data, -- .data
+ avalon_st_rxstatus_error => avalon_st_rxstatus_error, -- .error
+ link_fault_status_xgmii_rx_data => link_fault_status_xgmii_rx_data -- link_fault_status_xgmii_rx.data
+ );
+
+end architecture rtl; -- of ip_stratixiv_mac_10g
+-- Retrieval info: <?xml version="1.0"?>
+--<!--
+-- Generated by Altera MegaWizard Launcher Utility version 1.0
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+-- ************************************************************
+-- Copyright (C) 1991-2014 Altera Corporation
+-- Any megafunction design, and related net list (encrypted or decrypted),
+-- support information, device programming or simulation file, and any other
+-- associated documentation or information provided by Altera or a partner
+-- under Altera's Megafunction Partnership Program may be used only to
+-- program PLD devices (but not masked PLD devices) from Altera. Any other
+-- use of such megafunction design, net list, support information, device
+-- programming or simulation file, or any other related documentation or
+-- information is prohibited for any other purpose, including, but not
+-- limited to modification, reverse engineering, de-compiling, or use with
+-- any other silicon devices, unless such use is explicitly licensed under
+-- a separate agreement with Altera or a megafunction partner. Title to
+-- the intellectual property, including patents, copyrights, trademarks,
+-- trade secrets, or maskworks, embodied in any such megafunction design,
+-- net list, support information, device programming or simulation file, or
+-- any other related documentation or information provided by Altera or a
+-- megafunction partner, remains with Altera, the megafunction partner, or
+-- their respective licensors. No other licenses, including any licenses
+-- needed under any third party's intellectual property, are provided herein.
+---->
+-- Retrieval info: <instance entity-name="altera_eth_10g_mac" version="11.1" >
+-- Retrieval info: <generic name="PREAMBLE_PASSTHROUGH" value="0" />
+-- Retrieval info: <generic name="ENABLE_PFC" value="0" />
+-- Retrieval info: <generic name="PFC_PRIORITY_NUM" value="8" />
+-- Retrieval info: <generic name="DATAPATH_OPTION" value="3" />
+-- Retrieval info: <generic name="ENABLE_SUPP_ADDR" value="1" />
+-- Retrieval info: <generic name="INSTANTIATE_TX_CRC" value="1" />
+-- Retrieval info: <generic name="INSTANTIATE_STATISTICS" value="1" />
+-- Retrieval info: <generic name="REGISTER_BASED_STATISTICS" value="0" />
+-- Retrieval info: <generic name="DEVICE_FAMILY" value="Stratix IV" />
+-- Retrieval info: </instance>
+-- IPFS_FILES : ip_stratixiv_mac_10g.vho
+-- RELATED_FILES: ip_stratixiv_mac_10g.vhd, ip_stratixiv_mac_10g_0002.v, altera_merlin_master_translator.sv, altera_avalon_mm_bridge.v, altera_eth_packet_underflow_control.v, altera_eth_pad_inserter.v, altera_eth_pkt_backpressure_control.v, altera_eth_pause_beat_conversion.v, altera_eth_pause_controller.v, altera_eth_pause_ctrl_gen.v, altera_eth_pause_gen.v, ip_stratixiv_mac_10g_tx_st_pause_ctrl_error_adapter.v, ip_stratixiv_mac_10g_tx_st_mux_flow_control_user_frame.v, altera_eth_address_inserter.v, altera_eth_crc.v, crc32.v, gf_mult32_kc.v, altera_avalon_st_pipeline_stage.sv, altera_avalon_st_pipeline_base.v, altera_avalon_st_splitter.sv, ip_stratixiv_mac_10g_tx_st_timing_adapter_frame_decoder.v, altera_eth_frame_decoder.v, ip_stratixiv_mac_10g_tx_st_error_adapter_stat.v, ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_in.v, ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_output.v, altera_avalon_st_splitter.sv, ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_output.v, altera_eth_10gmem_statistics_collector.v, altera_eth_packet_formatter.v, altera_eth_xgmii_termination.v, altera_eth_link_fault_generation.v, altera_avalon_mm_bridge.v, ip_stratixiv_mac_10g_rx_st_timing_adapter_interface_conversion.v, altera_avalon_st_splitter.sv, ip_stratixiv_mac_10g_rx_st_timing_adapter_lane_decoder.v, ip_stratixiv_mac_10g_rx_st_timing_adapter_lane_decoder.v, altera_eth_link_fault_detection.v, altera_eth_lane_decoder.v, altera_eth_pkt_backpressure_control.v, ip_stratixiv_mac_10g_rx_st_timing_adapter_frame_status_in.v, altera_avalon_st_splitter.sv, altera_eth_frame_decoder.v, altera_avalon_st_pipeline_stage.sv, altera_avalon_st_pipeline_base.v, altera_eth_crc.v, crc32.v, gf_mult32_kc.v, ip_stratixiv_mac_10g_rx_timing_adapter_frame_status_out_frame_decoder.v, ip_stratixiv_mac_10g_rx_timing_adapter_frame_status_out_frame_decoder.v, altera_eth_frame_status_merger.v, altera_eth_crc_pad_rem.v, altera_eth_crc_rem.v, altera_packet_stripper.v, altera_eth_packet_overflow_control.v, altera_avalon_st_delay.sv, ip_stratixiv_mac_10g_rx_st_error_adapter_stat.v, ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_in.v, altera_avalon_st_splitter.sv, ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_output.v, ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_output.v, altera_avalon_st_delay.sv, altera_eth_10gmem_statistics_collector.v, ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_rx.v, altera_avalon_st_splitter.sv, ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_export.v, altera_avalon_dc_fifo.v, altera_dcfifo_synchronizer_bundle.v, ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_export.v, ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_rx.v, altera_avalon_dc_fifo.v, altera_dcfifo_synchronizer_bundle.v, ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_tx.v, altera_merlin_master_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_master_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_master_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_avalon_sc_fifo.v, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_avalon_sc_fifo.v, altera_merlin_master_agent.sv, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_merlin_master_agent.sv, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_merlin_master_agent.sv, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, ip_stratixiv_mac_10g_addr_router.sv, ip_stratixiv_mac_10g_id_router.sv, ip_stratixiv_mac_10g_id_router.sv, ip_stratixiv_mac_10g_addr_router_001.sv, ip_stratixiv_mac_10g_id_router_002.sv, ip_stratixiv_mac_10g_id_router_002.sv, ip_stratixiv_mac_10g_id_router_002.sv, ip_stratixiv_mac_10g_id_router_002.sv, ip_stratixiv_mac_10g_id_router_002.sv, ip_stratixiv_mac_10g_id_router_002.sv, ip_stratixiv_mac_10g_id_router_002.sv, ip_stratixiv_mac_10g_id_router_002.sv, ip_stratixiv_mac_10g_addr_router_002.sv, ip_stratixiv_mac_10g_id_router_010.sv, ip_stratixiv_mac_10g_id_router_010.sv, ip_stratixiv_mac_10g_id_router_010.sv, ip_stratixiv_mac_10g_id_router_010.sv, ip_stratixiv_mac_10g_id_router_010.sv, ip_stratixiv_mac_10g_id_router_010.sv, ip_stratixiv_mac_10g_id_router_010.sv, altera_merlin_traffic_limiter.sv, altera_merlin_traffic_limiter.sv, altera_avalon_st_pipeline_base.v, altera_merlin_traffic_limiter.sv, altera_avalon_st_pipeline_base.v, altera_reset_controller.v, altera_reset_synchronizer.v, altera_reset_controller.v, altera_reset_synchronizer.v, altera_reset_controller.v, altera_reset_synchronizer.v, ip_stratixiv_mac_10g_cmd_xbar_demux.sv, ip_stratixiv_mac_10g_rsp_xbar_demux.sv, ip_stratixiv_mac_10g_rsp_xbar_demux.sv, altera_merlin_arbitrator.sv, ip_stratixiv_mac_10g_rsp_xbar_mux.sv, ip_stratixiv_mac_10g_cmd_xbar_demux_001.sv, ip_stratixiv_mac_10g_rsp_xbar_demux_002.sv, ip_stratixiv_mac_10g_rsp_xbar_demux_002.sv, ip_stratixiv_mac_10g_rsp_xbar_demux_002.sv, ip_stratixiv_mac_10g_rsp_xbar_demux_002.sv, ip_stratixiv_mac_10g_rsp_xbar_demux_002.sv, ip_stratixiv_mac_10g_rsp_xbar_demux_002.sv, ip_stratixiv_mac_10g_rsp_xbar_demux_002.sv, ip_stratixiv_mac_10g_rsp_xbar_demux_002.sv, ip_stratixiv_mac_10g_rsp_xbar_mux_001.sv, ip_stratixiv_mac_10g_cmd_xbar_demux_002.sv, ip_stratixiv_mac_10g_rsp_xbar_demux_010.sv, ip_stratixiv_mac_10g_rsp_xbar_demux_010.sv, ip_stratixiv_mac_10g_rsp_xbar_demux_010.sv, ip_stratixiv_mac_10g_rsp_xbar_demux_010.sv, ip_stratixiv_mac_10g_rsp_xbar_demux_010.sv, ip_stratixiv_mac_10g_rsp_xbar_demux_010.sv, ip_stratixiv_mac_10g_rsp_xbar_demux_010.sv, ip_stratixiv_mac_10g_rsp_xbar_mux_002.sv, altera_avalon_st_handshake_clock_crosser.v, altera_avalon_st_clock_crosser.v, altera_avalon_st_handshake_clock_crosser.v, altera_avalon_st_clock_crosser.v, altera_avalon_st_pipeline_base.v, altera_avalon_st_handshake_clock_crosser.v, altera_avalon_st_clock_crosser.v, altera_avalon_st_pipeline_base.v, altera_avalon_st_handshake_clock_crosser.v, altera_avalon_st_clock_crosser.v, altera_avalon_st_pipeline_base.v
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_dc_fifo.sdc b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_dc_fifo.sdc
new file mode 100644
index 0000000000000000000000000000000000000000..f9857f8af6eb103cc94fb9f7e49925363ae6f04d
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_dc_fifo.sdc
@@ -0,0 +1,12 @@
+# $Id: //acds/rel/11.1sp2/ip/sopc/components/altera_avalon_dc_fifo/altera_avalon_dc_fifo.sdc#1 $
+# $Revision: #1 $
+# $Date: 2011/11/10 $
+#-------------------------------------------------------------------------------
+# TimeQuest constraints to cut all false timing paths across asynchronous
+# clock domains. The paths are from the Gray Code read and write pointers to
+# their respective synchronizer banks.
+
+set_false_path -from [get_registers {*|in_wr_ptr_gray[*]}] -to [get_registers {*|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[*].u|din_s1}]
+
+set_false_path -from [get_registers {*|out_rd_ptr_gray[*]}] -to [get_registers {*|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[*].u|din_s1}]
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_dc_fifo.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_dc_fifo.v
new file mode 100644
index 0000000000000000000000000000000000000000..b9883ca9b4dae5b31b21f0548325078979f57a4a
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_dc_fifo.v
@@ -0,0 +1,662 @@
+// ---------------------------------------------------------------------
+// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
+// use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any
+// output files any of the foregoing (including device programming or
+// simulation files), and any associated documentation or information are
+// expressly subject to the terms and conditions of the Altera Program
+// License Subscription Agreement or other applicable license agreement,
+// including, without limitation, that your use is for the sole purpose
+// of programming logic devices manufactured by Altera and sold by Altera
+// or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+//
+// Description: Dual clocked single channel FIFO with fill levels and status
+// information.
+// ---------------------------------------------------------------------
+
+`timescale 1 ns / 100 ps
+
+//altera message_off 10036 10858 10230 10030 10034
+module altera_avalon_dc_fifo (
+
+ in_clk,
+ in_reset_n,
+
+ out_clk,
+ out_reset_n,
+
+ // sink
+ in_data,
+ in_valid,
+ in_ready,
+ in_startofpacket,
+ in_endofpacket,
+ in_empty,
+ in_error,
+ in_channel,
+
+ // source
+ out_data,
+ out_valid,
+ out_ready,
+ out_startofpacket,
+ out_endofpacket,
+ out_empty,
+ out_error,
+ out_channel,
+
+ // in csr
+ in_csr_address,
+ in_csr_write,
+ in_csr_read,
+ in_csr_readdata,
+ in_csr_writedata,
+
+ // out csr
+ out_csr_address,
+ out_csr_write,
+ out_csr_read,
+ out_csr_readdata,
+ out_csr_writedata,
+
+ // streaming in status
+ almost_full_valid,
+ almost_full_data,
+
+ // streaming out status
+ almost_empty_valid,
+ almost_empty_data,
+
+ // (internal, experimental interface) space available st source
+ space_avail_data
+
+);
+
+ // ---------------------------------------------------------------------
+ // Parameters
+ // ---------------------------------------------------------------------
+ parameter SYMBOLS_PER_BEAT = 1;
+ parameter BITS_PER_SYMBOL = 8;
+ parameter FIFO_DEPTH = 16;
+ parameter CHANNEL_WIDTH = 0;
+ parameter ERROR_WIDTH = 0;
+ parameter USE_PACKETS = 0;
+
+ parameter USE_IN_FILL_LEVEL = 0;
+ parameter USE_OUT_FILL_LEVEL = 0;
+ parameter WR_SYNC_DEPTH = 2;
+ parameter RD_SYNC_DEPTH = 2;
+ parameter STREAM_ALMOST_FULL = 0;
+ parameter STREAM_ALMOST_EMPTY = 0;
+
+ // experimental, internal parameter
+ parameter USE_SPACE_AVAIL_IF = 0;
+
+ localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
+ localparam DEPTH = 2 ** ADDR_WIDTH;
+ localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
+ localparam EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT);
+ localparam PACKET_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
+ localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
+ 2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
+ DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
+
+ // ---------------------------------------------------------------------
+ // Input/Output Signals
+ // ---------------------------------------------------------------------
+ input in_clk;
+ input in_reset_n;
+
+ input out_clk;
+ input out_reset_n;
+
+ input [DATA_WIDTH - 1 : 0] in_data;
+ input in_valid;
+ input in_startofpacket;
+ input in_endofpacket;
+ input [EMPTY_WIDTH - 1 : 0] in_empty;
+ input [ERROR_WIDTH - 1 : 0] in_error;
+ input [CHANNEL_WIDTH - 1: 0] in_channel;
+ output in_ready;
+
+ output [DATA_WIDTH - 1 : 0] out_data;
+ output reg out_valid;
+ output out_startofpacket;
+ output out_endofpacket;
+ output [EMPTY_WIDTH - 1 : 0] out_empty;
+ output [ERROR_WIDTH - 1 : 0] out_error;
+ output [CHANNEL_WIDTH - 1: 0] out_channel;
+ input out_ready;
+
+ input in_csr_address;
+ input in_csr_read;
+ input in_csr_write;
+ input [31 : 0] in_csr_writedata;
+ output reg [31 : 0] in_csr_readdata;
+
+ input out_csr_address;
+ input out_csr_read;
+ input out_csr_write;
+ input [31 : 0] out_csr_writedata;
+ output reg [31 : 0] out_csr_readdata;
+
+ output reg almost_full_valid;
+ output reg almost_full_data;
+ output reg almost_empty_valid;
+ output reg almost_empty_data;
+
+ output [ADDR_WIDTH : 0] space_avail_data;
+
+ // ---------------------------------------------------------------------
+ // Memory Pointers
+ // ---------------------------------------------------------------------
+ reg [PAYLOAD_WIDTH - 1 : 0] mem [DEPTH - 1 : 0];
+
+ wire [ADDR_WIDTH - 1 : 0] mem_wr_ptr;
+ wire [ADDR_WIDTH - 1 : 0] mem_rd_ptr;
+
+ reg [ADDR_WIDTH : 0] in_wr_ptr;
+ reg [ADDR_WIDTH : 0] out_rd_ptr;
+
+ // ---------------------------------------------------------------------
+ // Internal Signals
+ // ---------------------------------------------------------------------
+ wire [ADDR_WIDTH : 0] next_out_wr_ptr;
+ wire [ADDR_WIDTH : 0] next_in_wr_ptr;
+ wire [ADDR_WIDTH : 0] next_out_rd_ptr;
+ wire [ADDR_WIDTH : 0] next_in_rd_ptr;
+
+ reg [ADDR_WIDTH : 0] in_wr_ptr_gray /*synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D102" */;
+ wire [ADDR_WIDTH : 0] out_wr_ptr_gray;
+
+ reg [ADDR_WIDTH : 0] out_rd_ptr_gray /*synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D102" */;
+ wire [ADDR_WIDTH : 0] in_rd_ptr_gray;
+
+ reg full;
+ reg empty;
+
+ wire [PAYLOAD_WIDTH - 1 : 0] in_payload;
+ reg [PAYLOAD_WIDTH - 1 : 0] out_payload;
+ reg [PAYLOAD_WIDTH - 1 : 0] internal_out_payload;
+
+ wire [PACKET_SIGNALS_WIDTH - 1 : 0] in_packet_signals;
+ wire [PACKET_SIGNALS_WIDTH - 1 : 0] out_packet_signals;
+
+ wire internal_out_ready;
+ wire internal_out_valid;
+
+ wire [ADDR_WIDTH : 0] out_fill_level;
+ reg [ADDR_WIDTH : 0] out_fifo_fill_level;
+ reg [ADDR_WIDTH : 0] in_fill_level;
+ reg [ADDR_WIDTH : 0] in_space_avail;
+
+ reg [23 : 0] almost_empty_threshold;
+ reg [23 : 0] almost_full_threshold;
+
+ // --------------------------------------------------
+ // Define Payload
+ //
+ // Icky part where we decide which signals form the
+ // payload to the FIFO.
+ // --------------------------------------------------
+ generate
+ if (EMPTY_WIDTH > 0) begin
+ assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
+ assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
+ end
+ else begin
+ assign in_packet_signals = {in_startofpacket, in_endofpacket};
+ assign {out_startofpacket, out_endofpacket} = out_packet_signals;
+ end
+ endgenerate
+
+ generate
+ if (USE_PACKETS) begin
+ if (ERROR_WIDTH > 0) begin
+ if (CHANNEL_WIDTH > 0) begin
+ assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
+ assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
+ end
+ else begin
+ assign in_payload = {in_packet_signals, in_data, in_error};
+ assign {out_packet_signals, out_data, out_error} = out_payload;
+ end
+ end
+ else begin
+ if (CHANNEL_WIDTH > 0) begin
+ assign in_payload = {in_packet_signals, in_data, in_channel};
+ assign {out_packet_signals, out_data, out_channel} = out_payload;
+ end
+ else begin
+ assign in_payload = {in_packet_signals, in_data};
+ assign {out_packet_signals, out_data} = out_payload;
+ end
+ end
+ end
+ else begin
+ if (ERROR_WIDTH > 0) begin
+ if (CHANNEL_WIDTH > 0) begin
+ assign in_payload = {in_data, in_error, in_channel};
+ assign {out_data, out_error, out_channel} = out_payload;
+ end
+ else begin
+ assign in_payload = {in_data, in_error};
+ assign {out_data, out_error} = out_payload;
+ end
+ end
+ else begin
+ if (CHANNEL_WIDTH > 0) begin
+ assign in_payload = {in_data, in_channel};
+ assign {out_data, out_channel} = out_payload;
+ end
+ else begin
+ assign in_payload = in_data;
+ assign out_data = out_payload;
+ end
+ end
+ end
+ endgenerate
+
+ // ---------------------------------------------------------------------
+ // Memory
+ //
+ // Infers a simple dual clock memory with unregistered outputs
+ // ---------------------------------------------------------------------
+ always @(posedge in_clk) begin
+ if (in_valid && in_ready)
+ mem[mem_wr_ptr] <= in_payload;
+ end
+
+ always @(posedge out_clk) begin
+ internal_out_payload <= mem[mem_rd_ptr];
+ end
+
+ assign mem_rd_ptr = next_out_rd_ptr;
+ assign mem_wr_ptr = in_wr_ptr;
+
+
+ // ---------------------------------------------------------------------
+ // Pointer Management
+ //
+ // Increment our good old read and write pointers on their native
+ // clock domains.
+ // ---------------------------------------------------------------------
+ always @(posedge in_clk or negedge in_reset_n) begin
+ if (!in_reset_n)
+ in_wr_ptr <= 0;
+ else
+ in_wr_ptr <= next_in_wr_ptr;
+ end
+
+ always @(posedge out_clk or negedge out_reset_n) begin
+ if (!out_reset_n)
+ out_rd_ptr <= 0;
+ else
+ out_rd_ptr <= next_out_rd_ptr;
+ end
+
+ assign next_in_wr_ptr = (in_ready && in_valid) ? in_wr_ptr + 1'b1 : in_wr_ptr;
+ assign next_out_rd_ptr = (internal_out_ready && internal_out_valid) ? out_rd_ptr + 1'b1 : out_rd_ptr;
+
+
+ // ---------------------------------------------------------------------
+ // Empty/Full Signal Generation
+ //
+ // We keep read and write pointers that are one bit wider than
+ // required, and use that additional bit to figure out if we're
+ // full or empty.
+ // ---------------------------------------------------------------------
+ always @(posedge out_clk or negedge out_reset_n) begin
+ if(!out_reset_n)
+ empty <= 1;
+ else
+ empty <= (next_out_rd_ptr == next_out_wr_ptr);
+ end
+
+ always @(posedge in_clk or negedge in_reset_n) begin
+ if (!in_reset_n)
+ full <= 0;
+ else
+ full <= (next_in_rd_ptr[ADDR_WIDTH - 1 : 0] == next_in_wr_ptr[ADDR_WIDTH - 1 : 0]) && (next_in_rd_ptr[ADDR_WIDTH] != next_in_wr_ptr[ADDR_WIDTH]);
+ end
+
+
+ // ---------------------------------------------------------------------
+ // Write Pointer Clock Crossing
+ //
+ // Clock crossing is done with gray encoding of the pointers. What? You
+ // want to know more? We ensure a one bit change at sampling time,
+ // and then metastable harden the sampled gray pointer.
+ // ---------------------------------------------------------------------
+ always @(posedge in_clk or negedge in_reset_n) begin
+ if (!in_reset_n)
+ in_wr_ptr_gray <= 0;
+ else
+ in_wr_ptr_gray <= bin2gray(in_wr_ptr);
+ end
+
+ altera_dcfifo_synchronizer_bundle write_crosser (
+ .clk(out_clk),
+ .reset_n(out_reset_n),
+ .din(in_wr_ptr_gray),
+ .dout(out_wr_ptr_gray)
+ );
+
+ defparam write_crosser.WIDTH = ADDR_WIDTH + 1;
+ defparam write_crosser.DEPTH = WR_SYNC_DEPTH;
+
+ assign next_out_wr_ptr = gray2bin(out_wr_ptr_gray);
+
+ // ---------------------------------------------------------------------
+ // Read Pointer Clock Crossing
+ //
+ // Go the other way, go the other way...
+ // ---------------------------------------------------------------------
+ always @(posedge out_clk or negedge out_reset_n) begin
+ if (!out_reset_n)
+ out_rd_ptr_gray <= 0;
+ else
+ out_rd_ptr_gray <= bin2gray(out_rd_ptr);
+ end
+
+ altera_dcfifo_synchronizer_bundle read_crosser (
+ .clk(in_clk),
+ .reset_n(in_reset_n),
+ .din(out_rd_ptr_gray),
+ .dout(in_rd_ptr_gray)
+ );
+
+ defparam read_crosser.WIDTH = ADDR_WIDTH + 1;
+ defparam read_crosser.DEPTH = RD_SYNC_DEPTH;
+
+ assign next_in_rd_ptr = gray2bin(in_rd_ptr_gray);
+
+ // ---------------------------------------------------------------------
+ // Avalon ST Signals
+ // ---------------------------------------------------------------------
+ assign in_ready = !full;
+ assign internal_out_valid = !empty;
+
+ // --------------------------------------------------
+ // Output Pipeline Stage
+ //
+ // We do this on the single clock FIFO to keep fmax
+ // up because the memory outputs are kind of slow.
+ // Therefore, this stage is even more critical on a dual clock
+ // FIFO, wouldn't you say? No one wants a slow dcfifo.
+ // --------------------------------------------------
+ assign internal_out_ready = out_ready || !out_valid;
+
+ always @(posedge out_clk or negedge out_reset_n) begin
+ if (!out_reset_n) begin
+ out_valid <= 0;
+ out_payload <= 0;
+ end
+ else begin
+ if (internal_out_ready) begin
+ out_valid <= internal_out_valid;
+ out_payload <= internal_out_payload;
+ end
+ end
+ end
+
+ // ---------------------------------------------------------------------
+ // Out Fill Level
+ //
+ // As in the SCFIFO, we account for the output stage as well in the
+ // fill level calculations. This means that the out fill level always
+ // gives the most accurate fill level report.
+ //
+ // On a full 16-deep FIFO, the out fill level will read 17. Funny, but
+ // accurate.
+ //
+ // That's essential on the output side, because a downstream component
+ // might want to know the exact amount of data in the FIFO at any time.
+ // ---------------------------------------------------------------------
+ generate
+ if (USE_OUT_FILL_LEVEL || STREAM_ALMOST_EMPTY) begin
+
+ always @(posedge out_clk or negedge out_reset_n) begin
+ if (!out_reset_n) begin
+ out_fifo_fill_level <= 0;
+ end
+ else begin
+ out_fifo_fill_level <= next_out_wr_ptr - next_out_rd_ptr;
+ end
+ end
+
+ assign out_fill_level = out_fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
+ end
+ endgenerate
+
+ // ---------------------------------------------------------------------
+ // Almost Empty Streaming Status & Out CSR
+ //
+ // This is banal by now, but where's the empty signal? The output side.
+ // Where's the almost empty status? The output side.
+ //
+ // The almost empty signal is asserted when the output fill level
+ // in the FIFO falls below the user-specified threshold.
+ //
+ // Output CSR address map:
+ //
+ // | Addr | RW | 31 - 24 | 23 - 0 |
+ // | 0 | R | Reserved | Out fill level |
+ // | 1 | RW | Reserved | Almost empty threshold |
+ // ---------------------------------------------------------------------
+ generate
+ if (USE_OUT_FILL_LEVEL || STREAM_ALMOST_EMPTY) begin
+
+ always @(posedge out_clk or negedge out_reset_n) begin
+ if (!out_reset_n) begin
+ out_csr_readdata <= 0;
+ if (STREAM_ALMOST_EMPTY)
+ almost_empty_threshold <= 0;
+ end
+ else begin
+ if (out_csr_write) begin
+ if (STREAM_ALMOST_EMPTY && (out_csr_address == 1))
+ almost_empty_threshold <= out_csr_writedata[23 : 0];
+ end
+ else if (out_csr_read) begin
+ out_csr_readdata <= 0;
+
+ if (out_csr_address == 0)
+ out_csr_readdata[23 : 0] <= out_fill_level;
+ else if (STREAM_ALMOST_EMPTY && (out_csr_address == 1))
+ out_csr_readdata[23 : 0] <= almost_empty_threshold;
+ end
+ end
+ end
+
+ end
+
+ if (STREAM_ALMOST_EMPTY) begin
+
+ always @(posedge out_clk or negedge out_reset_n) begin
+ if (!out_reset_n) begin
+ almost_empty_valid <= 0;
+ almost_empty_data <= 0;
+ end
+ else begin
+ almost_empty_valid <= 1'b1;
+ almost_empty_data <= (out_fill_level <= almost_empty_threshold);
+ end
+ end
+
+ end
+ endgenerate
+
+ // ---------------------------------------------------------------------
+ // In Fill Level & In Status Connection Point
+ //
+ // Note that the input fill level does not account for the output
+ // stage i.e it is only the fifo fill level.
+ //
+ // Is this a problem? No, because the input fill is usually used to
+ // see how much data can still be pushed into this FIFO. The FIFO
+ // fill level gives exactly this information, and there's no need to
+ // make our lives more difficult by including the output stage here.
+ //
+ // One might ask: why not just report a space available level on the
+ // input side? Well, I'd like to make this FIFO be as similar as possible
+ // to its single clock cousin, and that uses fill levels and
+ // fill thresholds with nary a mention of space available.
+ // ---------------------------------------------------------------------
+ generate
+ if (USE_IN_FILL_LEVEL || STREAM_ALMOST_FULL) begin
+
+ always @(posedge in_clk or negedge in_reset_n) begin
+ if (!in_reset_n) begin
+ in_fill_level <= 0;
+ end
+ else begin
+ in_fill_level <= next_in_wr_ptr - next_in_rd_ptr;
+ end
+ end
+
+ end
+ endgenerate
+
+ generate
+ if (USE_SPACE_AVAIL_IF) begin
+
+ always @(posedge in_clk or negedge in_reset_n) begin
+ if (!in_reset_n) begin
+ in_space_avail <= FIFO_DEPTH;
+ end
+ else begin
+ // -------------------------------------
+ // space = DEPTH-fill = DEPTH-(wr-rd) = DEPTH+rd-wr
+ // Conveniently, DEPTH requires the same number of bits
+ // as the pointers, e.g. a dcfifo with depth = 8
+ // requires 4-bit pointers.
+ //
+ // Adding 8 to a 4-bit pointer is simply negating the
+ // first bit... as is done below.
+ // -------------------------------------
+
+ in_space_avail <= {~next_in_rd_ptr[ADDR_WIDTH],
+ next_in_rd_ptr[ADDR_WIDTH-1:0]} -
+ next_in_wr_ptr;
+ end
+ end
+ end
+
+ assign space_avail_data = in_space_avail;
+ endgenerate
+
+ // ---------------------------------------------------------------------
+ // Almost Full Streaming Status & In CSR
+ //
+ // Where's the full signal? The input side.
+ // Where's the almost full status? The input side.
+ //
+ // The almost full data bit is asserted when the input fill level
+ // in the FIFO goes above the user-specified threshold.
+ //
+ // Input csr port address map:
+ //
+ // | Addr | RW | 31 - 24 | 23 - 0 |
+ // | 0 | R | Reserved | In fill level |
+ // | 1 | RW | Reserved | Almost full threshold |
+ // ---------------------------------------------------------------------
+ generate
+ if (USE_IN_FILL_LEVEL || STREAM_ALMOST_FULL) begin
+
+ always @(posedge in_clk or negedge in_reset_n) begin
+ if (!in_reset_n) begin
+ in_csr_readdata <= 0;
+ if (STREAM_ALMOST_FULL)
+ almost_full_threshold <= 0;
+ end
+ else begin
+ if (in_csr_write) begin
+ if (STREAM_ALMOST_FULL && (in_csr_address == 1))
+ almost_full_threshold <= in_csr_writedata[23 : 0];
+ end
+ else if (in_csr_read) begin
+ in_csr_readdata <= 0;
+
+ if (in_csr_address == 0)
+ in_csr_readdata[23 : 0] <= in_fill_level;
+ else if (STREAM_ALMOST_FULL && (in_csr_address == 1))
+ in_csr_readdata[23 : 0] <= almost_full_threshold;
+ end
+ end
+ end
+
+ end
+
+ if (STREAM_ALMOST_FULL) begin
+
+ always @(posedge in_clk or negedge in_reset_n) begin
+ if (!in_reset_n) begin
+ almost_full_valid <= 0;
+ almost_full_data <= 0;
+ end
+ else begin
+ almost_full_valid <= 1'b1;
+ almost_full_data <= (in_fill_level >= almost_full_threshold);
+ end
+ end
+
+ end
+
+ endgenerate
+
+ // ---------------------------------------------------------------------
+ // Gray Functions
+ //
+ // These are real beasts when you look at them. But they'll be
+ // tested thoroughly.
+ // ---------------------------------------------------------------------
+ function [ADDR_WIDTH : 0] bin2gray;
+ input [ADDR_WIDTH : 0] bin_val;
+ integer i;
+
+ for (i = 0; i <= ADDR_WIDTH; i = i + 1)
+ begin
+ if (i == ADDR_WIDTH)
+ bin2gray[i] = bin_val[i];
+ else
+ bin2gray[i] = bin_val[i+1] ^ bin_val[i];
+ end
+ endfunction
+
+ function [ADDR_WIDTH : 0] gray2bin;
+ input [ADDR_WIDTH : 0] gray_val;
+ integer i;
+ integer j;
+
+ for (i = 0; i <= ADDR_WIDTH; i = i + 1) begin
+
+ gray2bin[i] = gray_val[i];
+
+ for (j = ADDR_WIDTH; j > i; j = j - 1) begin
+ gray2bin[i] = gray2bin[i] ^ gray_val[j];
+ end
+
+ end
+ endfunction
+
+ // --------------------------------------------------
+ // Calculates the log2ceil of the input value
+ // --------------------------------------------------
+ function integer log2ceil;
+ input integer val;
+ integer i;
+
+ begin
+ i = 1;
+ log2ceil = 0;
+
+ while (i < val) begin
+ log2ceil = log2ceil + 1;
+ i = i << 1;
+ end
+ end
+ endfunction
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_mm_bridge.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_mm_bridge.v
new file mode 100644
index 0000000000000000000000000000000000000000..57bda33657bcae1258fbc3a665487b3e794724de
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_mm_bridge.v
@@ -0,0 +1,291 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/rel/11.1sp2/ip/merlin/altera_avalon_mm_bridge/altera_avalon_mm_bridge.v#1 $
+// $Revision: #1 $
+// $Date: 2011/11/10 $
+// $Author: max $
+// --------------------------------------
+// Avalon-MM pipeline bridge
+//
+// Optionally registers Avalon-MM command and response signals
+// --------------------------------------
+
+`timescale 1 ns / 1 ns
+module altera_avalon_mm_bridge
+#(
+ parameter DATA_WIDTH = 32,
+ parameter SYMBOL_WIDTH = 8,
+ parameter ADDRESS_WIDTH = 10,
+ parameter BURSTCOUNT_WIDTH = 1,
+
+ parameter PIPELINE_COMMAND = 1,
+ parameter PIPELINE_RESPONSE = 1,
+
+ // --------------------------------------
+ // Derived parameters
+ // --------------------------------------
+ parameter BYTEEN_WIDTH = DATA_WIDTH / SYMBOL_WIDTH
+)
+(
+ input clk,
+ input reset,
+
+ output s0_waitrequest,
+ output [DATA_WIDTH-1:0] s0_readdata,
+ output s0_readdatavalid,
+ input [BURSTCOUNT_WIDTH-1:0] s0_burstcount,
+ input [DATA_WIDTH-1:0] s0_writedata,
+ input [ADDRESS_WIDTH-1:0] s0_address,
+ input s0_write,
+ input s0_read,
+ input [BYTEEN_WIDTH-1:0] s0_byteenable,
+ input s0_debugaccess,
+
+ input m0_waitrequest,
+ input [DATA_WIDTH-1:0] m0_readdata,
+ input m0_readdatavalid,
+ output [BURSTCOUNT_WIDTH-1:0] m0_burstcount,
+ output [DATA_WIDTH-1:0] m0_writedata,
+ output [ADDRESS_WIDTH-1:0] m0_address,
+ output m0_write,
+ output m0_read,
+ output [BYTEEN_WIDTH-1:0] m0_byteenable,
+ output m0_debugaccess
+);
+ // --------------------------------------
+ // Registers & signals
+ // --------------------------------------
+ reg [BURSTCOUNT_WIDTH-1:0] cmd_burstcount;
+ reg [DATA_WIDTH-1:0] cmd_writedata;
+ reg [ADDRESS_WIDTH-1:0] cmd_address;
+ reg cmd_write;
+ reg cmd_read;
+ reg [BYTEEN_WIDTH-1:0] cmd_byteenable;
+ wire cmd_waitrequest;
+ reg cmd_debugaccess;
+
+ reg [BURSTCOUNT_WIDTH-1:0] wr_burstcount;
+ reg [DATA_WIDTH-1:0] wr_writedata;
+ reg [ADDRESS_WIDTH-1:0] wr_address;
+ reg wr_write;
+ reg wr_read;
+ reg [BYTEEN_WIDTH-1:0] wr_byteenable;
+ reg wr_debugaccess;
+
+ reg [BURSTCOUNT_WIDTH-1:0] wr_reg_burstcount;
+ reg [DATA_WIDTH-1:0] wr_reg_writedata;
+ reg [ADDRESS_WIDTH-1:0] wr_reg_address;
+ reg wr_reg_write;
+ reg wr_reg_read;
+ reg [BYTEEN_WIDTH-1:0] wr_reg_byteenable;
+ reg wr_reg_waitrequest;
+ reg wr_reg_debugaccess;
+
+ reg use_reg;
+ wire wait_rise;
+
+ reg [DATA_WIDTH-1:0] rsp_readdata;
+ reg rsp_readdatavalid;
+
+ // --------------------------------------
+ // Command pipeline
+ //
+ // Registers all command signals, including waitrequest
+ // --------------------------------------
+ generate if (PIPELINE_COMMAND == 1) begin
+
+ // --------------------------------------
+ // Waitrequest Pipeline Stage
+ //
+ // Output waitrequest is delayed by one cycle, which means
+ // that a master will see waitrequest assertions one cycle
+ // too late.
+ //
+ // Solution: buffer the command when waitrequest transitions
+ // from low->high. As an optimization, we can safely assume
+ // waitrequest is low by default because downstream logic
+ // in the bridge ensures this.
+ //
+ // Note: this implementation buffers idle cycles should
+ // waitrequest transition on such cycles. This is a potential
+ // cause for throughput loss, but ye olde pipeline bridge did
+ // the same for years and no one complained. Not buffering idle
+ // cycles costs logic on the waitrequest path.
+ // --------------------------------------
+ assign s0_waitrequest = wr_reg_waitrequest;
+ assign wait_rise = ~wr_reg_waitrequest & cmd_waitrequest;
+
+ always @(posedge clk, posedge reset) begin
+ if (reset) begin
+ wr_reg_waitrequest <= 1'b1;
+ // --------------------------------------
+ // Bit of trickiness here, deserving of a long comment.
+ //
+ // On the first cycle after reset, the pass-through
+ // must not be used or downstream logic may sample
+ // the same command twice because of the delay in
+ // transmitting a falling waitrequest.
+ //
+ // Using the registered command works on the condition
+ // that downstream logic deasserts waitrequest
+ // immediately after reset, which is true of the
+ // next stage in this bridge.
+ // --------------------------------------
+ use_reg <= 1'b1;
+
+ wr_reg_burstcount <= 1'b1;
+ wr_reg_writedata <= 0;
+ wr_reg_byteenable <= {BYTEEN_WIDTH{1'b1}};
+ wr_reg_address <= 0;
+ wr_reg_write <= 1'b0;
+ wr_reg_read <= 1'b0;
+ wr_reg_debugaccess <= 1'b0;
+ end else begin
+ wr_reg_waitrequest <= cmd_waitrequest;
+
+ if (wait_rise) begin
+ use_reg <= 1'b1;
+
+ wr_reg_writedata <= s0_writedata;
+ wr_reg_byteenable <= s0_byteenable;
+ wr_reg_address <= s0_address;
+ wr_reg_write <= s0_write;
+ wr_reg_read <= s0_read;
+ wr_reg_burstcount <= s0_burstcount;
+ wr_reg_debugaccess <= s0_debugaccess;
+ end
+
+ // stop using the buffer when waitrequest is low
+ if (~cmd_waitrequest)
+ use_reg <= 1'b0;
+ end
+ end
+
+ always @* begin
+ wr_burstcount = s0_burstcount;
+ wr_writedata = s0_writedata;
+ wr_address = s0_address;
+ wr_write = s0_write;
+ wr_read = s0_read;
+ wr_byteenable = s0_byteenable;
+ wr_debugaccess = s0_debugaccess;
+
+ if (use_reg) begin
+ wr_burstcount = wr_reg_burstcount;
+ wr_writedata = wr_reg_writedata;
+ wr_address = wr_reg_address;
+ wr_write = wr_reg_write;
+ wr_read = wr_reg_read;
+ wr_byteenable = wr_reg_byteenable;
+ wr_debugaccess = wr_reg_debugaccess;
+ end
+ end
+
+ // --------------------------------------
+ // Master-Slave Signal Pipeline Stage
+ //
+ // One notable detail is that cmd_waitrequest is deasserted
+ // when this stage is idle. This allows us to make logic
+ // optimizations in the waitrequest pipeline stage.
+ //
+ // Also note that cmd_waitrequest is deasserted during reset,
+ // which is not spec-compliant, but is ok for an internal
+ // signal.
+ // --------------------------------------
+ wire no_command;
+ assign no_command = ~(cmd_read || cmd_write);
+ assign cmd_waitrequest = m0_waitrequest & ~no_command;
+
+ always @(posedge clk, posedge reset) begin
+ if (reset) begin
+ cmd_burstcount <= 1'b1;
+ cmd_writedata <= 0;
+ cmd_byteenable <= {BYTEEN_WIDTH{1'b1}};
+ cmd_address <= 0;
+ cmd_write <= 1'b0;
+ cmd_read <= 1'b0;
+ cmd_debugaccess <= 1'b0;
+ end
+ else begin
+ if (~cmd_waitrequest) begin
+ cmd_writedata <= wr_writedata;
+ cmd_byteenable <= wr_byteenable;
+ cmd_address <= wr_address;
+ cmd_write <= wr_write;
+ cmd_read <= wr_read;
+ cmd_burstcount <= wr_burstcount;
+ cmd_debugaccess <= wr_debugaccess;
+ end
+ end
+ end
+
+ end // conditional command pipeline
+ else begin
+
+ assign s0_waitrequest = m0_waitrequest;
+
+ always @* begin
+ cmd_burstcount = s0_burstcount;
+ cmd_writedata = s0_writedata;
+ cmd_address = s0_address;
+ cmd_write = s0_write;
+ cmd_read = s0_read;
+ cmd_byteenable = s0_byteenable;
+ cmd_debugaccess = s0_debugaccess;
+ end
+
+ end
+ endgenerate
+
+ assign m0_burstcount = cmd_burstcount;
+ assign m0_writedata = cmd_writedata;
+ assign m0_address = cmd_address;
+ assign m0_write = cmd_write;
+ assign m0_read = cmd_read;
+ assign m0_byteenable = cmd_byteenable;
+ assign m0_debugaccess = cmd_debugaccess;
+
+ // --------------------------------------
+ // Response pipeline
+ //
+ // Registers all response signals
+ // --------------------------------------
+ generate if (PIPELINE_RESPONSE == 1) begin
+
+ always @(posedge clk, posedge reset) begin
+ if (reset) begin
+ rsp_readdatavalid <= 1'b0;
+ rsp_readdata <= 0;
+ end
+ else begin
+ rsp_readdatavalid <= m0_readdatavalid;
+ rsp_readdata <= m0_readdata;
+ end
+ end
+
+ end // conditional response pipeline
+ else begin
+
+ always @* begin
+ rsp_readdatavalid = m0_readdatavalid;
+ rsp_readdata = m0_readdata;
+ end
+
+ end
+ endgenerate
+
+ assign s0_readdatavalid = rsp_readdatavalid;
+ assign s0_readdata = rsp_readdata;
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_sc_fifo.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_sc_fifo.v
new file mode 100644
index 0000000000000000000000000000000000000000..32d01214bc2d28d1883c4afe4acfeb333384002a
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_sc_fifo.v
@@ -0,0 +1,879 @@
+// -----------------------------------------------------------
+// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
+// use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any
+// output files any of the foregoing (including device programming or
+// simulation files), and any associated documentation or information are
+// expressly subject to the terms and conditions of the Altera Program
+// License Subscription Agreement or other applicable license agreement,
+// including, without limitation, that your use is for the sole purpose
+// of programming logic devices manufactured by Altera and sold by Altera
+// or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+//
+// Description: Single clock Avalon-ST FIFO.
+// -----------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+//altera message_off 10036
+module altera_avalon_sc_fifo
+#(
+ // --------------------------------------------------
+ // Parameters
+ // --------------------------------------------------
+ parameter SYMBOLS_PER_BEAT = 1,
+ parameter BITS_PER_SYMBOL = 8,
+ parameter FIFO_DEPTH = 16,
+ parameter CHANNEL_WIDTH = 0,
+ parameter ERROR_WIDTH = 0,
+ parameter USE_PACKETS = 0,
+ parameter USE_FILL_LEVEL = 0,
+ parameter USE_STORE_FORWARD = 0,
+ parameter USE_ALMOST_FULL_IF = 0,
+ parameter USE_ALMOST_EMPTY_IF = 0,
+
+ // --------------------------------------------------
+ // Empty latency is defined as the number of cycles
+ // required for a write to deassert the empty flag.
+ // For example, a latency of 1 means that the empty
+ // flag is deasserted on the cycle after a write.
+ //
+ // Another way to think of it is the latency for a
+ // write to propagate to the output.
+ //
+ // An empty latency of 0 implies lookahead, which is
+ // only implemented for the register-based FIFO.
+ // --------------------------------------------------
+ parameter EMPTY_LATENCY = 3,
+ parameter USE_MEMORY_BLOCKS = 1,
+
+ // --------------------------------------------------
+ // Internal Parameters
+ // --------------------------------------------------
+ parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
+ parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
+)
+(
+ // --------------------------------------------------
+ // Ports
+ // --------------------------------------------------
+ input clk,
+ input reset,
+
+ input [DATA_WIDTH-1: 0] in_data,
+ input in_valid,
+ input in_startofpacket,
+ input in_endofpacket,
+ input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
+ input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
+ input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
+ output in_ready,
+
+ output [DATA_WIDTH-1 : 0] out_data,
+ output reg out_valid,
+ output out_startofpacket,
+ output out_endofpacket,
+ output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
+ output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
+ output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
+ input out_ready,
+
+ input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
+ input csr_write,
+ input csr_read,
+ input [31 : 0] csr_writedata,
+ output reg [31 : 0] csr_readdata,
+
+ output wire almost_full_data,
+ output wire almost_empty_data
+);
+
+ // --------------------------------------------------
+ // Local Parameters
+ // --------------------------------------------------
+ localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
+ localparam DEPTH = FIFO_DEPTH;
+ localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
+ localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
+ 2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
+ DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
+
+ // --------------------------------------------------
+ // Internal Signals
+ // --------------------------------------------------
+ genvar i;
+
+ reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
+ reg [ADDR_WIDTH-1 : 0] wr_ptr;
+ reg [ADDR_WIDTH-1 : 0] rd_ptr;
+ reg [DEPTH-1 : 0] mem_used;
+
+ wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
+ wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
+ wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
+ wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
+
+ wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
+
+ wire read;
+ wire write;
+
+ reg empty;
+ reg next_empty;
+ reg full;
+ reg next_full;
+
+ wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
+ wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
+ wire [PAYLOAD_WIDTH-1 : 0] in_payload;
+ reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
+ reg [PAYLOAD_WIDTH-1 : 0] out_payload;
+
+ reg internal_out_valid;
+ wire internal_out_ready;
+
+ reg [ADDR_WIDTH : 0] fifo_fill_level;
+ reg [ADDR_WIDTH : 0] fill_level;
+
+ reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
+ reg [23:0] almost_full_threshold;
+ reg [23:0] almost_empty_threshold;
+ reg [23:0] cut_through_threshold;
+ reg [15:0] pkt_cnt;
+ reg [15:0] pkt_cnt_r;
+ reg [15:0] pkt_cnt_plusone;
+ reg [15:0] pkt_cnt_minusone;
+ reg drop_on_error_en;
+ reg error_in_pkt;
+ reg pkt_has_started;
+ reg sop_has_left_fifo;
+ reg fifo_too_small_r;
+ reg pkt_cnt_eq_zero;
+ reg pkt_cnt_eq_one;
+ reg pkt_cnt_changed;
+
+ wire wait_for_threshold;
+ reg pkt_mode;
+ wire wait_for_pkt;
+ wire ok_to_forward;
+ wire in_pkt_eop_arrive;
+ wire out_pkt_leave;
+ wire in_pkt_start;
+ wire in_pkt_error;
+ wire drop_on_error;
+ wire fifo_too_small;
+ wire out_pkt_sop_leave;
+ wire [31:0] max_fifo_size;
+ reg fifo_fill_level_lt_cut_through_threshold;
+
+ // --------------------------------------------------
+ // Define Payload
+ //
+ // Icky part where we decide which signals form the
+ // payload to the FIFO with generate blocks.
+ // --------------------------------------------------
+ generate
+ if (EMPTY_WIDTH > 0) begin
+ assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
+ assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
+ end
+ else begin
+ assign out_empty = in_error;
+ assign in_packet_signals = {in_startofpacket, in_endofpacket};
+ assign {out_startofpacket, out_endofpacket} = out_packet_signals;
+ end
+ endgenerate
+
+ generate
+ if (USE_PACKETS) begin
+ if (ERROR_WIDTH > 0) begin
+ if (CHANNEL_WIDTH > 0) begin
+ assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
+ assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
+ end
+ else begin
+ assign out_channel = in_channel;
+ assign in_payload = {in_packet_signals, in_data, in_error};
+ assign {out_packet_signals, out_data, out_error} = out_payload;
+ end
+ end
+ else begin
+ assign out_error = in_error;
+ if (CHANNEL_WIDTH > 0) begin
+ assign in_payload = {in_packet_signals, in_data, in_channel};
+ assign {out_packet_signals, out_data, out_channel} = out_payload;
+ end
+ else begin
+ assign out_channel = in_channel;
+ assign in_payload = {in_packet_signals, in_data};
+ assign {out_packet_signals, out_data} = out_payload;
+ end
+ end
+ end
+ else begin
+ assign out_packet_signals = 0;
+ if (ERROR_WIDTH > 0) begin
+ if (CHANNEL_WIDTH > 0) begin
+ assign in_payload = {in_data, in_error, in_channel};
+ assign {out_data, out_error, out_channel} = out_payload;
+ end
+ else begin
+ assign out_channel = in_channel;
+ assign in_payload = {in_data, in_error};
+ assign {out_data, out_error} = out_payload;
+ end
+ end
+ else begin
+ assign out_error = in_error;
+ if (CHANNEL_WIDTH > 0) begin
+ assign in_payload = {in_data, in_channel};
+ assign {out_data, out_channel} = out_payload;
+ end
+ else begin
+ assign out_channel = in_channel;
+ assign in_payload = in_data;
+ assign out_data = out_payload;
+ end
+ end
+ end
+ endgenerate
+
+ // --------------------------------------------------
+ // Memory-based FIFO storage
+ //
+ // To allow a ready latency of 0, the read index is
+ // obtained from the next read pointer and memory
+ // outputs are unregistered.
+ //
+ // If the empty latency is 1, we infer bypass logic
+ // around the memory so writes propagate to the
+ // outputs on the next cycle.
+ //
+ // Do not change the way this is coded: Quartus needs
+ // a perfect match to the template, and any attempt to
+ // refactor the two always blocks into one will break
+ // memory inference.
+ // --------------------------------------------------
+ generate if (USE_MEMORY_BLOCKS == 1) begin
+
+ if (EMPTY_LATENCY == 1) begin
+
+ always @(posedge clk) begin
+ if (in_valid && in_ready)
+ mem[wr_ptr] = in_payload;
+
+ internal_out_payload = mem[mem_rd_ptr];
+ end
+
+ end else begin
+
+ always @(posedge clk) begin
+ if (in_valid && in_ready)
+ mem[wr_ptr] <= in_payload;
+
+ internal_out_payload <= mem[mem_rd_ptr];
+ end
+
+ end
+
+ assign mem_rd_ptr = next_rd_ptr;
+
+ end else begin
+
+ // --------------------------------------------------
+ // Register-based FIFO storage
+ //
+ // Uses a shift register as the storage element. Each
+ // shift register slot has a bit which indicates if
+ // the slot is occupied (credit to Sam H for the idea).
+ // The occupancy bits are contiguous and start from the
+ // lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
+ // FIFO.
+ //
+ // Each slot is enabled during a read or when it
+ // is unoccupied. New data is always written to every
+ // going-to-be-empty slot (we keep track of which ones
+ // are actually useful with the occupancy bits). On a
+ // read we shift occupied slots.
+ //
+ // The exception is the last slot, which always gets
+ // new data when it is unoccupied.
+ // --------------------------------------------------
+ for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ mem[i] <= 0;
+ end
+ else if (read || !mem_used[i]) begin
+ if (!mem_used[i+1])
+ mem[i] <= in_payload;
+ else
+ mem[i] <= mem[i+1];
+ end
+ end
+ end
+
+ always @(posedge clk, posedge reset) begin
+ if (reset) begin
+ mem[DEPTH-1] <= 0;
+ end
+ else begin
+ if (!mem_used[DEPTH-1])
+ mem[DEPTH-1] <= in_payload;
+
+ if (DEPTH == 1) begin
+ if (write)
+ mem[DEPTH-1] <= in_payload;
+ end
+ end
+ end
+
+ end
+ endgenerate
+
+ assign read = internal_out_ready && internal_out_valid && ok_to_forward;
+ assign write = in_ready && in_valid;
+
+ // --------------------------------------------------
+ // Pointer Management
+ // --------------------------------------------------
+ generate if (USE_MEMORY_BLOCKS == 1) begin
+
+ assign incremented_wr_ptr = wr_ptr + 1'b1;
+ assign incremented_rd_ptr = rd_ptr + 1'b1;
+ assign next_wr_ptr = drop_on_error ? sop_ptr : write ? incremented_wr_ptr : wr_ptr;
+ assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
+
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ wr_ptr <= 0;
+ rd_ptr <= 0;
+ end
+ else begin
+ wr_ptr <= next_wr_ptr;
+ rd_ptr <= next_rd_ptr;
+ end
+ end
+
+ end else begin
+
+ // --------------------------------------------------
+ // Shift Register Occupancy Bits
+ //
+ // Consider a 4-deep FIFO with 2 entries: 0011
+ // On a read and write, do not modify the bits.
+ // On a write, left-shift the bits to get 0111.
+ // On a read, right-shift the bits to get 0001.
+ //
+ // Also, on a write we set bit0 (the head), while
+ // clearing the tail on a read.
+ // --------------------------------------------------
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ mem_used[0] <= 0;
+ end
+ else begin
+ if (write ^ read) begin
+ if (read) begin
+ if (DEPTH > 1)
+ mem_used[0] <= mem_used[1];
+ else
+ mem_used[0] <= 0;
+ end
+ if (write)
+ mem_used[0] <= 1;
+ end
+ end
+ end
+
+ if (DEPTH > 1) begin
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ mem_used[DEPTH-1] <= 0;
+ end
+ else begin
+ if (write ^ read) begin
+ mem_used[DEPTH-1] <= 0;
+ if (write)
+ mem_used[DEPTH-1] <= mem_used[DEPTH-2];
+ end
+ end
+ end
+ end
+
+ for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
+ always @(posedge clk, posedge reset) begin
+ if (reset) begin
+ mem_used[i] <= 0;
+ end
+ else begin
+ if (write ^ read) begin
+ if (read)
+ mem_used[i] <= mem_used[i+1];
+ if (write)
+ mem_used[i] <= mem_used[i-1];
+ end
+ end
+ end
+ end
+
+ end
+ endgenerate
+
+
+ // --------------------------------------------------
+ // Memory FIFO Status Management
+ //
+ // Generates the full and empty signals from the
+ // pointers. The FIFO is full when the next write
+ // pointer will be equal to the read pointer after
+ // a write. Reading from a FIFO clears full.
+ //
+ // The FIFO is empty when the next read pointer will
+ // be equal to the write pointer after a read. Writing
+ // to a FIFO clears empty.
+ //
+ // A simultaneous read and write must not change any of
+ // the empty or full flags unless there is a drop on error event.
+ // --------------------------------------------------
+ generate if (USE_MEMORY_BLOCKS == 1) begin
+
+ always @* begin
+ next_full = full;
+ next_empty = empty;
+
+ if (read && !write) begin
+ next_full = 1'b0;
+
+ if (incremented_rd_ptr == wr_ptr)
+ next_empty = 1'b1;
+ end
+
+ if (write && !read) begin
+ if (!drop_on_error)
+ next_empty = 1'b0;
+ else if (sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
+ next_empty = 1'b1;
+
+ if (incremented_wr_ptr == rd_ptr && !drop_on_error)
+ next_full = 1'b1;
+ end
+
+ if (write && read && drop_on_error) begin
+ if (sop_ptr == next_rd_ptr)
+ next_empty = 1'b1;
+ end
+ end
+
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ empty <= 1;
+ full <= 0;
+ end
+ else begin
+ empty <= next_empty;
+ full <= next_full;
+ end
+ end
+
+ end else begin
+ // --------------------------------------------------
+ // Register FIFO Status Management
+ //
+ // Full when the tail occupancy bit is 1. Empty when
+ // the head occupancy bit is 0.
+ // --------------------------------------------------
+ always @* begin
+ full = mem_used[DEPTH-1];
+ empty = !mem_used[0];
+
+ // ------------------------------------------
+ // For a single slot FIFO, reading clears the
+ // full status immediately.
+ // ------------------------------------------
+ if (DEPTH == 1)
+ full = mem_used[0] && !read;
+
+ internal_out_payload = mem[0];
+
+ // ------------------------------------------
+ // Writes clear empty immediately for lookahead modes.
+ // Note that we use in_valid instead of write to avoid
+ // combinational loops (in lookahead mode, qualifying
+ // with in_ready is meaningless).
+ //
+ // In a 1-deep FIFO, a possible combinational loop runs
+ // from write -> out_valid -> out_ready -> write
+ // ------------------------------------------
+ if (EMPTY_LATENCY == 0) begin
+ empty = !mem_used[0] && !in_valid;
+
+ if (!mem_used[0] && in_valid)
+ internal_out_payload = in_payload;
+ end
+ end
+
+ end
+ endgenerate
+
+ // --------------------------------------------------
+ // Avalon-ST Signals
+ //
+ // The in_ready signal is straightforward.
+ //
+ // To match memory latency when empty latency > 1,
+ // out_valid assertions must be delayed by one clock
+ // cycle.
+ //
+ // Note: out_valid deassertions must not be delayed or
+ // the FIFO will underflow.
+ // --------------------------------------------------
+ assign in_ready = !full;
+ assign internal_out_ready = out_ready || !out_valid;
+
+ generate if (EMPTY_LATENCY > 1) begin
+ always @(posedge clk or posedge reset) begin
+ if (reset)
+ internal_out_valid <= 0;
+ else begin
+ internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
+
+ if (read) begin
+ if (incremented_rd_ptr == wr_ptr)
+ internal_out_valid <= 1'b0;
+ end
+ end
+ end
+ end else begin
+ always @* begin
+ internal_out_valid = !empty & ok_to_forward;
+ end
+ end
+ endgenerate
+
+ // --------------------------------------------------
+ // Single Output Pipeline Stage
+ //
+ // This output pipeline stage is enabled if the FIFO's
+ // empty latency is set to 3 (default). It is disabled
+ // for all other allowed latencies.
+ //
+ // Reason: The memory outputs are unregistered, so we have to
+ // register the output or fmax will drop if combinatorial
+ // logic is present on the output datapath.
+ //
+ // Q: The Avalon-ST spec says that I have to register my outputs
+ // But isn't the memory counted as a register?
+ // A: The path from the address lookup to the memory output is
+ // slow. Registering the memory outputs is a good idea.
+ //
+ // The registers get packed into the memory by the fitter
+ // which means minimal resources are consumed (the result
+ // is a altsyncram with registered outputs, available on
+ // all modern Altera devices).
+ //
+ // This output stage acts as an extra slot in the FIFO,
+ // and complicates the fill level.
+ // --------------------------------------------------
+ generate if (EMPTY_LATENCY == 3) begin
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ out_valid <= 0;
+ out_payload <= 0;
+ end
+ else begin
+ if (internal_out_ready) begin
+ out_valid <= internal_out_valid & ok_to_forward;
+ out_payload <= internal_out_payload;
+ end
+ end
+ end
+ end
+ else begin
+ always @* begin
+ out_valid = internal_out_valid;
+ out_payload = internal_out_payload;
+ end
+ end
+ endgenerate
+
+ // --------------------------------------------------
+ // Fill Level
+ //
+ // The fill level is calculated from the next write
+ // and read pointers to avoid unnecessary latency.
+ //
+ // If the output pipeline is enabled, the fill level
+ // must account for it, or we'll always be off by one.
+ // This may, or may not be important depending on the
+ // application.
+ //
+ // For now, we'll always calculate the exact fill level
+ // at the cost of an extra adder when the output stage
+ // is enabled.
+ // --------------------------------------------------
+ generate if (USE_FILL_LEVEL) begin
+ wire [31:0] depth32;
+ assign depth32 = DEPTH;
+ always @(posedge clk or posedge reset) begin
+ if (reset)
+ fifo_fill_level <= 0;
+ else if (next_full & !drop_on_error)
+ fifo_fill_level <= depth32[ADDR_WIDTH:0];
+ else begin
+ fifo_fill_level[ADDR_WIDTH] <= 1'b0;
+ fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
+ end
+ end
+
+ always @* begin
+ fill_level = fifo_fill_level;
+
+ if (EMPTY_LATENCY == 3)
+ fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
+ end
+ end
+ else begin
+ always @* begin
+ fill_level = 0;
+ end
+ end
+ endgenerate
+
+ generate if (USE_ALMOST_FULL_IF) begin
+ assign almost_full_data = (fill_level >= almost_full_threshold);
+ end
+ else
+ assign almost_full_data = 0;
+ endgenerate
+
+ generate if (USE_ALMOST_EMPTY_IF) begin
+ assign almost_empty_data = (fill_level <= almost_empty_threshold);
+ end
+ else
+ assign almost_empty_data = 0;
+ endgenerate
+
+ // --------------------------------------------------
+ // Avalon-MM Status & Control Connection Point
+ //
+ // Register map:
+ //
+ // | Addr | RW | 31 - 0 |
+ // | 0 | R | Fill level |
+ //
+ // The registering of this connection point means
+ // that there is a cycle of latency between
+ // reads/writes and the updating of the fill level.
+ // --------------------------------------------------
+ generate if (USE_STORE_FORWARD) begin
+ assign max_fifo_size = FIFO_DEPTH - 1;
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ almost_full_threshold <= max_fifo_size[23 : 0];
+ almost_empty_threshold <= 0;
+ cut_through_threshold <= 0;
+ drop_on_error_en <= 0;
+ csr_readdata <= 0;
+ pkt_mode <= 1'b1;
+ end
+ else begin
+ if (csr_write) begin
+ if(csr_address == 3'b010)
+ almost_full_threshold <= csr_writedata[23:0];
+ if(csr_address == 3'b011)
+ almost_empty_threshold <= csr_writedata[23:0];
+ if(csr_address == 3'b100) begin
+ cut_through_threshold <= csr_writedata[23:0];
+ pkt_mode <= (csr_writedata[23:0] == 0);
+ end
+ if(csr_address == 3'b101)
+ drop_on_error_en <= csr_writedata[0];
+ end
+
+ if (csr_read) begin
+ csr_readdata <= 32'b0;
+ if (csr_address == 0)
+ csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
+ if (csr_address == 2)
+ csr_readdata <= {8'b0, almost_full_threshold};
+ if (csr_address == 3)
+ csr_readdata <= {8'b0, almost_empty_threshold};
+ if (csr_address == 4)
+ csr_readdata <= {8'b0, cut_through_threshold};
+ if (csr_address == 5)
+ csr_readdata <= {31'b0, drop_on_error_en};
+ end
+ end
+ end
+ end
+ else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin
+ assign max_fifo_size = FIFO_DEPTH - 1;
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ almost_full_threshold <= max_fifo_size[23 : 0];
+ almost_empty_threshold <= 0;
+ csr_readdata <= 0;
+ end
+ else begin
+ if (csr_write) begin
+ if(csr_address == 3'b010)
+ almost_full_threshold <= csr_writedata[23:0];
+ if(csr_address == 3'b011)
+ almost_empty_threshold <= csr_writedata[23:0];
+ end
+
+ if (csr_read) begin
+ csr_readdata <= 32'b0;
+ if (csr_address == 0)
+ csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
+ if (csr_address == 2)
+ csr_readdata <= {8'b0, almost_full_threshold};
+ if (csr_address == 3)
+ csr_readdata <= {8'b0, almost_empty_threshold};
+ end
+ end
+ end
+ end
+ else begin
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ csr_readdata <= 0;
+ end
+ else if (csr_read) begin
+ csr_readdata <= 0;
+
+ if (csr_address == 0)
+ csr_readdata <= fill_level;
+ end
+ end
+ end
+ endgenerate
+
+ // --------------------------------------------------
+ // Store and forward logic
+ // --------------------------------------------------
+ // if the fifo gets full before the entire packet or the
+ // cut-threshold condition is met then start sending out
+ // data in order to avoid dead-lock situation
+
+ generate if (USE_STORE_FORWARD) begin
+ assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
+ assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
+ assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
+ ~wait_for_threshold) | fifo_too_small_r;
+ assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
+ assign in_pkt_start = in_valid & in_ready & in_startofpacket;
+ assign in_pkt_error = in_valid & in_ready & |in_error;
+ assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
+ assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
+ assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
+
+ // count packets coming and going into the fifo
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ pkt_cnt <= 0;
+ pkt_cnt_r <= 0;
+ pkt_cnt_plusone <= 1;
+ pkt_cnt_minusone <= 0;
+ pkt_cnt_changed <= 0;
+ pkt_has_started <= 0;
+ sop_has_left_fifo <= 0;
+ fifo_too_small_r <= 0;
+ pkt_cnt_eq_zero <= 1'b1;
+ pkt_cnt_eq_one <= 1'b0;
+ fifo_fill_level_lt_cut_through_threshold <= 1'b1;
+ end
+ else begin
+ fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
+ fifo_too_small_r <= fifo_too_small;
+ pkt_cnt_plusone <= pkt_cnt + 1'b1;
+ pkt_cnt_minusone <= pkt_cnt - 1'b1;
+ pkt_cnt_r <= pkt_cnt;
+ pkt_cnt_changed <= 1'b0;
+
+ if( in_pkt_eop_arrive )
+ sop_has_left_fifo <= 1'b0;
+ else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
+ sop_has_left_fifo <= 1'b1;
+
+ if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
+ pkt_cnt_changed <= 1'b1;
+ pkt_cnt <= pkt_cnt_changed ? pkt_cnt_r : pkt_cnt_plusone;
+ pkt_cnt_eq_zero <= 0;
+ if (pkt_cnt == 0)
+ pkt_cnt_eq_one <= 1'b1;
+ else
+ pkt_cnt_eq_one <= 1'b0;
+ end
+ else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
+ pkt_cnt_changed <= 1'b1;
+ pkt_cnt <= pkt_cnt_changed ? pkt_cnt_r : pkt_cnt_minusone;
+ if (pkt_cnt == 1)
+ pkt_cnt_eq_zero <= 1'b1;
+ else
+ pkt_cnt_eq_zero <= 1'b0;
+ if (pkt_cnt == 2)
+ pkt_cnt_eq_one <= 1'b1;
+ else
+ pkt_cnt_eq_one <= 1'b0;
+ end
+
+ if (in_pkt_start)
+ pkt_has_started <= 1'b1;
+ else if (in_pkt_eop_arrive)
+ pkt_has_started <= 1'b0;
+ end
+ end
+
+ // drop on error logic
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ sop_ptr <= 0;
+ error_in_pkt <= 0;
+ end
+ else begin
+ // save the location of the SOP
+ if ( in_pkt_start )
+ sop_ptr <= wr_ptr;
+
+ // remember if error in pkt
+ // log error only if packet has already started
+ if (in_pkt_eop_arrive)
+ error_in_pkt <= 1'b0;
+ else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
+ error_in_pkt <= 1'b1;
+ end
+ end
+ assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
+ ~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
+
+ end
+ else begin
+ assign ok_to_forward = 1'b1;
+ assign drop_on_error = 1'b0;
+ end
+ endgenerate
+
+
+ // --------------------------------------------------
+ // Calculates the log2ceil of the input value
+ // --------------------------------------------------
+ function integer log2ceil;
+ input integer val;
+ integer i;
+
+ begin
+ i = 1;
+ log2ceil = 0;
+
+ while (i < val) begin
+ log2ceil = log2ceil + 1;
+ i = i << 1;
+ end
+ end
+ endfunction
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_st_clock_crosser.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_st_clock_crosser.v
new file mode 100644
index 0000000000000000000000000000000000000000..91805b13d675f58d99e57f07593b13476838dd2e
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_st_clock_crosser.v
@@ -0,0 +1,135 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1ns / 1ns
+
+module altera_avalon_st_clock_crosser(
+ in_clk,
+ in_reset,
+ in_ready,
+ in_valid,
+ in_data,
+ out_clk,
+ out_reset,
+ out_ready,
+ out_valid,
+ out_data
+ );
+
+ parameter SYMBOLS_PER_BEAT = 1;
+ parameter BITS_PER_SYMBOL = 8;
+ parameter FORWARD_SYNC_DEPTH = 2;
+ parameter BACKWARD_SYNC_DEPTH = 2;
+ parameter USE_OUTPUT_PIPELINE = 1;
+
+ localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
+
+ input in_clk;
+ input in_reset;
+ output in_ready;
+ input in_valid;
+ input [DATA_WIDTH-1:0] in_data;
+
+ input out_clk;
+ input out_reset;
+ input out_ready;
+ output out_valid;
+ output [DATA_WIDTH-1:0] out_data;
+
+ // Data is guaranteed valid by control signal clock crossing. Cut data
+ // buffer false path.
+ (* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\" ; -name SDC_STATEMENT \"set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
+ reg [DATA_WIDTH-1:0] out_data_buffer;
+
+ reg in_data_toggle;
+ wire in_data_toggle_returned;
+ wire out_data_toggle;
+ reg out_data_toggle_flopped;
+
+ wire take_in_data;
+ wire out_data_taken;
+
+ wire out_valid_internal;
+ wire out_ready_internal;
+
+ assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
+ assign take_in_data = in_valid & in_ready;
+ assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
+ assign out_data_taken = out_ready_internal & out_valid_internal;
+
+ always @(posedge in_clk or posedge in_reset) begin
+ if (in_reset) begin
+ in_data_buffer <= 'b0;
+ in_data_toggle <= 1'b0;
+ end else begin
+ if (take_in_data) begin
+ in_data_toggle <= ~in_data_toggle;
+ in_data_buffer <= in_data;
+ end
+ end //in_reset
+ end //in_clk always block
+
+ always @(posedge out_clk or posedge out_reset) begin
+ if (out_reset) begin
+ out_data_toggle_flopped <= 1'b0;
+ out_data_buffer <= 'b0;
+ end else begin
+ out_data_buffer <= in_data_buffer;
+ if (out_data_taken) begin
+ out_data_toggle_flopped <= out_data_toggle;
+ end
+ end //end if
+ end //out_clk always block
+
+ altera_std_synchronizer #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
+ .clk(out_clk),
+ .reset_n(~out_reset),
+ .din(in_data_toggle),
+ .dout(out_data_toggle)
+ );
+
+ altera_std_synchronizer #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
+ .clk(in_clk),
+ .reset_n(~in_reset),
+ .din(out_data_toggle_flopped),
+ .dout(in_data_toggle_returned)
+ );
+
+ generate if (USE_OUTPUT_PIPELINE == 1) begin
+
+ altera_avalon_st_pipeline_base
+ #(
+ .BITS_PER_SYMBOL(BITS_PER_SYMBOL),
+ .SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
+ ) output_stage (
+ .clk(out_clk),
+ .reset(out_reset),
+ .in_ready(out_ready_internal),
+ .in_valid(out_valid_internal),
+ .in_data(out_data_buffer),
+ .out_ready(out_ready),
+ .out_valid(out_valid),
+ .out_data(out_data)
+ );
+
+ end else begin
+
+ assign out_valid = out_valid_internal;
+ assign out_ready_internal = out_ready;
+ assign out_data = out_data_buffer;
+
+ end
+
+ endgenerate
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_st_delay.sv b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_st_delay.sv
new file mode 100644
index 0000000000000000000000000000000000000000..2a0832dbb194490e7d24e35b52b4b9fdc2b61266
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_st_delay.sv
@@ -0,0 +1,174 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1ns / 1ns
+
+module altera_avalon_st_delay #(
+ parameter
+ NUMBER_OF_DELAY_CLOCKS = 1,
+
+ DATA_WIDTH = 8,
+ BITS_PER_SYMBOL = 8,
+
+ USE_PACKETS = 0,
+
+ USE_CHANNEL = 0,
+ CHANNEL_WIDTH = 1,
+
+ USE_ERROR = 0,
+ ERROR_WIDTH = 1,
+
+ // Derived parameters
+ SYMBOLS_PER_BEAT = DATA_WIDTH / BITS_PER_SYMBOL,
+ EMPTY_WV = USE_PACKETS ? (
+ (SYMBOLS_PER_BEAT > 128) ? 8 :
+ (SYMBOLS_PER_BEAT > 64) ? 7 :
+ (SYMBOLS_PER_BEAT > 32) ? 6 :
+ (SYMBOLS_PER_BEAT > 16) ? 5 :
+ (SYMBOLS_PER_BEAT > 8) ? 4 :
+ (SYMBOLS_PER_BEAT > 4) ? 3 :
+ (SYMBOLS_PER_BEAT > 2) ? 2 :
+ (SYMBOLS_PER_BEAT > 1) ? 1 :
+ 1) : 1,
+
+ CHANNEL_WV = USE_CHANNEL ? CHANNEL_WIDTH : 1,
+
+ ERROR_WV = USE_ERROR ? ERROR_WIDTH : 1
+ )
+(
+ input wire in0_valid,
+ input wire [DATA_WIDTH-1 :0] in0_data,
+ input wire [CHANNEL_WV-1 :0] in0_channel,
+ input wire [ERROR_WV-1 :0] in0_error,
+ input wire in0_startofpacket,
+ input wire in0_endofpacket,
+ input wire [EMPTY_WV-1 :0] in0_empty,
+
+ output wire out0_valid,
+ output wire [DATA_WIDTH-1 :0] out0_data,
+ output wire [CHANNEL_WV-1 :0] out0_channel,
+ output wire [ERROR_WV-1 :0] out0_error,
+ output wire out0_startofpacket,
+ output wire out0_endofpacket,
+ output wire [EMPTY_WV-1 :0] out0_empty,
+
+ input wire reset_n,
+ input wire clk
+);
+
+
+// ********************************************************************
+// Module Wiring
+
+wire [16:0] OutValid;
+wire [DATA_WIDTH-1 :0] OutData [16:0];
+wire [CHANNEL_WV-1 :0] OutChannel [16:0];
+wire [ERROR_WV-1 :0] OutError [16:0];
+wire [16:0] OutSOP;
+wire [16:0] OutEOP;
+wire [EMPTY_WV-1 :0] OutEmpty [16:0];
+
+genvar i;
+
+
+// ********************************************************************
+// Module Logic
+
+assign OutValid[0] = in0_valid;
+assign OutData[0] = in0_data;
+assign OutChannel[0] = in0_channel;
+assign OutError[0] = in0_error;
+assign OutSOP[0] = in0_startofpacket;
+assign OutEOP[0] = in0_endofpacket;
+assign OutEmpty[0] = in0_empty;
+
+
+generate
+ for (i=0; i < NUMBER_OF_DELAY_CLOCKS; i=i+1) begin : DELAY_PORT
+ altera_st_delay_reg #(DATA_WIDTH, CHANNEL_WV, ERROR_WV, EMPTY_WV) U
+ (OutValid[i],
+ OutData[i],
+ OutChannel[i],
+ OutError[i],
+ OutSOP[i],
+ OutEOP[i],
+ OutEmpty[i],
+ OutValid[i+1],
+ OutData[i+1],
+ OutChannel[i+1],
+ OutError[i+1],
+ OutSOP[i+1],
+ OutEOP[i+1],
+ OutEmpty[i+1],
+ reset_n,
+ clk);
+ end
+endgenerate
+
+
+assign out0_valid = OutValid[NUMBER_OF_DELAY_CLOCKS];
+assign out0_data = OutData[NUMBER_OF_DELAY_CLOCKS];
+assign out0_channel = OutChannel[NUMBER_OF_DELAY_CLOCKS];
+assign out0_error = OutError[NUMBER_OF_DELAY_CLOCKS];
+assign out0_startofpacket = OutSOP[NUMBER_OF_DELAY_CLOCKS];
+assign out0_endofpacket = OutEOP[NUMBER_OF_DELAY_CLOCKS];
+assign out0_empty = OutEmpty[NUMBER_OF_DELAY_CLOCKS];
+
+
+endmodule
+
+
+module altera_st_delay_reg #(
+ parameter DATA_WIDTH = 8, CHANNEL_WV = 1, ERROR_WV = 1, EMPTY_WV = 1)
+(
+ input wire in_valid,
+ input wire [DATA_WIDTH-1 :0] in_data,
+ input wire [CHANNEL_WV-1 :0] in_channel,
+ input wire [ERROR_WV-1 :0] in_error,
+ input wire in_startofpacket,
+ input wire in_endofpacket,
+ input wire [EMPTY_WV-1 :0] in_empty,
+
+ output reg out_valid,
+ output reg [DATA_WIDTH-1 :0] out_data,
+ output reg [CHANNEL_WV-1 :0] out_channel,
+ output reg [ERROR_WV-1 :0] out_error,
+ output reg out_startofpacket,
+ output reg out_endofpacket,
+ output reg [EMPTY_WV-1 :0] out_empty,
+
+ input wire reset_n,
+ input wire clk
+);
+
+
+always @(posedge clk) begin
+ if (!reset_n)
+ out_valid <= 1'b0;
+ else
+ out_valid <= in_valid;
+end
+
+
+always @(posedge clk) begin
+ out_data <= in_data;
+ out_channel <= in_channel;
+ out_error <= in_error;
+ out_startofpacket <= in_startofpacket;
+ out_endofpacket <= in_endofpacket;
+ out_empty <= in_empty;
+end
+
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_st_handshake_clock_crosser.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_st_handshake_clock_crosser.v
new file mode 100644
index 0000000000000000000000000000000000000000..6ab493fa823a074eaccb781d90fd089dae5877e7
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_st_handshake_clock_crosser.v
@@ -0,0 +1,212 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// -----------------------------------------------
+// Clock crosser module with handshaking mechanism
+// -----------------------------------------------
+
+module altera_avalon_st_handshake_clock_crosser
+#(
+ parameter DATA_WIDTH = 8,
+ BITS_PER_SYMBOL = 8,
+ USE_PACKETS = 0,
+
+ // ------------------------------
+ // Optional signal widths
+ // ------------------------------
+ USE_CHANNEL = 0,
+ CHANNEL_WIDTH = 1,
+ USE_ERROR = 0,
+ ERROR_WIDTH = 1,
+
+ VALID_SYNC_DEPTH = 2,
+ READY_SYNC_DEPTH = 2,
+
+ USE_OUTPUT_PIPELINE = 1,
+
+ // ------------------------------
+ // Derived parameters
+ // ------------------------------
+ SYMBOLS_PER_BEAT = DATA_WIDTH / BITS_PER_SYMBOL,
+ EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
+)
+(
+ input in_clk,
+ input in_reset,
+ input out_clk,
+ input out_reset,
+
+ output in_ready,
+ input in_valid,
+ input [DATA_WIDTH - 1 : 0] in_data,
+ input [CHANNEL_WIDTH - 1 : 0] in_channel,
+ input [ERROR_WIDTH - 1 : 0] in_error,
+ input in_startofpacket,
+ input in_endofpacket,
+ input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
+
+ input out_ready,
+ output out_valid,
+ output [DATA_WIDTH - 1 : 0] out_data,
+ output [CHANNEL_WIDTH - 1 : 0] out_channel,
+ output [ERROR_WIDTH - 1 : 0] out_error,
+ output out_startofpacket,
+ output out_endofpacket,
+ output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
+);
+
+ // ------------------------------
+ // Payload-specific widths
+ // ------------------------------
+ localparam PACKET_WIDTH = (USE_PACKETS) ? 2 + EMPTY_WIDTH : 0;
+ localparam PCHANNEL_W = (USE_CHANNEL) ? CHANNEL_WIDTH : 0;
+ localparam PERROR_W = (USE_ERROR) ? ERROR_WIDTH : 0;
+
+ localparam PAYLOAD_WIDTH = DATA_WIDTH +
+ PACKET_WIDTH +
+ PCHANNEL_W +
+ EMPTY_WIDTH +
+ PERROR_W;
+
+
+ wire [PAYLOAD_WIDTH - 1: 0] in_payload;
+ wire [PAYLOAD_WIDTH - 1: 0] out_payload;
+
+ // ------------------------------
+ // Assign in_data and other optional sink interface
+ // signals to in_payload.
+ // ------------------------------
+ assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
+ generate
+ // optional packet inputs
+ if (PACKET_WIDTH) begin
+ assign in_payload[
+ DATA_WIDTH + PACKET_WIDTH - 1 :
+ DATA_WIDTH
+ ] = {in_startofpacket, in_endofpacket};
+ end
+ // optional channel input
+ if (USE_CHANNEL) begin
+ assign in_payload[
+ DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
+ DATA_WIDTH + PACKET_WIDTH
+ ] = in_channel;
+ end
+ // optional empty input
+ if (EMPTY_WIDTH) begin
+ assign in_payload[
+ DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
+ DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
+ ] = in_empty;
+ end
+ // optional error input
+ if (USE_ERROR) begin
+ assign in_payload[
+ DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
+ DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
+ ] = in_error;
+ end
+ endgenerate
+
+ // --------------------------------------------------
+ // Pipe the input payload to our inner module which handles the
+ // actual clock crossing
+ // --------------------------------------------------
+ altera_avalon_st_clock_crosser
+ #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (PAYLOAD_WIDTH),
+ .FORWARD_SYNC_DEPTH (VALID_SYNC_DEPTH),
+ .BACKWARD_SYNC_DEPTH (READY_SYNC_DEPTH),
+ .USE_OUTPUT_PIPELINE (USE_OUTPUT_PIPELINE)
+ ) clock_xer (
+ .in_clk (in_clk ),
+ .in_reset (in_reset ),
+ .in_ready (in_ready ),
+ .in_valid (in_valid ),
+ .in_data (in_payload ),
+ .out_clk (out_clk ),
+ .out_reset (out_reset ),
+ .out_ready (out_ready ),
+ .out_valid (out_valid ),
+ .out_data (out_payload )
+ );
+
+ // --------------------------------------------------
+ // Split out_payload into the output signals.
+ // --------------------------------------------------
+ assign out_data = out_payload[DATA_WIDTH - 1 : 0];
+
+ generate
+ // optional packet outputs
+ if (USE_PACKETS) begin
+ assign {out_startofpacket, out_endofpacket} =
+ out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
+ end else begin
+ // avoid a "has no driver" warning.
+ assign {out_startofpacket, out_endofpacket} = 2'b0;
+ end
+
+ // optional channel output
+ if (USE_CHANNEL) begin
+ assign out_channel = out_payload[
+ DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
+ DATA_WIDTH + PACKET_WIDTH
+ ];
+ end else begin
+ // avoid a "has no driver" warning.
+ assign out_channel = 1'b0;
+ end
+
+ // optional empty output
+ if (EMPTY_WIDTH) begin
+ assign out_empty = out_payload[
+ DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
+ DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
+ ];
+ end else begin
+ // avoid a "has no driver" warning.
+ assign out_empty = 1'b0;
+ end
+
+ // optional error output
+ if (USE_ERROR) begin
+ assign out_error = out_payload[
+ DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
+ DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
+ ];
+ end else begin
+ // avoid a "has no driver" warning.
+ assign out_error = 1'b0;
+ end
+ endgenerate
+
+ // --------------------------------------------------
+ // Calculates the log2ceil of the input value.
+ // --------------------------------------------------
+ function integer log2ceil;
+ input integer val;
+ integer i;
+
+ begin
+ i = 1;
+ log2ceil = 0;
+
+ while (i < val) begin
+ log2ceil = log2ceil + 1;
+ i = i << 1;
+ end
+ end
+ endfunction
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_st_pipeline_base.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_st_pipeline_base.v
new file mode 100644
index 0000000000000000000000000000000000000000..d4edf573860c7fdc4727abf8d58db933c23d0664
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_st_pipeline_base.v
@@ -0,0 +1,136 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1ns / 1ns
+
+module altera_avalon_st_pipeline_base (
+ clk,
+ reset,
+ in_ready,
+ in_valid,
+ in_data,
+ out_ready,
+ out_valid,
+ out_data
+ );
+
+ parameter SYMBOLS_PER_BEAT = 1;
+ parameter BITS_PER_SYMBOL = 8;
+ parameter PIPELINE_READY = 1;
+ localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
+
+ input clk;
+ input reset;
+
+ output in_ready;
+ input in_valid;
+ input [DATA_WIDTH-1:0] in_data;
+
+ input out_ready;
+ output out_valid;
+ output [DATA_WIDTH-1:0] out_data;
+
+ reg full0;
+ reg full1;
+ reg [DATA_WIDTH-1:0] data0;
+ reg [DATA_WIDTH-1:0] data1;
+
+ assign out_valid = full1;
+ assign out_data = data1;
+
+ generate if (PIPELINE_READY == 1)
+ begin : REGISTERED_READY_PLINE
+
+ assign in_ready = !full0;
+
+ always @(posedge clk, posedge reset) begin
+ if (reset) begin
+ data0 <= 1'b0;
+ data1 <= 1'b0;
+ end else begin
+ // ----------------------------
+ // always load the second slot if we can
+ // ----------------------------
+ if (~full0)
+ data0 <= in_data;
+ // ----------------------------
+ // first slot is loaded either from the second,
+ // or with new data
+ // ----------------------------
+ if (~full1 || (out_ready && out_valid)) begin
+ if (full0)
+ data1 <= data0;
+ else
+ data1 <= in_data;
+ end
+ end
+ end
+
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ full0 <= 1'b0;
+ full1 <= 1'b0;
+ end else begin
+ // no data in pipeline
+ if (~full0 & ~full1) begin
+ if (in_valid) begin
+ full1 <= 1'b1;
+ end
+ end // ~f1 & ~f0
+
+ // one datum in pipeline
+ if (full1 & ~full0) begin
+ if (in_valid & ~out_ready) begin
+ full0 <= 1'b1;
+ end
+ // back to empty
+ if (~in_valid & out_ready) begin
+ full1 <= 1'b0;
+ end
+ end // f1 & ~f0
+
+ // two data in pipeline
+ if (full1 & full0) begin
+ // go back to one datum state
+ if (out_ready) begin
+ full0 <= 1'b0;
+ end
+ end // end go back to one datum stage
+ end
+ end
+
+ end
+ else
+ begin : UNREGISTERED_READY_PLINE
+
+ // in_ready will be a pass through of the out_ready signal as it is not registered
+ assign in_ready = (~full1) | out_ready;
+
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ data1 <= 'b0;
+ full1 <= 1'b0;
+ end
+ else begin
+ if (in_ready) begin
+ data1 <= in_data;
+ full1 <= in_valid;
+ end
+ end
+ end
+
+ end
+ endgenerate
+
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_st_pipeline_stage.sv b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_st_pipeline_stage.sv
new file mode 100644
index 0000000000000000000000000000000000000000..1d22052c0796462cdc1bcf6069c3fb4f53ba0045
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_st_pipeline_stage.sv
@@ -0,0 +1,160 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1ns / 1ns
+
+module altera_avalon_st_pipeline_stage #(
+ parameter
+ SYMBOLS_PER_BEAT = 1,
+ BITS_PER_SYMBOL = 8,
+ USE_PACKETS = 0,
+ USE_EMPTY = 0,
+ PIPELINE_READY = 1,
+
+ // Optional ST signal widths. Value "0" means no such port.
+ CHANNEL_WIDTH = 0,
+ ERROR_WIDTH = 0,
+
+ // Derived parameters
+ DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
+ PACKET_WIDTH = 0,
+ EMPTY_WIDTH = 0
+ )
+ (
+ input clk,
+ input reset,
+
+ output in_ready,
+ input in_valid,
+ input [DATA_WIDTH - 1 : 0] in_data,
+ input [(CHANNEL_WIDTH ? (CHANNEL_WIDTH - 1) : 0) : 0] in_channel,
+ input [(ERROR_WIDTH ? (ERROR_WIDTH - 1) : 0) : 0] in_error,
+ input in_startofpacket,
+ input in_endofpacket,
+ input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
+
+ input out_ready,
+ output out_valid,
+ output [DATA_WIDTH - 1 : 0] out_data,
+ output [(CHANNEL_WIDTH ? (CHANNEL_WIDTH - 1) : 0) : 0] out_channel,
+ output [(ERROR_WIDTH ? (ERROR_WIDTH - 1) : 0) : 0] out_error,
+ output out_startofpacket,
+ output out_endofpacket,
+ output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
+);
+ localparam
+ PAYLOAD_WIDTH =
+ DATA_WIDTH +
+ PACKET_WIDTH +
+ CHANNEL_WIDTH +
+ EMPTY_WIDTH +
+ ERROR_WIDTH;
+
+ wire [PAYLOAD_WIDTH - 1: 0] in_payload;
+ wire [PAYLOAD_WIDTH - 1: 0] out_payload;
+
+ // Assign in_data and other optional in_* interface signals to in_payload.
+ assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
+ generate
+ // optional packet inputs
+ if (PACKET_WIDTH) begin
+ assign in_payload[
+ DATA_WIDTH + PACKET_WIDTH - 1 :
+ DATA_WIDTH
+ ] = {in_startofpacket, in_endofpacket};
+ end
+ // optional channel input
+ if (CHANNEL_WIDTH) begin
+ assign in_payload[
+ DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH - 1 :
+ DATA_WIDTH + PACKET_WIDTH
+ ] = in_channel;
+ end
+ // optional empty input
+ if (EMPTY_WIDTH) begin
+ assign in_payload[
+ DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH - 1 :
+ DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH
+ ] = in_empty;
+ end
+ // optional error input
+ if (ERROR_WIDTH) begin
+ assign in_payload[
+ DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ERROR_WIDTH - 1 :
+ DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH
+ ] = in_error;
+ end
+ endgenerate
+
+ altera_avalon_st_pipeline_base #(
+ .SYMBOLS_PER_BEAT (PAYLOAD_WIDTH),
+ .BITS_PER_SYMBOL (1),
+ .PIPELINE_READY (PIPELINE_READY)
+ ) core (
+ .clk (clk),
+ .reset (reset),
+ .in_ready (in_ready),
+ .in_valid (in_valid),
+ .in_data (in_payload),
+ .out_ready (out_ready),
+ .out_valid (out_valid),
+ .out_data (out_payload)
+ );
+
+ // Assign out_data and other optional out_* interface signals from out_payload.
+ assign out_data = out_payload[DATA_WIDTH - 1 : 0];
+ generate
+ // optional packet outputs
+ if (PACKET_WIDTH) begin
+ assign {out_startofpacket, out_endofpacket} =
+ out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
+ end else begin
+ // Avoid a "has no driver" warning.
+ assign {out_startofpacket, out_endofpacket} = '0;
+ end
+
+ // optional channel output
+ if (CHANNEL_WIDTH) begin
+ assign out_channel = out_payload[
+ DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH - 1 :
+ DATA_WIDTH + PACKET_WIDTH
+ ];
+ end else begin
+ // Avoid a "has no driver" warning.
+ assign out_channel = '0;
+ end
+ // optional empty output
+ if (EMPTY_WIDTH) begin
+ assign out_empty = out_payload[
+ DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH - 1 :
+ DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH
+ ];
+ end else begin
+ // Avoid a "has no driver" warning.
+ assign out_empty = '0;
+ end
+ // optional error output
+ if (ERROR_WIDTH) begin
+ assign out_error = out_payload[
+ DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ERROR_WIDTH - 1 :
+ DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH
+ ];
+ end else begin
+ // Avoid a "has no driver" warning.
+ assign out_error = '0;
+ end
+ endgenerate
+
+endmodule
+
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_st_splitter.sv b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_st_splitter.sv
new file mode 100644
index 0000000000000000000000000000000000000000..316cae6a6918fd4591da379e502c81be0f7e5191
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_avalon_st_splitter.sv
@@ -0,0 +1,415 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1ns / 1ns
+
+module altera_avalon_st_splitter #(
+ parameter
+ NUMBER_OF_OUTPUTS = 2,
+ QUALIFY_VALID_OUT = 1,
+ DATA_WIDTH = 8,
+ BITS_PER_SYMBOL = 8,
+ USE_PACKETS = 0,
+ CHANNEL_WIDTH = 1,
+ ERROR_WIDTH = 1,
+ EMPTY_WIDTH = 1
+ )
+(
+ output wire in0_ready,
+ input wire in0_valid,
+ input wire [DATA_WIDTH-1 :0] in0_data,
+ input wire [CHANNEL_WIDTH-1 :0] in0_channel,
+ input wire [ERROR_WIDTH-1 :0] in0_error,
+ input wire in0_startofpacket,
+ input wire in0_endofpacket,
+ input wire [EMPTY_WIDTH-1 :0] in0_empty,
+
+ input wire out0_ready,
+ output wire out0_valid,
+ output wire [DATA_WIDTH-1 :0] out0_data,
+ output wire [CHANNEL_WIDTH-1 :0] out0_channel,
+ output wire [ERROR_WIDTH-1 :0] out0_error,
+ output wire out0_startofpacket,
+ output wire out0_endofpacket,
+ output wire [EMPTY_WIDTH-1 :0] out0_empty,
+
+ input wire out1_ready,
+ output wire out1_valid,
+ output wire [DATA_WIDTH-1 :0] out1_data,
+ output wire [CHANNEL_WIDTH-1 :0] out1_channel,
+ output wire [ERROR_WIDTH-1 :0] out1_error,
+ output wire out1_startofpacket,
+ output wire out1_endofpacket,
+ output wire [EMPTY_WIDTH-1 :0] out1_empty,
+
+ input wire out2_ready,
+ output wire out2_valid,
+ output wire [DATA_WIDTH-1 :0] out2_data,
+ output wire [CHANNEL_WIDTH-1 :0] out2_channel,
+ output wire [ERROR_WIDTH-1 :0] out2_error,
+ output wire out2_startofpacket,
+ output wire out2_endofpacket,
+ output wire [EMPTY_WIDTH-1 :0] out2_empty,
+
+ input wire out3_ready,
+ output wire out3_valid,
+ output wire [DATA_WIDTH-1 :0] out3_data,
+ output wire [CHANNEL_WIDTH-1 :0] out3_channel,
+ output wire [ERROR_WIDTH-1 :0] out3_error,
+ output wire out3_startofpacket,
+ output wire out3_endofpacket,
+ output wire [EMPTY_WIDTH-1 :0] out3_empty,
+
+ input wire out4_ready,
+ output wire out4_valid,
+ output wire [DATA_WIDTH-1 :0] out4_data,
+ output wire [CHANNEL_WIDTH-1 :0] out4_channel,
+ output wire [ERROR_WIDTH-1 :0] out4_error,
+ output wire out4_startofpacket,
+ output wire out4_endofpacket,
+ output wire [EMPTY_WIDTH-1 :0] out4_empty,
+
+ input wire out5_ready,
+ output wire out5_valid,
+ output wire [DATA_WIDTH-1 :0] out5_data,
+ output wire [CHANNEL_WIDTH-1 :0] out5_channel,
+ output wire [ERROR_WIDTH-1 :0] out5_error,
+ output wire out5_startofpacket,
+ output wire out5_endofpacket,
+ output wire [EMPTY_WIDTH-1 :0] out5_empty,
+
+ input wire out6_ready,
+ output wire out6_valid,
+ output wire [DATA_WIDTH-1 :0] out6_data,
+ output wire [CHANNEL_WIDTH-1 :0] out6_channel,
+ output wire [ERROR_WIDTH-1 :0] out6_error,
+ output wire out6_startofpacket,
+ output wire out6_endofpacket,
+ output wire [EMPTY_WIDTH-1 :0] out6_empty,
+
+ input wire out7_ready,
+ output wire out7_valid,
+ output wire [DATA_WIDTH-1 :0] out7_data,
+ output wire [CHANNEL_WIDTH-1 :0] out7_channel,
+ output wire [ERROR_WIDTH-1 :0] out7_error,
+ output wire out7_startofpacket,
+ output wire out7_endofpacket,
+ output wire [EMPTY_WIDTH-1 :0] out7_empty,
+
+ input wire out8_ready,
+ output wire out8_valid,
+ output wire [DATA_WIDTH-1 :0] out8_data,
+ output wire [CHANNEL_WIDTH-1 :0] out8_channel,
+ output wire [ERROR_WIDTH-1 :0] out8_error,
+ output wire out8_startofpacket,
+ output wire out8_endofpacket,
+ output wire [EMPTY_WIDTH-1 :0] out8_empty,
+
+ input wire out9_ready,
+ output wire out9_valid,
+ output wire [DATA_WIDTH-1 :0] out9_data,
+ output wire [CHANNEL_WIDTH-1 :0] out9_channel,
+ output wire [ERROR_WIDTH-1 :0] out9_error,
+ output wire out9_startofpacket,
+ output wire out9_endofpacket,
+ output wire [EMPTY_WIDTH-1 :0] out9_empty,
+
+ input wire out10_ready,
+ output wire out10_valid,
+ output wire [DATA_WIDTH-1 :0] out10_data,
+ output wire [CHANNEL_WIDTH-1 :0] out10_channel,
+ output wire [ERROR_WIDTH-1 :0] out10_error,
+ output wire out10_startofpacket,
+ output wire out10_endofpacket,
+ output wire [EMPTY_WIDTH-1 :0] out10_empty,
+
+ input wire out11_ready,
+ output wire out11_valid,
+ output wire [DATA_WIDTH-1 :0] out11_data,
+ output wire [CHANNEL_WIDTH-1 :0] out11_channel,
+ output wire [ERROR_WIDTH-1 :0] out11_error,
+ output wire out11_startofpacket,
+ output wire out11_endofpacket,
+ output wire [EMPTY_WIDTH-1 :0] out11_empty,
+
+ input wire out12_ready,
+ output wire out12_valid,
+ output wire [DATA_WIDTH-1 :0] out12_data,
+ output wire [CHANNEL_WIDTH-1 :0] out12_channel,
+ output wire [ERROR_WIDTH-1 :0] out12_error,
+ output wire out12_startofpacket,
+ output wire out12_endofpacket,
+ output wire [EMPTY_WIDTH-1 :0] out12_empty,
+
+ input wire out13_ready,
+ output wire out13_valid,
+ output wire [DATA_WIDTH-1 :0] out13_data,
+ output wire [CHANNEL_WIDTH-1 :0] out13_channel,
+ output wire [ERROR_WIDTH-1 :0] out13_error,
+ output wire out13_startofpacket,
+ output wire out13_endofpacket,
+ output wire [EMPTY_WIDTH-1 :0] out13_empty,
+
+ input wire out14_ready,
+ output wire out14_valid,
+ output wire [DATA_WIDTH-1 :0] out14_data,
+ output wire [CHANNEL_WIDTH-1 :0] out14_channel,
+ output wire [ERROR_WIDTH-1 :0] out14_error,
+ output wire out14_startofpacket,
+ output wire out14_endofpacket,
+ output wire [EMPTY_WIDTH-1 :0] out14_empty,
+
+ input wire out15_ready,
+ output wire out15_valid,
+ output wire [DATA_WIDTH-1 :0] out15_data,
+ output wire [CHANNEL_WIDTH-1 :0] out15_channel,
+ output wire [ERROR_WIDTH-1 :0] out15_error,
+ output wire out15_startofpacket,
+ output wire out15_endofpacket,
+ output wire [EMPTY_WIDTH-1 :0] out15_empty,
+
+ input wire clk
+);
+
+
+// ********************************************************************
+// Module Wiring
+
+wire [15:0] OutReady;
+wire [15:0] OutValid;
+wire [DATA_WIDTH-1 :0] OutData [15:0];
+wire [CHANNEL_WIDTH-1 :0] OutChannel [15:0];
+wire [ERROR_WIDTH-1 :0] OutError [15:0];
+wire [15:0] OutSOP;
+wire [15:0] OutEOP;
+wire [EMPTY_WIDTH-1 :0] OutEmpty [15:0];
+
+genvar i, j;
+
+
+// ********************************************************************
+// Module Logic
+
+assign in0_ready = &(OutReady[NUMBER_OF_OUTPUTS-1:0]);
+
+
+generate
+ for (i=0; i < NUMBER_OF_OUTPUTS; i=i+1) begin : SPLIT_PORT
+ assign OutData[i] = in0_data;
+ assign OutChannel[i] = in0_channel;
+ assign OutError[i] = in0_error;
+ assign OutSOP[i] = in0_startofpacket;
+ assign OutEOP[i] = in0_endofpacket;
+ assign OutEmpty[i] = in0_empty;
+ end
+endgenerate
+
+
+generate
+ for (j=NUMBER_OF_OUTPUTS; j <16; j=j+1) begin : NULL_PORT
+ assign OutData[j] = {DATA_WIDTH{1'b0}};
+ assign OutChannel[j] = {CHANNEL_WIDTH{1'b0}};
+ assign OutError[j] = {ERROR_WIDTH{1'b0}};
+ assign OutSOP[j] = 1'b0;
+ assign OutEOP[j] = 1'b0;
+ assign OutEmpty[j] = {EMPTY_WIDTH{1'b0}};
+ end
+endgenerate
+
+
+generate
+ if (QUALIFY_VALID_OUT) begin
+ assign OutValid[0] = &{in0_valid, OutReady[15:1]};
+ assign OutValid[1] = &{in0_valid, OutReady[15:2], OutReady[0]};
+ assign OutValid[2] = &{in0_valid, OutReady[15:3], OutReady[1:0]};
+ assign OutValid[3] = &{in0_valid, OutReady[15:4], OutReady[2:0]};
+ assign OutValid[4] = &{in0_valid, OutReady[15:5], OutReady[3:0]};
+ assign OutValid[5] = &{in0_valid, OutReady[15:6], OutReady[4:0]};
+ assign OutValid[6] = &{in0_valid, OutReady[15:7], OutReady[5:0]};
+ assign OutValid[7] = &{in0_valid, OutReady[15:8], OutReady[6:0]};
+ assign OutValid[8] = &{in0_valid, OutReady[15:9], OutReady[7:0]};
+ assign OutValid[9] = &{in0_valid, OutReady[15:10], OutReady[8:0]};
+ assign OutValid[10] = &{in0_valid, OutReady[15:11], OutReady[9:0]};
+ assign OutValid[11] = &{in0_valid, OutReady[15:12], OutReady[10:0]};
+ assign OutValid[12] = &{in0_valid, OutReady[15:13], OutReady[11:0]};
+ assign OutValid[13] = &{in0_valid, OutReady[15:14], OutReady[12:0]};
+ assign OutValid[14] = &{in0_valid, OutReady[15], OutReady[13:0]};
+ assign OutValid[15] = &{in0_valid, OutReady[14:0]};
+ end
+ else begin
+ assign OutValid[0] = in0_valid;
+ assign OutValid[1] = in0_valid;
+ assign OutValid[2] = in0_valid;
+ assign OutValid[3] = in0_valid;
+ assign OutValid[4] = in0_valid;
+ assign OutValid[5] = in0_valid;
+ assign OutValid[6] = in0_valid;
+ assign OutValid[7] = in0_valid;
+ assign OutValid[8] = in0_valid;
+ assign OutValid[9] = in0_valid;
+ assign OutValid[10] = in0_valid;
+ assign OutValid[11] = in0_valid;
+ assign OutValid[12] = in0_valid;
+ assign OutValid[13] = in0_valid;
+ assign OutValid[14] = in0_valid;
+ assign OutValid[15] = in0_valid;
+ end
+endgenerate
+
+
+assign OutReady[0] = out0_ready;
+assign out0_valid = OutValid[0];
+assign out0_data = OutData[0];
+assign out0_channel = OutChannel[0];
+assign out0_error = OutError[0];
+assign out0_startofpacket = OutSOP[0];
+assign out0_endofpacket = OutEOP[0];
+assign out0_empty = OutEmpty[0];
+
+assign OutReady[1] = out1_ready;
+assign out1_valid = OutValid[1];
+assign out1_data = OutData[1];
+assign out1_channel = OutChannel[1];
+assign out1_error = OutError[1];
+assign out1_startofpacket = OutSOP[1];
+assign out1_endofpacket = OutEOP[1];
+assign out1_empty = OutEmpty[1];
+
+assign OutReady[2] = out2_ready;
+assign out2_valid = OutValid[2];
+assign out2_data = OutData[2];
+assign out2_channel = OutChannel[2];
+assign out2_error = OutError[2];
+assign out2_startofpacket = OutSOP[2];
+assign out2_endofpacket = OutEOP[2];
+assign out2_empty = OutEmpty[2];
+
+assign OutReady[3] = out3_ready;
+assign out3_valid = OutValid[3];
+assign out3_data = OutData[3];
+assign out3_channel = OutChannel[3];
+assign out3_error = OutError[3];
+assign out3_startofpacket = OutSOP[3];
+assign out3_endofpacket = OutEOP[3];
+assign out3_empty = OutEmpty[3];
+
+assign OutReady[4] = out4_ready;
+assign out4_valid = OutValid[4];
+assign out4_data = OutData[4];
+assign out4_channel = OutChannel[4];
+assign out4_error = OutError[4];
+assign out4_startofpacket = OutSOP[4];
+assign out4_endofpacket = OutEOP[4];
+assign out4_empty = OutEmpty[4];
+
+assign OutReady[5] = out5_ready;
+assign out5_valid = OutValid[5];
+assign out5_data = OutData[5];
+assign out5_channel = OutChannel[5];
+assign out5_error = OutError[5];
+assign out5_startofpacket = OutSOP[5];
+assign out5_endofpacket = OutEOP[5];
+assign out5_empty = OutEmpty[5];
+
+assign OutReady[6] = out6_ready;
+assign out6_valid = OutValid[6];
+assign out6_data = OutData[6];
+assign out6_channel = OutChannel[6];
+assign out6_error = OutError[6];
+assign out6_startofpacket = OutSOP[6];
+assign out6_endofpacket = OutEOP[6];
+assign out6_empty = OutEmpty[6];
+
+assign OutReady[7] = out7_ready;
+assign out7_valid = OutValid[7];
+assign out7_data = OutData[7];
+assign out7_channel = OutChannel[7];
+assign out7_error = OutError[7];
+assign out7_startofpacket = OutSOP[7];
+assign out7_endofpacket = OutEOP[7];
+assign out7_empty = OutEmpty[7];
+
+assign OutReady[8] = out8_ready;
+assign out8_valid = OutValid[8];
+assign out8_data = OutData[8];
+assign out8_channel = OutChannel[8];
+assign out8_error = OutError[8];
+assign out8_startofpacket = OutSOP[8];
+assign out8_endofpacket = OutEOP[8];
+assign out8_empty = OutEmpty[8];
+
+assign OutReady[9] = out9_ready;
+assign out9_valid = OutValid[9];
+assign out9_data = OutData[9];
+assign out9_channel = OutChannel[9];
+assign out9_error = OutError[9];
+assign out9_startofpacket = OutSOP[9];
+assign out9_endofpacket = OutEOP[9];
+assign out9_empty = OutEmpty[9];
+
+assign OutReady[10] = out10_ready;
+assign out10_valid = OutValid[10];
+assign out10_data = OutData[10];
+assign out10_channel = OutChannel[10];
+assign out10_error = OutError[10];
+assign out10_startofpacket = OutSOP[10];
+assign out10_endofpacket = OutEOP[10];
+assign out10_empty = OutEmpty[10];
+
+assign OutReady[11] = out11_ready;
+assign out11_valid = OutValid[11];
+assign out11_data = OutData[11];
+assign out11_channel = OutChannel[11];
+assign out11_error = OutError[11];
+assign out11_startofpacket = OutSOP[11];
+assign out11_endofpacket = OutEOP[11];
+assign out11_empty = OutEmpty[11];
+
+assign OutReady[12] = out12_ready;
+assign out12_valid = OutValid[12];
+assign out12_data = OutData[12];
+assign out12_channel = OutChannel[12];
+assign out12_error = OutError[12];
+assign out12_startofpacket = OutSOP[12];
+assign out12_endofpacket = OutEOP[12];
+assign out12_empty = OutEmpty[12];
+
+assign OutReady[13] = out13_ready;
+assign out13_valid = OutValid[13];
+assign out13_data = OutData[13];
+assign out13_channel = OutChannel[13];
+assign out13_error = OutError[13];
+assign out13_startofpacket = OutSOP[13];
+assign out13_endofpacket = OutEOP[13];
+assign out13_empty = OutEmpty[13];
+
+assign OutReady[14] = out14_ready;
+assign out14_valid = OutValid[14];
+assign out14_data = OutData[14];
+assign out14_channel = OutChannel[14];
+assign out14_error = OutError[14];
+assign out14_startofpacket = OutSOP[14];
+assign out14_endofpacket = OutEOP[14];
+assign out14_empty = OutEmpty[14];
+
+assign OutReady[15] = out15_ready;
+assign out15_valid = OutValid[15];
+assign out15_data = OutData[15];
+assign out15_channel = OutChannel[15];
+assign out15_error = OutError[15];
+assign out15_startofpacket = OutSOP[15];
+assign out15_endofpacket = OutEOP[15];
+assign out15_empty = OutEmpty[15];
+
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_dcfifo_synchronizer_bundle.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_dcfifo_synchronizer_bundle.v
new file mode 100644
index 0000000000000000000000000000000000000000..e2f1490f9753942a6dfd32dee3e2378731f1f250
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_dcfifo_synchronizer_bundle.v
@@ -0,0 +1,50 @@
+// $Id: //acds/main/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer_bundle.v#1 $
+// $Revision: #1 $
+// $Date: 2008/09/23 $
+//----------------------------------------------------------------
+//
+// File: altera_dcfifo_synchronizer_bundle.v
+//
+// Abstract: Bundle of bit synchronizers.
+// WARNING: only use this to synchronize a bundle of
+// *independent* single bit signals or a Gray encoded
+// bus of signals. Also remember that pulses entering
+// the synchronizer will be swallowed upon a metastable
+// condition if the pulse width is shorter than twice
+// the synchronizing clock period.
+//
+// Copyright (C) Altera Corporation 2008, All Rights Reserved
+//----------------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+module altera_dcfifo_synchronizer_bundle(
+ clk,
+ reset_n,
+ din,
+ dout
+ );
+ parameter WIDTH = 1;
+ parameter DEPTH = 3;
+
+ input clk;
+ input reset_n;
+ input [WIDTH-1:0] din;
+ output [WIDTH-1:0] dout;
+
+ genvar i;
+
+ generate
+ for (i=0; i<WIDTH; i=i+1)
+ begin : sync
+ altera_std_synchronizer #(.depth(DEPTH))
+ u (
+ .clk(clk),
+ .reset_n(reset_n),
+ .din(din[i]),
+ .dout(dout[i])
+ );
+ end
+ endgenerate
+
+endmodule
+
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@@ -0,0 +1,270 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// (C) 2001-2010 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/main/ip/merlin/altera_merlin_std_arbitrator/altera_merlin_std_arbitrator_core.sv#3 $
+// $Revision: #3 $
+// $Date: 2010/07/07 $
+// $Author: jyeap $
+
+/* -----------------------------------------------------------------------
+Round-robin/fixed arbitration implementation.
+
+Q: how do you find the least-significant set-bit in an n-bit binary number, X?
+
+A: M = X & (~X + 1)
+
+Example: X = 101000100
+ 101000100 &
+ 010111011 + 1 =
+
+ 101000100 &
+ 010111100 =
+ -----------
+ 000000100
+
+The method can be generalized to find the first set-bit
+at a bit index no lower than bit-index N, simply by adding
+2**N rather than 1.
+
+
+Q: how does this relate to round-robin arbitration?
+A:
+Let X be the concatenation of all request signals.
+Let the number to be added to X (hereafter called the
+top_priority) initialize to 1, and be assigned from the
+concatenation of the previous saved-grant, left-rotated
+by one position, each time arbitration occurs. The
+concatenation of grants is then M.
+
+Problem: consider this case:
+
+top_priority = 010000
+request = 001001
+~request + top_priority = 000110
+next_grant = 000000 <- no one is granted!
+
+There was no "set bit at a bit index no lower than bit-index 4", so
+the result was 0.
+
+We need to propagate the carry out from (~request + top_priority) to the LSB, so
+that the sum becomes 000111, and next_grant is 000001. This operation could be
+called a "circular add".
+
+A bit of experimentation on the circular add reveals a significant amount of
+delay in exiting and re-entering the carry chain - this will vary with device
+family. Quartus also reports a combinational loop warning. Finally,
+Modelsim 6.3g has trouble with the expression, evaluating it to 'X'. But
+Modelsim _doesn't_ report a combinational loop!)
+
+An alternate solution: concatenate the request vector with itself, and OR
+corresponding bits from the top and bottom halves to determine next_grant.
+
+Example:
+
+top_priority = 010000
+{request, request} = 001001 001001
+{~request, ~request} + top_priority = 110111 000110
+result of & operation = 000001 000000
+next_grant = 000001
+
+Notice that if request = 0, the sum operation will overflow, but we can ignore
+this; the next_grant result is 0 (no one granted), as you might expect.
+In the implementation, the last-granted value must be maintained as
+a non-zero value - best probably simply not to update it when no requests
+occur.
+
+----------------------------------------------------------------------- */
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_arbitrator
+#(
+ parameter NUM_REQUESTERS = 8,
+ // --------------------------------------
+ // Implemented schemes
+ // "round-robin"
+ // "fixed-priority"
+ // "no-arb"
+ // --------------------------------------
+ parameter SCHEME = "round-robin",
+ parameter PIPELINE = 0
+)
+(
+ input clk,
+ input reset,
+
+ // --------------------------------------
+ // Requests
+ // --------------------------------------
+ input [NUM_REQUESTERS-1:0] request,
+
+ // --------------------------------------
+ // Grants
+ // --------------------------------------
+ output [NUM_REQUESTERS-1:0] grant,
+
+ // --------------------------------------
+ // Control Signals
+ // --------------------------------------
+ input increment_top_priority,
+ input save_top_priority
+);
+
+ // --------------------------------------
+ // Signals
+ // --------------------------------------
+ wire [NUM_REQUESTERS-1:0] top_priority;
+ reg [NUM_REQUESTERS-1:0] top_priority_reg;
+ reg [NUM_REQUESTERS-1:0] last_grant;
+ wire [2*NUM_REQUESTERS-1:0] result;
+
+ // --------------------------------------
+ // Scheme Selection
+ // --------------------------------------
+ generate
+ if (SCHEME == "round-robin" && NUM_REQUESTERS > 1) begin
+ assign top_priority = top_priority_reg;
+ end
+ else begin
+ // Fixed arbitration (or single-requester corner case)
+ assign top_priority = 1'b1;
+ end
+ endgenerate
+
+ // --------------------------------------
+ // Decision Logic
+ // --------------------------------------
+ altera_merlin_arb_adder
+ #(
+ .WIDTH (2 * NUM_REQUESTERS)
+ )
+ adder
+ (
+ .a ({ ~request, ~request }),
+ .b ({{NUM_REQUESTERS{1'b0}}, top_priority}),
+ .sum (result)
+ );
+
+
+ generate if (SCHEME == "no-arb") begin
+
+ // --------------------------------------
+ // No arbitration: just wire request directly to grant
+ // --------------------------------------
+ assign grant = request;
+
+ end else begin
+ // Do the math in double-vector domain
+ wire [2*NUM_REQUESTERS-1:0] grant_double_vector;
+ assign grant_double_vector = {request, request} & result;
+
+ // --------------------------------------
+ // Extract grant from the top and bottom halves
+ // of the double vector.
+ // --------------------------------------
+ assign grant =
+ grant_double_vector[NUM_REQUESTERS - 1 : 0] |
+ grant_double_vector[2 * NUM_REQUESTERS - 1 : NUM_REQUESTERS];
+
+ end
+ endgenerate
+
+ // --------------------------------------
+ // Left-rotate the last grant vector to create top_priority.
+ // --------------------------------------
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ top_priority_reg <= 1'b1;
+ end
+ else begin
+ if (PIPELINE) begin
+ if (increment_top_priority) begin
+ top_priority_reg <= (|request) ? {grant[NUM_REQUESTERS-2:0],
+ grant[NUM_REQUESTERS-1]} : top_priority_reg;
+ end
+ end else begin
+ if (save_top_priority) begin
+ top_priority_reg <= grant;
+ end
+ if (increment_top_priority) begin
+ if (|request)
+ top_priority_reg <= { grant[NUM_REQUESTERS-2:0],
+ grant[NUM_REQUESTERS-1] };
+ else
+ top_priority_reg <= { top_priority_reg[NUM_REQUESTERS-2:0], top_priority_reg[NUM_REQUESTERS-1] };
+ end
+ end
+ end
+ end
+
+endmodule
+
+// ----------------------------------------------
+// Adder for the standard arbitrator
+// ----------------------------------------------
+module altera_merlin_arb_adder
+#(
+ parameter WIDTH = 8
+)
+(
+ input [WIDTH-1:0] a,
+ input [WIDTH-1:0] b,
+
+ output [WIDTH-1:0] sum
+);
+
+ // ----------------------------------------------
+ // Benchmarks indicate that for small widths, the full
+ // adder has higher fmax because synthesis can merge
+ // it with the mux, allowing partial decisions to be
+ // made early.
+ //
+ // The magic number is 4 requesters, which means an
+ // 8 bit adder.
+ // ----------------------------------------------
+ genvar i;
+ generate if (WIDTH <= 8) begin : full_adder
+
+ wire cout[WIDTH-1:0];
+
+ assign sum[0] = (a[0] ^ b[0]);
+ assign cout[0] = (a[0] & b[0]);
+
+ for (i = 1; i < WIDTH; i = i+1) begin : arb
+
+ assign sum[i] = (a[i] ^ b[i]) ^ cout[i-1];
+ assign cout[i] = (a[i] & b[i]) | (cout[i-1] & (a[i] ^ b[i]));
+
+ end
+
+ end else begin : carry_chain
+
+ assign sum = a + b;
+
+ end
+ endgenerate
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_merlin_burst_uncompressor.sv b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_merlin_burst_uncompressor.sv
new file mode 100644
index 0000000000000000000000000000000000000000..1f2a39f6f30c19681edf47c0a9c587089517b846
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_merlin_burst_uncompressor.sv
@@ -0,0 +1,240 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/rel/11.1sp2/ip/merlin/altera_merlin_slave_agent/altera_merlin_burst_uncompressor.sv#1 $
+// $Revision: #1 $
+// $Date: 2011/11/10 $
+// $Author: max $
+
+// ------------------------------------------
+// Merlin Burst Uncompressor
+//
+// Compressed read bursts -> uncompressed
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_burst_uncompressor
+#(
+ parameter ADDR_W = 16,
+ parameter BURSTWRAP_W = 3,
+ parameter BYTE_CNT_W = 4,
+ parameter PKT_SYMBOLS = 4
+)
+(
+ input clk,
+ input reset,
+
+ // sink ST signals
+ input sink_startofpacket,
+ input sink_endofpacket,
+ input sink_valid,
+ output sink_ready,
+
+ // sink ST "data"
+ input [ADDR_W - 1: 0] sink_addr,
+ input [BURSTWRAP_W - 1 : 0] sink_burstwrap,
+ input [BYTE_CNT_W - 1 : 0] sink_byte_cnt,
+ input sink_is_compressed,
+
+ // source ST signals
+ output source_startofpacket,
+ output source_endofpacket,
+ output source_valid,
+ input source_ready,
+
+ // source ST "data"
+ output [ADDR_W - 1: 0] source_addr,
+ output [BURSTWRAP_W - 1 : 0] source_burstwrap,
+ output [BYTE_CNT_W - 1 : 0] source_byte_cnt,
+
+ // Note: in the slave agent, the output should always be uncompressed. In
+ // other applications, it may be required to leave-compressed or not. How to
+ // control? Seems like a simple mux - pass-through if no uncompression is
+ // required.
+ output source_is_compressed
+);
+ // num_symbols is PKT_SYMBOLS, appropriately sized.
+ wire [31:0] int_num_symbols = PKT_SYMBOLS;
+ wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0];
+
+ // def: Burst Compression. In a merlin network, a compressed burst is one
+ // which is transmitted in a single beat. Example: read burst. In
+ // constrast, an uncompressed burst (example: write burst) is transmitted in
+ // one beat per writedata item.
+ //
+ // For compressed bursts which require response packets, burst
+ // uncompression is required. Concrete example: a read burst of size 8
+ // occupies one response-fifo position. When that fifo position reaches the
+ // front of the FIFO, the slave starts providing the required 8 readdatavalid
+ // pulses. The 8 return response beats must be provided in a single packet,
+ // with incrementing address and decrementing byte_cnt fields. Upon receipt
+ // of the final readdata item of the burst, the response FIFO item is
+ // retired.
+ // Burst uncompression logic provides:
+ // a) 2-state FSM (idle, busy)
+ // reset to idle state
+ // transition to busy state for 2nd and subsequent rdv pulses
+ // - a single-cycle burst (aka non-burst read) causes no transition to
+ // busy state.
+ // b) response startofpacket/endofpacket logic. The response FIFO item
+ // will have sop asserted, and may have eop asserted. (In the case of
+ // multiple read bursts transmit in the command fabric in a single packet,
+ // the eop assertion will come in a later FIFO item.) To support packet
+ // conservation, and emit a well-formed packet on the response fabric,
+ // i) response fabric startofpacket is asserted only for the first resp.
+ // beat;
+ // ii) response fabric endofpacket is asserted only for the last resp.
+ // beat.
+ // c) response address field. The response address field contains an
+ // incrementing sequence, such that each readdata item is associated with
+ // its slave-map location. N.b. a) computing the address correctly requires
+ // knowledge of burstwrap behavior b) there may be no clients of the address
+ // field, which makes this field a good target for optimization. See
+ // burst_uncompress_address_counter below.
+ // d) response byte_cnt field. The response byte_cnt field contains a
+ // decrementing sequence, such that each beat of the response contains the
+ // count of bytes to follow. In the case of sub-bursts in a single packet,
+ // the byte_cnt field may decrement down to num_symbols, then back up to
+ // some value, multiple times in the packet.
+
+ reg burst_uncompress_busy;
+ reg [BYTE_CNT_W-1:0] burst_uncompress_byte_counter;
+ wire first_packet_beat;
+ wire last_packet_beat;
+
+ assign first_packet_beat = sink_valid & ~burst_uncompress_busy;
+
+ // First cycle: burst_uncompress_byte_counter isn't ready yet, mux the input to
+ // the output.
+ assign source_byte_cnt =
+ first_packet_beat ? sink_byte_cnt : burst_uncompress_byte_counter;
+ assign source_valid = sink_valid;
+
+ // Last packet beat is set throughout receipt of an uncompressed read burst
+ // from the response FIFO - this forces all the burst uncompression machinery
+ // idle.
+ assign last_packet_beat = ~sink_is_compressed |
+ (
+ burst_uncompress_busy ?
+ (sink_valid & (burst_uncompress_byte_counter == num_symbols)) :
+ sink_valid & (sink_byte_cnt == num_symbols)
+ );
+
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ burst_uncompress_busy <= '0;
+ burst_uncompress_byte_counter <= '0;
+ end
+ else begin
+ if (source_valid & source_ready & sink_valid) begin
+ // No matter what the current state, last_packet_beat leads to
+ // idle.
+ if (last_packet_beat) begin
+ burst_uncompress_busy <= '0;
+ burst_uncompress_byte_counter <= '0;
+ end
+ else begin
+ if (burst_uncompress_busy) begin
+ burst_uncompress_byte_counter <= burst_uncompress_byte_counter ?
+ (burst_uncompress_byte_counter - num_symbols) :
+ (sink_byte_cnt - num_symbols);
+ end
+ else begin // not busy, at least one more beat to go
+ burst_uncompress_byte_counter <= sink_byte_cnt - num_symbols;
+ // To do: should busy go true for numsymbols-size compressed
+ // bursts?
+ burst_uncompress_busy <= '1;
+ end
+ end
+ end
+ end
+ end
+
+ wire [ADDR_W - 1 : 0 ] addr_width_burstwrap;
+ reg [ADDR_W - 1 : 0 ] burst_uncompress_address_base;
+ reg [ADDR_W - 1 : 0] burst_uncompress_address_offset;
+
+ // The input burstwrap value can be used as a mask against address values,
+ // but with one caveat: the address width may be (probably is) wider than
+ // the burstwrap width. The spec says: extend the msb of the burstwrap
+ // value out over the entire address width (but only if the address width
+ // actually is wider than the burstwrap width; otherwise it's a 0-width or
+ // negative range and concatenation multiplier).
+ assign addr_width_burstwrap[BURSTWRAP_W - 1 : 0] = sink_burstwrap;
+ generate
+ if (ADDR_W > BURSTWRAP_W) begin : addr_sign_extend
+ // Sign-extend, just wires:
+ assign addr_width_burstwrap[ADDR_W - 1 : BURSTWRAP_W] =
+ {(ADDR_W - BURSTWRAP_W) {sink_burstwrap[BURSTWRAP_W - 1]}};
+ end
+ endgenerate
+
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ burst_uncompress_address_base <= '0;
+ end
+ else if (first_packet_beat & source_ready) begin
+ burst_uncompress_address_base <= sink_addr & ~addr_width_burstwrap;
+ end
+ end
+
+ wire [ADDR_W - 1 : 0] p1_burst_uncompress_address_offset =
+ (
+ (first_packet_beat ?
+ sink_addr :
+ burst_uncompress_address_offset) + num_symbols
+ ) &
+ addr_width_burstwrap;
+
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ burst_uncompress_address_offset <= '0;
+ end
+ else begin
+ if (source_ready & source_valid) begin
+ burst_uncompress_address_offset <= p1_burst_uncompress_address_offset;
+ // if (first_packet_beat) begin
+ // burst_uncompress_address_offset <=
+ // (sink_addr + num_symbols) & addr_width_burstwrap;
+ // end
+ // else begin
+ // burst_uncompress_address_offset <=
+ // (burst_uncompress_address_offset + num_symbols) & addr_width_burstwrap;
+ // end
+ end
+ end
+ end
+
+ // On the first packet beat, send the input address out unchanged,
+ // while values are computed/registered for 2nd and subsequent beats.
+ assign source_addr = first_packet_beat ? sink_addr :
+ burst_uncompress_address_base | burst_uncompress_address_offset;
+ assign source_burstwrap = sink_burstwrap;
+
+ //-------------------------------------------------------------------
+ // A single (compressed) read burst will have sop/eop in the same beat.
+ // A sequence of read sub-bursts emitted by a burst adapter in response to a
+ // single read burst will have sop on the first sub-burst, eop on the last.
+ // Assert eop only upon (sink_endofpacket & last_packet_beat) to preserve
+ // packet conservation.
+ assign source_startofpacket = sink_startofpacket & ~burst_uncompress_busy;
+ assign source_endofpacket = sink_endofpacket & last_packet_beat;
+ assign sink_ready = source_valid & source_ready & last_packet_beat;
+
+ // This is correct for the slave agent usage, but won't always be true in the
+ // width adapter. To do: add an "please uncompress" input, and use it to
+ // pass-through or modify, and set source_is_compressed accordingly.
+ assign source_is_compressed = 1'b0;
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_merlin_master_agent.sv b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_merlin_master_agent.sv
new file mode 100644
index 0000000000000000000000000000000000000000..b35b6c7839bd558b7e871e1bb8c5d43a63db0d2c
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_merlin_master_agent.sv
@@ -0,0 +1,239 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/rel/11.1sp2/ip/merlin/altera_merlin_master_agent/altera_merlin_master_agent.sv#1 $
+// $Revision: #1 $
+// $Date: 2011/11/10 $
+// $Author: max $
+
+// --------------------------------------
+// Merlin Master Agent
+//
+// Converts Avalon-MM transactions into
+// Merlin network packets.
+// --------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_master_agent
+#(
+ // -------------------
+ // Packet Format Parameters
+ // -------------------
+ parameter PKT_BEGIN_BURST = 81,
+ PKT_PROTECTION_H = 80,
+ PKT_PROTECTION_L = 80,
+ PKT_BURSTWRAP_H = 79,
+ PKT_BURSTWRAP_L = 77,
+ PKT_BYTE_CNT_H = 76,
+ PKT_BYTE_CNT_L = 74,
+ PKT_ADDR_H = 73,
+ PKT_ADDR_L = 42,
+ PKT_TRANS_LOCK = 82,
+ PKT_TRANS_COMPRESSED_READ = 41,
+ PKT_TRANS_POSTED = 40,
+ PKT_TRANS_WRITE = 39,
+ PKT_TRANS_READ = 38,
+ PKT_DATA_H = 37,
+ PKT_DATA_L = 6,
+ PKT_BYTEEN_H = 5,
+ PKT_BYTEEN_L = 2,
+ PKT_SRC_ID_H = 1,
+ PKT_SRC_ID_L = 1,
+ PKT_DEST_ID_H = 0,
+ PKT_DEST_ID_L = 0,
+ ST_DATA_W = 83,
+ ST_CHANNEL_W = 1,
+
+ // -------------------
+ // Agent Parameters
+ // -------------------
+ AV_BURSTCOUNT_W = 3,
+ ID = 1,
+ SUPPRESS_0_BYTEEN_RSP = 1,
+ BURSTWRAP_VALUE = 4,
+
+ // -------------------
+ // Derived Parameters
+ // -------------------
+ PKT_BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1,
+ PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1,
+ PKT_ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1,
+ PKT_DATA_W = PKT_DATA_H - PKT_DATA_L + 1,
+ PKT_BYTEEN_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1,
+ PKT_SRC_ID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1,
+ PKT_DEST_ID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1
+)
+(
+ // -------------------
+ // Clock & Reset
+ // -------------------
+ input clk,
+ input reset,
+
+ // -------------------
+ // Avalon-MM Anti-Master
+ // -------------------
+ input [PKT_ADDR_W-1 : 0] av_address,
+ input av_write,
+ input av_read,
+ input [PKT_DATA_W-1 : 0] av_writedata,
+ output reg [PKT_DATA_W-1 : 0] av_readdata,
+ output reg av_waitrequest,
+ output reg av_readdatavalid,
+ input [PKT_BYTEEN_W-1 : 0] av_byteenable,
+ input [AV_BURSTCOUNT_W-1 : 0] av_burstcount,
+ input av_debugaccess,
+ input av_lock,
+
+ // -------------------
+ // Command Source
+ // -------------------
+ output reg cp_valid,
+ output reg [ST_DATA_W-1 : 0] cp_data,
+ output wire cp_startofpacket,
+ output wire cp_endofpacket,
+ input cp_ready,
+
+ // -------------------
+ // Response Sink
+ // -------------------
+ input rp_valid,
+ input [ST_DATA_W-1 : 0] rp_data,
+ input [ST_CHANNEL_W-1 : 0] rp_channel,
+ input rp_startofpacket,
+ input rp_endofpacket,
+ output reg rp_ready
+);
+ // ------------------------------------------------------------
+ // Utility Functions
+ // ------------------------------------------------------------
+ function integer clogb2;
+ input [31:0] value;
+ begin
+ for (clogb2=0; value>0; clogb2=clogb2+1)
+ value = value >> 1;
+ clogb2 = clogb2 - 1;
+ end
+ endfunction // clogb2
+
+ localparam MAX_BURST = 1 << (AV_BURSTCOUNT_W - 1);
+ localparam NUMSYMBOLS = PKT_BYTEEN_W;
+ localparam BURSTING = (MAX_BURST > NUMSYMBOLS);
+ localparam BITS_TO_ZERO = clogb2(NUMSYMBOLS);
+
+ // --------------------------------------
+ // Optimization: compare in words to save bits?
+ // --------------------------------------
+ wire is_burst;
+ assign is_burst = (BURSTING) & (av_burstcount > NUMSYMBOLS);
+
+ // --------------------------------------
+ // Command & Response Construction
+ // --------------------------------------
+ wire [31:0] burstwrap_value_int = BURSTWRAP_VALUE;
+ wire [31:0] id_int = ID;
+
+ // --------------------------------------
+ // Address alignment
+ // --------------------------------------
+ wire [PKT_ADDR_W-1 : 0] av_address_aligned;
+ generate
+ if (NUMSYMBOLS > 1) begin
+ assign av_address_aligned =
+ {av_address[PKT_ADDR_W-1 : BITS_TO_ZERO], {BITS_TO_ZERO {1'b0}}};
+ end
+ else begin
+ assign av_address_aligned = av_address;
+ end
+ endgenerate
+
+ always @* begin
+ cp_data = '0; // Default assignment; override below as needed.
+
+ cp_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = av_debugaccess;
+ cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = burstwrap_value_int[PKT_BURSTWRAP_W-1:0];
+ cp_data[PKT_BYTE_CNT_H :PKT_BYTE_CNT_L ] = av_burstcount;
+ cp_data[PKT_ADDR_H :PKT_ADDR_L ] = av_address_aligned;
+ cp_data[PKT_TRANS_LOCK ] = av_lock;
+ cp_data[PKT_TRANS_COMPRESSED_READ ] = av_read & is_burst;
+ cp_data[PKT_TRANS_READ ] = av_read;
+ cp_data[PKT_TRANS_WRITE ] = av_write;
+ cp_data[PKT_TRANS_POSTED ] = av_write;
+ cp_data[PKT_DATA_H :PKT_DATA_L ] = av_writedata;
+ cp_data[PKT_BYTEEN_H :PKT_BYTEEN_L ] = av_byteenable;
+ cp_data[PKT_SRC_ID_H :PKT_SRC_ID_L ] = id_int[PKT_SRC_ID_W-1:0];
+
+ av_readdata = rp_data[PKT_DATA_H : PKT_DATA_L];
+ end
+
+ // --------------------------------------
+ // Command Control
+ // --------------------------------------
+ always @* begin
+ cp_valid = 0;
+
+ if (av_write || av_read)
+ cp_valid = 1;
+ end
+
+ generate if (BURSTING) begin
+ reg sop_enable;
+
+ always @(posedge clk, posedge reset) begin
+ if (reset) begin
+ sop_enable <= 1'b1;
+ end
+ else begin
+ if (cp_valid && cp_ready) begin
+ sop_enable <= 1'b0;
+ if (cp_endofpacket)
+ sop_enable <= 1'b1;
+ end
+ end
+ end
+
+ assign cp_startofpacket = sop_enable;
+ assign cp_endofpacket = (av_read) | (av_burstcount == NUMSYMBOLS);
+
+ end
+ else begin
+
+ assign cp_startofpacket = 1'b1;
+ assign cp_endofpacket = 1'b1;
+
+ end
+ endgenerate
+
+ // --------------------------------------
+ // Backpressure & Readdatavalid
+ // --------------------------------------
+ always @* begin
+ rp_ready = 1;
+ av_waitrequest = 0;
+ av_readdatavalid = 0;
+
+ av_waitrequest = !cp_ready;
+
+ // --------------------------------------
+ // Currently, responses are _always_ read responses.
+ // --------------------------------------
+ av_readdatavalid = rp_valid;
+
+ if (SUPPRESS_0_BYTEEN_RSP) begin
+ if (rp_data[PKT_BYTEEN_H:PKT_BYTEEN_L] == 0)
+ av_readdatavalid = 0;
+ end
+ end
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_merlin_master_translator.sv b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_merlin_master_translator.sv
new file mode 100644
index 0000000000000000000000000000000000000000..bdb674529fc6fa5c351a870d327bb1f689e14a7b
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_merlin_master_translator.sv
@@ -0,0 +1,450 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/rel/11.1sp2/ip/merlin/altera_merlin_master_translator/altera_merlin_master_translator.sv#1 $
+// $Revision: #1 $
+// $Date: 2011/11/10 $
+// $Author: max $
+
+// --------------------------------------
+// Merlin Master Translator
+//
+// Converts Avalon-MM Master Interfaces into
+// Avalon-MM Universal Master Interfaces
+// --------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+
+module altera_merlin_master_translator #(
+ parameter
+ AV_ADDRESS_W = 32,
+ AV_DATA_W = 32,
+ AV_BURSTCOUNT_W = 4,
+ AV_BYTEENABLE_W = 4,
+
+ //Optional Port Declarations
+
+ USE_BURSTCOUNT = 1,
+ USE_BEGINBURSTTRANSFER = 0,
+ USE_BEGINTRANSFER = 0,
+ USE_CHIPSELECT = 0,
+ USE_READ = 1,
+ USE_READDATAVALID = 1,
+ USE_WRITE = 1,
+ USE_WAITREQUEST = 1,
+
+ AV_REGISTERINCOMINGSIGNALS = 0,
+ AV_SYMBOLS_PER_WORD = 4,
+ AV_ADDRESS_SYMBOLS = 0,
+ AV_CONSTANT_BURST_BEHAVIOR = 1,
+ AV_BURSTCOUNT_SYMBOLS = 0,
+ AV_LINEWRAPBURSTS = 0,
+ UAV_ADDRESS_W = 38,
+ UAV_BURSTCOUNT_W = 10,
+ UAV_CONSTANT_BURST_BEHAVIOR = 0
+ )(
+ //Universal Avalon Master
+ input wire clk,
+ input wire reset,
+ output reg uav_write,
+ output reg uav_read,
+ output reg [UAV_ADDRESS_W -1 : 0] uav_address,
+ output reg [UAV_BURSTCOUNT_W -1 : 0] uav_burstcount,
+ output wire [AV_BYTEENABLE_W -1 : 0] uav_byteenable,
+ output wire [AV_DATA_W -1 : 0] uav_writedata,
+ output wire uav_lock,
+ output wire uav_debugaccess,
+ output wire uav_clken,
+
+ input wire [ AV_DATA_W -1 : 0] uav_readdata,
+ input wire uav_readdatavalid,
+ input wire uav_waitrequest,
+
+ //Avalon-MM !Master
+ input reg av_write,
+ input reg av_read,
+ input wire [AV_ADDRESS_W -1 : 0] av_address,
+ input wire [AV_BYTEENABLE_W -1 : 0] av_byteenable,
+ input wire [AV_BURSTCOUNT_W -1 : 0] av_burstcount,
+ input wire [AV_DATA_W -1 : 0] av_writedata,
+ input wire av_begintransfer,
+ input wire av_beginbursttransfer,
+ input wire av_lock,
+ input wire av_chipselect,
+ input wire av_debugaccess,
+ input wire av_clken,
+
+ output wire [AV_DATA_W -1 : 0] av_readdata,
+ output wire av_readdatavalid,
+ output reg av_waitrequest
+ );
+
+
+ localparam BITS_PER_WORD = clog2(AV_SYMBOLS_PER_WORD - 1);
+ localparam AV_MAX_SYMBOL_BURST = flog2( pow2(AV_BURSTCOUNT_W - 1) * (AV_BURSTCOUNT_SYMBOLS ? 1 : (AV_SYMBOLS_PER_WORD)) );
+ localparam AV_MAX_SYMBOL_BURST_MINUS_ONE = AV_MAX_SYMBOL_BURST ? AV_MAX_SYMBOL_BURST - 1 : 0 ;
+
+ localparam UAV_BURSTCOUNT_W_OR_32 = UAV_BURSTCOUNT_W > 32 ? 31 : UAV_BURSTCOUNT_W -1;
+ localparam UAV_ADDRESS_W_OR_32 = UAV_ADDRESS_W > 32 ? 31 : UAV_ADDRESS_W -1;
+
+
+ // -1 for burstcount restriction 2^(n-1)
+
+ localparam BITS_PER_WORD_BURSTCOUNT = UAV_BURSTCOUNT_W == 1 ? 0 : BITS_PER_WORD;
+ localparam BITS_PER_WORD_ADDRESS = UAV_ADDRESS_W == 1 ? 0 : BITS_PER_WORD;
+
+ localparam ADDRESS_LOW = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD_ADDRESS;
+ localparam BURSTCOUNT_LOW = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD_BURSTCOUNT;
+
+ localparam ADDRESS_HIGH = UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_LOW ? AV_ADDRESS_W : UAV_ADDRESS_W - ADDRESS_LOW;
+ localparam BURSTCOUNT_HIGH = UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_LOW ? AV_BURSTCOUNT_W : UAV_BURSTCOUNT_W - BURSTCOUNT_LOW;
+
+ function integer flog2;
+ input [31:0] Depth;
+ integer i;
+ begin
+ i = Depth;
+ if ( i <= 0 ) flog2 = 0;
+ else begin
+ for(flog2 = -1; i > 0; flog2 = flog2 + 1)
+ i = i >> 1;
+ end
+ end
+
+ endfunction // flog2
+
+ function integer clog2;
+ input [31:0] Depth;
+ integer i;
+ begin
+ i = Depth;
+ for(clog2 = 0; i > 0; clog2 = clog2 + 1)
+ i = i >> 1;
+ end
+
+ endfunction
+
+ function integer pow2;
+ input [31:0] toShift;
+ begin
+ pow2=1;
+ pow2= pow2 << toShift;
+ end
+ endfunction // pow2
+
+ // -------------------------------------------------
+ // Assign some constants to appropriately-sized signals to
+ // avoid synthesis warnings. This also helps some simulators
+ // with their inferred sensitivity lists.
+ // -------------------------------------------------
+ // Calculate the symbols per word as the power of 2 extended symbols per word
+ wire [31:0] symbols_per_word_int = 2**(clog2(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W_OR_32 : 0] - 1));
+ wire [UAV_BURSTCOUNT_W_OR_32 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W_OR_32 : 0];
+
+
+ reg internal_beginbursttransfer;
+ reg internal_begintransfer;
+ reg [UAV_ADDRESS_W - 1: 0 ] uav_address_pre;
+ reg [UAV_BURSTCOUNT_W - 1 : 0 ] uav_burstcount_pre;
+
+
+
+ reg uav_read_pre;
+ reg uav_write_pre;
+ reg read_accepted;
+
+ //Passthru assignmenst
+
+ assign uav_writedata = av_writedata;
+ assign av_readdata = uav_readdata;
+ assign uav_byteenable = av_byteenable;
+ assign uav_lock = av_lock;
+ assign av_readdatavalid = uav_readdatavalid;
+ assign uav_debugaccess = av_debugaccess;
+ assign uav_clken = av_clken;
+
+ //address + burstcount assignment
+
+ reg [UAV_ADDRESS_W - 1 : 0] address_register;
+ reg [UAV_BURSTCOUNT_W - 1 : 0] burstcount_register;
+
+ always @* begin
+ uav_address=uav_address_pre;
+ uav_burstcount=uav_burstcount_pre;
+
+ if(AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~internal_beginbursttransfer) begin
+ uav_address=address_register;
+ uav_burstcount=burstcount_register;
+ end
+ end
+
+ reg first_burst_stalled;
+ reg burst_stalled;
+
+
+ wire[UAV_ADDRESS_W-1:0] combi_burst_addr_reg;
+ wire [UAV_ADDRESS_W-1:0] combi_addr_reg;
+ generate
+ if(AV_LINEWRAPBURSTS && AV_MAX_SYMBOL_BURST!=0) begin
+ if(AV_MAX_SYMBOL_BURST > UAV_ADDRESS_W - 1) begin
+ assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] };
+ assign combi_addr_reg = { address_register[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] };
+ end
+ else begin
+ assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], uav_address_pre[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] };
+ assign combi_addr_reg = { address_register[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], address_register[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] };
+ end
+ end
+ else begin
+ assign combi_burst_addr_reg =
+ uav_address_pre + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W_OR_32:0];
+ assign combi_addr_reg =
+ address_register + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W_OR_32:0];
+ end
+ endgenerate
+
+ always@(posedge clk, posedge reset) begin
+
+ if(reset) begin
+ address_register <= '0;
+ burstcount_register <= '0;
+ first_burst_stalled <= 1'b0;
+ burst_stalled <= 1'b0;
+ end
+ else begin
+ address_register <= address_register;
+ burstcount_register <= burstcount_register;
+
+ if(internal_beginbursttransfer||first_burst_stalled) begin
+
+ if(av_waitrequest) begin
+ first_burst_stalled <= 1'b1;
+ address_register <= uav_address_pre;
+ burstcount_register <= uav_burstcount_pre;
+ end else begin
+ first_burst_stalled <= 1'b0;
+ address_register <= combi_burst_addr_reg;
+ burstcount_register <= uav_burstcount_pre - symbols_per_word;
+ end
+ end
+
+ else if(internal_begintransfer || burst_stalled) begin
+ if(~av_waitrequest) begin
+ burst_stalled <= 1'b0;
+ address_register <= combi_addr_reg;
+ burstcount_register <= burstcount_register - symbols_per_word;
+ end else
+ burst_stalled<=1'b1;
+ end
+ end
+
+ end
+
+ //Address
+ always @* begin
+ uav_address_pre = '0;
+
+ if(AV_ADDRESS_SYMBOLS)
+ uav_address_pre=av_address[ ( ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0 ) : 0 ];
+ else begin
+ uav_address_pre[ UAV_ADDRESS_W - 1 : ADDRESS_LOW ] = av_address[( ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0 ];
+ end
+ end
+
+ //Burstcount
+ always@* begin
+ uav_burstcount_pre = symbols_per_word; // default to a single transfer
+
+ if(USE_BURSTCOUNT) begin
+ uav_burstcount_pre = '0;
+
+ if(AV_BURSTCOUNT_SYMBOLS)
+ uav_burstcount_pre = av_burstcount[( BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0 ) :0 ];
+ else begin
+ uav_burstcount_pre[ UAV_BURSTCOUNT_W - 1 : BURSTCOUNT_LOW] = av_burstcount[( BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0 ) : 0 ];
+ end
+
+ end
+
+ end
+
+
+ //waitrequest translation
+
+ always@(posedge clk, posedge reset) begin
+ if(reset)
+ read_accepted <= 1'b0;
+ else begin
+ read_accepted <= read_accepted;
+
+ if(read_accepted == 1 && uav_readdatavalid == 1) // reset acceptance only when rdv arrives
+ read_accepted <= 1'b0;
+
+ if(read_accepted == 0)
+ read_accepted<=av_waitrequest ? uav_read_pre & ~uav_waitrequest : 1'b0;
+ end
+
+ end
+
+ reg write_accepted = 0;
+ generate if (AV_REGISTERINCOMINGSIGNALS) begin
+ always@(posedge clk, posedge reset) begin
+ if(reset)
+ write_accepted <= 1'b0;
+ else begin
+ write_accepted <=
+ ~av_waitrequest ? 1'b0 :
+ uav_write & ~uav_waitrequest? 1'b1 :
+ write_accepted;
+ end
+ end
+ end endgenerate
+
+ always@* begin
+ av_waitrequest = uav_waitrequest;
+
+ if(USE_READDATAVALID == 0 ) begin
+ av_waitrequest = uav_read_pre ? ~uav_readdatavalid : uav_waitrequest;
+ end
+
+ if (AV_REGISTERINCOMINGSIGNALS) begin
+ av_waitrequest =
+ uav_read_pre ? ~uav_readdatavalid :
+ uav_write_pre ? (internal_begintransfer | uav_waitrequest) & ~write_accepted :
+ 1'b1;
+ end
+
+ if(USE_WAITREQUEST == 0) begin
+ av_waitrequest = 0;
+ end
+ end
+
+ //read/write generation
+ always@* begin
+
+ uav_write = 1'b0;
+ uav_write_pre = 1'b0;
+ uav_read = 1'b0;
+ uav_read_pre = 1'b0;
+
+ if(!USE_CHIPSELECT) begin
+ if (USE_READ) begin
+ uav_read_pre=av_read;
+ end
+
+ if (USE_WRITE) begin
+ uav_write_pre=av_write;
+ end
+ end
+ else begin
+ if(!USE_WRITE && USE_READ) begin
+ uav_read_pre=av_read;
+ uav_write_pre=av_chipselect & ~av_read;
+ end
+ else if(!USE_READ && USE_WRITE) begin
+ uav_write_pre=av_write;
+ uav_read_pre = av_chipselect & ~av_write;
+ end
+ else if (USE_READ && USE_WRITE) begin
+ uav_write_pre=av_write;
+ uav_read_pre=av_read;
+ end
+ end
+
+ if(USE_READDATAVALID == 0)
+ uav_read = uav_read_pre & ~read_accepted;
+ else
+ uav_read = uav_read_pre;
+
+ if(AV_REGISTERINCOMINGSIGNALS == 0)
+ uav_write=uav_write_pre;
+ else
+ uav_write=uav_write_pre & ~write_accepted;
+
+
+ end
+
+ // -------------------
+ // Begintransfer Assigment
+ // -------------------
+
+ reg end_begintransfer;
+
+ always@* begin
+ if(USE_BEGINTRANSFER) begin
+ internal_begintransfer = av_begintransfer;
+ end else begin
+ internal_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer;
+ end
+ end
+
+ always@ ( posedge clk or posedge reset ) begin
+
+ if(reset) begin
+ end_begintransfer <= 1'b0;
+ end
+ else begin
+
+ if(internal_begintransfer == 1 && uav_waitrequest)
+ end_begintransfer <= 1'b1;
+ else if(uav_waitrequest)
+ end_begintransfer <= end_begintransfer;
+ else
+ end_begintransfer <= 1'b0;
+
+ end
+
+ end
+
+ // -------------------
+ // Beginbursttransfer Assigment
+ // -------------------
+
+ reg end_beginbursttransfer;
+ wire last_burst_transfer_pre;
+ wire last_burst_transfer_reg;
+ wire last_burst_transfer;
+
+ // compare values before the mux to shorten critical path; benchmark before changing
+ assign last_burst_transfer_pre = (uav_burstcount_pre == symbols_per_word);
+ assign last_burst_transfer_reg = (burstcount_register == symbols_per_word);
+ assign last_burst_transfer = (internal_beginbursttransfer) ? last_burst_transfer_pre : last_burst_transfer_reg;
+
+ always@* begin
+ if(USE_BEGINBURSTTRANSFER) begin
+ internal_beginbursttransfer = av_beginbursttransfer;
+ end else begin
+ internal_beginbursttransfer = uav_read ? internal_begintransfer : internal_begintransfer && ~end_beginbursttransfer;
+ end
+ end
+
+ always@ ( posedge clk or posedge reset ) begin
+
+ if(reset) begin
+ end_beginbursttransfer <= 1'b0;
+ end
+ else begin
+ end_beginbursttransfer <= end_beginbursttransfer;
+ if( last_burst_transfer && internal_begintransfer || uav_read ) begin
+ end_beginbursttransfer <= 1'b0;
+ end
+ else if(uav_write && internal_begintransfer) begin
+ end_beginbursttransfer <= 1'b1;
+ end
+ end
+
+ end
+
+ endmodule
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_merlin_slave_agent.sv b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_merlin_slave_agent.sv
new file mode 100644
index 0000000000000000000000000000000000000000..d12023a975d007e362e54b93c79fe89fd7541ca7
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_merlin_slave_agent.sv
@@ -0,0 +1,416 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/rel/11.1sp2/ip/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent.sv#1 $
+// $Revision: #1 $
+// $Date: 2011/11/10 $
+// $Author: max $
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_slave_agent
+ #(
+ // Packet parameters
+ parameter PKT_BEGIN_BURST = 81,
+ parameter PKT_DATA_H = 31,
+ parameter PKT_DATA_L = 0,
+ parameter PKT_SYMBOL_W = 8,
+ parameter PKT_BYTEEN_H = 71,
+ parameter PKT_BYTEEN_L = 68,
+ parameter PKT_ADDR_H = 63,
+ parameter PKT_ADDR_L = 32,
+ parameter PKT_TRANS_LOCK = 87,
+ parameter PKT_TRANS_COMPRESSED_READ = 67,
+ parameter PKT_TRANS_POSTED = 66,
+ parameter PKT_TRANS_WRITE = 65,
+ parameter PKT_TRANS_READ = 64,
+ parameter PKT_SRC_ID_H = 74,
+ parameter PKT_SRC_ID_L = 72,
+ parameter PKT_DEST_ID_H = 77,
+ parameter PKT_DEST_ID_L = 75,
+ parameter PKT_BURSTWRAP_H = 85,
+ parameter PKT_BURSTWRAP_L = 82,
+ parameter PKT_BYTE_CNT_H = 81,
+ parameter PKT_BYTE_CNT_L = 78,
+ parameter PKT_PROTECTION_H = 86,
+ parameter PKT_PROTECTION_L = 86,
+ parameter ST_DATA_W = 90,
+ parameter ST_CHANNEL_W = 32,
+// parameter PKT_AXI_RESP_L = 88,
+// parameter PKT_AXI_RESP_H = 89,
+
+
+ // Slave parameters
+ parameter ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1,
+ parameter AVS_DATA_W = PKT_DATA_H - PKT_DATA_L + 1,
+ parameter AVS_BURSTCOUNT_W = 4,
+ parameter PKT_SYMBOLS = AVS_DATA_W / PKT_SYMBOL_W,
+
+ // Slave agent parameters
+ parameter PREVENT_FIFO_OVERFLOW = 0,
+ parameter SUPPRESS_0_BYTEEN_CMD = 1,
+
+ // Derived slave parameters
+ parameter AVS_BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1,
+
+ // Derived FIFO width
+ parameter FIFO_DATA_W = ST_DATA_W + 1
+ )
+ (
+
+ input clk,
+ input reset,
+
+ // Universal-Avalon anti-slave
+ output [ADDR_W-1:0] m0_address,
+ output [AVS_BURSTCOUNT_W-1:0] m0_burstcount,
+ output [AVS_BE_W-1:0] m0_byteenable,
+ output m0_read,
+ input [AVS_DATA_W-1:0] m0_readdata,
+ input m0_waitrequest,
+ output m0_write,
+ output [AVS_DATA_W-1:0] m0_writedata,
+ input m0_readdatavalid,
+ output m0_debugaccess,
+ output m0_lock,
+
+ // Avalon-ST FIFO interfaces.
+ // Note: there's no need to include the "data" field here, at least for
+ // reads, since readdata is filled in from slave info. To keep life
+ // simple, have a data field, but fill it with 0s.
+ // Av-st response fifo source interface
+ output reg [FIFO_DATA_W-1:0] rf_source_data,
+ output rf_source_valid,
+ output rf_source_startofpacket,
+ output rf_source_endofpacket,
+ input rf_source_ready,
+
+ // Av-st response fifo sink interface
+ input [FIFO_DATA_W-1:0] rf_sink_data,
+ input rf_sink_valid,
+ input rf_sink_startofpacket,
+ input rf_sink_endofpacket,
+ output rf_sink_ready,
+
+ // Av-st readdata fifo src interface
+ output [AVS_DATA_W-1:0] rdata_fifo_src_data,
+ output rdata_fifo_src_valid,
+ input rdata_fifo_src_ready,
+
+ // Av-st readdata fifo sink interface
+ input [AVS_DATA_W-1:0] rdata_fifo_sink_data,
+ input rdata_fifo_sink_valid,
+ output rdata_fifo_sink_ready,
+
+ // Av-st sink command packet interface
+ output cp_ready,
+ input cp_valid,
+ input [ST_DATA_W-1:0] cp_data,
+ input [ST_CHANNEL_W-1:0] cp_channel,
+ input cp_startofpacket,
+ input cp_endofpacket,
+
+ // Av-st source response packet interface
+ input rp_ready,
+ output rp_valid,
+ output reg [ST_DATA_W-1:0] rp_data,
+ output rp_startofpacket,
+ output rp_endofpacket
+);
+
+ function integer clog2;
+ input [31:0] Depth;
+ integer i;
+ begin
+ i = Depth;
+ for(clog2 = 0; i > 0; clog2 = clog2 + 1)
+ i = i >> 1;
+ end
+
+ endfunction // clog2
+
+
+ // ------------------------------------------------
+ // Local Parameters
+ // ------------------------------------------------
+ localparam DATA_W = PKT_DATA_H - PKT_DATA_L + 1;
+ localparam BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1;
+ localparam MID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1;
+ localparam SID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1;
+ localparam BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1;
+ localparam BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1;
+// localparam RESP_W = PKT_AXI_RESP_H - PKT_AXI_RESP_L + 1;
+
+ // ------------------------------------------------
+ // Signals
+ // ------------------------------------------------
+ wire [DATA_W-1:0] cmd_data;
+ wire [BE_W-1:0] cmd_byteen;
+ wire [ADDR_W-1:0] cmd_addr;
+ wire [MID_W-1:0] cmd_mid;
+ wire [SID_W-1:0] cmd_sid;
+ wire cmd_read;
+ wire cmd_write;
+ wire cmd_compressed;
+ wire cmd_posted;
+ wire [BYTE_CNT_W-1:0] cmd_byte_cnt;
+ wire [BURSTWRAP_W-1:0] cmd_burstwrap;
+ wire cmd_debugaccess;
+// wire [RESP_W-1:0] cmd_response;
+
+ wire byteen_asserted;
+ wire read_suppressed;
+ wire generate_response;
+ wire nonposted_write_endofpacket; //llim: to get a condition where it is the end of packet and a write command packet. This is to push command packet into fifo
+
+ // Assign command fields //for axi writes
+ assign cmd_data = cp_data[PKT_DATA_H :PKT_DATA_L ]; //wdata //0 default
+ assign cmd_byteen = cp_data[PKT_BYTEEN_H:PKT_BYTEEN_L]; //wstrb //MISSING
+ assign cmd_addr = cp_data[PKT_ADDR_H :PKT_ADDR_L ]; //awaddr //araddr
+ assign cmd_compressed = cp_data[PKT_TRANS_COMPRESSED_READ]; //always 0 //0
+ assign cmd_posted = cp_data[PKT_TRANS_POSTED]; //alwyas 0 //0
+ assign cmd_write = cp_data[PKT_TRANS_WRITE]; // 1 //0
+ assign cmd_read = cp_data[PKT_TRANS_READ]; // 0 //1
+ assign cmd_mid = cp_data[PKT_SRC_ID_H :PKT_SRC_ID_L]; //take in the mid from transform
+ assign cmd_sid = cp_data[PKT_DEST_ID_H:PKT_DEST_ID_L]; //dump out the sid from the slave
+ assign cmd_byte_cnt = cp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]; //0 for now //0
+ assign cmd_burstwrap= cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]; //MISSING //missing
+ assign cmd_debugaccess = cp_data[PKT_PROTECTION_L]; // awprot bit0 //arprotbit0
+
+ // Local "ready_for_command" signal: deasserted when the agent is unable to accept
+ // another command, e.g. rdv FIFO is full, (local readdata storage is full &&
+ // ~rp_ready), ...
+ // Say, this could depend on the type of command, for example, even if the
+ // rdv FIFO is full, a write request can be accepted. For later.
+
+ wire ready_for_command;
+
+ wire local_lock = cp_valid & cp_data[PKT_TRANS_LOCK];
+ wire local_write = cp_valid & cp_data[PKT_TRANS_WRITE];
+ wire local_read = cp_valid & cp_data[PKT_TRANS_READ];
+ wire local_compressed_read = cp_valid & cp_data[PKT_TRANS_COMPRESSED_READ];
+ assign nonposted_write_endofpacket = local_write & cp_endofpacket & ~cp_data[PKT_TRANS_POSTED];
+ //wire rf_sink_write = rf_sink_valid & rf_sink_data[PKT_TRANS_WRITE]; //llim: need a set of signals from the rf_sink to connect to sink_valid of burst uncompressor
+ //assign rf_nonposted_write_endofpacket = rf_sink_write & rf_sink_endofpacket & ~rf_sink_data[PKT_TRANS_POSTED];
+
+ // num_symbols is PKT_SYMBOLS, appropriately sized.
+ wire [31:0] int_num_symbols = PKT_SYMBOLS;
+ wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0];
+
+ generate
+ if (PREVENT_FIFO_OVERFLOW) begin : prevent_fifo_overflow
+ //---------------------------------------------------
+ // Backpressure if the slave says to, or if FIFO overflow may occur.
+ //
+ // All commands are backpressured once the FIFO is full
+ // even if they don't need storage. This breaks a long
+ // combinatorial path from the master read/write through
+ // this logic and back to the master via the backpressure
+ // path.
+ //
+ // To avoid a loss of throughput the FIFO will be parameterized
+ // one slot deeper. The extra slot should never be used in normal
+ // operation, but should a slave misbehave and accept one more
+ // read than it should then backpressure will kick in.
+ //
+ // An example: assume a slave with MPRT = 2. It can accept a
+ // command sequence RRWW without backpressuring. If the FIFO is
+ // only 2 deep, we'd backpressure the writes leading to loss of
+ // throughput. If the FIFO is 3 deep, we'll only backpressure when
+ // RRR... which is an illegal condition anyway.
+ //---------------------------------------------------
+ // assign cp_ready = ~m0_waitrequest && ready_for_command;
+ assign cp_ready = (~m0_waitrequest | ~byteen_asserted) && ready_for_command;
+ assign ready_for_command = rf_source_ready;
+ end else begin : no_prevent_fifo_overflow
+ // Backpressure only if the slave says to.
+ assign cp_ready = ~m0_waitrequest | ~byteen_asserted;
+ // Do not suppress the command or the slave will
+ // not be able to waitrequest
+ assign ready_for_command = 1'b1;
+ end
+ endgenerate
+
+ generate if (SUPPRESS_0_BYTEEN_CMD) begin : suppress_0_byteen_cmd
+ assign byteen_asserted = |cmd_byteen;
+ end else begin : no_suppress_0_byteen_cmd
+ assign byteen_asserted = 1'b1;
+ end
+ endgenerate
+
+ //-------------------------------------------------------------------
+ // Extract avalon signals from command packet.
+ //-------------------------------------------------------------------
+ assign m0_address = cmd_addr;
+ assign m0_byteenable = cmd_byteen;
+ assign m0_writedata = cmd_data;
+
+ // Note: no Avalon-MM slave in existence accepts uncompressed read bursts -
+ // this sort of burst exists only in merlin fabric ST packets. What to do
+ // if we see such a burst? All beats in that burst need to be transmitted
+ // to the slave so we have enough space-time for byteenable expression.
+ //
+ // There can be multiple bursts in a packet, but only one beat per burst
+ // in <most> cases. The exception is when we've decided not to insert a
+ // burst adapter for efficiency reasons, in which case this agent is also
+ // responsible for driving burstcount to 1 on each beat of an uncompressed
+ // read burst.
+
+ assign m0_read = ready_for_command & byteen_asserted &
+ (local_compressed_read | local_read);
+
+ generate
+ begin : m0_burstcount_zero_pad
+ // AVS_BURSTCOUNT_W and BYTE_CNT_W may not be equal. Assign m0_burstcount
+ // from a sub-range, or 0-pad, as appropriate.
+ if (AVS_BURSTCOUNT_W > BYTE_CNT_W) begin
+ wire [AVS_BURSTCOUNT_W - BYTE_CNT_W - 1 : 0] zero_pad =
+ {(AVS_BURSTCOUNT_W - BYTE_CNT_W) {1'b0}};
+ assign m0_burstcount = (local_read & ~local_compressed_read) ?
+ {zero_pad, num_symbols} :
+ {zero_pad, cmd_byte_cnt};
+ end
+ else begin : mo_burstcount_no_pad
+ assign m0_burstcount = (local_read & ~local_compressed_read) ?
+ num_symbols[AVS_BURSTCOUNT_W-1:0] :
+ cmd_byte_cnt[AVS_BURSTCOUNT_W-1:0];
+ end
+ end
+ endgenerate
+
+ assign m0_write = ready_for_command & local_write & byteen_asserted;
+ assign m0_lock = ready_for_command & local_lock & (m0_read | m0_write);
+ assign m0_debugaccess = cmd_debugaccess;
+
+ //-------------------------------------------------------------------
+ // Indirection layer for response packet values. Some may always wire
+ // directly from the slave translator; others will no doubt emerge from
+ // various FIFOs.
+ // What to put in resp_data when a write occured? For now, there's simply no
+ // response packet for writes.
+
+ assign rdata_fifo_src_valid = m0_readdatavalid;
+ assign rdata_fifo_src_data = m0_readdata;
+
+ // ------------------------------------------------------------------
+ // Generate a token when read commands are suppressed. The token
+ // is stored in the response FIFO, and will be used to synthesize
+ // a read response.
+
+ // llim: token also used for generating write responses at the end of each packet for nonposted_write
+ //
+ // Note: this token is not generated for suppressed uncompressed read cycles;
+ // the burst uncompression logic at the read side of the response FIFO
+ // generates the correct number of responses.
+ // ------------------------------------------------------------------
+ assign read_suppressed = ((local_read | local_compressed_read) & !byteen_asserted) | nonposted_write_endofpacket;
+
+ // Avalon-ST interfaces to external response fifo:
+ assign rf_source_valid = (local_read | local_compressed_read | nonposted_write_endofpacket) & ready_for_command & cp_ready; //llim: modifying this to allow non-posted write commands to also be stored in the response fifo.
+ assign rf_source_startofpacket = cp_startofpacket;
+ assign rf_source_endofpacket = cp_endofpacket;
+ always @* begin
+ // Default: assign every command packet field to the response FIFO...
+ rf_source_data = {1'b0, cp_data};
+
+ // ... and override select fields as needed.
+ rf_source_data[FIFO_DATA_W-1] = read_suppressed;
+ rf_source_data[PKT_DATA_H :PKT_DATA_L] = {DATA_W {1'b0}};
+ rf_source_data[PKT_BYTEEN_H :PKT_BYTEEN_L] = cmd_byteen;
+ rf_source_data[PKT_ADDR_H :PKT_ADDR_L] = cmd_addr;
+ rf_source_data[PKT_TRANS_COMPRESSED_READ] = cmd_compressed;
+ rf_source_data[PKT_TRANS_POSTED] = cmd_posted;
+ rf_source_data[PKT_TRANS_WRITE] = cmd_write;
+ rf_source_data[PKT_TRANS_READ] = cmd_read;
+ rf_source_data[PKT_SRC_ID_H :PKT_SRC_ID_L] = cmd_mid;
+ rf_source_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = cmd_sid;
+ rf_source_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L] = cmd_byte_cnt;
+ rf_source_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = cmd_burstwrap;
+ rf_source_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = '0;
+ rf_source_data[PKT_PROTECTION_L] = cmd_debugaccess;
+ end
+
+ wire uncompressor_source_valid;
+ assign generate_response = rf_sink_data[FIFO_DATA_W-1];
+ //assign rp_valid = rdata_fifo_sink_valid | (uncompressor_source_valid | generate_response);
+ assign rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid;
+
+ wire [BYTE_CNT_W-1:0] rf_sink_byte_cnt = rf_sink_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L];
+ wire rf_sink_compressed = rf_sink_data[PKT_TRANS_COMPRESSED_READ];
+ wire [BURSTWRAP_W-1:0] rf_sink_burstwrap = rf_sink_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L];
+ wire [ADDR_W-1:0] rf_sink_addr = rf_sink_data[PKT_ADDR_H:PKT_ADDR_L];
+
+ wire [BYTE_CNT_W-1:0] burst_byte_cnt;
+ wire [BURSTWRAP_W-1:0] rp_burstwrap;
+ wire [ADDR_W-1:0] rp_address;
+ wire rp_is_compressed;
+
+ // ------------------------------------------------------------------
+ // Backpressure the readdata fifo if we're supposed to synthesize a response
+ // llim: also backpressure the rdata fifo when there is a write response
+ // ------------------------------------------------------------------
+ assign rdata_fifo_sink_ready = rdata_fifo_sink_valid & rp_ready & ~(rf_sink_valid & generate_response);
+
+ always @* begin
+ // By default, return all fields...
+ rp_data = rf_sink_data[ST_DATA_W - 1 : 0];
+
+ // ... and override specific fields.
+ rp_data[PKT_DATA_H :PKT_DATA_L] = rdata_fifo_sink_data;
+ // Assignments directly from the response fifo.
+ rp_data[PKT_TRANS_POSTED] = rf_sink_data[PKT_TRANS_POSTED]; // should always be 1
+ rp_data[PKT_TRANS_WRITE] = rf_sink_data[PKT_TRANS_WRITE];
+ rp_data[PKT_SRC_ID_H :PKT_SRC_ID_L] = rf_sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+ rp_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = rf_sink_data[PKT_SRC_ID_H : PKT_SRC_ID_L];
+ rp_data[PKT_BYTEEN_H :PKT_BYTEEN_L] = rf_sink_data[PKT_BYTEEN_H : PKT_BYTEEN_L];
+ rp_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = rf_sink_data[PKT_PROTECTION_H:PKT_PROTECTION_L];
+
+ // Burst uncompressor assignments
+ rp_data[PKT_ADDR_H :PKT_ADDR_L] = rp_address;
+ rp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = rp_burstwrap;
+ rp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L] = burst_byte_cnt;
+ rp_data[PKT_TRANS_READ] = rf_sink_data[PKT_TRANS_READ] | rf_sink_data[PKT_TRANS_COMPRESSED_READ];
+ rp_data[PKT_TRANS_COMPRESSED_READ] = rp_is_compressed;
+// rp_data[PKT_AXI_RESP_H:PKT_AXI_RESP_L] = 2'b0; //llim: always return OKAY for avalon non bursting transaction
+ end
+
+ altera_merlin_burst_uncompressor #(
+ .ADDR_W (ADDR_W),
+ .BURSTWRAP_W (BURSTWRAP_W),
+ .BYTE_CNT_W (BYTE_CNT_W),
+ .PKT_SYMBOLS (PKT_SYMBOLS)
+ ) uncompressor
+ (
+ .clk (clk),
+ .reset (reset),
+ .sink_startofpacket (rf_sink_startofpacket),
+ .sink_endofpacket (rf_sink_endofpacket),
+ .sink_valid (rf_sink_valid & (rdata_fifo_sink_valid | generate_response )), //llim
+ .sink_ready (rf_sink_ready),
+ .sink_addr (rf_sink_addr),
+ .sink_burstwrap (rf_sink_burstwrap),
+ .sink_byte_cnt (rf_sink_byte_cnt),
+ .sink_is_compressed (rf_sink_compressed),
+
+ .source_startofpacket (rp_startofpacket),
+ .source_endofpacket (rp_endofpacket),
+ .source_valid (uncompressor_source_valid),
+ .source_ready (rp_ready),
+ .source_addr (rp_address),
+ .source_burstwrap (rp_burstwrap),
+ .source_byte_cnt (burst_byte_cnt),
+ .source_is_compressed (rp_is_compressed)
+ );
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_merlin_slave_translator.sv b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_merlin_slave_translator.sv
new file mode 100644
index 0000000000000000000000000000000000000000..ad91ee2aa23f0ffd6c9afbbdb54a5e10ee23efcf
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_merlin_slave_translator.sv
@@ -0,0 +1,514 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+
+// $Id: //acds/rel/11.1sp2/ip/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator.sv#1 $
+// $Revision: #1 $
+// $Date: 2011/11/10 $
+// $Author: max $
+
+// -------------------------------------
+// Merlin Slave Translator
+//
+// Translates Universal Avalon MM Slave
+// to any Avalon MM Slave
+// -------------------------------------
+//
+//Notable Note: 0 AV_READLATENCY is not allowed and will be converted to a 1 cycle readlatency in all cases but one
+//If you declare a slave with fixed read timing requirements, the readlatency of such a slave will be allowed to be zero
+//The key feature here is that no same cycle turnaround data is processed through the fabric.
+
+//import avalon_utilities_pkg::*;
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_slave_translator
+ #(
+ parameter
+ //Widths
+ AV_ADDRESS_W = 32,
+ AV_DATA_W = 32,
+ AV_BURSTCOUNT_W = 4,
+ AV_BYTEENABLE_W = 4,
+ UAV_BYTEENABLE_W = 4,
+
+ //Read Latency
+ AV_READLATENCY = 1,
+
+ //Timing
+ AV_READ_WAIT_CYCLES = 0,
+ AV_WRITE_WAIT_CYCLES = 0,
+ AV_SETUP_WAIT_CYCLES = 0,
+ AV_DATA_HOLD_CYCLES = 0,
+
+ //Optional Port Declarations
+ USE_READDATAVALID = 1,
+ USE_WAITREQUEST = 1,
+
+ //Variable Addressing
+ AV_SYMBOLS_PER_WORD = 4,
+ AV_ADDRESS_SYMBOLS = 0,
+ AV_BURSTCOUNT_SYMBOLS = 0,
+ BITS_PER_WORD = clog2(AV_SYMBOLS_PER_WORD - 1),
+ UAV_ADDRESS_W = 38,
+ UAV_BURSTCOUNT_W = 10,
+ UAV_DATA_W = 32,
+
+ AV_CONSTANT_BURST_BEHAVIOR = 0,
+ UAV_CONSTANT_BURST_BEHAVIOR = 0,
+ CHIPSELECT_THROUGH_READLATENCY = 0,
+
+ // Tightly-Coupled Options
+ USE_UAV_CLKEN = 0,
+ AV_REQUIRE_UNALIGNED_ADDRESSES = 0
+ )
+ (
+
+ // -------------------
+ // Clock & Reset
+ // -------------------
+ input wire clk,
+ input wire reset,
+
+ // -------------------
+ // Universal Avalon Slave
+ // -------------------
+
+ input wire [UAV_ADDRESS_W - 1 : 0] uav_address,
+ input wire [UAV_DATA_W - 1 : 0] uav_writedata,
+ input wire uav_write,
+ input wire uav_read,
+ input wire [UAV_BURSTCOUNT_W - 1 : 0] uav_burstcount,
+ input wire [UAV_BYTEENABLE_W - 1 : 0] uav_byteenable,
+ input wire uav_lock,
+ input wire uav_debugaccess,
+ input wire uav_clken,
+
+ output logic uav_readdatavalid,
+ output logic uav_waitrequest,
+ output logic[UAV_DATA_W - 1 : 0] uav_readdata,
+
+ // -------------------
+ // Customizable Avalon Master
+ // -------------------
+ output logic [AV_ADDRESS_W - 1 : 0] av_address,
+ output logic [AV_DATA_W - 1 : 0] av_writedata,
+ output logic av_write,
+ output logic av_read,
+ output logic[AV_BURSTCOUNT_W - 1 : 0] av_burstcount,
+ output logic[AV_BYTEENABLE_W - 1 : 0] av_byteenable,
+ output logic[AV_BYTEENABLE_W - 1 : 0] av_writebyteenable,
+ output logic av_begintransfer,
+ output wire av_chipselect,
+ output logic av_beginbursttransfer,
+ output logic av_lock,
+ output wire av_clken,
+ output wire av_debugaccess,
+ output wire av_outputenable,
+
+ input logic [AV_DATA_W - 1 : 0] av_readdata,
+ input logic av_readdatavalid,
+ input logic av_waitrequest
+ );
+
+ function integer clog2;
+ input [31:0] Depth;
+ integer i;
+ begin
+ i = Depth;
+ for(clog2 = 0; i > 0; clog2 = clog2 + 1)
+ i = i >> 1;
+ end
+
+ endfunction
+
+ function integer max;
+ //returns the larger of two passed arguments
+ input [31:0] one;
+ input [31:0] two;
+
+ if(one > two)
+ max=one;
+ else
+ max=two;
+ endfunction // int
+
+ localparam AV_READ_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_READ_WAIT_CYCLES);
+ localparam AV_WRITE_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_WRITE_WAIT_CYCLES);
+ localparam AV_DATA_HOLD_INDEXED = (AV_WRITE_WAIT_INDEXED + AV_DATA_HOLD_CYCLES);
+ localparam LOG2_OF_LATENCY_SUM = max(clog2(AV_READ_WAIT_INDEXED + 1),clog2(AV_DATA_HOLD_INDEXED + 1));
+ localparam BURSTCOUNT_SHIFT_SELECTOR = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD;
+ localparam ADDRESS_SHIFT_SELECTOR = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD;
+
+ localparam ADDRESS_HIGH = ( UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR ) ?
+ AV_ADDRESS_W :
+ UAV_ADDRESS_W - ADDRESS_SHIFT_SELECTOR;
+
+ localparam BURSTCOUNT_HIGH = ( UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_SHIFT_SELECTOR ) ?
+ AV_BURSTCOUNT_W :
+ UAV_BURSTCOUNT_W - BURSTCOUNT_SHIFT_SELECTOR;
+ localparam BYTEENABLE_ADDRESS_BITS = ( clog2(UAV_BYTEENABLE_W) - 1 ) >= 1 ? clog2(UAV_BYTEENABLE_W) - 1 : 1;
+
+
+ // Calculate the symbols per word as the power of 2 extended symbols per word
+ wire [31 : 0] symbols_per_word_int = 2**(clog2(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W : 0] - 1));
+ wire [UAV_BURSTCOUNT_W : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W : 0];
+
+ // +--------------------------------
+ // |Backwards Compatibility Signals
+ // +--------------------------------
+ assign av_clken = (USE_UAV_CLKEN) ? uav_clken : 1'b1;
+ assign av_debugaccess = uav_debugaccess;
+
+ // +-------------------
+ // |Passthru Signals
+ // +-------------------
+
+
+ //-------------------------
+ //Writedata and Byteenable
+ //-------------------------
+
+ always@* begin
+ av_byteenable = '0;
+ av_byteenable = uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
+ end
+
+ always@* begin
+ av_writedata = '0;
+ av_writedata = uav_writedata[AV_DATA_W - 1 : 0];
+ end
+
+ // +-------------------
+ // |Calculated Signals
+ // +-------------------
+
+ logic [UAV_ADDRESS_W - 1 : 0 ] real_uav_address;
+
+ function [BYTEENABLE_ADDRESS_BITS - 1 : 0 ] decode_byteenable;
+ input [UAV_BYTEENABLE_W - 1 : 0 ] byteenable;
+
+ for(int i = 0 ; i < UAV_BYTEENABLE_W; i++ ) begin
+ if(byteenable[i] == 1) begin
+ return i;
+ end
+ end
+
+ return '0;
+
+ endfunction
+
+ reg [AV_BURSTCOUNT_W - 1 : 0] burstcount_reg;
+ reg [AV_ADDRESS_W - 1 : 0] address_reg;
+
+
+ always@(posedge clk, posedge reset) begin
+ if(reset) begin
+ burstcount_reg <= '0;
+ address_reg <= '0;
+ end
+ else begin
+ burstcount_reg <= burstcount_reg;
+ address_reg <= address_reg;
+
+ if(av_beginbursttransfer) begin
+ burstcount_reg <= uav_burstcount [BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
+ address_reg <= real_uav_address [ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
+
+ end
+ end
+ end
+
+
+ logic [BYTEENABLE_ADDRESS_BITS-1:0] temp_wire;
+
+ always@* begin
+ if( AV_REQUIRE_UNALIGNED_ADDRESSES == 1) begin
+ temp_wire = decode_byteenable(uav_byteenable);
+
+ real_uav_address = { uav_address[UAV_ADDRESS_W - 1 : BYTEENABLE_ADDRESS_BITS ], temp_wire[BYTEENABLE_ADDRESS_BITS - 1 : 0 ] };
+ end
+ else begin
+ real_uav_address = uav_address;
+ end
+
+ av_address = real_uav_address[ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
+
+ if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
+ av_address = address_reg;
+ end
+
+ always@* begin
+ av_burstcount=uav_burstcount[BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
+
+ if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
+ av_burstcount = burstcount_reg;
+ end
+
+ always@* begin
+ av_lock = uav_lock;
+ end
+
+ // -------------------
+ // Writebyteenable Assignment
+ // -------------------
+
+always@* begin
+ av_writebyteenable = { (AV_BYTEENABLE_W){uav_write} } & uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
+end
+
+ // -------------------
+ // Waitrequest Assignment
+ // -------------------
+
+ reg av_waitrequest_generated;
+ reg av_waitrequest_generated_read;
+ reg av_waitrequest_generated_write;
+ reg waitrequest_reset_override;
+
+ reg [ ( LOG2_OF_LATENCY_SUM ? LOG2_OF_LATENCY_SUM - 1 : 0 ) : 0 ] wait_latency_counter;
+
+ always@(posedge reset, posedge clk) begin
+
+ if(reset) begin
+ wait_latency_counter <= '0;
+ waitrequest_reset_override <= 1'h1;
+ end
+ else begin
+ waitrequest_reset_override <= 1'h0;
+
+ wait_latency_counter <= '0;
+
+ if( uav_read | uav_write )
+ wait_latency_counter <= wait_latency_counter + 1'h1;
+
+ if( ~uav_waitrequest | waitrequest_reset_override )
+ wait_latency_counter <= '0;
+
+ end
+
+ end
+
+
+ always @* begin
+
+ av_read = uav_read;
+ av_write = uav_write;
+
+ av_waitrequest_generated = 1'h1;
+ av_waitrequest_generated_read = 1'h1;
+ av_waitrequest_generated_write = 1'h1;
+
+ if(LOG2_OF_LATENCY_SUM == 1)
+ av_waitrequest_generated = 0;
+
+ if(LOG2_OF_LATENCY_SUM > 1 && !USE_WAITREQUEST) begin
+ av_read = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_read;
+ av_write = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_write && wait_latency_counter <= AV_WRITE_WAIT_INDEXED;
+
+ av_waitrequest_generated_read = wait_latency_counter != AV_READ_WAIT_INDEXED;
+ av_waitrequest_generated_write = wait_latency_counter != AV_DATA_HOLD_INDEXED;
+
+ if(uav_write)
+ av_waitrequest_generated = av_waitrequest_generated_write;
+ else
+ av_waitrequest_generated = av_waitrequest_generated_read;
+
+ end
+
+ if(USE_WAITREQUEST) begin
+ uav_waitrequest = av_waitrequest;
+ end
+ else begin
+ uav_waitrequest = av_waitrequest_generated | waitrequest_reset_override;
+ end
+
+ end
+
+ // --------------
+ // Readdata Assignment
+ // --------------
+
+ reg[(AV_DATA_W ? AV_DATA_W -1 : 0 ): 0] av_readdata_pre;
+
+ always@(posedge clk, posedge reset) begin
+ if(reset)
+ av_readdata_pre <= 'b0;
+ else
+ av_readdata_pre <= av_readdata;
+ end
+
+ always@* begin
+ uav_readdata = '0;
+
+ if( AV_READLATENCY != 0 || USE_READDATAVALID ) begin
+ uav_readdata = av_readdata;
+ end
+ else begin
+ uav_readdata = av_readdata_pre;
+ end
+ end
+ // -------------------
+ // Readdatavalid Assigment
+ // -------------------
+
+ reg[(AV_READLATENCY>0 ? AV_READLATENCY-1:0) :0] read_latency_shift_reg;
+ reg top_read_latency_shift_reg;
+
+
+
+ always@* begin
+
+ uav_readdatavalid=top_read_latency_shift_reg;
+
+ if(USE_READDATAVALID) begin
+ uav_readdatavalid = av_readdatavalid;
+ end
+
+ end
+
+ always@* begin
+
+ top_read_latency_shift_reg = uav_read & ~uav_waitrequest & ~waitrequest_reset_override;
+
+ if(AV_READLATENCY == 1 || AV_READLATENCY == 0 ) begin
+ top_read_latency_shift_reg=read_latency_shift_reg;
+ end
+
+ if (AV_READLATENCY > 1) begin
+ top_read_latency_shift_reg = read_latency_shift_reg[(AV_READLATENCY ? AV_READLATENCY-1 : 0)];
+ end
+
+ end
+
+ always@(posedge reset, posedge clk) begin
+
+ if (reset) begin
+ read_latency_shift_reg <= '0;
+ end
+ else if (av_clken) begin
+
+ read_latency_shift_reg <= uav_read && ~uav_waitrequest & ~waitrequest_reset_override;
+
+ for (int i=0; i+1 < AV_READLATENCY ; i+=1 ) begin
+ read_latency_shift_reg[i+1] <= read_latency_shift_reg[i];
+ end
+
+ end
+
+ end
+
+ // ------------
+ // Chipselect and OutputEnable
+ // ------------
+
+ reg av_chipselect_pre;
+ wire cs_extension;
+ reg av_outputenable_pre;
+
+
+ assign av_chipselect = (uav_read | uav_write) ? 1'b1 : av_chipselect_pre;
+ assign cs_extension = ( (^ read_latency_shift_reg) & ~top_read_latency_shift_reg ) | ((| read_latency_shift_reg) & ~(^ read_latency_shift_reg));
+
+ assign av_outputenable = uav_read ? 1'b1 : av_outputenable_pre;
+
+ always@(posedge reset, posedge clk) begin
+ if(reset)
+ av_outputenable_pre <= 1'b0;
+ else if( AV_READLATENCY == 0 && AV_READ_WAIT_INDEXED != 0 )
+ av_outputenable_pre <= 0;
+ else
+ av_outputenable_pre <= cs_extension | uav_read;
+ end
+
+ always@(posedge reset, posedge clk) begin
+ if(reset) begin
+ av_chipselect_pre <= 1'b0;
+ end
+ else begin
+ av_chipselect_pre <= 1'b0;
+
+ if(AV_READLATENCY != 0 && CHIPSELECT_THROUGH_READLATENCY == 1) begin
+ //The AV_READLATENCY term is only here to prevent chipselect from remaining asserted while read and write fall.
+ //There is no functional impact as 0 cycle transactions are treated as 1 cycle on the other side of the translator.
+ if(uav_read) begin
+ av_chipselect_pre <= 1'b1;
+ end
+ else if(cs_extension == 1) begin
+ av_chipselect_pre <= 1'b1;
+ end
+
+ end
+ end
+ end
+
+ // -------------------
+ // Begintransfer Assigment
+ // -------------------
+
+ reg end_begintransfer;
+
+ always@* begin
+ av_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer;
+ end
+
+ always@ ( posedge clk or posedge reset ) begin
+
+ if(reset) begin
+ end_begintransfer <= 1'b0;
+ end
+ else begin
+
+ if(av_begintransfer == 1 && uav_waitrequest && ~waitrequest_reset_override)
+ end_begintransfer <= 1'b1;
+ else if(uav_waitrequest)
+ end_begintransfer <= end_begintransfer;
+ else
+ end_begintransfer <= 1'b0;
+
+ end
+
+ end
+
+ // -------------------
+ // Beginbursttransfer Assigment
+ // -------------------
+
+ reg end_beginbursttransfer;
+ reg in_transfer;
+
+
+
+ always@* begin
+ av_beginbursttransfer = uav_read ? av_begintransfer : (av_begintransfer && ~end_beginbursttransfer && ~in_transfer);
+ end
+
+ always@ ( posedge clk or posedge reset ) begin
+ if(reset) begin
+ end_beginbursttransfer <= 1'b0;
+ in_transfer <= 1'b0;
+ end
+ else begin
+
+ end_beginbursttransfer <= uav_write & ( uav_burstcount != symbols_per_word );
+
+ if(uav_write && uav_burstcount == symbols_per_word)
+ in_transfer <=1'b0;
+ else if(uav_write)
+ in_transfer <=1'b1;
+
+ end
+
+ end
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_merlin_traffic_limiter.sv b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_merlin_traffic_limiter.sv
new file mode 100644
index 0000000000000000000000000000000000000000..61ff14ee2fb69c4c7c1bb6f1d2894f3182b8d1ec
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_merlin_traffic_limiter.sv
@@ -0,0 +1,322 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/rel/11.1sp2/ip/merlin/altera_merlin_traffic_limiter/altera_merlin_traffic_limiter.sv#1 $
+// $Revision: #1 $
+// $Date: 2011/11/10 $
+// $Author: max $
+
+// -----------------------------------------------------
+// Merlin Traffic Limiter
+//
+// Ensures that non-posted transaction responses are returned
+// in order of request. Out-of-order responses can happen
+// when a master does a non-posted transaction on a slave
+// while responses are pending from a different slave.
+// Examples
+// 1) read to any latent slave, followed by a read to a
+// variable-latent slave
+// 2) read to any fixed-latency slave, followed by a read
+// to another fixed-latency slave whose fixed latency is smaller.
+//
+// For now, we'll backpressure to prevent a master from
+// switching slaves until all outstanding read responses have
+// returned. We also have to suppress the read, obviously.
+//
+// Note: folding this into the router may give better fmax,
+// consider after profiling. If folding into router, break
+// into separate components: address router and destid router.
+// This only needs to be in the address router.
+// -----------------------------------------------------
+
+`timescale 1 ns / 1 ns
+// altera message_off 10036
+module altera_merlin_traffic_limiter
+#(
+ parameter PKT_TRANS_POSTED = 1,
+ PKT_DEST_ID_H = 0,
+ PKT_DEST_ID_L = 0,
+ ST_DATA_W = 72,
+ ST_CHANNEL_W = 32,
+ MAX_OUTSTANDING_RESPONSES = 1,
+ PIPELINED = 0,
+ ENFORCE_ORDER = 1,
+ PKT_BYTE_CNT_H = 0,
+ PKT_BYTE_CNT_L = 0,
+ PKT_BYTEEN_H = 0,
+ PKT_BYTEEN_L = 0,
+ // -------------------------------------
+ // internal: allows optimization between this
+ // component and the demux
+ // -------------------------------------
+ VALID_WIDTH = 1
+)
+(
+ // -------------------
+ // Clock & Reset
+ // -------------------
+ input clk,
+ input reset,
+
+ // -------------------
+ // Command
+ // -------------------
+ input cmd_sink_valid,
+ input [ST_DATA_W-1 : 0] cmd_sink_data,
+ input [ST_CHANNEL_W-1 : 0] cmd_sink_channel,
+ input cmd_sink_startofpacket,
+ input cmd_sink_endofpacket,
+ output cmd_sink_ready,
+
+ output reg [VALID_WIDTH-1 : 0] cmd_src_valid,
+ output reg [ST_DATA_W-1 : 0] cmd_src_data,
+ output reg [ST_CHANNEL_W-1 : 0] cmd_src_channel,
+ output reg cmd_src_startofpacket,
+ output reg cmd_src_endofpacket,
+ input cmd_src_ready,
+
+ // -------------------
+ // Response
+ // -------------------
+ input rsp_sink_valid,
+ input [ST_DATA_W-1 : 0] rsp_sink_data,
+ input [ST_CHANNEL_W-1 : 0] rsp_sink_channel,
+ input rsp_sink_startofpacket,
+ input rsp_sink_endofpacket,
+ output reg rsp_sink_ready,
+
+ output reg rsp_src_valid,
+ output reg [ST_DATA_W-1 : 0] rsp_src_data,
+ output reg [ST_CHANNEL_W-1 : 0] rsp_src_channel,
+ output reg rsp_src_startofpacket,
+ output reg rsp_src_endofpacket,
+ input rsp_src_ready
+);
+
+ // -------------------------------------
+ // Local Parameters
+ // -------------------------------------
+ localparam DEST_ID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1;
+ localparam COUNTER_W = log2ceil(MAX_OUTSTANDING_RESPONSES + 1);
+ localparam PAYLOAD_W = ST_DATA_W + ST_CHANNEL_W + 3;
+ localparam NUMSYMBOLS = PKT_BYTEEN_H - PKT_BYTEEN_L + 1;
+
+ // -----------------------------------------------------
+ // Input Stage
+ //
+ // Figure out if the destination id has changed
+ // -----------------------------------------------------
+ wire stage1_nonposted_cmd;
+ wire stage1_dest_changed;
+ wire [PAYLOAD_W-1 : 0] stage1_payload;
+ wire [DEST_ID_W-1 : 0] dest_id;
+ reg [DEST_ID_W-1 : 0] last_dest_id;
+ reg [ST_CHANNEL_W-1:0] last_channel;
+ wire suppress;
+ wire save_dest_id;
+
+ assign dest_id = cmd_sink_data[PKT_DEST_ID_H:PKT_DEST_ID_L];
+ assign stage1_nonposted_cmd = (cmd_sink_data[PKT_TRANS_POSTED] == 0);
+
+ // ------------------------------------
+ // Optimization: for the unpipelined case, we can save the destid if
+ // this is an unsuppressed nonposted command. This eliminates
+ // dependence on the backpressure signal.
+ //
+ // Not a problem for the pipelined case.
+ // ------------------------------------
+ generate begin : pipelined_save_dest_id
+ if (PIPELINED)
+ assign save_dest_id = cmd_sink_valid & cmd_sink_ready & stage1_nonposted_cmd;
+ else
+ assign save_dest_id = cmd_sink_valid & ~suppress & stage1_nonposted_cmd;
+ end endgenerate
+
+ always @(posedge clk, posedge reset) begin
+ if (reset) begin
+ last_dest_id <= 0;
+ last_channel <= 0;
+ end
+ else if (save_dest_id) begin
+ last_dest_id <= dest_id;
+ last_channel <= cmd_sink_channel;
+ end
+ end
+
+ assign stage1_dest_changed = (last_dest_id != dest_id);
+
+ assign stage1_payload = { cmd_sink_data,
+ cmd_sink_channel,
+ cmd_sink_startofpacket,
+ cmd_sink_endofpacket,
+ stage1_dest_changed };
+
+ // -----------------------------------------------------
+ // (Optional) pipeline between input and output
+ // -----------------------------------------------------
+ wire stage2_valid;
+ reg stage2_ready;
+ wire [PAYLOAD_W-1 : 0] stage2_payload;
+
+ generate begin : pipelined_limiter
+ if (PIPELINED == 1) begin
+ altera_avalon_st_pipeline_base
+ #(
+ .BITS_PER_SYMBOL(PAYLOAD_W)
+ ) stage1_pipe (
+ .clk (clk),
+ .reset (reset),
+ .in_ready (cmd_sink_ready),
+ .in_valid (cmd_sink_valid),
+ .in_data (stage1_payload),
+ .out_valid (stage2_valid),
+ .out_ready (stage2_ready),
+ .out_data (stage2_payload)
+ );
+ end else begin
+ assign stage2_valid = cmd_sink_valid;
+ assign stage2_payload = stage1_payload;
+ assign cmd_sink_ready = stage2_ready;
+ end
+ end endgenerate
+
+ // -----------------------------------------------------
+ // Output Stage
+ // -----------------------------------------------------
+ wire [ST_DATA_W-1 : 0] stage2_data;
+ wire [ST_CHANNEL_W-1:0] stage2_channel;
+ wire stage2_startofpacket;
+ wire stage2_endofpacket;
+ wire stage2_dest_changed;
+ reg has_pending_responses;
+ reg [COUNTER_W-1 : 0] pending_response_count;
+ reg [COUNTER_W-1 : 0] next_pending_response_count;
+ wire nonposted_cmd;
+ wire nonposted_cmd_accepted;
+ wire response_accepted;
+ wire count_is_1;
+ wire count_is_0;
+ reg internal_valid;
+
+ assign { stage2_data,
+ stage2_channel,
+ stage2_startofpacket,
+ stage2_endofpacket,
+ stage2_dest_changed } = stage2_payload;
+
+ assign nonposted_cmd = (stage2_data[PKT_TRANS_POSTED] == 0);
+ assign nonposted_cmd_accepted = nonposted_cmd && internal_valid && (cmd_src_ready && cmd_src_endofpacket);
+ assign response_accepted = rsp_src_valid && rsp_src_ready && rsp_src_endofpacket;
+
+ always @* begin
+ next_pending_response_count = pending_response_count;
+
+ if (nonposted_cmd_accepted)
+ next_pending_response_count = pending_response_count + 1'b1;
+ if (response_accepted)
+ next_pending_response_count = pending_response_count - 1'b1;
+ if (nonposted_cmd_accepted && response_accepted)
+ next_pending_response_count = pending_response_count;
+ end
+
+ assign count_is_1 = (pending_response_count == 1);
+ assign count_is_0 = (pending_response_count == 0);
+
+ always @(posedge clk, posedge reset) begin
+ if (reset) begin
+ pending_response_count <= 0;
+ has_pending_responses <= 0;
+ end
+ else begin
+ pending_response_count <= next_pending_response_count;
+ // synthesis translate_off
+ if (count_is_0 && response_accepted)
+ $display("%t: %m: Error: unexpected response: pending_response_count underflow", $time());
+ // synthesis translate_on
+ has_pending_responses <= has_pending_responses
+ && ~(count_is_1 && response_accepted && ~nonposted_cmd_accepted)
+ || (count_is_0 && nonposted_cmd_accepted && ~response_accepted);
+ end
+ end
+
+ // -------------------------------------
+ // Pass-through command and response
+ // -------------------------------------
+ always @* begin
+ cmd_src_data = stage2_data;
+ cmd_src_channel = stage2_channel;
+ cmd_src_startofpacket = stage2_startofpacket;
+ cmd_src_endofpacket = stage2_endofpacket;
+
+ rsp_src_valid = rsp_sink_valid;
+ rsp_src_data = rsp_sink_data;
+ rsp_src_channel = rsp_sink_channel;
+ rsp_src_startofpacket = rsp_sink_startofpacket;
+ rsp_src_endofpacket = rsp_sink_endofpacket;
+ rsp_sink_ready = rsp_src_ready;
+ end
+
+ // -------------------------------------
+ // Backpressure & Suppression
+ // -------------------------------------
+ generate begin : enforce_order_block
+ if (ENFORCE_ORDER)
+ assign suppress = nonposted_cmd & has_pending_responses & stage2_dest_changed;
+ else
+ assign suppress = 1'b0;
+ end endgenerate
+
+ always @* begin
+ stage2_ready = cmd_src_ready;
+ internal_valid = stage2_valid;
+
+ if (suppress) begin
+ stage2_ready = 0;
+ internal_valid = 0;
+ end
+
+ if (VALID_WIDTH == 1) begin
+ cmd_src_valid = internal_valid;
+ end else begin
+ // -------------------------------------
+ // Use the one-hot channel to determine if the destination
+ // has changed. This results in a wide valid bus
+ // -------------------------------------
+ cmd_src_valid = { VALID_WIDTH {stage2_valid} } & cmd_sink_channel;
+ if (nonposted_cmd & has_pending_responses)
+ cmd_src_valid = cmd_src_valid & last_channel;
+ end
+ end
+
+ // --------------------------------------------------
+ // Calculates the log2ceil of the input value.
+ //
+ // This function occurs a lot... please refactor.
+ // --------------------------------------------------
+ function integer log2ceil;
+ input integer val;
+ integer i;
+
+ begin
+ i = 1;
+ log2ceil = 0;
+
+ while (i < val) begin
+ log2ceil = log2ceil + 1;
+ i = i << 1;
+ end
+ end
+ endfunction
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_packet_stripper.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_packet_stripper.v
new file mode 100644
index 0000000000000000000000000000000000000000..3bebc69d040bdbcebb57a81363282bcb4d8fdef9
Binary files /dev/null and b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_packet_stripper.v differ
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_reset_controller.sdc b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_reset_controller.sdc
new file mode 100644
index 0000000000000000000000000000000000000000..34471b2395122060426206b18f692fa35c7acc82
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_reset_controller.sdc
@@ -0,0 +1,18 @@
+# (C) 2001-2012 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and other
+# software and tools, and its AMPP partner logic functions, and any output
+# files any of the foregoing (including device programming or simulation
+# files), and any associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License Subscription
+# Agreement, Altera MegaCore Function License Agreement, or other applicable
+# license agreement, including, without limitation, that your use is for the
+# sole purpose of programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+
+# +---------------------------------------------------
+# | Cut the async clear paths
+# +---------------------------------------------------
+set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
+set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_reset_controller.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_reset_controller.v
new file mode 100644
index 0000000000000000000000000000000000000000..61b866ec3c1b562b273ea036dd8d80a47b841bd0
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_reset_controller.v
@@ -0,0 +1,110 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/rel/11.1sp2/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
+// $Revision: #1 $
+// $Date: 2011/11/10 $
+// $Author: max $
+
+// --------------------------------------
+// Reset controller
+//
+// Combines all the input resets and synchronizes
+// the result to the clk.
+// --------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module altera_reset_controller
+#(
+ parameter NUM_RESET_INPUTS = 6,
+ parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
+ parameter SYNC_DEPTH = 2
+)
+(
+ // --------------------------------------
+ // We support up to 16 reset inputs, for now
+ // --------------------------------------
+ input reset_in0,
+ input reset_in1,
+ input reset_in2,
+ input reset_in3,
+ input reset_in4,
+ input reset_in5,
+ input reset_in6,
+ input reset_in7,
+ input reset_in8,
+ input reset_in9,
+ input reset_in10,
+ input reset_in11,
+ input reset_in12,
+ input reset_in13,
+ input reset_in14,
+ input reset_in15,
+
+ input clk,
+ output reset_out
+);
+
+ localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
+
+ wire merged_reset;
+
+ // --------------------------------------
+ // "Or" all the input resets together
+ // --------------------------------------
+ assign merged_reset = (
+ reset_in0 |
+ reset_in1 |
+ reset_in2 |
+ reset_in3 |
+ reset_in4 |
+ reset_in5 |
+ reset_in6 |
+ reset_in7 |
+ reset_in8 |
+ reset_in9 |
+ reset_in10 |
+ reset_in11 |
+ reset_in12 |
+ reset_in13 |
+ reset_in14 |
+ reset_in15
+ );
+
+ // --------------------------------------
+ // And if required, synchronize it to the required clock domain,
+ // with the correct synchronization type
+ // --------------------------------------
+ generate if (OUTPUT_RESET_SYNC_EDGES == "none") begin
+
+ assign reset_out = merged_reset;
+
+ end else begin
+
+ altera_reset_synchronizer
+ #(
+ .DEPTH (SYNC_DEPTH),
+ .ASYNC_RESET(ASYNC_RESET)
+ )
+ alt_rst_sync_uq1
+ (
+ .clk (clk),
+ .reset_in (merged_reset),
+ .reset_out (reset_out)
+ );
+
+ end
+ endgenerate
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_reset_synchronizer.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_reset_synchronizer.v
new file mode 100644
index 0000000000000000000000000000000000000000..4345af2b3e0fa19f06b6ca6f884946e6ade3099a
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/altera_reset_synchronizer.v
@@ -0,0 +1,87 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/rel/11.1sp2/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
+// $Revision: #1 $
+// $Date: 2011/11/10 $
+// $Author: max $
+
+// -----------------------------------------------
+// Reset Synchronizer
+// -----------------------------------------------
+`timescale 1 ns / 1 ns
+
+module altera_reset_synchronizer
+#(
+ parameter ASYNC_RESET = 1,
+ parameter DEPTH = 2
+)
+(
+ input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
+
+ input clk,
+ output reset_out
+);
+
+ // -----------------------------------------------
+ // Synchronizer register chain. We cannot reuse the
+ // standard synchronizer in this implementation
+ // because our timing constraints are different.
+ //
+ // Instead of cutting the timing path to the d-input
+ // on the first flop we need to cut the aclr input.
+ //
+ // We omit the "preserve" attribute on the final
+ // output register, so that the synthesis tool can
+ // duplicate it where needed.
+ // -----------------------------------------------
+ (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
+ reg altera_reset_synchronizer_int_chain_out;
+
+ generate if (ASYNC_RESET) begin
+
+ // -----------------------------------------------
+ // Assert asynchronously, deassert synchronously.
+ // -----------------------------------------------
+ always @(posedge clk or posedge reset_in) begin
+ if (reset_in) begin
+ altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
+ altera_reset_synchronizer_int_chain_out <= 1'b1;
+ end
+ else begin
+ altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
+ altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
+ altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
+ end
+ end
+
+ assign reset_out = altera_reset_synchronizer_int_chain_out;
+
+ end else begin
+
+ // -----------------------------------------------
+ // Assert synchronously, deassert synchronously.
+ // -----------------------------------------------
+ always @(posedge clk) begin
+ altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
+ altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
+ altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
+ end
+
+ assign reset_out = altera_reset_synchronizer_int_chain_out;
+
+ end
+ endgenerate
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/crc32.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/crc32.v
new file mode 100644
index 0000000000000000000000000000000000000000..4d703a73fb77064984be5e1943e4e7fb6cd38646
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diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/gf_mult32_kc.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/gf_mult32_kc.v
new file mode 100644
index 0000000000000000000000000000000000000000..e52a3e16b3e87fdb27f03aecf286ecae28c8aca5
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diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_0002.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_0002.v
new file mode 100644
index 0000000000000000000000000000000000000000..c609d06e2bd8e3860c5c8ee4429f853914599a0b
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_0002.v
@@ -0,0 +1,7850 @@
+// ip_stratixiv_mac_10g_0002.v
+
+// This file was auto-generated from altera_eth_10g_mac_hw.tcl. If you edit it your changes
+// will probably be lost.
+//
+// Generated using ACDS version 11.1sp2 259 at 2014.10.02.11:39:44
+
+`timescale 1 ps / 1 ps
+module ip_stratixiv_mac_10g_0002 (
+ input wire csr_clk_clk, // csr_clk.clk
+ input wire csr_reset_reset_n, // csr_reset.reset_n
+ input wire [12:0] csr_address, // csr.address
+ output wire csr_waitrequest, // .waitrequest
+ input wire csr_read, // .read
+ output wire [31:0] csr_readdata, // .readdata
+ input wire csr_write, // .write
+ input wire [31:0] csr_writedata, // .writedata
+ input wire tx_clk_clk, // tx_clk.clk
+ input wire tx_reset_reset_n, // tx_reset.reset_n
+ input wire avalon_st_tx_startofpacket, // avalon_st_tx.startofpacket
+ input wire avalon_st_tx_valid, // .valid
+ input wire [63:0] avalon_st_tx_data, // .data
+ input wire [2:0] avalon_st_tx_empty, // .empty
+ output wire avalon_st_tx_ready, // .ready
+ input wire avalon_st_tx_error, // .error
+ input wire avalon_st_tx_endofpacket, // .endofpacket
+ input wire [1:0] avalon_st_pause_data, // avalon_st_pause.data
+ output wire [71:0] xgmii_tx_data, // xgmii_tx.data
+ output wire avalon_st_txstatus_valid, // avalon_st_txstatus.valid
+ output wire [39:0] avalon_st_txstatus_data, // .data
+ output wire [6:0] avalon_st_txstatus_error, // .error
+ input wire rx_clk_clk, // rx_clk.clk
+ input wire rx_reset_reset_n, // rx_reset.reset_n
+ input wire [71:0] xgmii_rx_data, // xgmii_rx.data
+ output wire avalon_st_rx_startofpacket, // avalon_st_rx.startofpacket
+ output wire avalon_st_rx_endofpacket, // .endofpacket
+ output wire avalon_st_rx_valid, // .valid
+ input wire avalon_st_rx_ready, // .ready
+ output wire [63:0] avalon_st_rx_data, // .data
+ output wire [2:0] avalon_st_rx_empty, // .empty
+ output wire [5:0] avalon_st_rx_error, // .error
+ output wire avalon_st_rxstatus_valid, // avalon_st_rxstatus.valid
+ output wire [39:0] avalon_st_rxstatus_data, // .data
+ output wire [6:0] avalon_st_rxstatus_error, // .error
+ output wire [1:0] link_fault_status_xgmii_rx_data // link_fault_status_xgmii_rx.data
+ );
+
+ wire tx_eth_packet_underflow_control_avalon_streaming_source_endofpacket; // tx_eth_packet_underflow_control:data_src_eop -> tx_eth_pad_inserter:data_sink_eop
+ wire tx_eth_packet_underflow_control_avalon_streaming_source_valid; // tx_eth_packet_underflow_control:data_src_valid -> tx_eth_pad_inserter:data_sink_valid
+ wire tx_eth_packet_underflow_control_avalon_streaming_source_startofpacket; // tx_eth_packet_underflow_control:data_src_sop -> tx_eth_pad_inserter:data_sink_sop
+ wire [1:0] tx_eth_packet_underflow_control_avalon_streaming_source_error; // tx_eth_packet_underflow_control:data_src_error -> tx_eth_pad_inserter:data_sink_error
+ wire [2:0] tx_eth_packet_underflow_control_avalon_streaming_source_empty; // tx_eth_packet_underflow_control:data_src_empty -> tx_eth_pad_inserter:data_sink_empty
+ wire [63:0] tx_eth_packet_underflow_control_avalon_streaming_source_data; // tx_eth_packet_underflow_control:data_src_data -> tx_eth_pad_inserter:data_sink_data
+ wire tx_eth_packet_underflow_control_avalon_streaming_source_ready; // tx_eth_pad_inserter:data_sink_ready -> tx_eth_packet_underflow_control:data_src_ready
+ wire tx_eth_pause_beat_conversion_pause_beat_src_valid; // tx_eth_pause_beat_conversion:pause_beat_src_valid -> tx_eth_pkt_backpressure_control:pausebeats_sink_valid
+ wire [31:0] tx_eth_pause_beat_conversion_pause_beat_src_data; // tx_eth_pause_beat_conversion:pause_beat_src_data -> tx_eth_pkt_backpressure_control:pausebeats_sink_data
+ wire tx_eth_pad_inserter_avalon_st_source_data_endofpacket; // tx_eth_pad_inserter:data_src_eop -> tx_eth_pkt_backpressure_control:data_sink_eop
+ wire tx_eth_pad_inserter_avalon_st_source_data_valid; // tx_eth_pad_inserter:data_src_valid -> tx_eth_pkt_backpressure_control:data_sink_valid
+ wire tx_eth_pad_inserter_avalon_st_source_data_startofpacket; // tx_eth_pad_inserter:data_src_sop -> tx_eth_pkt_backpressure_control:data_sink_sop
+ wire [1:0] tx_eth_pad_inserter_avalon_st_source_data_error; // tx_eth_pad_inserter:data_src_error -> tx_eth_pkt_backpressure_control:data_sink_error
+ wire [2:0] tx_eth_pad_inserter_avalon_st_source_data_empty; // tx_eth_pad_inserter:data_src_empty -> tx_eth_pkt_backpressure_control:data_sink_empty
+ wire [63:0] tx_eth_pad_inserter_avalon_st_source_data_data; // tx_eth_pad_inserter:data_src_data -> tx_eth_pkt_backpressure_control:data_sink_data
+ wire tx_eth_pad_inserter_avalon_st_source_data_ready; // tx_eth_pkt_backpressure_control:data_sink_ready -> tx_eth_pad_inserter:data_src_ready
+ wire tx_eth_pause_ctrl_gen_pause_packet_endofpacket; // tx_eth_pause_ctrl_gen:pause_source_eop -> tx_st_pause_ctrl_error_adapter:in_endofpacket
+ wire tx_eth_pause_ctrl_gen_pause_packet_valid; // tx_eth_pause_ctrl_gen:pause_source_valid -> tx_st_pause_ctrl_error_adapter:in_valid
+ wire tx_eth_pause_ctrl_gen_pause_packet_startofpacket; // tx_eth_pause_ctrl_gen:pause_source_sop -> tx_st_pause_ctrl_error_adapter:in_startofpacket
+ wire [0:0] tx_eth_pause_ctrl_gen_pause_packet_error; // tx_eth_pause_ctrl_gen:pause_source_error -> tx_st_pause_ctrl_error_adapter:in_error
+ wire [2:0] tx_eth_pause_ctrl_gen_pause_packet_empty; // tx_eth_pause_ctrl_gen:pause_source_empty -> tx_st_pause_ctrl_error_adapter:in_empty
+ wire [63:0] tx_eth_pause_ctrl_gen_pause_packet_data; // tx_eth_pause_ctrl_gen:pause_source_data -> tx_st_pause_ctrl_error_adapter:in_data
+ wire tx_eth_pause_ctrl_gen_pause_packet_ready; // tx_st_pause_ctrl_error_adapter:in_ready -> tx_eth_pause_ctrl_gen:pause_source_ready
+ wire tx_eth_pkt_backpressure_control_avalon_st_source_data_endofpacket; // tx_eth_pkt_backpressure_control:data_src_eop -> tx_st_mux_flow_control_user_frame:in0_endofpacket
+ wire tx_eth_pkt_backpressure_control_avalon_st_source_data_valid; // tx_eth_pkt_backpressure_control:data_src_valid -> tx_st_mux_flow_control_user_frame:in0_valid
+ wire tx_eth_pkt_backpressure_control_avalon_st_source_data_startofpacket; // tx_eth_pkt_backpressure_control:data_src_sop -> tx_st_mux_flow_control_user_frame:in0_startofpacket
+ wire [1:0] tx_eth_pkt_backpressure_control_avalon_st_source_data_error; // tx_eth_pkt_backpressure_control:data_src_error -> tx_st_mux_flow_control_user_frame:in0_error
+ wire [2:0] tx_eth_pkt_backpressure_control_avalon_st_source_data_empty; // tx_eth_pkt_backpressure_control:data_src_empty -> tx_st_mux_flow_control_user_frame:in0_empty
+ wire [63:0] tx_eth_pkt_backpressure_control_avalon_st_source_data_data; // tx_eth_pkt_backpressure_control:data_src_data -> tx_st_mux_flow_control_user_frame:in0_data
+ wire tx_eth_pkt_backpressure_control_avalon_st_source_data_ready; // tx_st_mux_flow_control_user_frame:in0_ready -> tx_eth_pkt_backpressure_control:data_src_ready
+ wire tx_st_pause_ctrl_error_adapter_out_endofpacket; // tx_st_pause_ctrl_error_adapter:out_endofpacket -> tx_st_mux_flow_control_user_frame:in1_endofpacket
+ wire tx_st_pause_ctrl_error_adapter_out_valid; // tx_st_pause_ctrl_error_adapter:out_valid -> tx_st_mux_flow_control_user_frame:in1_valid
+ wire tx_st_pause_ctrl_error_adapter_out_startofpacket; // tx_st_pause_ctrl_error_adapter:out_startofpacket -> tx_st_mux_flow_control_user_frame:in1_startofpacket
+ wire [1:0] tx_st_pause_ctrl_error_adapter_out_error; // tx_st_pause_ctrl_error_adapter:out_error -> tx_st_mux_flow_control_user_frame:in1_error
+ wire [2:0] tx_st_pause_ctrl_error_adapter_out_empty; // tx_st_pause_ctrl_error_adapter:out_empty -> tx_st_mux_flow_control_user_frame:in1_empty
+ wire [63:0] tx_st_pause_ctrl_error_adapter_out_data; // tx_st_pause_ctrl_error_adapter:out_data -> tx_st_mux_flow_control_user_frame:in1_data
+ wire tx_st_pause_ctrl_error_adapter_out_ready; // tx_st_mux_flow_control_user_frame:in1_ready -> tx_st_pause_ctrl_error_adapter:out_ready
+ wire tx_st_mux_flow_control_user_frame_out_endofpacket; // tx_st_mux_flow_control_user_frame:out_endofpacket -> tx_eth_address_inserter:data_sink_eop
+ wire tx_st_mux_flow_control_user_frame_out_valid; // tx_st_mux_flow_control_user_frame:out_valid -> tx_eth_address_inserter:data_sink_valid
+ wire tx_st_mux_flow_control_user_frame_out_startofpacket; // tx_st_mux_flow_control_user_frame:out_startofpacket -> tx_eth_address_inserter:data_sink_sop
+ wire [1:0] tx_st_mux_flow_control_user_frame_out_error; // tx_st_mux_flow_control_user_frame:out_error -> tx_eth_address_inserter:data_sink_error
+ wire [2:0] tx_st_mux_flow_control_user_frame_out_empty; // tx_st_mux_flow_control_user_frame:out_empty -> tx_eth_address_inserter:data_sink_empty
+ wire [63:0] tx_st_mux_flow_control_user_frame_out_data; // tx_st_mux_flow_control_user_frame:out_data -> tx_eth_address_inserter:data_sink_data
+ wire tx_st_mux_flow_control_user_frame_out_ready; // tx_eth_address_inserter:data_sink_ready -> tx_st_mux_flow_control_user_frame:out_ready
+ wire tx_eth_address_inserter_avalon_streaming_source_endofpacket; // tx_eth_address_inserter:data_src_eop -> tx_eth_crc_inserter:data_sink_eop
+ wire tx_eth_address_inserter_avalon_streaming_source_valid; // tx_eth_address_inserter:data_src_valid -> tx_eth_crc_inserter:data_sink_valid
+ wire tx_eth_address_inserter_avalon_streaming_source_startofpacket; // tx_eth_address_inserter:data_src_sop -> tx_eth_crc_inserter:data_sink_sop
+ wire [1:0] tx_eth_address_inserter_avalon_streaming_source_error; // tx_eth_address_inserter:data_src_error -> tx_eth_crc_inserter:data_sink_error
+ wire [2:0] tx_eth_address_inserter_avalon_streaming_source_empty; // tx_eth_address_inserter:data_src_empty -> tx_eth_crc_inserter:data_sink_empty
+ wire [63:0] tx_eth_address_inserter_avalon_streaming_source_data; // tx_eth_address_inserter:data_src_data -> tx_eth_crc_inserter:data_sink_data
+ wire tx_eth_address_inserter_avalon_streaming_source_ready; // tx_eth_crc_inserter:data_sink_ready -> tx_eth_address_inserter:data_src_ready
+ wire tx_eth_crc_inserter_avalon_streaming_source_endofpacket; // tx_eth_crc_inserter:data_src_eop -> tx_st_pipeline_stage_rs:in_endofpacket
+ wire tx_eth_crc_inserter_avalon_streaming_source_valid; // tx_eth_crc_inserter:data_src_valid -> tx_st_pipeline_stage_rs:in_valid
+ wire tx_eth_crc_inserter_avalon_streaming_source_startofpacket; // tx_eth_crc_inserter:data_src_sop -> tx_st_pipeline_stage_rs:in_startofpacket
+ wire [2:0] tx_eth_crc_inserter_avalon_streaming_source_error; // tx_eth_crc_inserter:data_src_error -> tx_st_pipeline_stage_rs:in_error
+ wire [2:0] tx_eth_crc_inserter_avalon_streaming_source_empty; // tx_eth_crc_inserter:data_src_empty -> tx_st_pipeline_stage_rs:in_empty
+ wire [63:0] tx_eth_crc_inserter_avalon_streaming_source_data; // tx_eth_crc_inserter:data_src_data -> tx_st_pipeline_stage_rs:in_data
+ wire tx_eth_crc_inserter_avalon_streaming_source_ready; // tx_st_pipeline_stage_rs:in_ready -> tx_eth_crc_inserter:data_src_ready
+ wire tx_st_pipeline_stage_rs_source0_endofpacket; // tx_st_pipeline_stage_rs:out_endofpacket -> tx_st_splitter_1:in0_endofpacket
+ wire tx_st_pipeline_stage_rs_source0_valid; // tx_st_pipeline_stage_rs:out_valid -> tx_st_splitter_1:in0_valid
+ wire tx_st_pipeline_stage_rs_source0_startofpacket; // tx_st_pipeline_stage_rs:out_startofpacket -> tx_st_splitter_1:in0_startofpacket
+ wire [2:0] tx_st_pipeline_stage_rs_source0_error; // tx_st_pipeline_stage_rs:out_error -> tx_st_splitter_1:in0_error
+ wire [63:0] tx_st_pipeline_stage_rs_source0_data; // tx_st_pipeline_stage_rs:out_data -> tx_st_splitter_1:in0_data
+ wire [2:0] tx_st_pipeline_stage_rs_source0_empty; // tx_st_pipeline_stage_rs:out_empty -> tx_st_splitter_1:in0_empty
+ wire tx_st_pipeline_stage_rs_source0_ready; // tx_st_splitter_1:in0_ready -> tx_st_pipeline_stage_rs:out_ready
+ wire tx_st_splitter_1_out0_endofpacket; // tx_st_splitter_1:out0_endofpacket -> tx_st_timing_adapter_frame_decoder:in_endofpacket
+ wire tx_st_splitter_1_out0_valid; // tx_st_splitter_1:out0_valid -> tx_st_timing_adapter_frame_decoder:in_valid
+ wire tx_st_splitter_1_out0_startofpacket; // tx_st_splitter_1:out0_startofpacket -> tx_st_timing_adapter_frame_decoder:in_startofpacket
+ wire [2:0] tx_st_splitter_1_out0_error; // tx_st_splitter_1:out0_error -> tx_st_timing_adapter_frame_decoder:in_error
+ wire [63:0] tx_st_splitter_1_out0_data; // tx_st_splitter_1:out0_data -> tx_st_timing_adapter_frame_decoder:in_data
+ wire [2:0] tx_st_splitter_1_out0_empty; // tx_st_splitter_1:out0_empty -> tx_st_timing_adapter_frame_decoder:in_empty
+ wire tx_st_splitter_1_out0_ready; // tx_st_timing_adapter_frame_decoder:in_ready -> tx_st_splitter_1:out0_ready
+ wire tx_st_splitter_1_out1_endofpacket; // tx_st_splitter_1:out1_endofpacket -> tx_eth_packet_formatter:data_sink_eop
+ wire tx_st_splitter_1_out1_valid; // tx_st_splitter_1:out1_valid -> tx_eth_packet_formatter:data_sink_valid
+ wire tx_st_splitter_1_out1_startofpacket; // tx_st_splitter_1:out1_startofpacket -> tx_eth_packet_formatter:data_sink_sop
+ wire [2:0] tx_st_splitter_1_out1_error; // tx_st_splitter_1:out1_error -> tx_eth_packet_formatter:data_sink_error
+ wire [63:0] tx_st_splitter_1_out1_data; // tx_st_splitter_1:out1_data -> tx_eth_packet_formatter:data_sink_data
+ wire [2:0] tx_st_splitter_1_out1_empty; // tx_st_splitter_1:out1_empty -> tx_eth_packet_formatter:data_sink_empty
+ wire tx_st_splitter_1_out1_ready; // tx_eth_packet_formatter:data_sink_ready -> tx_st_splitter_1:out1_ready
+ wire tx_st_timing_adapter_frame_decoder_out_endofpacket; // tx_st_timing_adapter_frame_decoder:out_endofpacket -> tx_eth_frame_decoder:data_sink_eop
+ wire tx_st_timing_adapter_frame_decoder_out_valid; // tx_st_timing_adapter_frame_decoder:out_valid -> tx_eth_frame_decoder:data_sink_valid
+ wire tx_st_timing_adapter_frame_decoder_out_startofpacket; // tx_st_timing_adapter_frame_decoder:out_startofpacket -> tx_eth_frame_decoder:data_sink_sop
+ wire [2:0] tx_st_timing_adapter_frame_decoder_out_error; // tx_st_timing_adapter_frame_decoder:out_error -> tx_eth_frame_decoder:data_sink_error
+ wire [2:0] tx_st_timing_adapter_frame_decoder_out_empty; // tx_st_timing_adapter_frame_decoder:out_empty -> tx_eth_frame_decoder:data_sink_empty
+ wire [63:0] tx_st_timing_adapter_frame_decoder_out_data; // tx_st_timing_adapter_frame_decoder:out_data -> tx_eth_frame_decoder:data_sink_data
+ wire tx_eth_frame_decoder_avalon_st_rxstatus_src_valid; // tx_eth_frame_decoder:rxstatus_src_valid -> tx_st_error_adapter_stat:in_valid
+ wire [5:0] tx_eth_frame_decoder_avalon_st_rxstatus_src_error; // tx_eth_frame_decoder:rxstatus_src_error -> tx_st_error_adapter_stat:in_error
+ wire [39:0] tx_eth_frame_decoder_avalon_st_rxstatus_src_data; // tx_eth_frame_decoder:rxstatus_src_data -> tx_st_error_adapter_stat:in_data
+ wire tx_st_error_adapter_stat_out_valid; // tx_st_error_adapter_stat:out_valid -> tx_st_timing_adapter_splitter_status_in:in_valid
+ wire [6:0] tx_st_error_adapter_stat_out_error; // tx_st_error_adapter_stat:out_error -> tx_st_timing_adapter_splitter_status_in:in_error
+ wire [39:0] tx_st_error_adapter_stat_out_data; // tx_st_error_adapter_stat:out_data -> tx_st_timing_adapter_splitter_status_in:in_data
+ wire tx_st_timing_adapter_splitter_status_in_out_valid; // tx_st_timing_adapter_splitter_status_in:out_valid -> tx_st_status_splitter:in0_valid
+ wire [6:0] tx_st_timing_adapter_splitter_status_in_out_error; // tx_st_timing_adapter_splitter_status_in:out_error -> tx_st_status_splitter:in0_error
+ wire [39:0] tx_st_timing_adapter_splitter_status_in_out_data; // tx_st_timing_adapter_splitter_status_in:out_data -> tx_st_status_splitter:in0_data
+ wire tx_st_timing_adapter_splitter_status_in_out_ready; // tx_st_status_splitter:in0_ready -> tx_st_timing_adapter_splitter_status_in:out_ready
+ wire tx_st_status_splitter_out0_valid; // tx_st_status_splitter:out0_valid -> tx_st_timing_adapter_splitter_status_statistics:in_valid
+ wire [6:0] tx_st_status_splitter_out0_error; // tx_st_status_splitter:out0_error -> tx_st_timing_adapter_splitter_status_statistics:in_error
+ wire [39:0] tx_st_status_splitter_out0_data; // tx_st_status_splitter:out0_data -> tx_st_timing_adapter_splitter_status_statistics:in_data
+ wire tx_st_status_splitter_out0_ready; // tx_st_timing_adapter_splitter_status_statistics:in_ready -> tx_st_status_splitter:out0_ready
+ wire tx_st_timing_adapter_splitter_status_statistics_out_valid; // tx_st_timing_adapter_splitter_status_statistics:out_valid -> tx_eth_statistics_collector:stat_sink_valid
+ wire [6:0] tx_st_timing_adapter_splitter_status_statistics_out_error; // tx_st_timing_adapter_splitter_status_statistics:out_error -> tx_eth_statistics_collector:stat_sink_error
+ wire [39:0] tx_st_timing_adapter_splitter_status_statistics_out_data; // tx_st_timing_adapter_splitter_status_statistics:out_data -> tx_eth_statistics_collector:stat_sink_data
+ wire tx_st_status_splitter_out1_valid; // tx_st_status_splitter:out1_valid -> tx_st_timing_adapter_splitter_status_output:in_valid
+ wire [6:0] tx_st_status_splitter_out1_error; // tx_st_status_splitter:out1_error -> tx_st_timing_adapter_splitter_status_output:in_error
+ wire [39:0] tx_st_status_splitter_out1_data; // tx_st_status_splitter:out1_data -> tx_st_timing_adapter_splitter_status_output:in_data
+ wire tx_st_status_splitter_out1_ready; // tx_st_timing_adapter_splitter_status_output:in_ready -> tx_st_status_splitter:out1_ready
+ wire tx_eth_packet_formatter_data_src_endofpacket; // tx_eth_packet_formatter:data_src_eop -> tx_eth_xgmii_termination:data_sink_eop
+ wire tx_eth_packet_formatter_data_src_valid; // tx_eth_packet_formatter:data_src_valid -> tx_eth_xgmii_termination:data_sink_valid
+ wire tx_eth_packet_formatter_data_src_startofpacket; // tx_eth_packet_formatter:data_src_sop -> tx_eth_xgmii_termination:data_sink_sop
+ wire [2:0] tx_eth_packet_formatter_data_src_empty; // tx_eth_packet_formatter:data_src_empty -> tx_eth_xgmii_termination:data_sink_empty
+ wire [71:0] tx_eth_packet_formatter_data_src_data; // tx_eth_packet_formatter:data_src_data -> tx_eth_xgmii_termination:data_sink_data
+ wire tx_eth_packet_formatter_data_src_ready; // tx_eth_xgmii_termination:data_sink_ready -> tx_eth_packet_formatter:data_src_ready
+ wire [71:0] tx_eth_xgmii_termination_avalon_streaming_source_data; // tx_eth_xgmii_termination:xgmii_src_data -> tx_eth_link_fault_generation:mii_sink_data
+ wire rx_st_timing_adapter_interface_conversion_out_valid; // rx_st_timing_adapter_interface_conversion:out_valid -> rx_st_splitter_xgmii:in0_valid
+ wire [71:0] rx_st_timing_adapter_interface_conversion_out_data; // rx_st_timing_adapter_interface_conversion:out_data -> rx_st_splitter_xgmii:in0_data
+ wire rx_st_timing_adapter_interface_conversion_out_ready; // rx_st_splitter_xgmii:in0_ready -> rx_st_timing_adapter_interface_conversion:out_ready
+ wire rx_st_splitter_xgmii_out0_valid; // rx_st_splitter_xgmii:out0_valid -> rx_st_timing_adapter_lane_decoder:in_valid
+ wire [71:0] rx_st_splitter_xgmii_out0_data; // rx_st_splitter_xgmii:out0_data -> rx_st_timing_adapter_lane_decoder:in_data
+ wire rx_st_splitter_xgmii_out0_ready; // rx_st_timing_adapter_lane_decoder:in_ready -> rx_st_splitter_xgmii:out0_ready
+ wire [71:0] rx_st_timing_adapter_lane_decoder_out_data; // rx_st_timing_adapter_lane_decoder:out_data -> rx_eth_lane_decoder:xgmii_sink_data
+ wire rx_st_splitter_xgmii_out1_valid; // rx_st_splitter_xgmii:out1_valid -> rx_st_timing_adapter_link_fault_detection:in_valid
+ wire [71:0] rx_st_splitter_xgmii_out1_data; // rx_st_splitter_xgmii:out1_data -> rx_st_timing_adapter_link_fault_detection:in_data
+ wire rx_st_splitter_xgmii_out1_ready; // rx_st_timing_adapter_link_fault_detection:in_ready -> rx_st_splitter_xgmii:out1_ready
+ wire [71:0] rx_st_timing_adapter_link_fault_detection_out_data; // rx_st_timing_adapter_link_fault_detection:out_data -> rx_eth_link_fault_detection:mii_sink_data
+ wire rx_eth_pkt_backpressure_control_avalon_st_source_data_endofpacket; // rx_eth_pkt_backpressure_control:data_src_eop -> rx_st_timing_adapter_frame_status_in:in_endofpacket
+ wire rx_eth_pkt_backpressure_control_avalon_st_source_data_valid; // rx_eth_pkt_backpressure_control:data_src_valid -> rx_st_timing_adapter_frame_status_in:in_valid
+ wire rx_eth_pkt_backpressure_control_avalon_st_source_data_startofpacket; // rx_eth_pkt_backpressure_control:data_src_sop -> rx_st_timing_adapter_frame_status_in:in_startofpacket
+ wire [0:0] rx_eth_pkt_backpressure_control_avalon_st_source_data_error; // rx_eth_pkt_backpressure_control:data_src_error -> rx_st_timing_adapter_frame_status_in:in_error
+ wire [2:0] rx_eth_pkt_backpressure_control_avalon_st_source_data_empty; // rx_eth_pkt_backpressure_control:data_src_empty -> rx_st_timing_adapter_frame_status_in:in_empty
+ wire [63:0] rx_eth_pkt_backpressure_control_avalon_st_source_data_data; // rx_eth_pkt_backpressure_control:data_src_data -> rx_st_timing_adapter_frame_status_in:in_data
+ wire rx_st_timing_adapter_frame_status_in_out_endofpacket; // rx_st_timing_adapter_frame_status_in:out_endofpacket -> rx_st_frame_status_splitter:in0_endofpacket
+ wire rx_st_timing_adapter_frame_status_in_out_valid; // rx_st_timing_adapter_frame_status_in:out_valid -> rx_st_frame_status_splitter:in0_valid
+ wire rx_st_timing_adapter_frame_status_in_out_startofpacket; // rx_st_timing_adapter_frame_status_in:out_startofpacket -> rx_st_frame_status_splitter:in0_startofpacket
+ wire rx_st_timing_adapter_frame_status_in_out_error; // rx_st_timing_adapter_frame_status_in:out_error -> rx_st_frame_status_splitter:in0_error
+ wire [2:0] rx_st_timing_adapter_frame_status_in_out_empty; // rx_st_timing_adapter_frame_status_in:out_empty -> rx_st_frame_status_splitter:in0_empty
+ wire [63:0] rx_st_timing_adapter_frame_status_in_out_data; // rx_st_timing_adapter_frame_status_in:out_data -> rx_st_frame_status_splitter:in0_data
+ wire rx_st_timing_adapter_frame_status_in_out_ready; // rx_st_frame_status_splitter:in0_ready -> rx_st_timing_adapter_frame_status_in:out_ready
+ wire rx_st_frame_status_splitter_out0_endofpacket; // rx_st_frame_status_splitter:out0_endofpacket -> rx_timing_adapter_frame_status_out_frame_decoder:in_endofpacket
+ wire rx_st_frame_status_splitter_out0_valid; // rx_st_frame_status_splitter:out0_valid -> rx_timing_adapter_frame_status_out_frame_decoder:in_valid
+ wire rx_st_frame_status_splitter_out0_startofpacket; // rx_st_frame_status_splitter:out0_startofpacket -> rx_timing_adapter_frame_status_out_frame_decoder:in_startofpacket
+ wire rx_st_frame_status_splitter_out0_error; // rx_st_frame_status_splitter:out0_error -> rx_timing_adapter_frame_status_out_frame_decoder:in_error
+ wire [63:0] rx_st_frame_status_splitter_out0_data; // rx_st_frame_status_splitter:out0_data -> rx_timing_adapter_frame_status_out_frame_decoder:in_data
+ wire [2:0] rx_st_frame_status_splitter_out0_empty; // rx_st_frame_status_splitter:out0_empty -> rx_timing_adapter_frame_status_out_frame_decoder:in_empty
+ wire rx_st_frame_status_splitter_out0_ready; // rx_timing_adapter_frame_status_out_frame_decoder:in_ready -> rx_st_frame_status_splitter:out0_ready
+ wire rx_timing_adapter_frame_status_out_frame_decoder_out_endofpacket; // rx_timing_adapter_frame_status_out_frame_decoder:out_endofpacket -> rx_eth_frame_decoder:data_sink_eop
+ wire rx_timing_adapter_frame_status_out_frame_decoder_out_valid; // rx_timing_adapter_frame_status_out_frame_decoder:out_valid -> rx_eth_frame_decoder:data_sink_valid
+ wire rx_timing_adapter_frame_status_out_frame_decoder_out_startofpacket; // rx_timing_adapter_frame_status_out_frame_decoder:out_startofpacket -> rx_eth_frame_decoder:data_sink_sop
+ wire rx_timing_adapter_frame_status_out_frame_decoder_out_error; // rx_timing_adapter_frame_status_out_frame_decoder:out_error -> rx_eth_frame_decoder:data_sink_error
+ wire [2:0] rx_timing_adapter_frame_status_out_frame_decoder_out_empty; // rx_timing_adapter_frame_status_out_frame_decoder:out_empty -> rx_eth_frame_decoder:data_sink_empty
+ wire [63:0] rx_timing_adapter_frame_status_out_frame_decoder_out_data; // rx_timing_adapter_frame_status_out_frame_decoder:out_data -> rx_eth_frame_decoder:data_sink_data
+ wire rx_eth_frame_decoder_avalon_st_data_src_endofpacket; // rx_eth_frame_decoder:data_src_eop -> rx_eth_frame_status_merger:frame_decoder_data_sink_eop
+ wire rx_eth_frame_decoder_avalon_st_data_src_valid; // rx_eth_frame_decoder:data_src_valid -> rx_eth_frame_status_merger:frame_decoder_data_sink_valid
+ wire rx_eth_frame_decoder_avalon_st_data_src_startofpacket; // rx_eth_frame_decoder:data_src_sop -> rx_eth_frame_status_merger:frame_decoder_data_sink_sop
+ wire [3:0] rx_eth_frame_decoder_avalon_st_data_src_error; // rx_eth_frame_decoder:data_src_error -> rx_eth_frame_status_merger:frame_decoder_data_sink_error
+ wire [2:0] rx_eth_frame_decoder_avalon_st_data_src_empty; // rx_eth_frame_decoder:data_src_empty -> rx_eth_frame_status_merger:frame_decoder_data_sink_empty
+ wire [63:0] rx_eth_frame_decoder_avalon_st_data_src_data; // rx_eth_frame_decoder:data_src_data -> rx_eth_frame_status_merger:frame_decoder_data_sink_data
+ wire rx_eth_frame_decoder_avalon_st_pauselen_src_valid; // rx_eth_frame_decoder:pauselen_src_valid -> rx_eth_frame_status_merger:pauselen_sink_valid
+ wire [15:0] rx_eth_frame_decoder_avalon_st_pauselen_src_data; // rx_eth_frame_decoder:pauselen_src_data -> rx_eth_frame_status_merger:pauselen_sink_data
+ wire rx_st_frame_status_splitter_out1_endofpacket; // rx_st_frame_status_splitter:out1_endofpacket -> rx_timing_adapter_frame_status_out_crc_checker:in_endofpacket
+ wire rx_st_frame_status_splitter_out1_valid; // rx_st_frame_status_splitter:out1_valid -> rx_timing_adapter_frame_status_out_crc_checker:in_valid
+ wire rx_st_frame_status_splitter_out1_startofpacket; // rx_st_frame_status_splitter:out1_startofpacket -> rx_timing_adapter_frame_status_out_crc_checker:in_startofpacket
+ wire rx_st_frame_status_splitter_out1_error; // rx_st_frame_status_splitter:out1_error -> rx_timing_adapter_frame_status_out_crc_checker:in_error
+ wire [63:0] rx_st_frame_status_splitter_out1_data; // rx_st_frame_status_splitter:out1_data -> rx_timing_adapter_frame_status_out_crc_checker:in_data
+ wire [2:0] rx_st_frame_status_splitter_out1_empty; // rx_st_frame_status_splitter:out1_empty -> rx_timing_adapter_frame_status_out_crc_checker:in_empty
+ wire rx_st_frame_status_splitter_out1_ready; // rx_timing_adapter_frame_status_out_crc_checker:in_ready -> rx_st_frame_status_splitter:out1_ready
+ wire rx_timing_adapter_frame_status_out_crc_checker_out_endofpacket; // rx_timing_adapter_frame_status_out_crc_checker:out_endofpacket -> rx_eth_crc_checker:data_sink_eop
+ wire rx_timing_adapter_frame_status_out_crc_checker_out_valid; // rx_timing_adapter_frame_status_out_crc_checker:out_valid -> rx_eth_crc_checker:data_sink_valid
+ wire rx_timing_adapter_frame_status_out_crc_checker_out_startofpacket; // rx_timing_adapter_frame_status_out_crc_checker:out_startofpacket -> rx_eth_crc_checker:data_sink_sop
+ wire rx_timing_adapter_frame_status_out_crc_checker_out_error; // rx_timing_adapter_frame_status_out_crc_checker:out_error -> rx_eth_crc_checker:data_sink_error
+ wire [2:0] rx_timing_adapter_frame_status_out_crc_checker_out_empty; // rx_timing_adapter_frame_status_out_crc_checker:out_empty -> rx_eth_crc_checker:data_sink_empty
+ wire [63:0] rx_timing_adapter_frame_status_out_crc_checker_out_data; // rx_timing_adapter_frame_status_out_crc_checker:out_data -> rx_eth_crc_checker:data_sink_data
+ wire rx_eth_frame_status_merger_data_src_endofpacket; // rx_eth_frame_status_merger:data_src_eop -> rx_eth_crc_pad_rem:data_sink_eop
+ wire rx_eth_frame_status_merger_data_src_valid; // rx_eth_frame_status_merger:data_src_valid -> rx_eth_crc_pad_rem:data_sink_valid
+ wire rx_eth_frame_status_merger_data_src_startofpacket; // rx_eth_frame_status_merger:data_src_sop -> rx_eth_crc_pad_rem:data_sink_sop
+ wire [4:0] rx_eth_frame_status_merger_data_src_error; // rx_eth_frame_status_merger:data_src_error -> rx_eth_crc_pad_rem:data_sink_error
+ wire [2:0] rx_eth_frame_status_merger_data_src_empty; // rx_eth_frame_status_merger:data_src_empty -> rx_eth_crc_pad_rem:data_sink_empty
+ wire [63:0] rx_eth_frame_status_merger_data_src_data; // rx_eth_frame_status_merger:data_src_data -> rx_eth_crc_pad_rem:data_sink_data
+ wire rx_eth_frame_decoder_avalon_st_pktinfo_src_valid; // rx_eth_frame_decoder:pktinfo_src_valid -> rx_eth_crc_pad_rem:status_sink_valid
+ wire [22:0] rx_eth_frame_decoder_avalon_st_pktinfo_src_data; // rx_eth_frame_decoder:pktinfo_src_data -> rx_eth_crc_pad_rem:status_sink_data
+ wire rx_eth_crc_pad_rem_avalon_streaming_source_data_endofpacket; // rx_eth_crc_pad_rem:data_source_eop -> rx_eth_packet_overflow_control:data_sink_eop
+ wire rx_eth_crc_pad_rem_avalon_streaming_source_data_valid; // rx_eth_crc_pad_rem:data_source_valid -> rx_eth_packet_overflow_control:data_sink_valid
+ wire rx_eth_crc_pad_rem_avalon_streaming_source_data_startofpacket; // rx_eth_crc_pad_rem:data_source_sop -> rx_eth_packet_overflow_control:data_sink_sop
+ wire [4:0] rx_eth_crc_pad_rem_avalon_streaming_source_data_error; // rx_eth_crc_pad_rem:data_source_error -> rx_eth_packet_overflow_control:data_sink_error
+ wire [2:0] rx_eth_crc_pad_rem_avalon_streaming_source_data_empty; // rx_eth_crc_pad_rem:data_source_empty -> rx_eth_packet_overflow_control:data_sink_empty
+ wire [63:0] rx_eth_crc_pad_rem_avalon_streaming_source_data_data; // rx_eth_crc_pad_rem:data_source_data -> rx_eth_packet_overflow_control:data_sink_data
+ wire rx_eth_crc_checker_avalon_streaming_source_endofpacket; // rx_eth_crc_checker:data_src_eop -> rx_eth_frame_status_merger:crc_checker_data_sink_eop
+ wire rx_eth_crc_checker_avalon_streaming_source_valid; // rx_eth_crc_checker:data_src_valid -> rx_eth_frame_status_merger:crc_checker_data_sink_valid
+ wire rx_eth_crc_checker_avalon_streaming_source_startofpacket; // rx_eth_crc_checker:data_src_sop -> rx_eth_frame_status_merger:crc_checker_data_sink_sop
+ wire [1:0] rx_eth_crc_checker_avalon_streaming_source_error; // rx_eth_crc_checker:data_src_error -> rx_eth_frame_status_merger:crc_checker_data_sink_error
+ wire [2:0] rx_eth_crc_checker_avalon_streaming_source_empty; // rx_eth_crc_checker:data_src_empty -> rx_eth_frame_status_merger:crc_checker_data_sink_empty
+ wire [63:0] rx_eth_crc_checker_avalon_streaming_source_data; // rx_eth_crc_checker:data_src_data -> rx_eth_frame_status_merger:crc_checker_data_sink_data
+ wire rx_eth_frame_decoder_avalon_st_rxstatus_src_valid; // rx_eth_frame_decoder:rxstatus_src_valid -> rx_eth_frame_status_merger:rxstatus_sink_valid
+ wire [3:0] rx_eth_frame_decoder_avalon_st_rxstatus_src_error; // rx_eth_frame_decoder:rxstatus_src_error -> rx_eth_frame_status_merger:rxstatus_sink_error
+ wire [39:0] rx_eth_frame_decoder_avalon_st_rxstatus_src_data; // rx_eth_frame_decoder:rxstatus_src_data -> rx_eth_frame_status_merger:rxstatus_sink_data
+ wire rx_eth_frame_status_merger_rxstatus_src_valid; // rx_eth_frame_status_merger:rxstatus_src_valid -> rx_st_error_adapter_stat:in_valid
+ wire [4:0] rx_eth_frame_status_merger_rxstatus_src_error; // rx_eth_frame_status_merger:rxstatus_src_error -> rx_st_error_adapter_stat:in_error
+ wire [39:0] rx_eth_frame_status_merger_rxstatus_src_data; // rx_eth_frame_status_merger:rxstatus_src_data -> rx_st_error_adapter_stat:in_data
+ wire rx_st_error_adapter_stat_out_valid; // rx_st_error_adapter_stat:out_valid -> rx_st_timing_adapter_splitter_status_in:in_valid
+ wire [6:0] rx_st_error_adapter_stat_out_error; // rx_st_error_adapter_stat:out_error -> rx_st_timing_adapter_splitter_status_in:in_error
+ wire [39:0] rx_st_error_adapter_stat_out_data; // rx_st_error_adapter_stat:out_data -> rx_st_timing_adapter_splitter_status_in:in_data
+ wire rx_st_timing_adapter_splitter_status_in_out_valid; // rx_st_timing_adapter_splitter_status_in:out_valid -> rx_st_status_splitter:in0_valid
+ wire [6:0] rx_st_timing_adapter_splitter_status_in_out_error; // rx_st_timing_adapter_splitter_status_in:out_error -> rx_st_status_splitter:in0_error
+ wire [39:0] rx_st_timing_adapter_splitter_status_in_out_data; // rx_st_timing_adapter_splitter_status_in:out_data -> rx_st_status_splitter:in0_data
+ wire rx_st_timing_adapter_splitter_status_in_out_ready; // rx_st_status_splitter:in0_ready -> rx_st_timing_adapter_splitter_status_in:out_ready
+ wire rx_st_status_splitter_out0_valid; // rx_st_status_splitter:out0_valid -> rx_st_timing_adapter_splitter_status_statistics:in_valid
+ wire [6:0] rx_st_status_splitter_out0_error; // rx_st_status_splitter:out0_error -> rx_st_timing_adapter_splitter_status_statistics:in_error
+ wire [39:0] rx_st_status_splitter_out0_data; // rx_st_status_splitter:out0_data -> rx_st_timing_adapter_splitter_status_statistics:in_data
+ wire rx_st_status_splitter_out0_ready; // rx_st_timing_adapter_splitter_status_statistics:in_ready -> rx_st_status_splitter:out0_ready
+ wire rx_st_timing_adapter_splitter_status_statistics_out_valid; // rx_st_timing_adapter_splitter_status_statistics:out_valid -> rx_st_status_statistics_delay:in0_valid
+ wire [6:0] rx_st_timing_adapter_splitter_status_statistics_out_error; // rx_st_timing_adapter_splitter_status_statistics:out_error -> rx_st_status_statistics_delay:in0_error
+ wire [39:0] rx_st_timing_adapter_splitter_status_statistics_out_data; // rx_st_timing_adapter_splitter_status_statistics:out_data -> rx_st_status_statistics_delay:in0_data
+ wire rx_st_status_statistics_delay_out_valid; // rx_st_status_statistics_delay:out0_valid -> rx_eth_statistics_collector:stat_sink_valid
+ wire [6:0] rx_st_status_statistics_delay_out_error; // rx_st_status_statistics_delay:out0_error -> rx_eth_statistics_collector:stat_sink_error
+ wire [39:0] rx_st_status_statistics_delay_out_data; // rx_st_status_statistics_delay:out0_data -> rx_eth_statistics_collector:stat_sink_data
+ wire rx_st_status_splitter_out1_valid; // rx_st_status_splitter:out1_valid -> rx_st_timing_adapter_splitter_status_output:in_valid
+ wire [6:0] rx_st_status_splitter_out1_error; // rx_st_status_splitter:out1_error -> rx_st_timing_adapter_splitter_status_output:in_error
+ wire [39:0] rx_st_status_splitter_out1_data; // rx_st_status_splitter:out1_data -> rx_st_timing_adapter_splitter_status_output:in_data
+ wire rx_st_status_splitter_out1_ready; // rx_st_timing_adapter_splitter_status_output:in_ready -> rx_st_status_splitter:out1_ready
+ wire rx_st_timing_adapter_splitter_status_output_out_valid; // rx_st_timing_adapter_splitter_status_output:out_valid -> rx_st_status_output_delay:in0_valid
+ wire [6:0] rx_st_timing_adapter_splitter_status_output_out_error; // rx_st_timing_adapter_splitter_status_output:out_error -> rx_st_status_output_delay:in0_error
+ wire [39:0] rx_st_timing_adapter_splitter_status_output_out_data; // rx_st_timing_adapter_splitter_status_output:out_data -> rx_st_status_output_delay:in0_data
+ wire rx_eth_lane_decoder_avalon_streaming_source_endofpacket; // rx_eth_lane_decoder:rxdata_src_eop -> rx_eth_pkt_backpressure_control:data_sink_eop
+ wire rx_eth_lane_decoder_avalon_streaming_source_valid; // rx_eth_lane_decoder:rxdata_src_valid -> rx_eth_pkt_backpressure_control:data_sink_valid
+ wire rx_eth_lane_decoder_avalon_streaming_source_startofpacket; // rx_eth_lane_decoder:rxdata_src_sop -> rx_eth_pkt_backpressure_control:data_sink_sop
+ wire [0:0] rx_eth_lane_decoder_avalon_streaming_source_error; // rx_eth_lane_decoder:rxdata_src_error -> rx_eth_pkt_backpressure_control:data_sink_error
+ wire [2:0] rx_eth_lane_decoder_avalon_streaming_source_empty; // rx_eth_lane_decoder:rxdata_src_empty -> rx_eth_pkt_backpressure_control:data_sink_empty
+ wire [63:0] rx_eth_lane_decoder_avalon_streaming_source_data; // rx_eth_lane_decoder:rxdata_src_data -> rx_eth_pkt_backpressure_control:data_sink_data
+ wire [1:0] rx_eth_link_fault_detection_link_fault_src_data; // rx_eth_link_fault_detection:link_fault_src_data -> txrx_timing_adapter_link_fault_status_rx:in_data
+ wire txrx_timing_adapter_link_fault_status_rx_out_valid; // txrx_timing_adapter_link_fault_status_rx:out_valid -> txrx_st_splitter_link_fault_status:in0_valid
+ wire [1:0] txrx_timing_adapter_link_fault_status_rx_out_data; // txrx_timing_adapter_link_fault_status_rx:out_data -> txrx_st_splitter_link_fault_status:in0_data
+ wire txrx_timing_adapter_link_fault_status_rx_out_ready; // txrx_st_splitter_link_fault_status:in0_ready -> txrx_timing_adapter_link_fault_status_rx:out_ready
+ wire txrx_st_splitter_link_fault_status_out0_valid; // txrx_st_splitter_link_fault_status:out0_valid -> txrx_timing_adapter_link_fault_status_export:in_valid
+ wire [1:0] txrx_st_splitter_link_fault_status_out0_data; // txrx_st_splitter_link_fault_status:out0_data -> txrx_timing_adapter_link_fault_status_export:in_data
+ wire txrx_st_splitter_link_fault_status_out0_ready; // txrx_timing_adapter_link_fault_status_export:in_ready -> txrx_st_splitter_link_fault_status:out0_ready
+ wire txrx_st_splitter_link_fault_status_out1_valid; // txrx_st_splitter_link_fault_status:out1_valid -> rxtx_dc_fifo_link_fault_status:in_valid
+ wire [1:0] txrx_st_splitter_link_fault_status_out1_data; // txrx_st_splitter_link_fault_status:out1_data -> rxtx_dc_fifo_link_fault_status:in_data
+ wire txrx_st_splitter_link_fault_status_out1_ready; // rxtx_dc_fifo_link_fault_status:in_ready -> txrx_st_splitter_link_fault_status:out1_ready
+ wire rxtx_dc_fifo_link_fault_status_out_valid; // rxtx_dc_fifo_link_fault_status:out_valid -> rxtx_timing_adapter_link_fault_status_tx:in_valid
+ wire [1:0] rxtx_dc_fifo_link_fault_status_out_data; // rxtx_dc_fifo_link_fault_status:out_data -> rxtx_timing_adapter_link_fault_status_tx:in_data
+ wire rxtx_dc_fifo_link_fault_status_out_ready; // rxtx_timing_adapter_link_fault_status_tx:in_ready -> rxtx_dc_fifo_link_fault_status:out_ready
+ wire [1:0] rxtx_timing_adapter_link_fault_status_tx_out_data; // rxtx_timing_adapter_link_fault_status_tx:out_data -> tx_eth_link_fault_generation:link_fault_sink_data
+ wire rx_eth_frame_status_merger_pauselen_src_valid; // rx_eth_frame_status_merger:pauselen_src_valid -> rxtx_timing_adapter_pauselen_rx:in_valid
+ wire [15:0] rx_eth_frame_status_merger_pauselen_src_data; // rx_eth_frame_status_merger:pauselen_src_data -> rxtx_timing_adapter_pauselen_rx:in_data
+ wire rxtx_timing_adapter_pauselen_rx_out_valid; // rxtx_timing_adapter_pauselen_rx:out_valid -> rxtx_dc_fifo_pauselen:in_valid
+ wire [15:0] rxtx_timing_adapter_pauselen_rx_out_data; // rxtx_timing_adapter_pauselen_rx:out_data -> rxtx_dc_fifo_pauselen:in_data
+ wire rxtx_timing_adapter_pauselen_rx_out_ready; // rxtx_dc_fifo_pauselen:in_ready -> rxtx_timing_adapter_pauselen_rx:out_ready
+ wire rxtx_dc_fifo_pauselen_out_valid; // rxtx_dc_fifo_pauselen:out_valid -> rxtx_timing_adapter_pauselen_tx:in_valid
+ wire [15:0] rxtx_dc_fifo_pauselen_out_data; // rxtx_dc_fifo_pauselen:out_data -> rxtx_timing_adapter_pauselen_tx:in_data
+ wire rxtx_dc_fifo_pauselen_out_ready; // rxtx_timing_adapter_pauselen_tx:in_ready -> rxtx_dc_fifo_pauselen:out_ready
+ wire rxtx_timing_adapter_pauselen_tx_out_valid; // rxtx_timing_adapter_pauselen_tx:out_valid -> tx_eth_pause_beat_conversion:pause_quanta_sink_valid
+ wire [15:0] rxtx_timing_adapter_pauselen_tx_out_data; // rxtx_timing_adapter_pauselen_tx:out_data -> tx_eth_pause_beat_conversion:pause_quanta_sink_data
+ wire merlin_master_translator_avalon_universal_master_0_waitrequest; // merlin_master_translator_avalon_universal_master_0_translator:av_waitrequest -> merlin_master_translator:uav_waitrequest
+ wire [2:0] merlin_master_translator_avalon_universal_master_0_burstcount; // merlin_master_translator:uav_burstcount -> merlin_master_translator_avalon_universal_master_0_translator:av_burstcount
+ wire [31:0] merlin_master_translator_avalon_universal_master_0_writedata; // merlin_master_translator:uav_writedata -> merlin_master_translator_avalon_universal_master_0_translator:av_writedata
+ wire [14:0] merlin_master_translator_avalon_universal_master_0_address; // merlin_master_translator:uav_address -> merlin_master_translator_avalon_universal_master_0_translator:av_address
+ wire merlin_master_translator_avalon_universal_master_0_lock; // merlin_master_translator:uav_lock -> merlin_master_translator_avalon_universal_master_0_translator:av_lock
+ wire merlin_master_translator_avalon_universal_master_0_write; // merlin_master_translator:uav_write -> merlin_master_translator_avalon_universal_master_0_translator:av_write
+ wire merlin_master_translator_avalon_universal_master_0_read; // merlin_master_translator:uav_read -> merlin_master_translator_avalon_universal_master_0_translator:av_read
+ wire [31:0] merlin_master_translator_avalon_universal_master_0_readdata; // merlin_master_translator_avalon_universal_master_0_translator:av_readdata -> merlin_master_translator:uav_readdata
+ wire merlin_master_translator_avalon_universal_master_0_debugaccess; // merlin_master_translator:uav_debugaccess -> merlin_master_translator_avalon_universal_master_0_translator:av_debugaccess
+ wire [3:0] merlin_master_translator_avalon_universal_master_0_byteenable; // merlin_master_translator:uav_byteenable -> merlin_master_translator_avalon_universal_master_0_translator:av_byteenable
+ wire merlin_master_translator_avalon_universal_master_0_readdatavalid; // merlin_master_translator_avalon_universal_master_0_translator:av_readdatavalid -> merlin_master_translator:uav_readdatavalid
+ wire tx_bridge_s0_translator_avalon_anti_slave_0_waitrequest; // tx_bridge:s0_waitrequest -> tx_bridge_s0_translator:av_waitrequest
+ wire tx_bridge_s0_translator_avalon_anti_slave_0_burstcount; // tx_bridge_s0_translator:av_burstcount -> tx_bridge:s0_burstcount
+ wire [31:0] tx_bridge_s0_translator_avalon_anti_slave_0_writedata; // tx_bridge_s0_translator:av_writedata -> tx_bridge:s0_writedata
+ wire [13:0] tx_bridge_s0_translator_avalon_anti_slave_0_address; // tx_bridge_s0_translator:av_address -> tx_bridge:s0_address
+ wire tx_bridge_s0_translator_avalon_anti_slave_0_write; // tx_bridge_s0_translator:av_write -> tx_bridge:s0_write
+ wire tx_bridge_s0_translator_avalon_anti_slave_0_read; // tx_bridge_s0_translator:av_read -> tx_bridge:s0_read
+ wire [31:0] tx_bridge_s0_translator_avalon_anti_slave_0_readdata; // tx_bridge:s0_readdata -> tx_bridge_s0_translator:av_readdata
+ wire tx_bridge_s0_translator_avalon_anti_slave_0_debugaccess; // tx_bridge_s0_translator:av_debugaccess -> tx_bridge:s0_debugaccess
+ wire tx_bridge_s0_translator_avalon_anti_slave_0_readdatavalid; // tx_bridge:s0_readdatavalid -> tx_bridge_s0_translator:av_readdatavalid
+ wire [3:0] tx_bridge_s0_translator_avalon_anti_slave_0_byteenable; // tx_bridge_s0_translator:av_byteenable -> tx_bridge:s0_byteenable
+ wire rx_bridge_s0_translator_avalon_anti_slave_0_waitrequest; // rx_bridge:s0_waitrequest -> rx_bridge_s0_translator:av_waitrequest
+ wire rx_bridge_s0_translator_avalon_anti_slave_0_burstcount; // rx_bridge_s0_translator:av_burstcount -> rx_bridge:s0_burstcount
+ wire [31:0] rx_bridge_s0_translator_avalon_anti_slave_0_writedata; // rx_bridge_s0_translator:av_writedata -> rx_bridge:s0_writedata
+ wire [13:0] rx_bridge_s0_translator_avalon_anti_slave_0_address; // rx_bridge_s0_translator:av_address -> rx_bridge:s0_address
+ wire rx_bridge_s0_translator_avalon_anti_slave_0_write; // rx_bridge_s0_translator:av_write -> rx_bridge:s0_write
+ wire rx_bridge_s0_translator_avalon_anti_slave_0_read; // rx_bridge_s0_translator:av_read -> rx_bridge:s0_read
+ wire [31:0] rx_bridge_s0_translator_avalon_anti_slave_0_readdata; // rx_bridge:s0_readdata -> rx_bridge_s0_translator:av_readdata
+ wire rx_bridge_s0_translator_avalon_anti_slave_0_debugaccess; // rx_bridge_s0_translator:av_debugaccess -> rx_bridge:s0_debugaccess
+ wire rx_bridge_s0_translator_avalon_anti_slave_0_readdatavalid; // rx_bridge:s0_readdatavalid -> rx_bridge_s0_translator:av_readdatavalid
+ wire [3:0] rx_bridge_s0_translator_avalon_anti_slave_0_byteenable; // rx_bridge_s0_translator:av_byteenable -> rx_bridge:s0_byteenable
+ wire [0:0] tx_bridge_m0_burstcount; // tx_bridge:m0_burstcount -> tx_bridge_m0_translator:av_burstcount
+ wire tx_bridge_m0_waitrequest; // tx_bridge_m0_translator:av_waitrequest -> tx_bridge:m0_waitrequest
+ wire [13:0] tx_bridge_m0_address; // tx_bridge:m0_address -> tx_bridge_m0_translator:av_address
+ wire [31:0] tx_bridge_m0_writedata; // tx_bridge:m0_writedata -> tx_bridge_m0_translator:av_writedata
+ wire tx_bridge_m0_write; // tx_bridge:m0_write -> tx_bridge_m0_translator:av_write
+ wire tx_bridge_m0_read; // tx_bridge:m0_read -> tx_bridge_m0_translator:av_read
+ wire [31:0] tx_bridge_m0_readdata; // tx_bridge_m0_translator:av_readdata -> tx_bridge:m0_readdata
+ wire tx_bridge_m0_debugaccess; // tx_bridge:m0_debugaccess -> tx_bridge_m0_translator:av_debugaccess
+ wire [3:0] tx_bridge_m0_byteenable; // tx_bridge:m0_byteenable -> tx_bridge_m0_translator:av_byteenable
+ wire tx_bridge_m0_readdatavalid; // tx_bridge_m0_translator:av_readdatavalid -> tx_bridge:m0_readdatavalid
+ wire [31:0] tx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_writedata; // tx_eth_pkt_backpressure_control_csr_translator:av_writedata -> tx_eth_pkt_backpressure_control:csr_writedata
+ wire tx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_address; // tx_eth_pkt_backpressure_control_csr_translator:av_address -> tx_eth_pkt_backpressure_control:csr_address
+ wire tx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_write; // tx_eth_pkt_backpressure_control_csr_translator:av_write -> tx_eth_pkt_backpressure_control:csr_write
+ wire tx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_read; // tx_eth_pkt_backpressure_control_csr_translator:av_read -> tx_eth_pkt_backpressure_control:csr_read
+ wire [31:0] tx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_readdata; // tx_eth_pkt_backpressure_control:csr_readdata -> tx_eth_pkt_backpressure_control_csr_translator:av_readdata
+ wire [31:0] tx_eth_pad_inserter_csr_translator_avalon_anti_slave_0_writedata; // tx_eth_pad_inserter_csr_translator:av_writedata -> tx_eth_pad_inserter:csr_writedata
+ wire tx_eth_pad_inserter_csr_translator_avalon_anti_slave_0_address; // tx_eth_pad_inserter_csr_translator:av_address -> tx_eth_pad_inserter:csr_address
+ wire tx_eth_pad_inserter_csr_translator_avalon_anti_slave_0_write; // tx_eth_pad_inserter_csr_translator:av_write -> tx_eth_pad_inserter:csr_write
+ wire tx_eth_pad_inserter_csr_translator_avalon_anti_slave_0_read; // tx_eth_pad_inserter_csr_translator:av_read -> tx_eth_pad_inserter:csr_read
+ wire [31:0] tx_eth_pad_inserter_csr_translator_avalon_anti_slave_0_readdata; // tx_eth_pad_inserter:csr_readdata -> tx_eth_pad_inserter_csr_translator:av_readdata
+ wire [31:0] tx_eth_crc_inserter_csr_translator_avalon_anti_slave_0_writedata; // tx_eth_crc_inserter_csr_translator:av_writedata -> tx_eth_crc_inserter:csr_writedata
+ wire tx_eth_crc_inserter_csr_translator_avalon_anti_slave_0_address; // tx_eth_crc_inserter_csr_translator:av_address -> tx_eth_crc_inserter:csr_address
+ wire tx_eth_crc_inserter_csr_translator_avalon_anti_slave_0_write; // tx_eth_crc_inserter_csr_translator:av_write -> tx_eth_crc_inserter:csr_write
+ wire tx_eth_crc_inserter_csr_translator_avalon_anti_slave_0_read; // tx_eth_crc_inserter_csr_translator:av_read -> tx_eth_crc_inserter:csr_read
+ wire [31:0] tx_eth_crc_inserter_csr_translator_avalon_anti_slave_0_readdata; // tx_eth_crc_inserter:csr_readdata -> tx_eth_crc_inserter_csr_translator:av_readdata
+ wire [31:0] tx_eth_pause_ctrl_gen_csr_translator_avalon_anti_slave_0_writedata; // tx_eth_pause_ctrl_gen_csr_translator:av_writedata -> tx_eth_pause_ctrl_gen:csr_writedata
+ wire [1:0] tx_eth_pause_ctrl_gen_csr_translator_avalon_anti_slave_0_address; // tx_eth_pause_ctrl_gen_csr_translator:av_address -> tx_eth_pause_ctrl_gen:csr_address
+ wire tx_eth_pause_ctrl_gen_csr_translator_avalon_anti_slave_0_write; // tx_eth_pause_ctrl_gen_csr_translator:av_write -> tx_eth_pause_ctrl_gen:csr_write
+ wire tx_eth_pause_ctrl_gen_csr_translator_avalon_anti_slave_0_read; // tx_eth_pause_ctrl_gen_csr_translator:av_read -> tx_eth_pause_ctrl_gen:csr_read
+ wire [31:0] tx_eth_pause_ctrl_gen_csr_translator_avalon_anti_slave_0_readdata; // tx_eth_pause_ctrl_gen:csr_readdata -> tx_eth_pause_ctrl_gen_csr_translator:av_readdata
+ wire [31:0] tx_eth_address_inserter_csr_translator_avalon_anti_slave_0_writedata; // tx_eth_address_inserter_csr_translator:av_writedata -> tx_eth_address_inserter:csr_writedata
+ wire [1:0] tx_eth_address_inserter_csr_translator_avalon_anti_slave_0_address; // tx_eth_address_inserter_csr_translator:av_address -> tx_eth_address_inserter:csr_address
+ wire tx_eth_address_inserter_csr_translator_avalon_anti_slave_0_write; // tx_eth_address_inserter_csr_translator:av_write -> tx_eth_address_inserter:csr_write
+ wire tx_eth_address_inserter_csr_translator_avalon_anti_slave_0_read; // tx_eth_address_inserter_csr_translator:av_read -> tx_eth_address_inserter:csr_read
+ wire [31:0] tx_eth_address_inserter_csr_translator_avalon_anti_slave_0_readdata; // tx_eth_address_inserter:csr_readdata -> tx_eth_address_inserter_csr_translator:av_readdata
+ wire tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_anti_slave_0_address; // tx_eth_packet_underflow_control_avalon_slave_0_translator:av_address -> tx_eth_packet_underflow_control:csr_address
+ wire tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_anti_slave_0_read; // tx_eth_packet_underflow_control_avalon_slave_0_translator:av_read -> tx_eth_packet_underflow_control:csr_read
+ wire [31:0] tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_anti_slave_0_readdata; // tx_eth_packet_underflow_control:csr_readdata -> tx_eth_packet_underflow_control_avalon_slave_0_translator:av_readdata
+ wire [31:0] tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_writedata; // tx_eth_frame_decoder_avalom_mm_csr_translator:av_writedata -> tx_eth_frame_decoder:csr_writedata
+ wire [4:0] tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_address; // tx_eth_frame_decoder_avalom_mm_csr_translator:av_address -> tx_eth_frame_decoder:csr_address
+ wire tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_write; // tx_eth_frame_decoder_avalom_mm_csr_translator:av_write -> tx_eth_frame_decoder:csr_write
+ wire tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_read; // tx_eth_frame_decoder_avalom_mm_csr_translator:av_read -> tx_eth_frame_decoder:csr_read
+ wire [31:0] tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_readdata; // tx_eth_frame_decoder:csr_readdata -> tx_eth_frame_decoder_avalom_mm_csr_translator:av_readdata
+ wire [31:0] tx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_writedata; // tx_eth_statistics_collector_csr_translator:av_writedata -> tx_eth_statistics_collector:csr_writedata
+ wire [5:0] tx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_address; // tx_eth_statistics_collector_csr_translator:av_address -> tx_eth_statistics_collector:csr_address
+ wire tx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_write; // tx_eth_statistics_collector_csr_translator:av_write -> tx_eth_statistics_collector:csr_write
+ wire tx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_read; // tx_eth_statistics_collector_csr_translator:av_read -> tx_eth_statistics_collector:csr_read
+ wire [31:0] tx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_readdata; // tx_eth_statistics_collector:csr_readdata -> tx_eth_statistics_collector_csr_translator:av_readdata
+ wire [0:0] rx_bridge_m0_burstcount; // rx_bridge:m0_burstcount -> rx_bridge_m0_translator:av_burstcount
+ wire rx_bridge_m0_waitrequest; // rx_bridge_m0_translator:av_waitrequest -> rx_bridge:m0_waitrequest
+ wire [13:0] rx_bridge_m0_address; // rx_bridge:m0_address -> rx_bridge_m0_translator:av_address
+ wire [31:0] rx_bridge_m0_writedata; // rx_bridge:m0_writedata -> rx_bridge_m0_translator:av_writedata
+ wire rx_bridge_m0_write; // rx_bridge:m0_write -> rx_bridge_m0_translator:av_write
+ wire rx_bridge_m0_read; // rx_bridge:m0_read -> rx_bridge_m0_translator:av_read
+ wire [31:0] rx_bridge_m0_readdata; // rx_bridge_m0_translator:av_readdata -> rx_bridge:m0_readdata
+ wire rx_bridge_m0_debugaccess; // rx_bridge:m0_debugaccess -> rx_bridge_m0_translator:av_debugaccess
+ wire [3:0] rx_bridge_m0_byteenable; // rx_bridge:m0_byteenable -> rx_bridge_m0_translator:av_byteenable
+ wire rx_bridge_m0_readdatavalid; // rx_bridge_m0_translator:av_readdatavalid -> rx_bridge:m0_readdatavalid
+ wire [31:0] rx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_writedata; // rx_eth_pkt_backpressure_control_csr_translator:av_writedata -> rx_eth_pkt_backpressure_control:csr_writedata
+ wire rx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_address; // rx_eth_pkt_backpressure_control_csr_translator:av_address -> rx_eth_pkt_backpressure_control:csr_address
+ wire rx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_write; // rx_eth_pkt_backpressure_control_csr_translator:av_write -> rx_eth_pkt_backpressure_control:csr_write
+ wire rx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_read; // rx_eth_pkt_backpressure_control_csr_translator:av_read -> rx_eth_pkt_backpressure_control:csr_read
+ wire [31:0] rx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_readdata; // rx_eth_pkt_backpressure_control:csr_readdata -> rx_eth_pkt_backpressure_control_csr_translator:av_readdata
+ wire [31:0] rx_eth_crc_pad_rem_csr_translator_avalon_anti_slave_0_writedata; // rx_eth_crc_pad_rem_csr_translator:av_writedata -> rx_eth_crc_pad_rem:csr_writedata
+ wire [1:0] rx_eth_crc_pad_rem_csr_translator_avalon_anti_slave_0_address; // rx_eth_crc_pad_rem_csr_translator:av_address -> rx_eth_crc_pad_rem:csr_address
+ wire rx_eth_crc_pad_rem_csr_translator_avalon_anti_slave_0_write; // rx_eth_crc_pad_rem_csr_translator:av_write -> rx_eth_crc_pad_rem:csr_write
+ wire rx_eth_crc_pad_rem_csr_translator_avalon_anti_slave_0_read; // rx_eth_crc_pad_rem_csr_translator:av_read -> rx_eth_crc_pad_rem:csr_read
+ wire [31:0] rx_eth_crc_pad_rem_csr_translator_avalon_anti_slave_0_readdata; // rx_eth_crc_pad_rem:csr_readdata -> rx_eth_crc_pad_rem_csr_translator:av_readdata
+ wire [31:0] rx_eth_crc_checker_csr_translator_avalon_anti_slave_0_writedata; // rx_eth_crc_checker_csr_translator:av_writedata -> rx_eth_crc_checker:csr_writedata
+ wire rx_eth_crc_checker_csr_translator_avalon_anti_slave_0_address; // rx_eth_crc_checker_csr_translator:av_address -> rx_eth_crc_checker:csr_address
+ wire rx_eth_crc_checker_csr_translator_avalon_anti_slave_0_write; // rx_eth_crc_checker_csr_translator:av_write -> rx_eth_crc_checker:csr_write
+ wire rx_eth_crc_checker_csr_translator_avalon_anti_slave_0_read; // rx_eth_crc_checker_csr_translator:av_read -> rx_eth_crc_checker:csr_read
+ wire [31:0] rx_eth_crc_checker_csr_translator_avalon_anti_slave_0_readdata; // rx_eth_crc_checker:csr_readdata -> rx_eth_crc_checker_csr_translator:av_readdata
+ wire [31:0] rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_writedata; // rx_eth_frame_decoder_avalom_mm_csr_translator:av_writedata -> rx_eth_frame_decoder:csr_writedata
+ wire [4:0] rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_address; // rx_eth_frame_decoder_avalom_mm_csr_translator:av_address -> rx_eth_frame_decoder:csr_address
+ wire rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_write; // rx_eth_frame_decoder_avalom_mm_csr_translator:av_write -> rx_eth_frame_decoder:csr_write
+ wire rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_read; // rx_eth_frame_decoder_avalom_mm_csr_translator:av_read -> rx_eth_frame_decoder:csr_read
+ wire [31:0] rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_readdata; // rx_eth_frame_decoder:csr_readdata -> rx_eth_frame_decoder_avalom_mm_csr_translator:av_readdata
+ wire [1:0] rx_eth_packet_overflow_control_csr_translator_avalon_anti_slave_0_address; // rx_eth_packet_overflow_control_csr_translator:av_address -> rx_eth_packet_overflow_control:csr_address
+ wire rx_eth_packet_overflow_control_csr_translator_avalon_anti_slave_0_read; // rx_eth_packet_overflow_control_csr_translator:av_read -> rx_eth_packet_overflow_control:csr_read
+ wire [31:0] rx_eth_packet_overflow_control_csr_translator_avalon_anti_slave_0_readdata; // rx_eth_packet_overflow_control:csr_readdata -> rx_eth_packet_overflow_control_csr_translator:av_readdata
+ wire [31:0] rx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_writedata; // rx_eth_statistics_collector_csr_translator:av_writedata -> rx_eth_statistics_collector:csr_writedata
+ wire [5:0] rx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_address; // rx_eth_statistics_collector_csr_translator:av_address -> rx_eth_statistics_collector:csr_address
+ wire rx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_write; // rx_eth_statistics_collector_csr_translator:av_write -> rx_eth_statistics_collector:csr_write
+ wire rx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_read; // rx_eth_statistics_collector_csr_translator:av_read -> rx_eth_statistics_collector:csr_read
+ wire [31:0] rx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_readdata; // rx_eth_statistics_collector:csr_readdata -> rx_eth_statistics_collector_csr_translator:av_readdata
+ wire [31:0] rx_eth_lane_decoder_csr_translator_avalon_anti_slave_0_writedata; // rx_eth_lane_decoder_csr_translator:av_writedata -> rx_eth_lane_decoder:csr_writedata
+ wire rx_eth_lane_decoder_csr_translator_avalon_anti_slave_0_address; // rx_eth_lane_decoder_csr_translator:av_address -> rx_eth_lane_decoder:csr_address
+ wire rx_eth_lane_decoder_csr_translator_avalon_anti_slave_0_write; // rx_eth_lane_decoder_csr_translator:av_write -> rx_eth_lane_decoder:csr_write
+ wire rx_eth_lane_decoder_csr_translator_avalon_anti_slave_0_read; // rx_eth_lane_decoder_csr_translator:av_read -> rx_eth_lane_decoder:csr_read
+ wire [31:0] rx_eth_lane_decoder_csr_translator_avalon_anti_slave_0_readdata; // rx_eth_lane_decoder:csr_readdata -> rx_eth_lane_decoder_csr_translator:av_readdata
+ wire rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest; // rx_bridge_s0_translator:uav_waitrequest -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ wire [2:0] rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount; // rx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_burstcount -> rx_bridge_s0_translator:uav_burstcount
+ wire [31:0] rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_writedata; // rx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_writedata -> rx_bridge_s0_translator:uav_writedata
+ wire [14:0] rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_address; // rx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_address -> rx_bridge_s0_translator:uav_address
+ wire rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_write; // rx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_write -> rx_bridge_s0_translator:uav_write
+ wire rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_lock; // rx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_lock -> rx_bridge_s0_translator:uav_lock
+ wire rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read; // rx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_read -> rx_bridge_s0_translator:uav_read
+ wire [31:0] rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdata; // rx_bridge_s0_translator:uav_readdata -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_readdata
+ wire rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // rx_bridge_s0_translator:uav_readdatavalid -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ wire rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess; // rx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> rx_bridge_s0_translator:uav_debugaccess
+ wire [3:0] rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_byteenable; // rx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_byteenable -> rx_bridge_s0_translator:uav_byteenable
+ wire rx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // rx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ wire rx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_valid; // rx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_source_valid -> rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ wire rx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // rx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ wire [66:0] rx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_data; // rx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_source_data -> rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ wire rx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_ready; // rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_source_ready
+ wire rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ wire rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ wire rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ wire [66:0] rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_sink_data
+ wire rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // rx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ wire rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // rx_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
+ wire [31:0] rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // rx_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
+ wire rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ wire rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid; // rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ wire [31:0] rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data; // rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ wire rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready; // rx_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
+ wire tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest; // tx_bridge_s0_translator:uav_waitrequest -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ wire [2:0] tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount; // tx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_burstcount -> tx_bridge_s0_translator:uav_burstcount
+ wire [31:0] tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_writedata; // tx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_writedata -> tx_bridge_s0_translator:uav_writedata
+ wire [14:0] tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_address; // tx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_address -> tx_bridge_s0_translator:uav_address
+ wire tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_write; // tx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_write -> tx_bridge_s0_translator:uav_write
+ wire tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_lock; // tx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_lock -> tx_bridge_s0_translator:uav_lock
+ wire tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read; // tx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_read -> tx_bridge_s0_translator:uav_read
+ wire [31:0] tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdata; // tx_bridge_s0_translator:uav_readdata -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_readdata
+ wire tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // tx_bridge_s0_translator:uav_readdatavalid -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ wire tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess; // tx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> tx_bridge_s0_translator:uav_debugaccess
+ wire [3:0] tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_byteenable; // tx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_byteenable -> tx_bridge_s0_translator:uav_byteenable
+ wire tx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // tx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ wire tx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_valid; // tx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_source_valid -> tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ wire tx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // tx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ wire [66:0] tx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_data; // tx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_source_data -> tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ wire tx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_ready; // tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_source_ready
+ wire tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ wire tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ wire tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ wire [66:0] tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_sink_data
+ wire tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // tx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ wire tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // tx_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
+ wire [31:0] tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // tx_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
+ wire tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ wire tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid; // tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ wire [31:0] tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data; // tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ wire tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready; // tx_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
+ wire merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_waitrequest; // merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:av_waitrequest -> merlin_master_translator_avalon_universal_master_0_translator:uav_waitrequest
+ wire [2:0] merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_burstcount; // merlin_master_translator_avalon_universal_master_0_translator:uav_burstcount -> merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:av_burstcount
+ wire [31:0] merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_writedata; // merlin_master_translator_avalon_universal_master_0_translator:uav_writedata -> merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:av_writedata
+ wire [14:0] merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_address; // merlin_master_translator_avalon_universal_master_0_translator:uav_address -> merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:av_address
+ wire merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_lock; // merlin_master_translator_avalon_universal_master_0_translator:uav_lock -> merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:av_lock
+ wire merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_write; // merlin_master_translator_avalon_universal_master_0_translator:uav_write -> merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:av_write
+ wire merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_read; // merlin_master_translator_avalon_universal_master_0_translator:uav_read -> merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:av_read
+ wire [31:0] merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_readdata; // merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:av_readdata -> merlin_master_translator_avalon_universal_master_0_translator:uav_readdata
+ wire merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_debugaccess; // merlin_master_translator_avalon_universal_master_0_translator:uav_debugaccess -> merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:av_debugaccess
+ wire [3:0] merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_byteenable; // merlin_master_translator_avalon_universal_master_0_translator:uav_byteenable -> merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:av_byteenable
+ wire merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_readdatavalid; // merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:av_readdatavalid -> merlin_master_translator_avalon_universal_master_0_translator:uav_readdatavalid
+ wire tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest; // tx_eth_pkt_backpressure_control_csr_translator:uav_waitrequest -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ wire [2:0] tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount; // tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_burstcount -> tx_eth_pkt_backpressure_control_csr_translator:uav_burstcount
+ wire [31:0] tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_writedata; // tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_writedata -> tx_eth_pkt_backpressure_control_csr_translator:uav_writedata
+ wire [13:0] tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_address; // tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_address -> tx_eth_pkt_backpressure_control_csr_translator:uav_address
+ wire tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_write; // tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_write -> tx_eth_pkt_backpressure_control_csr_translator:uav_write
+ wire tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_lock; // tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_lock -> tx_eth_pkt_backpressure_control_csr_translator:uav_lock
+ wire tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_read; // tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_read -> tx_eth_pkt_backpressure_control_csr_translator:uav_read
+ wire [31:0] tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_readdata; // tx_eth_pkt_backpressure_control_csr_translator:uav_readdata -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_readdata
+ wire tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // tx_eth_pkt_backpressure_control_csr_translator:uav_readdatavalid -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ wire tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess; // tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_debugaccess -> tx_eth_pkt_backpressure_control_csr_translator:uav_debugaccess
+ wire [3:0] tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_byteenable; // tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_byteenable -> tx_eth_pkt_backpressure_control_csr_translator:uav_byteenable
+ wire tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ wire tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_valid; // tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_source_valid -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ wire tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ wire [69:0] tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_data; // tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_source_data -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ wire tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_ready; // tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_source_ready
+ wire tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ wire tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ wire tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ wire [69:0] tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_sink_data
+ wire tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_sink_ready -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ wire tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ wire [31:0] tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ wire tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ wire tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest; // tx_eth_pause_ctrl_gen_csr_translator:uav_waitrequest -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ wire [2:0] tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_burstcount; // tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:m0_burstcount -> tx_eth_pause_ctrl_gen_csr_translator:uav_burstcount
+ wire [31:0] tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_writedata; // tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:m0_writedata -> tx_eth_pause_ctrl_gen_csr_translator:uav_writedata
+ wire [13:0] tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_address; // tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:m0_address -> tx_eth_pause_ctrl_gen_csr_translator:uav_address
+ wire tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_write; // tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:m0_write -> tx_eth_pause_ctrl_gen_csr_translator:uav_write
+ wire tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_lock; // tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:m0_lock -> tx_eth_pause_ctrl_gen_csr_translator:uav_lock
+ wire tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_read; // tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:m0_read -> tx_eth_pause_ctrl_gen_csr_translator:uav_read
+ wire [31:0] tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_readdata; // tx_eth_pause_ctrl_gen_csr_translator:uav_readdata -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:m0_readdata
+ wire tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // tx_eth_pause_ctrl_gen_csr_translator:uav_readdatavalid -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ wire tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess; // tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:m0_debugaccess -> tx_eth_pause_ctrl_gen_csr_translator:uav_debugaccess
+ wire [3:0] tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_byteenable; // tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:m0_byteenable -> tx_eth_pause_ctrl_gen_csr_translator:uav_byteenable
+ wire tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ wire tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rf_source_valid; // tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rf_source_valid -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ wire tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ wire [69:0] tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rf_source_data; // tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rf_source_data -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ wire tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rf_source_ready; // tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rf_source_ready
+ wire tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ wire tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ wire tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ wire [69:0] tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rf_sink_data
+ wire tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rf_sink_ready -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ wire tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ wire [31:0] tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ wire tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ wire tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest; // tx_eth_frame_decoder_avalom_mm_csr_translator:uav_waitrequest -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ wire [2:0] tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount; // tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_burstcount -> tx_eth_frame_decoder_avalom_mm_csr_translator:uav_burstcount
+ wire [31:0] tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_writedata; // tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_writedata -> tx_eth_frame_decoder_avalom_mm_csr_translator:uav_writedata
+ wire [13:0] tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_address; // tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_address -> tx_eth_frame_decoder_avalom_mm_csr_translator:uav_address
+ wire tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_write; // tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_write -> tx_eth_frame_decoder_avalom_mm_csr_translator:uav_write
+ wire tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_lock; // tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_lock -> tx_eth_frame_decoder_avalom_mm_csr_translator:uav_lock
+ wire tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_read; // tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_read -> tx_eth_frame_decoder_avalom_mm_csr_translator:uav_read
+ wire [31:0] tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_readdata; // tx_eth_frame_decoder_avalom_mm_csr_translator:uav_readdata -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_readdata
+ wire tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // tx_eth_frame_decoder_avalom_mm_csr_translator:uav_readdatavalid -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ wire tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess; // tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_debugaccess -> tx_eth_frame_decoder_avalom_mm_csr_translator:uav_debugaccess
+ wire [3:0] tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_byteenable; // tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_byteenable -> tx_eth_frame_decoder_avalom_mm_csr_translator:uav_byteenable
+ wire tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ wire tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_valid; // tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_source_valid -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ wire tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ wire [69:0] tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_data; // tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_source_data -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ wire tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_ready; // tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_source_ready
+ wire tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ wire tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ wire tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ wire [69:0] tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_sink_data
+ wire tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_sink_ready -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ wire tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ wire [31:0] tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ wire tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ wire tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest; // tx_eth_statistics_collector_csr_translator:uav_waitrequest -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ wire [2:0] tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount; // tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_burstcount -> tx_eth_statistics_collector_csr_translator:uav_burstcount
+ wire [31:0] tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_writedata; // tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_writedata -> tx_eth_statistics_collector_csr_translator:uav_writedata
+ wire [13:0] tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_address; // tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_address -> tx_eth_statistics_collector_csr_translator:uav_address
+ wire tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_write; // tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_write -> tx_eth_statistics_collector_csr_translator:uav_write
+ wire tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_lock; // tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_lock -> tx_eth_statistics_collector_csr_translator:uav_lock
+ wire tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_read; // tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_read -> tx_eth_statistics_collector_csr_translator:uav_read
+ wire [31:0] tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_readdata; // tx_eth_statistics_collector_csr_translator:uav_readdata -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_readdata
+ wire tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // tx_eth_statistics_collector_csr_translator:uav_readdatavalid -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ wire tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess; // tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_debugaccess -> tx_eth_statistics_collector_csr_translator:uav_debugaccess
+ wire [3:0] tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_byteenable; // tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_byteenable -> tx_eth_statistics_collector_csr_translator:uav_byteenable
+ wire tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ wire tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_valid; // tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_source_valid -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ wire tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ wire [69:0] tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_data; // tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_source_data -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ wire tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_ready; // tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_source_ready
+ wire tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ wire tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ wire tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ wire [69:0] tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_sink_data
+ wire tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_sink_ready -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ wire tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ wire [31:0] tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ wire tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ wire tx_bridge_m0_translator_avalon_universal_master_0_waitrequest; // tx_bridge_m0_translator_avalon_universal_master_0_agent:av_waitrequest -> tx_bridge_m0_translator:uav_waitrequest
+ wire [2:0] tx_bridge_m0_translator_avalon_universal_master_0_burstcount; // tx_bridge_m0_translator:uav_burstcount -> tx_bridge_m0_translator_avalon_universal_master_0_agent:av_burstcount
+ wire [31:0] tx_bridge_m0_translator_avalon_universal_master_0_writedata; // tx_bridge_m0_translator:uav_writedata -> tx_bridge_m0_translator_avalon_universal_master_0_agent:av_writedata
+ wire [13:0] tx_bridge_m0_translator_avalon_universal_master_0_address; // tx_bridge_m0_translator:uav_address -> tx_bridge_m0_translator_avalon_universal_master_0_agent:av_address
+ wire tx_bridge_m0_translator_avalon_universal_master_0_lock; // tx_bridge_m0_translator:uav_lock -> tx_bridge_m0_translator_avalon_universal_master_0_agent:av_lock
+ wire tx_bridge_m0_translator_avalon_universal_master_0_write; // tx_bridge_m0_translator:uav_write -> tx_bridge_m0_translator_avalon_universal_master_0_agent:av_write
+ wire tx_bridge_m0_translator_avalon_universal_master_0_read; // tx_bridge_m0_translator:uav_read -> tx_bridge_m0_translator_avalon_universal_master_0_agent:av_read
+ wire [31:0] tx_bridge_m0_translator_avalon_universal_master_0_readdata; // tx_bridge_m0_translator_avalon_universal_master_0_agent:av_readdata -> tx_bridge_m0_translator:uav_readdata
+ wire tx_bridge_m0_translator_avalon_universal_master_0_debugaccess; // tx_bridge_m0_translator:uav_debugaccess -> tx_bridge_m0_translator_avalon_universal_master_0_agent:av_debugaccess
+ wire [3:0] tx_bridge_m0_translator_avalon_universal_master_0_byteenable; // tx_bridge_m0_translator:uav_byteenable -> tx_bridge_m0_translator_avalon_universal_master_0_agent:av_byteenable
+ wire tx_bridge_m0_translator_avalon_universal_master_0_readdatavalid; // tx_bridge_m0_translator_avalon_universal_master_0_agent:av_readdatavalid -> tx_bridge_m0_translator:uav_readdatavalid
+ wire tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest; // tx_eth_packet_underflow_control_avalon_slave_0_translator:uav_waitrequest -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ wire [2:0] tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount; // tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> tx_eth_packet_underflow_control_avalon_slave_0_translator:uav_burstcount
+ wire [31:0] tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata; // tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> tx_eth_packet_underflow_control_avalon_slave_0_translator:uav_writedata
+ wire [13:0] tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address; // tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> tx_eth_packet_underflow_control_avalon_slave_0_translator:uav_address
+ wire tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write; // tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> tx_eth_packet_underflow_control_avalon_slave_0_translator:uav_write
+ wire tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock; // tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> tx_eth_packet_underflow_control_avalon_slave_0_translator:uav_lock
+ wire tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read; // tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> tx_eth_packet_underflow_control_avalon_slave_0_translator:uav_read
+ wire [31:0] tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata; // tx_eth_packet_underflow_control_avalon_slave_0_translator:uav_readdata -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
+ wire tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // tx_eth_packet_underflow_control_avalon_slave_0_translator:uav_readdatavalid -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ wire tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess; // tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> tx_eth_packet_underflow_control_avalon_slave_0_translator:uav_debugaccess
+ wire [3:0] tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable; // tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> tx_eth_packet_underflow_control_avalon_slave_0_translator:uav_byteenable
+ wire tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ wire tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid; // tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ wire tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ wire [69:0] tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data; // tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ wire tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready; // tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
+ wire tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ wire tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ wire tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ wire [69:0] tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
+ wire tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ wire tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ wire [31:0] tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ wire tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ wire tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest; // tx_eth_address_inserter_csr_translator:uav_waitrequest -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ wire [2:0] tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount; // tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:m0_burstcount -> tx_eth_address_inserter_csr_translator:uav_burstcount
+ wire [31:0] tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_writedata; // tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:m0_writedata -> tx_eth_address_inserter_csr_translator:uav_writedata
+ wire [13:0] tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_address; // tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:m0_address -> tx_eth_address_inserter_csr_translator:uav_address
+ wire tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_write; // tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:m0_write -> tx_eth_address_inserter_csr_translator:uav_write
+ wire tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_lock; // tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:m0_lock -> tx_eth_address_inserter_csr_translator:uav_lock
+ wire tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read; // tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:m0_read -> tx_eth_address_inserter_csr_translator:uav_read
+ wire [31:0] tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdata; // tx_eth_address_inserter_csr_translator:uav_readdata -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:m0_readdata
+ wire tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // tx_eth_address_inserter_csr_translator:uav_readdatavalid -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ wire tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess; // tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:m0_debugaccess -> tx_eth_address_inserter_csr_translator:uav_debugaccess
+ wire [3:0] tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_byteenable; // tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:m0_byteenable -> tx_eth_address_inserter_csr_translator:uav_byteenable
+ wire tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ wire tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_valid; // tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rf_source_valid -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ wire tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ wire [69:0] tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_data; // tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rf_source_data -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ wire tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_ready; // tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rf_source_ready
+ wire tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ wire tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ wire tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ wire [69:0] tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rf_sink_data
+ wire tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rf_sink_ready -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ wire tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ wire [31:0] tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ wire tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ wire tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest; // tx_eth_pad_inserter_csr_translator:uav_waitrequest -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ wire [2:0] tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount; // tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:m0_burstcount -> tx_eth_pad_inserter_csr_translator:uav_burstcount
+ wire [31:0] tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_writedata; // tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:m0_writedata -> tx_eth_pad_inserter_csr_translator:uav_writedata
+ wire [13:0] tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_address; // tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:m0_address -> tx_eth_pad_inserter_csr_translator:uav_address
+ wire tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_write; // tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:m0_write -> tx_eth_pad_inserter_csr_translator:uav_write
+ wire tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_lock; // tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:m0_lock -> tx_eth_pad_inserter_csr_translator:uav_lock
+ wire tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read; // tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:m0_read -> tx_eth_pad_inserter_csr_translator:uav_read
+ wire [31:0] tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdata; // tx_eth_pad_inserter_csr_translator:uav_readdata -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:m0_readdata
+ wire tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // tx_eth_pad_inserter_csr_translator:uav_readdatavalid -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ wire tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess; // tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:m0_debugaccess -> tx_eth_pad_inserter_csr_translator:uav_debugaccess
+ wire [3:0] tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_byteenable; // tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:m0_byteenable -> tx_eth_pad_inserter_csr_translator:uav_byteenable
+ wire tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ wire tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_valid; // tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rf_source_valid -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ wire tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ wire [69:0] tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_data; // tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rf_source_data -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ wire tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_ready; // tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rf_source_ready
+ wire tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ wire tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ wire tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ wire [69:0] tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rf_sink_data
+ wire tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rf_sink_ready -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ wire tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ wire [31:0] tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ wire tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ wire tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest; // tx_eth_crc_inserter_csr_translator:uav_waitrequest -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ wire [2:0] tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount; // tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:m0_burstcount -> tx_eth_crc_inserter_csr_translator:uav_burstcount
+ wire [31:0] tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_writedata; // tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:m0_writedata -> tx_eth_crc_inserter_csr_translator:uav_writedata
+ wire [13:0] tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_address; // tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:m0_address -> tx_eth_crc_inserter_csr_translator:uav_address
+ wire tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_write; // tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:m0_write -> tx_eth_crc_inserter_csr_translator:uav_write
+ wire tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_lock; // tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:m0_lock -> tx_eth_crc_inserter_csr_translator:uav_lock
+ wire tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read; // tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:m0_read -> tx_eth_crc_inserter_csr_translator:uav_read
+ wire [31:0] tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdata; // tx_eth_crc_inserter_csr_translator:uav_readdata -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:m0_readdata
+ wire tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // tx_eth_crc_inserter_csr_translator:uav_readdatavalid -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ wire tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess; // tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:m0_debugaccess -> tx_eth_crc_inserter_csr_translator:uav_debugaccess
+ wire [3:0] tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_byteenable; // tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:m0_byteenable -> tx_eth_crc_inserter_csr_translator:uav_byteenable
+ wire tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ wire tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_valid; // tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rf_source_valid -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ wire tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ wire [69:0] tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_data; // tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rf_source_data -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ wire tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_ready; // tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rf_source_ready
+ wire tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ wire tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ wire tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ wire [69:0] tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rf_sink_data
+ wire tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rf_sink_ready -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ wire tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ wire [31:0] tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ wire tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ wire rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest; // rx_eth_crc_pad_rem_csr_translator:uav_waitrequest -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ wire [2:0] rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_burstcount; // rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:m0_burstcount -> rx_eth_crc_pad_rem_csr_translator:uav_burstcount
+ wire [31:0] rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_writedata; // rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:m0_writedata -> rx_eth_crc_pad_rem_csr_translator:uav_writedata
+ wire [13:0] rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_address; // rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:m0_address -> rx_eth_crc_pad_rem_csr_translator:uav_address
+ wire rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_write; // rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:m0_write -> rx_eth_crc_pad_rem_csr_translator:uav_write
+ wire rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_lock; // rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:m0_lock -> rx_eth_crc_pad_rem_csr_translator:uav_lock
+ wire rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_read; // rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:m0_read -> rx_eth_crc_pad_rem_csr_translator:uav_read
+ wire [31:0] rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_readdata; // rx_eth_crc_pad_rem_csr_translator:uav_readdata -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:m0_readdata
+ wire rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // rx_eth_crc_pad_rem_csr_translator:uav_readdatavalid -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ wire rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess; // rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:m0_debugaccess -> rx_eth_crc_pad_rem_csr_translator:uav_debugaccess
+ wire [3:0] rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_byteenable; // rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:m0_byteenable -> rx_eth_crc_pad_rem_csr_translator:uav_byteenable
+ wire rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ wire rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rf_source_valid; // rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rf_source_valid -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ wire rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ wire [69:0] rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rf_source_data; // rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rf_source_data -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ wire rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rf_source_ready; // rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rf_source_ready
+ wire rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ wire rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ wire rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ wire [69:0] rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rf_sink_data
+ wire rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rf_sink_ready -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ wire rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ wire [31:0] rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ wire rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ wire rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest; // rx_eth_pkt_backpressure_control_csr_translator:uav_waitrequest -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ wire [2:0] rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount; // rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_burstcount -> rx_eth_pkt_backpressure_control_csr_translator:uav_burstcount
+ wire [31:0] rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_writedata; // rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_writedata -> rx_eth_pkt_backpressure_control_csr_translator:uav_writedata
+ wire [13:0] rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_address; // rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_address -> rx_eth_pkt_backpressure_control_csr_translator:uav_address
+ wire rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_write; // rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_write -> rx_eth_pkt_backpressure_control_csr_translator:uav_write
+ wire rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_lock; // rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_lock -> rx_eth_pkt_backpressure_control_csr_translator:uav_lock
+ wire rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_read; // rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_read -> rx_eth_pkt_backpressure_control_csr_translator:uav_read
+ wire [31:0] rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_readdata; // rx_eth_pkt_backpressure_control_csr_translator:uav_readdata -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_readdata
+ wire rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // rx_eth_pkt_backpressure_control_csr_translator:uav_readdatavalid -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ wire rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess; // rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_debugaccess -> rx_eth_pkt_backpressure_control_csr_translator:uav_debugaccess
+ wire [3:0] rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_byteenable; // rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_byteenable -> rx_eth_pkt_backpressure_control_csr_translator:uav_byteenable
+ wire rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ wire rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_valid; // rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_source_valid -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ wire rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ wire [69:0] rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_data; // rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_source_data -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ wire rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_ready; // rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_source_ready
+ wire rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ wire rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ wire rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ wire [69:0] rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_sink_data
+ wire rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_sink_ready -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ wire rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ wire [31:0] rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ wire rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ wire rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest; // rx_eth_packet_overflow_control_csr_translator:uav_waitrequest -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ wire [2:0] rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount; // rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:m0_burstcount -> rx_eth_packet_overflow_control_csr_translator:uav_burstcount
+ wire [31:0] rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_writedata; // rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:m0_writedata -> rx_eth_packet_overflow_control_csr_translator:uav_writedata
+ wire [13:0] rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_address; // rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:m0_address -> rx_eth_packet_overflow_control_csr_translator:uav_address
+ wire rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_write; // rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:m0_write -> rx_eth_packet_overflow_control_csr_translator:uav_write
+ wire rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_lock; // rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:m0_lock -> rx_eth_packet_overflow_control_csr_translator:uav_lock
+ wire rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_read; // rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:m0_read -> rx_eth_packet_overflow_control_csr_translator:uav_read
+ wire [31:0] rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_readdata; // rx_eth_packet_overflow_control_csr_translator:uav_readdata -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:m0_readdata
+ wire rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // rx_eth_packet_overflow_control_csr_translator:uav_readdatavalid -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ wire rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess; // rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:m0_debugaccess -> rx_eth_packet_overflow_control_csr_translator:uav_debugaccess
+ wire [3:0] rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_byteenable; // rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:m0_byteenable -> rx_eth_packet_overflow_control_csr_translator:uav_byteenable
+ wire rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ wire rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rf_source_valid; // rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rf_source_valid -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ wire rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ wire [69:0] rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rf_source_data; // rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rf_source_data -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ wire rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rf_source_ready; // rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rf_source_ready
+ wire rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ wire rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ wire rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ wire [69:0] rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rf_sink_data
+ wire rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rf_sink_ready -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ wire rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ wire [31:0] rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ wire rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ wire rx_bridge_m0_translator_avalon_universal_master_0_waitrequest; // rx_bridge_m0_translator_avalon_universal_master_0_agent:av_waitrequest -> rx_bridge_m0_translator:uav_waitrequest
+ wire [2:0] rx_bridge_m0_translator_avalon_universal_master_0_burstcount; // rx_bridge_m0_translator:uav_burstcount -> rx_bridge_m0_translator_avalon_universal_master_0_agent:av_burstcount
+ wire [31:0] rx_bridge_m0_translator_avalon_universal_master_0_writedata; // rx_bridge_m0_translator:uav_writedata -> rx_bridge_m0_translator_avalon_universal_master_0_agent:av_writedata
+ wire [13:0] rx_bridge_m0_translator_avalon_universal_master_0_address; // rx_bridge_m0_translator:uav_address -> rx_bridge_m0_translator_avalon_universal_master_0_agent:av_address
+ wire rx_bridge_m0_translator_avalon_universal_master_0_lock; // rx_bridge_m0_translator:uav_lock -> rx_bridge_m0_translator_avalon_universal_master_0_agent:av_lock
+ wire rx_bridge_m0_translator_avalon_universal_master_0_write; // rx_bridge_m0_translator:uav_write -> rx_bridge_m0_translator_avalon_universal_master_0_agent:av_write
+ wire rx_bridge_m0_translator_avalon_universal_master_0_read; // rx_bridge_m0_translator:uav_read -> rx_bridge_m0_translator_avalon_universal_master_0_agent:av_read
+ wire [31:0] rx_bridge_m0_translator_avalon_universal_master_0_readdata; // rx_bridge_m0_translator_avalon_universal_master_0_agent:av_readdata -> rx_bridge_m0_translator:uav_readdata
+ wire rx_bridge_m0_translator_avalon_universal_master_0_debugaccess; // rx_bridge_m0_translator:uav_debugaccess -> rx_bridge_m0_translator_avalon_universal_master_0_agent:av_debugaccess
+ wire [3:0] rx_bridge_m0_translator_avalon_universal_master_0_byteenable; // rx_bridge_m0_translator:uav_byteenable -> rx_bridge_m0_translator_avalon_universal_master_0_agent:av_byteenable
+ wire rx_bridge_m0_translator_avalon_universal_master_0_readdatavalid; // rx_bridge_m0_translator_avalon_universal_master_0_agent:av_readdatavalid -> rx_bridge_m0_translator:uav_readdatavalid
+ wire rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest; // rx_eth_statistics_collector_csr_translator:uav_waitrequest -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ wire [2:0] rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount; // rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_burstcount -> rx_eth_statistics_collector_csr_translator:uav_burstcount
+ wire [31:0] rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_writedata; // rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_writedata -> rx_eth_statistics_collector_csr_translator:uav_writedata
+ wire [13:0] rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_address; // rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_address -> rx_eth_statistics_collector_csr_translator:uav_address
+ wire rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_write; // rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_write -> rx_eth_statistics_collector_csr_translator:uav_write
+ wire rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_lock; // rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_lock -> rx_eth_statistics_collector_csr_translator:uav_lock
+ wire rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_read; // rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_read -> rx_eth_statistics_collector_csr_translator:uav_read
+ wire [31:0] rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_readdata; // rx_eth_statistics_collector_csr_translator:uav_readdata -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_readdata
+ wire rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // rx_eth_statistics_collector_csr_translator:uav_readdatavalid -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ wire rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess; // rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_debugaccess -> rx_eth_statistics_collector_csr_translator:uav_debugaccess
+ wire [3:0] rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_byteenable; // rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_byteenable -> rx_eth_statistics_collector_csr_translator:uav_byteenable
+ wire rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ wire rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_valid; // rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_source_valid -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ wire rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ wire [69:0] rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_data; // rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_source_data -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ wire rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_ready; // rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_source_ready
+ wire rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ wire rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ wire rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ wire [69:0] rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_sink_data
+ wire rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_sink_ready -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ wire rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ wire [31:0] rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ wire rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ wire rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest; // rx_eth_lane_decoder_csr_translator:uav_waitrequest -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ wire [2:0] rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_burstcount; // rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:m0_burstcount -> rx_eth_lane_decoder_csr_translator:uav_burstcount
+ wire [31:0] rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_writedata; // rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:m0_writedata -> rx_eth_lane_decoder_csr_translator:uav_writedata
+ wire [13:0] rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_address; // rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:m0_address -> rx_eth_lane_decoder_csr_translator:uav_address
+ wire rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_write; // rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:m0_write -> rx_eth_lane_decoder_csr_translator:uav_write
+ wire rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_lock; // rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:m0_lock -> rx_eth_lane_decoder_csr_translator:uav_lock
+ wire rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_read; // rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:m0_read -> rx_eth_lane_decoder_csr_translator:uav_read
+ wire [31:0] rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_readdata; // rx_eth_lane_decoder_csr_translator:uav_readdata -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:m0_readdata
+ wire rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // rx_eth_lane_decoder_csr_translator:uav_readdatavalid -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ wire rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess; // rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:m0_debugaccess -> rx_eth_lane_decoder_csr_translator:uav_debugaccess
+ wire [3:0] rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_byteenable; // rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:m0_byteenable -> rx_eth_lane_decoder_csr_translator:uav_byteenable
+ wire rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ wire rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rf_source_valid; // rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rf_source_valid -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ wire rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ wire [69:0] rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rf_source_data; // rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rf_source_data -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ wire rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rf_source_ready; // rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rf_source_ready
+ wire rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ wire rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ wire rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ wire [69:0] rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rf_sink_data
+ wire rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rf_sink_ready -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ wire rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ wire [31:0] rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ wire rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ wire rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest; // rx_eth_crc_checker_csr_translator:uav_waitrequest -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ wire [2:0] rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_burstcount; // rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:m0_burstcount -> rx_eth_crc_checker_csr_translator:uav_burstcount
+ wire [31:0] rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_writedata; // rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:m0_writedata -> rx_eth_crc_checker_csr_translator:uav_writedata
+ wire [13:0] rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_address; // rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:m0_address -> rx_eth_crc_checker_csr_translator:uav_address
+ wire rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_write; // rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:m0_write -> rx_eth_crc_checker_csr_translator:uav_write
+ wire rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_lock; // rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:m0_lock -> rx_eth_crc_checker_csr_translator:uav_lock
+ wire rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_read; // rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:m0_read -> rx_eth_crc_checker_csr_translator:uav_read
+ wire [31:0] rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_readdata; // rx_eth_crc_checker_csr_translator:uav_readdata -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:m0_readdata
+ wire rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // rx_eth_crc_checker_csr_translator:uav_readdatavalid -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ wire rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess; // rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:m0_debugaccess -> rx_eth_crc_checker_csr_translator:uav_debugaccess
+ wire [3:0] rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_byteenable; // rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:m0_byteenable -> rx_eth_crc_checker_csr_translator:uav_byteenable
+ wire rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ wire rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rf_source_valid; // rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rf_source_valid -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ wire rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ wire [69:0] rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rf_source_data; // rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rf_source_data -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ wire rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rf_source_ready; // rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rf_source_ready
+ wire rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ wire rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ wire rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ wire [69:0] rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rf_sink_data
+ wire rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rf_sink_ready -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ wire rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ wire [31:0] rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ wire rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ wire rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest; // rx_eth_frame_decoder_avalom_mm_csr_translator:uav_waitrequest -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ wire [2:0] rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount; // rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_burstcount -> rx_eth_frame_decoder_avalom_mm_csr_translator:uav_burstcount
+ wire [31:0] rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_writedata; // rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_writedata -> rx_eth_frame_decoder_avalom_mm_csr_translator:uav_writedata
+ wire [13:0] rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_address; // rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_address -> rx_eth_frame_decoder_avalom_mm_csr_translator:uav_address
+ wire rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_write; // rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_write -> rx_eth_frame_decoder_avalom_mm_csr_translator:uav_write
+ wire rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_lock; // rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_lock -> rx_eth_frame_decoder_avalom_mm_csr_translator:uav_lock
+ wire rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_read; // rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_read -> rx_eth_frame_decoder_avalom_mm_csr_translator:uav_read
+ wire [31:0] rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_readdata; // rx_eth_frame_decoder_avalom_mm_csr_translator:uav_readdata -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_readdata
+ wire rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // rx_eth_frame_decoder_avalom_mm_csr_translator:uav_readdatavalid -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ wire rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess; // rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_debugaccess -> rx_eth_frame_decoder_avalom_mm_csr_translator:uav_debugaccess
+ wire [3:0] rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_byteenable; // rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_byteenable -> rx_eth_frame_decoder_avalom_mm_csr_translator:uav_byteenable
+ wire rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ wire rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_valid; // rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_source_valid -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ wire rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ wire [69:0] rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_data; // rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_source_data -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ wire rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_ready; // rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_source_ready
+ wire rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ wire rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ wire rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ wire [69:0] rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_sink_data
+ wire rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_sink_ready -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ wire rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ wire [31:0] rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ wire rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ wire merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent_cp_endofpacket; // merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
+ wire merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent_cp_valid; // merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
+ wire merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent_cp_startofpacket; // merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
+ wire [65:0] merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent_cp_data; // merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
+ wire merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent_cp_ready; // addr_router:sink_ready -> merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:cp_ready
+ wire tx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket; // tx_bridge_s0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
+ wire tx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_valid; // tx_bridge_s0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
+ wire tx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket; // tx_bridge_s0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
+ wire [65:0] tx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_data; // tx_bridge_s0_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
+ wire tx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:rp_ready
+ wire rx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket; // rx_bridge_s0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
+ wire rx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_valid; // rx_bridge_s0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
+ wire rx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket; // rx_bridge_s0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
+ wire [65:0] rx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_data; // rx_bridge_s0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
+ wire rx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_001:sink_ready -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:rp_ready
+ wire tx_bridge_m0_translator_avalon_universal_master_0_agent_cp_endofpacket; // tx_bridge_m0_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket
+ wire tx_bridge_m0_translator_avalon_universal_master_0_agent_cp_valid; // tx_bridge_m0_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid
+ wire tx_bridge_m0_translator_avalon_universal_master_0_agent_cp_startofpacket; // tx_bridge_m0_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket
+ wire [68:0] tx_bridge_m0_translator_avalon_universal_master_0_agent_cp_data; // tx_bridge_m0_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data
+ wire tx_bridge_m0_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_001:sink_ready -> tx_bridge_m0_translator_avalon_universal_master_0_agent:cp_ready
+ wire tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket; // tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket
+ wire tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_valid; // tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid
+ wire tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket; // tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket
+ wire [68:0] tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_data; // tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data
+ wire tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_002:sink_ready -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rp_ready
+ wire tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket; // tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket
+ wire tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rp_valid; // tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid
+ wire tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket; // tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket
+ wire [68:0] tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rp_data; // tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data
+ wire tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_003:sink_ready -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rp_ready
+ wire tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket; // tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket
+ wire tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rp_valid; // tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid
+ wire tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket; // tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket
+ wire [68:0] tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rp_data; // tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data
+ wire tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_004:sink_ready -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rp_ready
+ wire tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket; // tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket
+ wire tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rp_valid; // tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid
+ wire tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket; // tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket
+ wire [68:0] tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rp_data; // tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data
+ wire tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_005:sink_ready -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rp_ready
+ wire tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket; // tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_006:sink_endofpacket
+ wire tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rp_valid; // tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_006:sink_valid
+ wire tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket; // tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_006:sink_startofpacket
+ wire [68:0] tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rp_data; // tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rp_data -> id_router_006:sink_data
+ wire tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_006:sink_ready -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rp_ready
+ wire tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket; // tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_007:sink_endofpacket
+ wire tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid; // tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_007:sink_valid
+ wire tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket; // tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_007:sink_startofpacket
+ wire [68:0] tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data; // tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_007:sink_data
+ wire tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_007:sink_ready -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
+ wire tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket; // tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_008:sink_endofpacket
+ wire tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_valid; // tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_008:sink_valid
+ wire tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket; // tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_008:sink_startofpacket
+ wire [68:0] tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_data; // tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rp_data -> id_router_008:sink_data
+ wire tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_008:sink_ready -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rp_ready
+ wire tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket; // tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_009:sink_endofpacket
+ wire tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_valid; // tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_009:sink_valid
+ wire tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket; // tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_009:sink_startofpacket
+ wire [68:0] tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_data; // tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rp_data -> id_router_009:sink_data
+ wire tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_009:sink_ready -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rp_ready
+ wire rx_bridge_m0_translator_avalon_universal_master_0_agent_cp_endofpacket; // rx_bridge_m0_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_002:sink_endofpacket
+ wire rx_bridge_m0_translator_avalon_universal_master_0_agent_cp_valid; // rx_bridge_m0_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_002:sink_valid
+ wire rx_bridge_m0_translator_avalon_universal_master_0_agent_cp_startofpacket; // rx_bridge_m0_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_002:sink_startofpacket
+ wire [68:0] rx_bridge_m0_translator_avalon_universal_master_0_agent_cp_data; // rx_bridge_m0_translator_avalon_universal_master_0_agent:cp_data -> addr_router_002:sink_data
+ wire rx_bridge_m0_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_002:sink_ready -> rx_bridge_m0_translator_avalon_universal_master_0_agent:cp_ready
+ wire rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket; // rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_010:sink_endofpacket
+ wire rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_valid; // rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_010:sink_valid
+ wire rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket; // rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_010:sink_startofpacket
+ wire [68:0] rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_data; // rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rp_data -> id_router_010:sink_data
+ wire rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_010:sink_ready -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rp_ready
+ wire rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket; // rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_011:sink_endofpacket
+ wire rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rp_valid; // rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_011:sink_valid
+ wire rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket; // rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_011:sink_startofpacket
+ wire [68:0] rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rp_data; // rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rp_data -> id_router_011:sink_data
+ wire rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_011:sink_ready -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rp_ready
+ wire rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket; // rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_012:sink_endofpacket
+ wire rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rp_valid; // rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_012:sink_valid
+ wire rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket; // rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_012:sink_startofpacket
+ wire [68:0] rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rp_data; // rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rp_data -> id_router_012:sink_data
+ wire rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_012:sink_ready -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rp_ready
+ wire rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket; // rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_013:sink_endofpacket
+ wire rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_valid; // rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_013:sink_valid
+ wire rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket; // rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_013:sink_startofpacket
+ wire [68:0] rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_data; // rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rp_data -> id_router_013:sink_data
+ wire rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_013:sink_ready -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rp_ready
+ wire rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket; // rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_014:sink_endofpacket
+ wire rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rp_valid; // rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_014:sink_valid
+ wire rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket; // rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_014:sink_startofpacket
+ wire [68:0] rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rp_data; // rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rp_data -> id_router_014:sink_data
+ wire rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_014:sink_ready -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rp_ready
+ wire rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket; // rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_015:sink_endofpacket
+ wire rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_valid; // rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_015:sink_valid
+ wire rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket; // rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_015:sink_startofpacket
+ wire [68:0] rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_data; // rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rp_data -> id_router_015:sink_data
+ wire rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_015:sink_ready -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rp_ready
+ wire rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket; // rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_016:sink_endofpacket
+ wire rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rp_valid; // rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_016:sink_valid
+ wire rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket; // rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_016:sink_startofpacket
+ wire [68:0] rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rp_data; // rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rp_data -> id_router_016:sink_data
+ wire rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_016:sink_ready -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rp_ready
+ wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> limiter:cmd_sink_endofpacket
+ wire addr_router_src_valid; // addr_router:src_valid -> limiter:cmd_sink_valid
+ wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> limiter:cmd_sink_startofpacket
+ wire [65:0] addr_router_src_data; // addr_router:src_data -> limiter:cmd_sink_data
+ wire [1:0] addr_router_src_channel; // addr_router:src_channel -> limiter:cmd_sink_channel
+ wire addr_router_src_ready; // limiter:cmd_sink_ready -> addr_router:src_ready
+ wire limiter_rsp_src_endofpacket; // limiter:rsp_src_endofpacket -> merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:rp_endofpacket
+ wire limiter_rsp_src_valid; // limiter:rsp_src_valid -> merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:rp_valid
+ wire limiter_rsp_src_startofpacket; // limiter:rsp_src_startofpacket -> merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:rp_startofpacket
+ wire [65:0] limiter_rsp_src_data; // limiter:rsp_src_data -> merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:rp_data
+ wire [1:0] limiter_rsp_src_channel; // limiter:rsp_src_channel -> merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:rp_channel
+ wire limiter_rsp_src_ready; // merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:rp_ready -> limiter:rsp_src_ready
+ wire addr_router_001_src_endofpacket; // addr_router_001:src_endofpacket -> limiter_001:cmd_sink_endofpacket
+ wire addr_router_001_src_valid; // addr_router_001:src_valid -> limiter_001:cmd_sink_valid
+ wire addr_router_001_src_startofpacket; // addr_router_001:src_startofpacket -> limiter_001:cmd_sink_startofpacket
+ wire [68:0] addr_router_001_src_data; // addr_router_001:src_data -> limiter_001:cmd_sink_data
+ wire [7:0] addr_router_001_src_channel; // addr_router_001:src_channel -> limiter_001:cmd_sink_channel
+ wire addr_router_001_src_ready; // limiter_001:cmd_sink_ready -> addr_router_001:src_ready
+ wire limiter_001_rsp_src_endofpacket; // limiter_001:rsp_src_endofpacket -> tx_bridge_m0_translator_avalon_universal_master_0_agent:rp_endofpacket
+ wire limiter_001_rsp_src_valid; // limiter_001:rsp_src_valid -> tx_bridge_m0_translator_avalon_universal_master_0_agent:rp_valid
+ wire limiter_001_rsp_src_startofpacket; // limiter_001:rsp_src_startofpacket -> tx_bridge_m0_translator_avalon_universal_master_0_agent:rp_startofpacket
+ wire [68:0] limiter_001_rsp_src_data; // limiter_001:rsp_src_data -> tx_bridge_m0_translator_avalon_universal_master_0_agent:rp_data
+ wire [7:0] limiter_001_rsp_src_channel; // limiter_001:rsp_src_channel -> tx_bridge_m0_translator_avalon_universal_master_0_agent:rp_channel
+ wire limiter_001_rsp_src_ready; // tx_bridge_m0_translator_avalon_universal_master_0_agent:rp_ready -> limiter_001:rsp_src_ready
+ wire addr_router_002_src_endofpacket; // addr_router_002:src_endofpacket -> limiter_002:cmd_sink_endofpacket
+ wire addr_router_002_src_valid; // addr_router_002:src_valid -> limiter_002:cmd_sink_valid
+ wire addr_router_002_src_startofpacket; // addr_router_002:src_startofpacket -> limiter_002:cmd_sink_startofpacket
+ wire [68:0] addr_router_002_src_data; // addr_router_002:src_data -> limiter_002:cmd_sink_data
+ wire [6:0] addr_router_002_src_channel; // addr_router_002:src_channel -> limiter_002:cmd_sink_channel
+ wire addr_router_002_src_ready; // limiter_002:cmd_sink_ready -> addr_router_002:src_ready
+ wire limiter_002_rsp_src_endofpacket; // limiter_002:rsp_src_endofpacket -> rx_bridge_m0_translator_avalon_universal_master_0_agent:rp_endofpacket
+ wire limiter_002_rsp_src_valid; // limiter_002:rsp_src_valid -> rx_bridge_m0_translator_avalon_universal_master_0_agent:rp_valid
+ wire limiter_002_rsp_src_startofpacket; // limiter_002:rsp_src_startofpacket -> rx_bridge_m0_translator_avalon_universal_master_0_agent:rp_startofpacket
+ wire [68:0] limiter_002_rsp_src_data; // limiter_002:rsp_src_data -> rx_bridge_m0_translator_avalon_universal_master_0_agent:rp_data
+ wire [6:0] limiter_002_rsp_src_channel; // limiter_002:rsp_src_channel -> rx_bridge_m0_translator_avalon_universal_master_0_agent:rp_channel
+ wire limiter_002_rsp_src_ready; // rx_bridge_m0_translator_avalon_universal_master_0_agent:rp_ready -> limiter_002:rsp_src_ready
+ wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [addr_router:reset, cmd_xbar_demux:reset, crosser:in_reset, crosser_001:in_reset, crosser_002:out_reset, crosser_003:out_reset, limiter:reset, merlin_master_translator:reset, merlin_master_translator_avalon_universal_master_0_translator:reset, merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:reset, rsp_xbar_mux:reset]
+ wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [addr_router_001:reset, cmd_xbar_demux_001:reset, crosser:out_reset, crosser_002:in_reset, id_router:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, id_router_006:reset, id_router_007:reset, id_router_008:reset, id_router_009:reset, limiter_001:reset, rsp_xbar_demux:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_demux_006:reset, rsp_xbar_demux_007:reset, rsp_xbar_demux_008:reset, rsp_xbar_demux_009:reset, rsp_xbar_mux_001:reset, rxtx_dc_fifo_link_fault_status:out_reset_n, rxtx_dc_fifo_pauselen:out_reset_n, rxtx_timing_adapter_link_fault_status_tx:reset_n, rxtx_timing_adapter_pauselen_tx:reset_n, tx_bridge:reset, tx_bridge_m0_translator:reset, tx_bridge_m0_translator_avalon_universal_master_0_agent:reset, tx_bridge_s0_translator:reset, tx_bridge_s0_translator_avalon_universal_slave_0_agent:reset, tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo:reset, tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, tx_eth_address_inserter:reset, tx_eth_address_inserter_csr_translator:reset, tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:reset, tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, tx_eth_crc_inserter:reset, tx_eth_crc_inserter_csr_translator:reset, tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:reset, tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, tx_eth_frame_decoder:reset, tx_eth_frame_decoder_avalom_mm_csr_translator:reset, tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:reset, tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, tx_eth_link_fault_generation:reset, tx_eth_packet_formatter:reset, tx_eth_packet_underflow_control:reset, tx_eth_packet_underflow_control_avalon_slave_0_translator:reset, tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:reset, tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, tx_eth_pad_inserter:reset, tx_eth_pad_inserter_csr_translator:reset, tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:reset, tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, tx_eth_pause_beat_conversion:reset, tx_eth_pause_ctrl_gen:reset, tx_eth_pause_ctrl_gen_csr_translator:reset, tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:reset, tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, tx_eth_pkt_backpressure_control:reset, tx_eth_pkt_backpressure_control_csr_translator:reset, tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:reset, tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, tx_eth_statistics_collector:reset, tx_eth_statistics_collector_csr_translator:reset, tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:reset, tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, tx_eth_xgmii_termination:reset, tx_st_error_adapter_stat:reset_n, tx_st_mux_flow_control_user_frame:reset_n, tx_st_pause_ctrl_error_adapter:reset_n, tx_st_pipeline_stage_rs:reset, tx_st_timing_adapter_frame_decoder:reset_n, tx_st_timing_adapter_splitter_status_in:reset_n, tx_st_timing_adapter_splitter_status_output:reset_n, tx_st_timing_adapter_splitter_status_statistics:reset_n]
+ wire rst_controller_002_reset_out_reset; // rst_controller_002:reset_out -> [addr_router_002:reset, cmd_xbar_demux_002:reset, crosser_001:out_reset, crosser_003:in_reset, id_router_001:reset, id_router_010:reset, id_router_011:reset, id_router_012:reset, id_router_013:reset, id_router_014:reset, id_router_015:reset, id_router_016:reset, limiter_002:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_010:reset, rsp_xbar_demux_011:reset, rsp_xbar_demux_012:reset, rsp_xbar_demux_013:reset, rsp_xbar_demux_014:reset, rsp_xbar_demux_015:reset, rsp_xbar_demux_016:reset, rsp_xbar_mux_002:reset, rx_bridge:reset, rx_bridge_m0_translator:reset, rx_bridge_m0_translator_avalon_universal_master_0_agent:reset, rx_bridge_s0_translator:reset, rx_bridge_s0_translator_avalon_universal_slave_0_agent:reset, rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo:reset, rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rx_eth_crc_checker:reset, rx_eth_crc_checker_csr_translator:reset, rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:reset, rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rx_eth_crc_pad_rem:reset, rx_eth_crc_pad_rem_csr_translator:reset, rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:reset, rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rx_eth_frame_decoder:reset, rx_eth_frame_decoder_avalom_mm_csr_translator:reset, rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:reset, rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rx_eth_frame_status_merger:reset, rx_eth_lane_decoder:reset, rx_eth_lane_decoder_csr_translator:reset, rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:reset, rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rx_eth_link_fault_detection:reset, rx_eth_packet_overflow_control:reset, rx_eth_packet_overflow_control_csr_translator:reset, rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:reset, rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rx_eth_pkt_backpressure_control:reset, rx_eth_pkt_backpressure_control_csr_translator:reset, rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:reset, rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rx_eth_statistics_collector:reset, rx_eth_statistics_collector_csr_translator:reset, rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:reset, rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rx_st_error_adapter_stat:reset_n, rx_st_status_output_delay:reset_n, rx_st_status_statistics_delay:reset_n, rx_st_timing_adapter_frame_status_in:reset_n, rx_st_timing_adapter_interface_conversion:reset_n, rx_st_timing_adapter_lane_decoder:reset_n, rx_st_timing_adapter_link_fault_detection:reset_n, rx_st_timing_adapter_splitter_status_in:reset_n, rx_st_timing_adapter_splitter_status_output:reset_n, rx_st_timing_adapter_splitter_status_statistics:reset_n, rx_timing_adapter_frame_status_out_crc_checker:reset_n, rx_timing_adapter_frame_status_out_frame_decoder:reset_n, rxtx_dc_fifo_link_fault_status:in_reset_n, rxtx_dc_fifo_pauselen:in_reset_n, rxtx_timing_adapter_pauselen_rx:reset_n, txrx_timing_adapter_link_fault_status_export:reset_n, txrx_timing_adapter_link_fault_status_rx:reset_n]
+ wire limiter_cmd_src_endofpacket; // limiter:cmd_src_endofpacket -> cmd_xbar_demux:sink_endofpacket
+ wire limiter_cmd_src_startofpacket; // limiter:cmd_src_startofpacket -> cmd_xbar_demux:sink_startofpacket
+ wire [65:0] limiter_cmd_src_data; // limiter:cmd_src_data -> cmd_xbar_demux:sink_data
+ wire [1:0] limiter_cmd_src_channel; // limiter:cmd_src_channel -> cmd_xbar_demux:sink_channel
+ wire limiter_cmd_src_ready; // cmd_xbar_demux:sink_ready -> limiter:cmd_src_ready
+ wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> limiter:rsp_sink_endofpacket
+ wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> limiter:rsp_sink_valid
+ wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> limiter:rsp_sink_startofpacket
+ wire [65:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> limiter:rsp_sink_data
+ wire [1:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> limiter:rsp_sink_channel
+ wire rsp_xbar_mux_src_ready; // limiter:rsp_sink_ready -> rsp_xbar_mux:src_ready
+ wire crosser_out_ready; // tx_bridge_s0_translator_avalon_universal_slave_0_agent:cp_ready -> crosser:out_ready
+ wire id_router_src_endofpacket; // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
+ wire id_router_src_valid; // id_router:src_valid -> rsp_xbar_demux:sink_valid
+ wire id_router_src_startofpacket; // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
+ wire [65:0] id_router_src_data; // id_router:src_data -> rsp_xbar_demux:sink_data
+ wire [1:0] id_router_src_channel; // id_router:src_channel -> rsp_xbar_demux:sink_channel
+ wire id_router_src_ready; // rsp_xbar_demux:sink_ready -> id_router:src_ready
+ wire crosser_001_out_ready; // rx_bridge_s0_translator_avalon_universal_slave_0_agent:cp_ready -> crosser_001:out_ready
+ wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
+ wire id_router_001_src_valid; // id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid
+ wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
+ wire [65:0] id_router_001_src_data; // id_router_001:src_data -> rsp_xbar_demux_001:sink_data
+ wire [1:0] id_router_001_src_channel; // id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel
+ wire id_router_001_src_ready; // rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready
+ wire cmd_xbar_demux_001_src0_endofpacket; // cmd_xbar_demux_001:src0_endofpacket -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ wire cmd_xbar_demux_001_src0_valid; // cmd_xbar_demux_001:src0_valid -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:cp_valid
+ wire cmd_xbar_demux_001_src0_startofpacket; // cmd_xbar_demux_001:src0_startofpacket -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ wire [68:0] cmd_xbar_demux_001_src0_data; // cmd_xbar_demux_001:src0_data -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:cp_data
+ wire [7:0] cmd_xbar_demux_001_src0_channel; // cmd_xbar_demux_001:src0_channel -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:cp_channel
+ wire cmd_xbar_demux_001_src1_endofpacket; // cmd_xbar_demux_001:src1_endofpacket -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ wire cmd_xbar_demux_001_src1_valid; // cmd_xbar_demux_001:src1_valid -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:cp_valid
+ wire cmd_xbar_demux_001_src1_startofpacket; // cmd_xbar_demux_001:src1_startofpacket -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ wire [68:0] cmd_xbar_demux_001_src1_data; // cmd_xbar_demux_001:src1_data -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:cp_data
+ wire [7:0] cmd_xbar_demux_001_src1_channel; // cmd_xbar_demux_001:src1_channel -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:cp_channel
+ wire cmd_xbar_demux_001_src2_endofpacket; // cmd_xbar_demux_001:src2_endofpacket -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ wire cmd_xbar_demux_001_src2_valid; // cmd_xbar_demux_001:src2_valid -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:cp_valid
+ wire cmd_xbar_demux_001_src2_startofpacket; // cmd_xbar_demux_001:src2_startofpacket -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ wire [68:0] cmd_xbar_demux_001_src2_data; // cmd_xbar_demux_001:src2_data -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:cp_data
+ wire [7:0] cmd_xbar_demux_001_src2_channel; // cmd_xbar_demux_001:src2_channel -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:cp_channel
+ wire cmd_xbar_demux_001_src3_endofpacket; // cmd_xbar_demux_001:src3_endofpacket -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ wire cmd_xbar_demux_001_src3_valid; // cmd_xbar_demux_001:src3_valid -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:cp_valid
+ wire cmd_xbar_demux_001_src3_startofpacket; // cmd_xbar_demux_001:src3_startofpacket -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ wire [68:0] cmd_xbar_demux_001_src3_data; // cmd_xbar_demux_001:src3_data -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:cp_data
+ wire [7:0] cmd_xbar_demux_001_src3_channel; // cmd_xbar_demux_001:src3_channel -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:cp_channel
+ wire cmd_xbar_demux_001_src4_endofpacket; // cmd_xbar_demux_001:src4_endofpacket -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ wire cmd_xbar_demux_001_src4_valid; // cmd_xbar_demux_001:src4_valid -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:cp_valid
+ wire cmd_xbar_demux_001_src4_startofpacket; // cmd_xbar_demux_001:src4_startofpacket -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ wire [68:0] cmd_xbar_demux_001_src4_data; // cmd_xbar_demux_001:src4_data -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:cp_data
+ wire [7:0] cmd_xbar_demux_001_src4_channel; // cmd_xbar_demux_001:src4_channel -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:cp_channel
+ wire cmd_xbar_demux_001_src5_endofpacket; // cmd_xbar_demux_001:src5_endofpacket -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ wire cmd_xbar_demux_001_src5_valid; // cmd_xbar_demux_001:src5_valid -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
+ wire cmd_xbar_demux_001_src5_startofpacket; // cmd_xbar_demux_001:src5_startofpacket -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ wire [68:0] cmd_xbar_demux_001_src5_data; // cmd_xbar_demux_001:src5_data -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
+ wire [7:0] cmd_xbar_demux_001_src5_channel; // cmd_xbar_demux_001:src5_channel -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
+ wire cmd_xbar_demux_001_src6_endofpacket; // cmd_xbar_demux_001:src6_endofpacket -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ wire cmd_xbar_demux_001_src6_valid; // cmd_xbar_demux_001:src6_valid -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:cp_valid
+ wire cmd_xbar_demux_001_src6_startofpacket; // cmd_xbar_demux_001:src6_startofpacket -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ wire [68:0] cmd_xbar_demux_001_src6_data; // cmd_xbar_demux_001:src6_data -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:cp_data
+ wire [7:0] cmd_xbar_demux_001_src6_channel; // cmd_xbar_demux_001:src6_channel -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:cp_channel
+ wire cmd_xbar_demux_001_src7_endofpacket; // cmd_xbar_demux_001:src7_endofpacket -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ wire cmd_xbar_demux_001_src7_valid; // cmd_xbar_demux_001:src7_valid -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:cp_valid
+ wire cmd_xbar_demux_001_src7_startofpacket; // cmd_xbar_demux_001:src7_startofpacket -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ wire [68:0] cmd_xbar_demux_001_src7_data; // cmd_xbar_demux_001:src7_data -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:cp_data
+ wire [7:0] cmd_xbar_demux_001_src7_channel; // cmd_xbar_demux_001:src7_channel -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:cp_channel
+ wire rsp_xbar_demux_002_src0_endofpacket; // rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket
+ wire rsp_xbar_demux_002_src0_valid; // rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux_001:sink0_valid
+ wire rsp_xbar_demux_002_src0_startofpacket; // rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket
+ wire [68:0] rsp_xbar_demux_002_src0_data; // rsp_xbar_demux_002:src0_data -> rsp_xbar_mux_001:sink0_data
+ wire [7:0] rsp_xbar_demux_002_src0_channel; // rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux_001:sink0_channel
+ wire rsp_xbar_demux_002_src0_ready; // rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux_002:src0_ready
+ wire rsp_xbar_demux_003_src0_endofpacket; // rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket
+ wire rsp_xbar_demux_003_src0_valid; // rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux_001:sink1_valid
+ wire rsp_xbar_demux_003_src0_startofpacket; // rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket
+ wire [68:0] rsp_xbar_demux_003_src0_data; // rsp_xbar_demux_003:src0_data -> rsp_xbar_mux_001:sink1_data
+ wire [7:0] rsp_xbar_demux_003_src0_channel; // rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux_001:sink1_channel
+ wire rsp_xbar_demux_003_src0_ready; // rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_003:src0_ready
+ wire rsp_xbar_demux_004_src0_endofpacket; // rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket
+ wire rsp_xbar_demux_004_src0_valid; // rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux_001:sink2_valid
+ wire rsp_xbar_demux_004_src0_startofpacket; // rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket
+ wire [68:0] rsp_xbar_demux_004_src0_data; // rsp_xbar_demux_004:src0_data -> rsp_xbar_mux_001:sink2_data
+ wire [7:0] rsp_xbar_demux_004_src0_channel; // rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux_001:sink2_channel
+ wire rsp_xbar_demux_004_src0_ready; // rsp_xbar_mux_001:sink2_ready -> rsp_xbar_demux_004:src0_ready
+ wire rsp_xbar_demux_005_src0_endofpacket; // rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket
+ wire rsp_xbar_demux_005_src0_valid; // rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink3_valid
+ wire rsp_xbar_demux_005_src0_startofpacket; // rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket
+ wire [68:0] rsp_xbar_demux_005_src0_data; // rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink3_data
+ wire [7:0] rsp_xbar_demux_005_src0_channel; // rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink3_channel
+ wire rsp_xbar_demux_005_src0_ready; // rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_005:src0_ready
+ wire rsp_xbar_demux_006_src0_endofpacket; // rsp_xbar_demux_006:src0_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket
+ wire rsp_xbar_demux_006_src0_valid; // rsp_xbar_demux_006:src0_valid -> rsp_xbar_mux_001:sink4_valid
+ wire rsp_xbar_demux_006_src0_startofpacket; // rsp_xbar_demux_006:src0_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket
+ wire [68:0] rsp_xbar_demux_006_src0_data; // rsp_xbar_demux_006:src0_data -> rsp_xbar_mux_001:sink4_data
+ wire [7:0] rsp_xbar_demux_006_src0_channel; // rsp_xbar_demux_006:src0_channel -> rsp_xbar_mux_001:sink4_channel
+ wire rsp_xbar_demux_006_src0_ready; // rsp_xbar_mux_001:sink4_ready -> rsp_xbar_demux_006:src0_ready
+ wire rsp_xbar_demux_007_src0_endofpacket; // rsp_xbar_demux_007:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket
+ wire rsp_xbar_demux_007_src0_valid; // rsp_xbar_demux_007:src0_valid -> rsp_xbar_mux_001:sink5_valid
+ wire rsp_xbar_demux_007_src0_startofpacket; // rsp_xbar_demux_007:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket
+ wire [68:0] rsp_xbar_demux_007_src0_data; // rsp_xbar_demux_007:src0_data -> rsp_xbar_mux_001:sink5_data
+ wire [7:0] rsp_xbar_demux_007_src0_channel; // rsp_xbar_demux_007:src0_channel -> rsp_xbar_mux_001:sink5_channel
+ wire rsp_xbar_demux_007_src0_ready; // rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_007:src0_ready
+ wire rsp_xbar_demux_008_src0_endofpacket; // rsp_xbar_demux_008:src0_endofpacket -> rsp_xbar_mux_001:sink6_endofpacket
+ wire rsp_xbar_demux_008_src0_valid; // rsp_xbar_demux_008:src0_valid -> rsp_xbar_mux_001:sink6_valid
+ wire rsp_xbar_demux_008_src0_startofpacket; // rsp_xbar_demux_008:src0_startofpacket -> rsp_xbar_mux_001:sink6_startofpacket
+ wire [68:0] rsp_xbar_demux_008_src0_data; // rsp_xbar_demux_008:src0_data -> rsp_xbar_mux_001:sink6_data
+ wire [7:0] rsp_xbar_demux_008_src0_channel; // rsp_xbar_demux_008:src0_channel -> rsp_xbar_mux_001:sink6_channel
+ wire rsp_xbar_demux_008_src0_ready; // rsp_xbar_mux_001:sink6_ready -> rsp_xbar_demux_008:src0_ready
+ wire rsp_xbar_demux_009_src0_endofpacket; // rsp_xbar_demux_009:src0_endofpacket -> rsp_xbar_mux_001:sink7_endofpacket
+ wire rsp_xbar_demux_009_src0_valid; // rsp_xbar_demux_009:src0_valid -> rsp_xbar_mux_001:sink7_valid
+ wire rsp_xbar_demux_009_src0_startofpacket; // rsp_xbar_demux_009:src0_startofpacket -> rsp_xbar_mux_001:sink7_startofpacket
+ wire [68:0] rsp_xbar_demux_009_src0_data; // rsp_xbar_demux_009:src0_data -> rsp_xbar_mux_001:sink7_data
+ wire [7:0] rsp_xbar_demux_009_src0_channel; // rsp_xbar_demux_009:src0_channel -> rsp_xbar_mux_001:sink7_channel
+ wire rsp_xbar_demux_009_src0_ready; // rsp_xbar_mux_001:sink7_ready -> rsp_xbar_demux_009:src0_ready
+ wire limiter_001_cmd_src_endofpacket; // limiter_001:cmd_src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
+ wire limiter_001_cmd_src_startofpacket; // limiter_001:cmd_src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
+ wire [68:0] limiter_001_cmd_src_data; // limiter_001:cmd_src_data -> cmd_xbar_demux_001:sink_data
+ wire [7:0] limiter_001_cmd_src_channel; // limiter_001:cmd_src_channel -> cmd_xbar_demux_001:sink_channel
+ wire limiter_001_cmd_src_ready; // cmd_xbar_demux_001:sink_ready -> limiter_001:cmd_src_ready
+ wire rsp_xbar_mux_001_src_endofpacket; // rsp_xbar_mux_001:src_endofpacket -> limiter_001:rsp_sink_endofpacket
+ wire rsp_xbar_mux_001_src_valid; // rsp_xbar_mux_001:src_valid -> limiter_001:rsp_sink_valid
+ wire rsp_xbar_mux_001_src_startofpacket; // rsp_xbar_mux_001:src_startofpacket -> limiter_001:rsp_sink_startofpacket
+ wire [68:0] rsp_xbar_mux_001_src_data; // rsp_xbar_mux_001:src_data -> limiter_001:rsp_sink_data
+ wire [7:0] rsp_xbar_mux_001_src_channel; // rsp_xbar_mux_001:src_channel -> limiter_001:rsp_sink_channel
+ wire rsp_xbar_mux_001_src_ready; // limiter_001:rsp_sink_ready -> rsp_xbar_mux_001:src_ready
+ wire cmd_xbar_demux_001_src0_ready; // tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src0_ready
+ wire id_router_002_src_endofpacket; // id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket
+ wire id_router_002_src_valid; // id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid
+ wire id_router_002_src_startofpacket; // id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket
+ wire [68:0] id_router_002_src_data; // id_router_002:src_data -> rsp_xbar_demux_002:sink_data
+ wire [7:0] id_router_002_src_channel; // id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel
+ wire id_router_002_src_ready; // rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready
+ wire cmd_xbar_demux_001_src1_ready; // tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src1_ready
+ wire id_router_003_src_endofpacket; // id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket
+ wire id_router_003_src_valid; // id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid
+ wire id_router_003_src_startofpacket; // id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket
+ wire [68:0] id_router_003_src_data; // id_router_003:src_data -> rsp_xbar_demux_003:sink_data
+ wire [7:0] id_router_003_src_channel; // id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel
+ wire id_router_003_src_ready; // rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready
+ wire cmd_xbar_demux_001_src2_ready; // tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src2_ready
+ wire id_router_004_src_endofpacket; // id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket
+ wire id_router_004_src_valid; // id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid
+ wire id_router_004_src_startofpacket; // id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket
+ wire [68:0] id_router_004_src_data; // id_router_004:src_data -> rsp_xbar_demux_004:sink_data
+ wire [7:0] id_router_004_src_channel; // id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel
+ wire id_router_004_src_ready; // rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready
+ wire cmd_xbar_demux_001_src3_ready; // tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src3_ready
+ wire id_router_005_src_endofpacket; // id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket
+ wire id_router_005_src_valid; // id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid
+ wire id_router_005_src_startofpacket; // id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket
+ wire [68:0] id_router_005_src_data; // id_router_005:src_data -> rsp_xbar_demux_005:sink_data
+ wire [7:0] id_router_005_src_channel; // id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel
+ wire id_router_005_src_ready; // rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready
+ wire cmd_xbar_demux_001_src4_ready; // tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src4_ready
+ wire id_router_006_src_endofpacket; // id_router_006:src_endofpacket -> rsp_xbar_demux_006:sink_endofpacket
+ wire id_router_006_src_valid; // id_router_006:src_valid -> rsp_xbar_demux_006:sink_valid
+ wire id_router_006_src_startofpacket; // id_router_006:src_startofpacket -> rsp_xbar_demux_006:sink_startofpacket
+ wire [68:0] id_router_006_src_data; // id_router_006:src_data -> rsp_xbar_demux_006:sink_data
+ wire [7:0] id_router_006_src_channel; // id_router_006:src_channel -> rsp_xbar_demux_006:sink_channel
+ wire id_router_006_src_ready; // rsp_xbar_demux_006:sink_ready -> id_router_006:src_ready
+ wire cmd_xbar_demux_001_src5_ready; // tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready
+ wire id_router_007_src_endofpacket; // id_router_007:src_endofpacket -> rsp_xbar_demux_007:sink_endofpacket
+ wire id_router_007_src_valid; // id_router_007:src_valid -> rsp_xbar_demux_007:sink_valid
+ wire id_router_007_src_startofpacket; // id_router_007:src_startofpacket -> rsp_xbar_demux_007:sink_startofpacket
+ wire [68:0] id_router_007_src_data; // id_router_007:src_data -> rsp_xbar_demux_007:sink_data
+ wire [7:0] id_router_007_src_channel; // id_router_007:src_channel -> rsp_xbar_demux_007:sink_channel
+ wire id_router_007_src_ready; // rsp_xbar_demux_007:sink_ready -> id_router_007:src_ready
+ wire cmd_xbar_demux_001_src6_ready; // tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src6_ready
+ wire id_router_008_src_endofpacket; // id_router_008:src_endofpacket -> rsp_xbar_demux_008:sink_endofpacket
+ wire id_router_008_src_valid; // id_router_008:src_valid -> rsp_xbar_demux_008:sink_valid
+ wire id_router_008_src_startofpacket; // id_router_008:src_startofpacket -> rsp_xbar_demux_008:sink_startofpacket
+ wire [68:0] id_router_008_src_data; // id_router_008:src_data -> rsp_xbar_demux_008:sink_data
+ wire [7:0] id_router_008_src_channel; // id_router_008:src_channel -> rsp_xbar_demux_008:sink_channel
+ wire id_router_008_src_ready; // rsp_xbar_demux_008:sink_ready -> id_router_008:src_ready
+ wire cmd_xbar_demux_001_src7_ready; // tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src7_ready
+ wire id_router_009_src_endofpacket; // id_router_009:src_endofpacket -> rsp_xbar_demux_009:sink_endofpacket
+ wire id_router_009_src_valid; // id_router_009:src_valid -> rsp_xbar_demux_009:sink_valid
+ wire id_router_009_src_startofpacket; // id_router_009:src_startofpacket -> rsp_xbar_demux_009:sink_startofpacket
+ wire [68:0] id_router_009_src_data; // id_router_009:src_data -> rsp_xbar_demux_009:sink_data
+ wire [7:0] id_router_009_src_channel; // id_router_009:src_channel -> rsp_xbar_demux_009:sink_channel
+ wire id_router_009_src_ready; // rsp_xbar_demux_009:sink_ready -> id_router_009:src_ready
+ wire cmd_xbar_demux_002_src0_endofpacket; // cmd_xbar_demux_002:src0_endofpacket -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ wire cmd_xbar_demux_002_src0_valid; // cmd_xbar_demux_002:src0_valid -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:cp_valid
+ wire cmd_xbar_demux_002_src0_startofpacket; // cmd_xbar_demux_002:src0_startofpacket -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ wire [68:0] cmd_xbar_demux_002_src0_data; // cmd_xbar_demux_002:src0_data -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:cp_data
+ wire [6:0] cmd_xbar_demux_002_src0_channel; // cmd_xbar_demux_002:src0_channel -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:cp_channel
+ wire cmd_xbar_demux_002_src1_endofpacket; // cmd_xbar_demux_002:src1_endofpacket -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ wire cmd_xbar_demux_002_src1_valid; // cmd_xbar_demux_002:src1_valid -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:cp_valid
+ wire cmd_xbar_demux_002_src1_startofpacket; // cmd_xbar_demux_002:src1_startofpacket -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ wire [68:0] cmd_xbar_demux_002_src1_data; // cmd_xbar_demux_002:src1_data -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:cp_data
+ wire [6:0] cmd_xbar_demux_002_src1_channel; // cmd_xbar_demux_002:src1_channel -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:cp_channel
+ wire cmd_xbar_demux_002_src2_endofpacket; // cmd_xbar_demux_002:src2_endofpacket -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ wire cmd_xbar_demux_002_src2_valid; // cmd_xbar_demux_002:src2_valid -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:cp_valid
+ wire cmd_xbar_demux_002_src2_startofpacket; // cmd_xbar_demux_002:src2_startofpacket -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ wire [68:0] cmd_xbar_demux_002_src2_data; // cmd_xbar_demux_002:src2_data -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:cp_data
+ wire [6:0] cmd_xbar_demux_002_src2_channel; // cmd_xbar_demux_002:src2_channel -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:cp_channel
+ wire cmd_xbar_demux_002_src3_endofpacket; // cmd_xbar_demux_002:src3_endofpacket -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ wire cmd_xbar_demux_002_src3_valid; // cmd_xbar_demux_002:src3_valid -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:cp_valid
+ wire cmd_xbar_demux_002_src3_startofpacket; // cmd_xbar_demux_002:src3_startofpacket -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ wire [68:0] cmd_xbar_demux_002_src3_data; // cmd_xbar_demux_002:src3_data -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:cp_data
+ wire [6:0] cmd_xbar_demux_002_src3_channel; // cmd_xbar_demux_002:src3_channel -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:cp_channel
+ wire cmd_xbar_demux_002_src4_endofpacket; // cmd_xbar_demux_002:src4_endofpacket -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ wire cmd_xbar_demux_002_src4_valid; // cmd_xbar_demux_002:src4_valid -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:cp_valid
+ wire cmd_xbar_demux_002_src4_startofpacket; // cmd_xbar_demux_002:src4_startofpacket -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ wire [68:0] cmd_xbar_demux_002_src4_data; // cmd_xbar_demux_002:src4_data -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:cp_data
+ wire [6:0] cmd_xbar_demux_002_src4_channel; // cmd_xbar_demux_002:src4_channel -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:cp_channel
+ wire cmd_xbar_demux_002_src5_endofpacket; // cmd_xbar_demux_002:src5_endofpacket -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ wire cmd_xbar_demux_002_src5_valid; // cmd_xbar_demux_002:src5_valid -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:cp_valid
+ wire cmd_xbar_demux_002_src5_startofpacket; // cmd_xbar_demux_002:src5_startofpacket -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ wire [68:0] cmd_xbar_demux_002_src5_data; // cmd_xbar_demux_002:src5_data -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:cp_data
+ wire [6:0] cmd_xbar_demux_002_src5_channel; // cmd_xbar_demux_002:src5_channel -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:cp_channel
+ wire cmd_xbar_demux_002_src6_endofpacket; // cmd_xbar_demux_002:src6_endofpacket -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ wire cmd_xbar_demux_002_src6_valid; // cmd_xbar_demux_002:src6_valid -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:cp_valid
+ wire cmd_xbar_demux_002_src6_startofpacket; // cmd_xbar_demux_002:src6_startofpacket -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ wire [68:0] cmd_xbar_demux_002_src6_data; // cmd_xbar_demux_002:src6_data -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:cp_data
+ wire [6:0] cmd_xbar_demux_002_src6_channel; // cmd_xbar_demux_002:src6_channel -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:cp_channel
+ wire rsp_xbar_demux_010_src0_endofpacket; // rsp_xbar_demux_010:src0_endofpacket -> rsp_xbar_mux_002:sink0_endofpacket
+ wire rsp_xbar_demux_010_src0_valid; // rsp_xbar_demux_010:src0_valid -> rsp_xbar_mux_002:sink0_valid
+ wire rsp_xbar_demux_010_src0_startofpacket; // rsp_xbar_demux_010:src0_startofpacket -> rsp_xbar_mux_002:sink0_startofpacket
+ wire [68:0] rsp_xbar_demux_010_src0_data; // rsp_xbar_demux_010:src0_data -> rsp_xbar_mux_002:sink0_data
+ wire [6:0] rsp_xbar_demux_010_src0_channel; // rsp_xbar_demux_010:src0_channel -> rsp_xbar_mux_002:sink0_channel
+ wire rsp_xbar_demux_010_src0_ready; // rsp_xbar_mux_002:sink0_ready -> rsp_xbar_demux_010:src0_ready
+ wire rsp_xbar_demux_011_src0_endofpacket; // rsp_xbar_demux_011:src0_endofpacket -> rsp_xbar_mux_002:sink1_endofpacket
+ wire rsp_xbar_demux_011_src0_valid; // rsp_xbar_demux_011:src0_valid -> rsp_xbar_mux_002:sink1_valid
+ wire rsp_xbar_demux_011_src0_startofpacket; // rsp_xbar_demux_011:src0_startofpacket -> rsp_xbar_mux_002:sink1_startofpacket
+ wire [68:0] rsp_xbar_demux_011_src0_data; // rsp_xbar_demux_011:src0_data -> rsp_xbar_mux_002:sink1_data
+ wire [6:0] rsp_xbar_demux_011_src0_channel; // rsp_xbar_demux_011:src0_channel -> rsp_xbar_mux_002:sink1_channel
+ wire rsp_xbar_demux_011_src0_ready; // rsp_xbar_mux_002:sink1_ready -> rsp_xbar_demux_011:src0_ready
+ wire rsp_xbar_demux_012_src0_endofpacket; // rsp_xbar_demux_012:src0_endofpacket -> rsp_xbar_mux_002:sink2_endofpacket
+ wire rsp_xbar_demux_012_src0_valid; // rsp_xbar_demux_012:src0_valid -> rsp_xbar_mux_002:sink2_valid
+ wire rsp_xbar_demux_012_src0_startofpacket; // rsp_xbar_demux_012:src0_startofpacket -> rsp_xbar_mux_002:sink2_startofpacket
+ wire [68:0] rsp_xbar_demux_012_src0_data; // rsp_xbar_demux_012:src0_data -> rsp_xbar_mux_002:sink2_data
+ wire [6:0] rsp_xbar_demux_012_src0_channel; // rsp_xbar_demux_012:src0_channel -> rsp_xbar_mux_002:sink2_channel
+ wire rsp_xbar_demux_012_src0_ready; // rsp_xbar_mux_002:sink2_ready -> rsp_xbar_demux_012:src0_ready
+ wire rsp_xbar_demux_013_src0_endofpacket; // rsp_xbar_demux_013:src0_endofpacket -> rsp_xbar_mux_002:sink3_endofpacket
+ wire rsp_xbar_demux_013_src0_valid; // rsp_xbar_demux_013:src0_valid -> rsp_xbar_mux_002:sink3_valid
+ wire rsp_xbar_demux_013_src0_startofpacket; // rsp_xbar_demux_013:src0_startofpacket -> rsp_xbar_mux_002:sink3_startofpacket
+ wire [68:0] rsp_xbar_demux_013_src0_data; // rsp_xbar_demux_013:src0_data -> rsp_xbar_mux_002:sink3_data
+ wire [6:0] rsp_xbar_demux_013_src0_channel; // rsp_xbar_demux_013:src0_channel -> rsp_xbar_mux_002:sink3_channel
+ wire rsp_xbar_demux_013_src0_ready; // rsp_xbar_mux_002:sink3_ready -> rsp_xbar_demux_013:src0_ready
+ wire rsp_xbar_demux_014_src0_endofpacket; // rsp_xbar_demux_014:src0_endofpacket -> rsp_xbar_mux_002:sink4_endofpacket
+ wire rsp_xbar_demux_014_src0_valid; // rsp_xbar_demux_014:src0_valid -> rsp_xbar_mux_002:sink4_valid
+ wire rsp_xbar_demux_014_src0_startofpacket; // rsp_xbar_demux_014:src0_startofpacket -> rsp_xbar_mux_002:sink4_startofpacket
+ wire [68:0] rsp_xbar_demux_014_src0_data; // rsp_xbar_demux_014:src0_data -> rsp_xbar_mux_002:sink4_data
+ wire [6:0] rsp_xbar_demux_014_src0_channel; // rsp_xbar_demux_014:src0_channel -> rsp_xbar_mux_002:sink4_channel
+ wire rsp_xbar_demux_014_src0_ready; // rsp_xbar_mux_002:sink4_ready -> rsp_xbar_demux_014:src0_ready
+ wire rsp_xbar_demux_015_src0_endofpacket; // rsp_xbar_demux_015:src0_endofpacket -> rsp_xbar_mux_002:sink5_endofpacket
+ wire rsp_xbar_demux_015_src0_valid; // rsp_xbar_demux_015:src0_valid -> rsp_xbar_mux_002:sink5_valid
+ wire rsp_xbar_demux_015_src0_startofpacket; // rsp_xbar_demux_015:src0_startofpacket -> rsp_xbar_mux_002:sink5_startofpacket
+ wire [68:0] rsp_xbar_demux_015_src0_data; // rsp_xbar_demux_015:src0_data -> rsp_xbar_mux_002:sink5_data
+ wire [6:0] rsp_xbar_demux_015_src0_channel; // rsp_xbar_demux_015:src0_channel -> rsp_xbar_mux_002:sink5_channel
+ wire rsp_xbar_demux_015_src0_ready; // rsp_xbar_mux_002:sink5_ready -> rsp_xbar_demux_015:src0_ready
+ wire rsp_xbar_demux_016_src0_endofpacket; // rsp_xbar_demux_016:src0_endofpacket -> rsp_xbar_mux_002:sink6_endofpacket
+ wire rsp_xbar_demux_016_src0_valid; // rsp_xbar_demux_016:src0_valid -> rsp_xbar_mux_002:sink6_valid
+ wire rsp_xbar_demux_016_src0_startofpacket; // rsp_xbar_demux_016:src0_startofpacket -> rsp_xbar_mux_002:sink6_startofpacket
+ wire [68:0] rsp_xbar_demux_016_src0_data; // rsp_xbar_demux_016:src0_data -> rsp_xbar_mux_002:sink6_data
+ wire [6:0] rsp_xbar_demux_016_src0_channel; // rsp_xbar_demux_016:src0_channel -> rsp_xbar_mux_002:sink6_channel
+ wire rsp_xbar_demux_016_src0_ready; // rsp_xbar_mux_002:sink6_ready -> rsp_xbar_demux_016:src0_ready
+ wire limiter_002_cmd_src_endofpacket; // limiter_002:cmd_src_endofpacket -> cmd_xbar_demux_002:sink_endofpacket
+ wire limiter_002_cmd_src_startofpacket; // limiter_002:cmd_src_startofpacket -> cmd_xbar_demux_002:sink_startofpacket
+ wire [68:0] limiter_002_cmd_src_data; // limiter_002:cmd_src_data -> cmd_xbar_demux_002:sink_data
+ wire [6:0] limiter_002_cmd_src_channel; // limiter_002:cmd_src_channel -> cmd_xbar_demux_002:sink_channel
+ wire limiter_002_cmd_src_ready; // cmd_xbar_demux_002:sink_ready -> limiter_002:cmd_src_ready
+ wire rsp_xbar_mux_002_src_endofpacket; // rsp_xbar_mux_002:src_endofpacket -> limiter_002:rsp_sink_endofpacket
+ wire rsp_xbar_mux_002_src_valid; // rsp_xbar_mux_002:src_valid -> limiter_002:rsp_sink_valid
+ wire rsp_xbar_mux_002_src_startofpacket; // rsp_xbar_mux_002:src_startofpacket -> limiter_002:rsp_sink_startofpacket
+ wire [68:0] rsp_xbar_mux_002_src_data; // rsp_xbar_mux_002:src_data -> limiter_002:rsp_sink_data
+ wire [6:0] rsp_xbar_mux_002_src_channel; // rsp_xbar_mux_002:src_channel -> limiter_002:rsp_sink_channel
+ wire rsp_xbar_mux_002_src_ready; // limiter_002:rsp_sink_ready -> rsp_xbar_mux_002:src_ready
+ wire cmd_xbar_demux_002_src0_ready; // rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src0_ready
+ wire id_router_010_src_endofpacket; // id_router_010:src_endofpacket -> rsp_xbar_demux_010:sink_endofpacket
+ wire id_router_010_src_valid; // id_router_010:src_valid -> rsp_xbar_demux_010:sink_valid
+ wire id_router_010_src_startofpacket; // id_router_010:src_startofpacket -> rsp_xbar_demux_010:sink_startofpacket
+ wire [68:0] id_router_010_src_data; // id_router_010:src_data -> rsp_xbar_demux_010:sink_data
+ wire [6:0] id_router_010_src_channel; // id_router_010:src_channel -> rsp_xbar_demux_010:sink_channel
+ wire id_router_010_src_ready; // rsp_xbar_demux_010:sink_ready -> id_router_010:src_ready
+ wire cmd_xbar_demux_002_src1_ready; // rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src1_ready
+ wire id_router_011_src_endofpacket; // id_router_011:src_endofpacket -> rsp_xbar_demux_011:sink_endofpacket
+ wire id_router_011_src_valid; // id_router_011:src_valid -> rsp_xbar_demux_011:sink_valid
+ wire id_router_011_src_startofpacket; // id_router_011:src_startofpacket -> rsp_xbar_demux_011:sink_startofpacket
+ wire [68:0] id_router_011_src_data; // id_router_011:src_data -> rsp_xbar_demux_011:sink_data
+ wire [6:0] id_router_011_src_channel; // id_router_011:src_channel -> rsp_xbar_demux_011:sink_channel
+ wire id_router_011_src_ready; // rsp_xbar_demux_011:sink_ready -> id_router_011:src_ready
+ wire cmd_xbar_demux_002_src2_ready; // rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src2_ready
+ wire id_router_012_src_endofpacket; // id_router_012:src_endofpacket -> rsp_xbar_demux_012:sink_endofpacket
+ wire id_router_012_src_valid; // id_router_012:src_valid -> rsp_xbar_demux_012:sink_valid
+ wire id_router_012_src_startofpacket; // id_router_012:src_startofpacket -> rsp_xbar_demux_012:sink_startofpacket
+ wire [68:0] id_router_012_src_data; // id_router_012:src_data -> rsp_xbar_demux_012:sink_data
+ wire [6:0] id_router_012_src_channel; // id_router_012:src_channel -> rsp_xbar_demux_012:sink_channel
+ wire id_router_012_src_ready; // rsp_xbar_demux_012:sink_ready -> id_router_012:src_ready
+ wire cmd_xbar_demux_002_src3_ready; // rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src3_ready
+ wire id_router_013_src_endofpacket; // id_router_013:src_endofpacket -> rsp_xbar_demux_013:sink_endofpacket
+ wire id_router_013_src_valid; // id_router_013:src_valid -> rsp_xbar_demux_013:sink_valid
+ wire id_router_013_src_startofpacket; // id_router_013:src_startofpacket -> rsp_xbar_demux_013:sink_startofpacket
+ wire [68:0] id_router_013_src_data; // id_router_013:src_data -> rsp_xbar_demux_013:sink_data
+ wire [6:0] id_router_013_src_channel; // id_router_013:src_channel -> rsp_xbar_demux_013:sink_channel
+ wire id_router_013_src_ready; // rsp_xbar_demux_013:sink_ready -> id_router_013:src_ready
+ wire cmd_xbar_demux_002_src4_ready; // rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src4_ready
+ wire id_router_014_src_endofpacket; // id_router_014:src_endofpacket -> rsp_xbar_demux_014:sink_endofpacket
+ wire id_router_014_src_valid; // id_router_014:src_valid -> rsp_xbar_demux_014:sink_valid
+ wire id_router_014_src_startofpacket; // id_router_014:src_startofpacket -> rsp_xbar_demux_014:sink_startofpacket
+ wire [68:0] id_router_014_src_data; // id_router_014:src_data -> rsp_xbar_demux_014:sink_data
+ wire [6:0] id_router_014_src_channel; // id_router_014:src_channel -> rsp_xbar_demux_014:sink_channel
+ wire id_router_014_src_ready; // rsp_xbar_demux_014:sink_ready -> id_router_014:src_ready
+ wire cmd_xbar_demux_002_src5_ready; // rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src5_ready
+ wire id_router_015_src_endofpacket; // id_router_015:src_endofpacket -> rsp_xbar_demux_015:sink_endofpacket
+ wire id_router_015_src_valid; // id_router_015:src_valid -> rsp_xbar_demux_015:sink_valid
+ wire id_router_015_src_startofpacket; // id_router_015:src_startofpacket -> rsp_xbar_demux_015:sink_startofpacket
+ wire [68:0] id_router_015_src_data; // id_router_015:src_data -> rsp_xbar_demux_015:sink_data
+ wire [6:0] id_router_015_src_channel; // id_router_015:src_channel -> rsp_xbar_demux_015:sink_channel
+ wire id_router_015_src_ready; // rsp_xbar_demux_015:sink_ready -> id_router_015:src_ready
+ wire cmd_xbar_demux_002_src6_ready; // rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src6_ready
+ wire id_router_016_src_endofpacket; // id_router_016:src_endofpacket -> rsp_xbar_demux_016:sink_endofpacket
+ wire id_router_016_src_valid; // id_router_016:src_valid -> rsp_xbar_demux_016:sink_valid
+ wire id_router_016_src_startofpacket; // id_router_016:src_startofpacket -> rsp_xbar_demux_016:sink_startofpacket
+ wire [68:0] id_router_016_src_data; // id_router_016:src_data -> rsp_xbar_demux_016:sink_data
+ wire [6:0] id_router_016_src_channel; // id_router_016:src_channel -> rsp_xbar_demux_016:sink_channel
+ wire id_router_016_src_ready; // rsp_xbar_demux_016:sink_ready -> id_router_016:src_ready
+ wire crosser_out_endofpacket; // crosser:out_endofpacket -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ wire crosser_out_valid; // crosser:out_valid -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:cp_valid
+ wire crosser_out_startofpacket; // crosser:out_startofpacket -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ wire [65:0] crosser_out_data; // crosser:out_data -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:cp_data
+ wire [1:0] crosser_out_channel; // crosser:out_channel -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:cp_channel
+ wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> crosser:in_endofpacket
+ wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> crosser:in_valid
+ wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> crosser:in_startofpacket
+ wire [65:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> crosser:in_data
+ wire [1:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> crosser:in_channel
+ wire cmd_xbar_demux_src0_ready; // crosser:in_ready -> cmd_xbar_demux:src0_ready
+ wire crosser_001_out_endofpacket; // crosser_001:out_endofpacket -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ wire crosser_001_out_valid; // crosser_001:out_valid -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:cp_valid
+ wire crosser_001_out_startofpacket; // crosser_001:out_startofpacket -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ wire [65:0] crosser_001_out_data; // crosser_001:out_data -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:cp_data
+ wire [1:0] crosser_001_out_channel; // crosser_001:out_channel -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:cp_channel
+ wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> crosser_001:in_endofpacket
+ wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> crosser_001:in_valid
+ wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> crosser_001:in_startofpacket
+ wire [65:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> crosser_001:in_data
+ wire [1:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> crosser_001:in_channel
+ wire cmd_xbar_demux_src1_ready; // crosser_001:in_ready -> cmd_xbar_demux:src1_ready
+ wire crosser_002_out_endofpacket; // crosser_002:out_endofpacket -> rsp_xbar_mux:sink0_endofpacket
+ wire crosser_002_out_valid; // crosser_002:out_valid -> rsp_xbar_mux:sink0_valid
+ wire crosser_002_out_startofpacket; // crosser_002:out_startofpacket -> rsp_xbar_mux:sink0_startofpacket
+ wire [65:0] crosser_002_out_data; // crosser_002:out_data -> rsp_xbar_mux:sink0_data
+ wire [1:0] crosser_002_out_channel; // crosser_002:out_channel -> rsp_xbar_mux:sink0_channel
+ wire crosser_002_out_ready; // rsp_xbar_mux:sink0_ready -> crosser_002:out_ready
+ wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> crosser_002:in_endofpacket
+ wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> crosser_002:in_valid
+ wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> crosser_002:in_startofpacket
+ wire [65:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> crosser_002:in_data
+ wire [1:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> crosser_002:in_channel
+ wire rsp_xbar_demux_src0_ready; // crosser_002:in_ready -> rsp_xbar_demux:src0_ready
+ wire crosser_003_out_endofpacket; // crosser_003:out_endofpacket -> rsp_xbar_mux:sink1_endofpacket
+ wire crosser_003_out_valid; // crosser_003:out_valid -> rsp_xbar_mux:sink1_valid
+ wire crosser_003_out_startofpacket; // crosser_003:out_startofpacket -> rsp_xbar_mux:sink1_startofpacket
+ wire [65:0] crosser_003_out_data; // crosser_003:out_data -> rsp_xbar_mux:sink1_data
+ wire [1:0] crosser_003_out_channel; // crosser_003:out_channel -> rsp_xbar_mux:sink1_channel
+ wire crosser_003_out_ready; // rsp_xbar_mux:sink1_ready -> crosser_003:out_ready
+ wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> crosser_003:in_endofpacket
+ wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> crosser_003:in_valid
+ wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> crosser_003:in_startofpacket
+ wire [65:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> crosser_003:in_data
+ wire [1:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> crosser_003:in_channel
+ wire rsp_xbar_demux_001_src0_ready; // crosser_003:in_ready -> rsp_xbar_demux_001:src0_ready
+ wire [1:0] limiter_cmd_valid_data; // limiter:cmd_src_valid -> cmd_xbar_demux:sink_valid
+ wire [7:0] limiter_001_cmd_valid_data; // limiter_001:cmd_src_valid -> cmd_xbar_demux_001:sink_valid
+ wire [6:0] limiter_002_cmd_valid_data; // limiter_002:cmd_src_valid -> cmd_xbar_demux_002:sink_valid
+
+ altera_merlin_master_translator #(
+ .AV_ADDRESS_W (13),
+ .AV_DATA_W (32),
+ .AV_BURSTCOUNT_W (1),
+ .AV_BYTEENABLE_W (4),
+ .UAV_ADDRESS_W (15),
+ .UAV_BURSTCOUNT_W (3),
+ .USE_READ (1),
+ .USE_WRITE (1),
+ .USE_BEGINBURSTTRANSFER (0),
+ .USE_BEGINTRANSFER (0),
+ .USE_CHIPSELECT (0),
+ .USE_BURSTCOUNT (0),
+ .USE_READDATAVALID (0),
+ .USE_WAITREQUEST (1),
+ .AV_SYMBOLS_PER_WORD (4),
+ .AV_ADDRESS_SYMBOLS (0),
+ .AV_BURSTCOUNT_SYMBOLS (0),
+ .AV_CONSTANT_BURST_BEHAVIOR (0),
+ .UAV_CONSTANT_BURST_BEHAVIOR (0),
+ .AV_LINEWRAPBURSTS (0),
+ .AV_REGISTERINCOMINGSIGNALS (0)
+ ) merlin_master_translator (
+ .clk (csr_clk_clk), // clk.clk
+ .reset (rst_controller_reset_out_reset), // reset.reset
+ .uav_address (merlin_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
+ .uav_burstcount (merlin_master_translator_avalon_universal_master_0_burstcount), // .burstcount
+ .uav_read (merlin_master_translator_avalon_universal_master_0_read), // .read
+ .uav_write (merlin_master_translator_avalon_universal_master_0_write), // .write
+ .uav_waitrequest (merlin_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
+ .uav_readdatavalid (merlin_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
+ .uav_byteenable (merlin_master_translator_avalon_universal_master_0_byteenable), // .byteenable
+ .uav_readdata (merlin_master_translator_avalon_universal_master_0_readdata), // .readdata
+ .uav_writedata (merlin_master_translator_avalon_universal_master_0_writedata), // .writedata
+ .uav_lock (merlin_master_translator_avalon_universal_master_0_lock), // .lock
+ .uav_debugaccess (merlin_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
+ .av_address (csr_address), // avalon_anti_master_0.address
+ .av_waitrequest (csr_waitrequest), // .waitrequest
+ .av_read (csr_read), // .read
+ .av_readdata (csr_readdata), // .readdata
+ .av_write (csr_write), // .write
+ .av_writedata (csr_writedata), // .writedata
+ .av_burstcount (1'b1), // (terminated)
+ .av_byteenable (4'b1111), // (terminated)
+ .av_beginbursttransfer (1'b0), // (terminated)
+ .av_begintransfer (1'b0), // (terminated)
+ .av_chipselect (1'b0), // (terminated)
+ .av_readdatavalid (), // (terminated)
+ .av_lock (1'b0), // (terminated)
+ .av_debugaccess (1'b0), // (terminated)
+ .uav_clken (), // (terminated)
+ .av_clken (1'b1) // (terminated)
+ );
+
+ altera_avalon_mm_bridge #(
+ .DATA_WIDTH (32),
+ .SYMBOL_WIDTH (8),
+ .ADDRESS_WIDTH (14),
+ .BURSTCOUNT_WIDTH (1),
+ .PIPELINE_COMMAND (0),
+ .PIPELINE_RESPONSE (0)
+ ) tx_bridge (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // reset.reset
+ .s0_waitrequest (tx_bridge_s0_translator_avalon_anti_slave_0_waitrequest), // s0.waitrequest
+ .s0_readdata (tx_bridge_s0_translator_avalon_anti_slave_0_readdata), // .readdata
+ .s0_readdatavalid (tx_bridge_s0_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid
+ .s0_burstcount (tx_bridge_s0_translator_avalon_anti_slave_0_burstcount), // .burstcount
+ .s0_writedata (tx_bridge_s0_translator_avalon_anti_slave_0_writedata), // .writedata
+ .s0_address (tx_bridge_s0_translator_avalon_anti_slave_0_address), // .address
+ .s0_write (tx_bridge_s0_translator_avalon_anti_slave_0_write), // .write
+ .s0_read (tx_bridge_s0_translator_avalon_anti_slave_0_read), // .read
+ .s0_byteenable (tx_bridge_s0_translator_avalon_anti_slave_0_byteenable), // .byteenable
+ .s0_debugaccess (tx_bridge_s0_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
+ .m0_waitrequest (tx_bridge_m0_waitrequest), // m0.waitrequest
+ .m0_readdata (tx_bridge_m0_readdata), // .readdata
+ .m0_readdatavalid (tx_bridge_m0_readdatavalid), // .readdatavalid
+ .m0_burstcount (tx_bridge_m0_burstcount), // .burstcount
+ .m0_writedata (tx_bridge_m0_writedata), // .writedata
+ .m0_address (tx_bridge_m0_address), // .address
+ .m0_write (tx_bridge_m0_write), // .write
+ .m0_read (tx_bridge_m0_read), // .read
+ .m0_byteenable (tx_bridge_m0_byteenable), // .byteenable
+ .m0_debugaccess (tx_bridge_m0_debugaccess) // .debugaccess
+ );
+
+ altera_eth_packet_underflow_control #(
+ .BITSPERSYMBOL (8),
+ .SYMBOLSPERBEAT (8),
+ .ERROR_WIDTH (1)
+ ) tx_eth_packet_underflow_control (
+ .clk (tx_clk_clk), // clock_reset.clk
+ .reset (rst_controller_001_reset_out_reset), // clock_reset_reset.reset
+ .csr_readdata (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_anti_slave_0_readdata), // avalon_slave_0.readdata
+ .csr_read (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_anti_slave_0_read), // .read
+ .csr_address (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_anti_slave_0_address), // .address
+ .data_sink_sop (avalon_st_tx_startofpacket), // avalon_streaming_sink.startofpacket
+ .data_sink_valid (avalon_st_tx_valid), // .valid
+ .data_sink_data (avalon_st_tx_data), // .data
+ .data_sink_empty (avalon_st_tx_empty), // .empty
+ .data_sink_ready (avalon_st_tx_ready), // .ready
+ .data_sink_error (avalon_st_tx_error), // .error
+ .data_sink_eop (avalon_st_tx_endofpacket), // .endofpacket
+ .data_src_sop (tx_eth_packet_underflow_control_avalon_streaming_source_startofpacket), // avalon_streaming_source.startofpacket
+ .data_src_eop (tx_eth_packet_underflow_control_avalon_streaming_source_endofpacket), // .endofpacket
+ .data_src_valid (tx_eth_packet_underflow_control_avalon_streaming_source_valid), // .valid
+ .data_src_data (tx_eth_packet_underflow_control_avalon_streaming_source_data), // .data
+ .data_src_empty (tx_eth_packet_underflow_control_avalon_streaming_source_empty), // .empty
+ .data_src_ready (tx_eth_packet_underflow_control_avalon_streaming_source_ready), // .ready
+ .data_src_error (tx_eth_packet_underflow_control_avalon_streaming_source_error) // .error
+ );
+
+ altera_eth_pad_inserter #(
+ .SYMBOLSPERBEAT (8),
+ .ERROR_WIDTH (2)
+ ) tx_eth_pad_inserter (
+ .clk (tx_clk_clk), // clock_reset.clk
+ .reset (rst_controller_001_reset_out_reset), // clock_reset_reset.reset
+ .csr_write (tx_eth_pad_inserter_csr_translator_avalon_anti_slave_0_write), // csr.write
+ .csr_read (tx_eth_pad_inserter_csr_translator_avalon_anti_slave_0_read), // .read
+ .csr_address (tx_eth_pad_inserter_csr_translator_avalon_anti_slave_0_address), // .address
+ .csr_writedata (tx_eth_pad_inserter_csr_translator_avalon_anti_slave_0_writedata), // .writedata
+ .csr_readdata (tx_eth_pad_inserter_csr_translator_avalon_anti_slave_0_readdata), // .readdata
+ .data_src_sop (tx_eth_pad_inserter_avalon_st_source_data_startofpacket), // avalon_st_source_data.startofpacket
+ .data_src_eop (tx_eth_pad_inserter_avalon_st_source_data_endofpacket), // .endofpacket
+ .data_src_valid (tx_eth_pad_inserter_avalon_st_source_data_valid), // .valid
+ .data_src_ready (tx_eth_pad_inserter_avalon_st_source_data_ready), // .ready
+ .data_src_data (tx_eth_pad_inserter_avalon_st_source_data_data), // .data
+ .data_src_empty (tx_eth_pad_inserter_avalon_st_source_data_empty), // .empty
+ .data_src_error (tx_eth_pad_inserter_avalon_st_source_data_error), // .error
+ .data_sink_sop (tx_eth_packet_underflow_control_avalon_streaming_source_startofpacket), // avalon_st_sink_data.startofpacket
+ .data_sink_eop (tx_eth_packet_underflow_control_avalon_streaming_source_endofpacket), // .endofpacket
+ .data_sink_valid (tx_eth_packet_underflow_control_avalon_streaming_source_valid), // .valid
+ .data_sink_ready (tx_eth_packet_underflow_control_avalon_streaming_source_ready), // .ready
+ .data_sink_data (tx_eth_packet_underflow_control_avalon_streaming_source_data), // .data
+ .data_sink_empty (tx_eth_packet_underflow_control_avalon_streaming_source_empty), // .empty
+ .data_sink_error (tx_eth_packet_underflow_control_avalon_streaming_source_error) // .error
+ );
+
+ altera_eth_pkt_backpressure_control #(
+ .BITSPERSYMBOL (8),
+ .SYMBOLSPERBEAT (8),
+ .ERROR_WIDTH (2),
+ .USE_READY (1)
+ ) tx_eth_pkt_backpressure_control (
+ .clk (tx_clk_clk), // clock_reset.clk
+ .reset (rst_controller_001_reset_out_reset), // clock_reset_reset.reset
+ .csr_write (tx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_write), // csr.write
+ .csr_read (tx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_read), // .read
+ .csr_address (tx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_address), // .address
+ .csr_writedata (tx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_writedata), // .writedata
+ .csr_readdata (tx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_readdata), // .readdata
+ .data_src_sop (tx_eth_pkt_backpressure_control_avalon_st_source_data_startofpacket), // avalon_st_source_data.startofpacket
+ .data_src_eop (tx_eth_pkt_backpressure_control_avalon_st_source_data_endofpacket), // .endofpacket
+ .data_src_valid (tx_eth_pkt_backpressure_control_avalon_st_source_data_valid), // .valid
+ .data_src_ready (tx_eth_pkt_backpressure_control_avalon_st_source_data_ready), // .ready
+ .data_src_data (tx_eth_pkt_backpressure_control_avalon_st_source_data_data), // .data
+ .data_src_empty (tx_eth_pkt_backpressure_control_avalon_st_source_data_empty), // .empty
+ .data_src_error (tx_eth_pkt_backpressure_control_avalon_st_source_data_error), // .error
+ .data_sink_sop (tx_eth_pad_inserter_avalon_st_source_data_startofpacket), // avalon_st_sink_data.startofpacket
+ .data_sink_eop (tx_eth_pad_inserter_avalon_st_source_data_endofpacket), // .endofpacket
+ .data_sink_valid (tx_eth_pad_inserter_avalon_st_source_data_valid), // .valid
+ .data_sink_ready (tx_eth_pad_inserter_avalon_st_source_data_ready), // .ready
+ .data_sink_data (tx_eth_pad_inserter_avalon_st_source_data_data), // .data
+ .data_sink_empty (tx_eth_pad_inserter_avalon_st_source_data_empty), // .empty
+ .data_sink_error (tx_eth_pad_inserter_avalon_st_source_data_error), // .error
+ .pausebeats_sink_valid (tx_eth_pause_beat_conversion_pause_beat_src_valid), // avalon_st_pause.valid
+ .pausebeats_sink_data (tx_eth_pause_beat_conversion_pause_beat_src_data) // .data
+ );
+
+ altera_eth_pause_beat_conversion tx_eth_pause_beat_conversion (
+ .clk (tx_clk_clk), // clock_reset.clk
+ .reset (rst_controller_001_reset_out_reset), // clock_reset_reset.reset
+ .pause_quanta_sink_valid (rxtx_timing_adapter_pauselen_tx_out_valid), // pause_quanta_sink.valid
+ .pause_quanta_sink_data (rxtx_timing_adapter_pauselen_tx_out_data), // .data
+ .pause_beat_src_valid (tx_eth_pause_beat_conversion_pause_beat_src_valid), // pause_beat_src.valid
+ .pause_beat_src_data (tx_eth_pause_beat_conversion_pause_beat_src_data) // .data
+ );
+
+ altera_eth_pause_ctrl_gen #(
+ .BITSPERSYMBOL (8),
+ .SYMBOLSPERBEAT (8),
+ .ERROR_WIDTH (1)
+ ) tx_eth_pause_ctrl_gen (
+ .clk (tx_clk_clk), // clock_reset.clk
+ .reset (rst_controller_001_reset_out_reset), // clock_reset_reset.reset
+ .csr_address (tx_eth_pause_ctrl_gen_csr_translator_avalon_anti_slave_0_address), // csr.address
+ .csr_read (tx_eth_pause_ctrl_gen_csr_translator_avalon_anti_slave_0_read), // .read
+ .csr_readdata (tx_eth_pause_ctrl_gen_csr_translator_avalon_anti_slave_0_readdata), // .readdata
+ .csr_write (tx_eth_pause_ctrl_gen_csr_translator_avalon_anti_slave_0_write), // .write
+ .csr_writedata (tx_eth_pause_ctrl_gen_csr_translator_avalon_anti_slave_0_writedata), // .writedata
+ .pause_ctrl_sink_data (avalon_st_pause_data), // pause_control.data
+ .pause_source_sop (tx_eth_pause_ctrl_gen_pause_packet_startofpacket), // pause_packet.startofpacket
+ .pause_source_eop (tx_eth_pause_ctrl_gen_pause_packet_endofpacket), // .endofpacket
+ .pause_source_valid (tx_eth_pause_ctrl_gen_pause_packet_valid), // .valid
+ .pause_source_data (tx_eth_pause_ctrl_gen_pause_packet_data), // .data
+ .pause_source_empty (tx_eth_pause_ctrl_gen_pause_packet_empty), // .empty
+ .pause_source_error (tx_eth_pause_ctrl_gen_pause_packet_error), // .error
+ .pause_source_ready (tx_eth_pause_ctrl_gen_pause_packet_ready) // .ready
+ );
+
+ ip_stratixiv_mac_10g_tx_st_pause_ctrl_error_adapter tx_st_pause_ctrl_error_adapter (
+ .clk (tx_clk_clk), // clk.clk
+ .reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
+ .in_ready (tx_eth_pause_ctrl_gen_pause_packet_ready), // in.ready
+ .in_valid (tx_eth_pause_ctrl_gen_pause_packet_valid), // .valid
+ .in_data (tx_eth_pause_ctrl_gen_pause_packet_data), // .data
+ .in_error (tx_eth_pause_ctrl_gen_pause_packet_error), // .error
+ .in_startofpacket (tx_eth_pause_ctrl_gen_pause_packet_startofpacket), // .startofpacket
+ .in_endofpacket (tx_eth_pause_ctrl_gen_pause_packet_endofpacket), // .endofpacket
+ .in_empty (tx_eth_pause_ctrl_gen_pause_packet_empty), // .empty
+ .out_ready (tx_st_pause_ctrl_error_adapter_out_ready), // out.ready
+ .out_valid (tx_st_pause_ctrl_error_adapter_out_valid), // .valid
+ .out_data (tx_st_pause_ctrl_error_adapter_out_data), // .data
+ .out_error (tx_st_pause_ctrl_error_adapter_out_error), // .error
+ .out_startofpacket (tx_st_pause_ctrl_error_adapter_out_startofpacket), // .startofpacket
+ .out_endofpacket (tx_st_pause_ctrl_error_adapter_out_endofpacket), // .endofpacket
+ .out_empty (tx_st_pause_ctrl_error_adapter_out_empty) // .empty
+ );
+
+ ip_stratixiv_mac_10g_tx_st_mux_flow_control_user_frame tx_st_mux_flow_control_user_frame (
+ .clk (tx_clk_clk), // clk.clk
+ .reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
+ .in0_valid (tx_eth_pkt_backpressure_control_avalon_st_source_data_valid), // in0.valid
+ .in0_ready (tx_eth_pkt_backpressure_control_avalon_st_source_data_ready), // .ready
+ .in0_data (tx_eth_pkt_backpressure_control_avalon_st_source_data_data), // .data
+ .in0_error (tx_eth_pkt_backpressure_control_avalon_st_source_data_error), // .error
+ .in0_startofpacket (tx_eth_pkt_backpressure_control_avalon_st_source_data_startofpacket), // .startofpacket
+ .in0_endofpacket (tx_eth_pkt_backpressure_control_avalon_st_source_data_endofpacket), // .endofpacket
+ .in0_empty (tx_eth_pkt_backpressure_control_avalon_st_source_data_empty), // .empty
+ .in1_valid (tx_st_pause_ctrl_error_adapter_out_valid), // in1.valid
+ .in1_ready (tx_st_pause_ctrl_error_adapter_out_ready), // .ready
+ .in1_data (tx_st_pause_ctrl_error_adapter_out_data), // .data
+ .in1_error (tx_st_pause_ctrl_error_adapter_out_error), // .error
+ .in1_startofpacket (tx_st_pause_ctrl_error_adapter_out_startofpacket), // .startofpacket
+ .in1_endofpacket (tx_st_pause_ctrl_error_adapter_out_endofpacket), // .endofpacket
+ .in1_empty (tx_st_pause_ctrl_error_adapter_out_empty), // .empty
+ .out_channel (), // out.channel
+ .out_valid (tx_st_mux_flow_control_user_frame_out_valid), // .valid
+ .out_ready (tx_st_mux_flow_control_user_frame_out_ready), // .ready
+ .out_data (tx_st_mux_flow_control_user_frame_out_data), // .data
+ .out_error (tx_st_mux_flow_control_user_frame_out_error), // .error
+ .out_startofpacket (tx_st_mux_flow_control_user_frame_out_startofpacket), // .startofpacket
+ .out_endofpacket (tx_st_mux_flow_control_user_frame_out_endofpacket), // .endofpacket
+ .out_empty (tx_st_mux_flow_control_user_frame_out_empty) // .empty
+ );
+
+ altera_eth_address_inserter #(
+ .BITSPERSYMBOL (8),
+ .SYMBOLSPERBEAT (8),
+ .ERROR_WIDTH (2)
+ ) tx_eth_address_inserter (
+ .clk (tx_clk_clk), // clock_reset.clk
+ .reset (rst_controller_001_reset_out_reset), // clock_reset_reset.reset
+ .csr_write (tx_eth_address_inserter_csr_translator_avalon_anti_slave_0_write), // csr.write
+ .csr_read (tx_eth_address_inserter_csr_translator_avalon_anti_slave_0_read), // .read
+ .csr_address (tx_eth_address_inserter_csr_translator_avalon_anti_slave_0_address), // .address
+ .csr_writedata (tx_eth_address_inserter_csr_translator_avalon_anti_slave_0_writedata), // .writedata
+ .csr_readdata (tx_eth_address_inserter_csr_translator_avalon_anti_slave_0_readdata), // .readdata
+ .data_sink_sop (tx_st_mux_flow_control_user_frame_out_startofpacket), // avalon_streaming_sink.startofpacket
+ .data_sink_eop (tx_st_mux_flow_control_user_frame_out_endofpacket), // .endofpacket
+ .data_sink_valid (tx_st_mux_flow_control_user_frame_out_valid), // .valid
+ .data_sink_ready (tx_st_mux_flow_control_user_frame_out_ready), // .ready
+ .data_sink_data (tx_st_mux_flow_control_user_frame_out_data), // .data
+ .data_sink_empty (tx_st_mux_flow_control_user_frame_out_empty), // .empty
+ .data_sink_error (tx_st_mux_flow_control_user_frame_out_error), // .error
+ .data_src_sop (tx_eth_address_inserter_avalon_streaming_source_startofpacket), // avalon_streaming_source.startofpacket
+ .data_src_eop (tx_eth_address_inserter_avalon_streaming_source_endofpacket), // .endofpacket
+ .data_src_valid (tx_eth_address_inserter_avalon_streaming_source_valid), // .valid
+ .data_src_ready (tx_eth_address_inserter_avalon_streaming_source_ready), // .ready
+ .data_src_data (tx_eth_address_inserter_avalon_streaming_source_data), // .data
+ .data_src_empty (tx_eth_address_inserter_avalon_streaming_source_empty), // .empty
+ .data_src_error (tx_eth_address_inserter_avalon_streaming_source_error) // .error
+ );
+
+ altera_eth_crc #(
+ .BITSPERSYMBOL (8),
+ .SYMBOLSPERBEAT (8),
+ .ERROR_WIDTH (2),
+ .MODE_CHECKER_0_INSERTER_1 (1)
+ ) tx_eth_crc_inserter (
+ .clk (tx_clk_clk), // clock_reset.clk
+ .reset (rst_controller_001_reset_out_reset), // clock_reset_reset.reset
+ .csr_write (tx_eth_crc_inserter_csr_translator_avalon_anti_slave_0_write), // csr.write
+ .csr_read (tx_eth_crc_inserter_csr_translator_avalon_anti_slave_0_read), // .read
+ .csr_address (tx_eth_crc_inserter_csr_translator_avalon_anti_slave_0_address), // .address
+ .csr_writedata (tx_eth_crc_inserter_csr_translator_avalon_anti_slave_0_writedata), // .writedata
+ .csr_readdata (tx_eth_crc_inserter_csr_translator_avalon_anti_slave_0_readdata), // .readdata
+ .data_sink_sop (tx_eth_address_inserter_avalon_streaming_source_startofpacket), // avalon_streaming_sink.startofpacket
+ .data_sink_eop (tx_eth_address_inserter_avalon_streaming_source_endofpacket), // .endofpacket
+ .data_sink_valid (tx_eth_address_inserter_avalon_streaming_source_valid), // .valid
+ .data_sink_ready (tx_eth_address_inserter_avalon_streaming_source_ready), // .ready
+ .data_sink_data (tx_eth_address_inserter_avalon_streaming_source_data), // .data
+ .data_sink_empty (tx_eth_address_inserter_avalon_streaming_source_empty), // .empty
+ .data_sink_error (tx_eth_address_inserter_avalon_streaming_source_error), // .error
+ .data_src_sop (tx_eth_crc_inserter_avalon_streaming_source_startofpacket), // avalon_streaming_source.startofpacket
+ .data_src_eop (tx_eth_crc_inserter_avalon_streaming_source_endofpacket), // .endofpacket
+ .data_src_valid (tx_eth_crc_inserter_avalon_streaming_source_valid), // .valid
+ .data_src_ready (tx_eth_crc_inserter_avalon_streaming_source_ready), // .ready
+ .data_src_data (tx_eth_crc_inserter_avalon_streaming_source_data), // .data
+ .data_src_empty (tx_eth_crc_inserter_avalon_streaming_source_empty), // .empty
+ .data_src_error (tx_eth_crc_inserter_avalon_streaming_source_error) // .error
+ );
+
+ altera_avalon_st_pipeline_stage #(
+ .SYMBOLS_PER_BEAT (8),
+ .BITS_PER_SYMBOL (8),
+ .USE_PACKETS (1),
+ .USE_EMPTY (1),
+ .EMPTY_WIDTH (3),
+ .CHANNEL_WIDTH (0),
+ .PACKET_WIDTH (2),
+ .ERROR_WIDTH (3),
+ .PIPELINE_READY (1)
+ ) tx_st_pipeline_stage_rs (
+ .clk (tx_clk_clk), // cr0.clk
+ .reset (rst_controller_001_reset_out_reset), // cr0_reset.reset
+ .in_ready (tx_eth_crc_inserter_avalon_streaming_source_ready), // sink0.ready
+ .in_valid (tx_eth_crc_inserter_avalon_streaming_source_valid), // .valid
+ .in_startofpacket (tx_eth_crc_inserter_avalon_streaming_source_startofpacket), // .startofpacket
+ .in_endofpacket (tx_eth_crc_inserter_avalon_streaming_source_endofpacket), // .endofpacket
+ .in_empty (tx_eth_crc_inserter_avalon_streaming_source_empty), // .empty
+ .in_error (tx_eth_crc_inserter_avalon_streaming_source_error), // .error
+ .in_data (tx_eth_crc_inserter_avalon_streaming_source_data), // .data
+ .out_ready (tx_st_pipeline_stage_rs_source0_ready), // source0.ready
+ .out_valid (tx_st_pipeline_stage_rs_source0_valid), // .valid
+ .out_startofpacket (tx_st_pipeline_stage_rs_source0_startofpacket), // .startofpacket
+ .out_endofpacket (tx_st_pipeline_stage_rs_source0_endofpacket), // .endofpacket
+ .out_empty (tx_st_pipeline_stage_rs_source0_empty), // .empty
+ .out_error (tx_st_pipeline_stage_rs_source0_error), // .error
+ .out_data (tx_st_pipeline_stage_rs_source0_data), // .data
+ .out_channel (), // (terminated)
+ .in_channel (1'b0) // (terminated)
+ );
+
+ altera_avalon_st_splitter #(
+ .NUMBER_OF_OUTPUTS (2),
+ .QUALIFY_VALID_OUT (1),
+ .USE_PACKETS (1),
+ .DATA_WIDTH (64),
+ .CHANNEL_WIDTH (1),
+ .ERROR_WIDTH (3),
+ .BITS_PER_SYMBOL (8),
+ .EMPTY_WIDTH (3)
+ ) tx_st_splitter_1 (
+ .clk (tx_clk_clk), // clk.clk
+ .in0_ready (tx_st_pipeline_stage_rs_source0_ready), // in.ready
+ .in0_valid (tx_st_pipeline_stage_rs_source0_valid), // .valid
+ .in0_startofpacket (tx_st_pipeline_stage_rs_source0_startofpacket), // .startofpacket
+ .in0_endofpacket (tx_st_pipeline_stage_rs_source0_endofpacket), // .endofpacket
+ .in0_empty (tx_st_pipeline_stage_rs_source0_empty), // .empty
+ .in0_error (tx_st_pipeline_stage_rs_source0_error), // .error
+ .in0_data (tx_st_pipeline_stage_rs_source0_data), // .data
+ .out0_ready (tx_st_splitter_1_out0_ready), // out0.ready
+ .out0_valid (tx_st_splitter_1_out0_valid), // .valid
+ .out0_startofpacket (tx_st_splitter_1_out0_startofpacket), // .startofpacket
+ .out0_endofpacket (tx_st_splitter_1_out0_endofpacket), // .endofpacket
+ .out0_empty (tx_st_splitter_1_out0_empty), // .empty
+ .out0_error (tx_st_splitter_1_out0_error), // .error
+ .out0_data (tx_st_splitter_1_out0_data), // .data
+ .out1_ready (tx_st_splitter_1_out1_ready), // out1.ready
+ .out1_valid (tx_st_splitter_1_out1_valid), // .valid
+ .out1_startofpacket (tx_st_splitter_1_out1_startofpacket), // .startofpacket
+ .out1_endofpacket (tx_st_splitter_1_out1_endofpacket), // .endofpacket
+ .out1_empty (tx_st_splitter_1_out1_empty), // .empty
+ .out1_error (tx_st_splitter_1_out1_error), // .error
+ .out1_data (tx_st_splitter_1_out1_data), // .data
+ .in0_channel (1'b0), // (terminated)
+ .out0_channel (), // (terminated)
+ .out1_channel (), // (terminated)
+ .out2_ready (1'b1), // (terminated)
+ .out2_valid (), // (terminated)
+ .out2_startofpacket (), // (terminated)
+ .out2_endofpacket (), // (terminated)
+ .out2_empty (), // (terminated)
+ .out2_channel (), // (terminated)
+ .out2_error (), // (terminated)
+ .out2_data (), // (terminated)
+ .out3_ready (1'b1), // (terminated)
+ .out3_valid (), // (terminated)
+ .out3_startofpacket (), // (terminated)
+ .out3_endofpacket (), // (terminated)
+ .out3_empty (), // (terminated)
+ .out3_channel (), // (terminated)
+ .out3_error (), // (terminated)
+ .out3_data (), // (terminated)
+ .out4_ready (1'b1), // (terminated)
+ .out4_valid (), // (terminated)
+ .out4_startofpacket (), // (terminated)
+ .out4_endofpacket (), // (terminated)
+ .out4_empty (), // (terminated)
+ .out4_channel (), // (terminated)
+ .out4_error (), // (terminated)
+ .out4_data (), // (terminated)
+ .out5_ready (1'b1), // (terminated)
+ .out5_valid (), // (terminated)
+ .out5_startofpacket (), // (terminated)
+ .out5_endofpacket (), // (terminated)
+ .out5_empty (), // (terminated)
+ .out5_channel (), // (terminated)
+ .out5_error (), // (terminated)
+ .out5_data (), // (terminated)
+ .out6_ready (1'b1), // (terminated)
+ .out6_valid (), // (terminated)
+ .out6_startofpacket (), // (terminated)
+ .out6_endofpacket (), // (terminated)
+ .out6_empty (), // (terminated)
+ .out6_channel (), // (terminated)
+ .out6_error (), // (terminated)
+ .out6_data (), // (terminated)
+ .out7_ready (1'b1), // (terminated)
+ .out7_valid (), // (terminated)
+ .out7_startofpacket (), // (terminated)
+ .out7_endofpacket (), // (terminated)
+ .out7_empty (), // (terminated)
+ .out7_channel (), // (terminated)
+ .out7_error (), // (terminated)
+ .out7_data (), // (terminated)
+ .out8_ready (1'b1), // (terminated)
+ .out8_valid (), // (terminated)
+ .out8_startofpacket (), // (terminated)
+ .out8_endofpacket (), // (terminated)
+ .out8_empty (), // (terminated)
+ .out8_channel (), // (terminated)
+ .out8_error (), // (terminated)
+ .out8_data (), // (terminated)
+ .out9_ready (1'b1), // (terminated)
+ .out9_valid (), // (terminated)
+ .out9_startofpacket (), // (terminated)
+ .out9_endofpacket (), // (terminated)
+ .out9_empty (), // (terminated)
+ .out9_channel (), // (terminated)
+ .out9_error (), // (terminated)
+ .out9_data (), // (terminated)
+ .out10_ready (1'b1), // (terminated)
+ .out10_valid (), // (terminated)
+ .out10_startofpacket (), // (terminated)
+ .out10_endofpacket (), // (terminated)
+ .out10_empty (), // (terminated)
+ .out10_channel (), // (terminated)
+ .out10_error (), // (terminated)
+ .out10_data (), // (terminated)
+ .out11_ready (1'b1), // (terminated)
+ .out11_valid (), // (terminated)
+ .out11_startofpacket (), // (terminated)
+ .out11_endofpacket (), // (terminated)
+ .out11_empty (), // (terminated)
+ .out11_channel (), // (terminated)
+ .out11_error (), // (terminated)
+ .out11_data (), // (terminated)
+ .out12_ready (1'b1), // (terminated)
+ .out12_valid (), // (terminated)
+ .out12_startofpacket (), // (terminated)
+ .out12_endofpacket (), // (terminated)
+ .out12_empty (), // (terminated)
+ .out12_channel (), // (terminated)
+ .out12_error (), // (terminated)
+ .out12_data (), // (terminated)
+ .out13_ready (1'b1), // (terminated)
+ .out13_valid (), // (terminated)
+ .out13_startofpacket (), // (terminated)
+ .out13_endofpacket (), // (terminated)
+ .out13_empty (), // (terminated)
+ .out13_channel (), // (terminated)
+ .out13_error (), // (terminated)
+ .out13_data (), // (terminated)
+ .out14_ready (1'b1), // (terminated)
+ .out14_valid (), // (terminated)
+ .out14_startofpacket (), // (terminated)
+ .out14_endofpacket (), // (terminated)
+ .out14_empty (), // (terminated)
+ .out14_channel (), // (terminated)
+ .out14_error (), // (terminated)
+ .out14_data (), // (terminated)
+ .out15_ready (1'b1), // (terminated)
+ .out15_valid (), // (terminated)
+ .out15_startofpacket (), // (terminated)
+ .out15_endofpacket (), // (terminated)
+ .out15_empty (), // (terminated)
+ .out15_channel (), // (terminated)
+ .out15_error (), // (terminated)
+ .out15_data () // (terminated)
+ );
+
+ ip_stratixiv_mac_10g_tx_st_timing_adapter_frame_decoder tx_st_timing_adapter_frame_decoder (
+ .clk (tx_clk_clk), // clk.clk
+ .reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
+ .in_ready (tx_st_splitter_1_out0_ready), // in.ready
+ .in_valid (tx_st_splitter_1_out0_valid), // .valid
+ .in_data (tx_st_splitter_1_out0_data), // .data
+ .in_error (tx_st_splitter_1_out0_error), // .error
+ .in_startofpacket (tx_st_splitter_1_out0_startofpacket), // .startofpacket
+ .in_endofpacket (tx_st_splitter_1_out0_endofpacket), // .endofpacket
+ .in_empty (tx_st_splitter_1_out0_empty), // .empty
+ .out_valid (tx_st_timing_adapter_frame_decoder_out_valid), // out.valid
+ .out_data (tx_st_timing_adapter_frame_decoder_out_data), // .data
+ .out_error (tx_st_timing_adapter_frame_decoder_out_error), // .error
+ .out_startofpacket (tx_st_timing_adapter_frame_decoder_out_startofpacket), // .startofpacket
+ .out_endofpacket (tx_st_timing_adapter_frame_decoder_out_endofpacket), // .endofpacket
+ .out_empty (tx_st_timing_adapter_frame_decoder_out_empty) // .empty
+ );
+
+ altera_eth_frame_decoder #(
+ .BITSPERSYMBOL (8),
+ .SYMBOLSPERBEAT (8),
+ .ERROR_WIDTH (3),
+ .ENABLE_SUPP_ADDR (0),
+ .ENABLE_PFC (0),
+ .PFC_PRIORITY_NUM (8)
+ ) tx_eth_frame_decoder (
+ .clk (tx_clk_clk), // clock_reset.clk
+ .reset (rst_controller_001_reset_out_reset), // clock_reset_reset.reset
+ .csr_readdata (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_readdata), // avalom_mm_csr.readdata
+ .csr_write (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_write), // .write
+ .csr_read (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_read), // .read
+ .csr_address (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_address), // .address
+ .csr_writedata (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_writedata), // .writedata
+ .data_sink_sop (tx_st_timing_adapter_frame_decoder_out_startofpacket), // avalon_st_data_sink.startofpacket
+ .data_sink_eop (tx_st_timing_adapter_frame_decoder_out_endofpacket), // .endofpacket
+ .data_sink_valid (tx_st_timing_adapter_frame_decoder_out_valid), // .valid
+ .data_sink_data (tx_st_timing_adapter_frame_decoder_out_data), // .data
+ .data_sink_empty (tx_st_timing_adapter_frame_decoder_out_empty), // .empty
+ .data_sink_error (tx_st_timing_adapter_frame_decoder_out_error), // .error
+ .rxstatus_src_valid (tx_eth_frame_decoder_avalon_st_rxstatus_src_valid), // avalon_st_rxstatus_src.valid
+ .rxstatus_src_data (tx_eth_frame_decoder_avalon_st_rxstatus_src_data), // .data
+ .rxstatus_src_error (tx_eth_frame_decoder_avalon_st_rxstatus_src_error), // .error
+ .data_sink_ready (), // (terminated)
+ .data_src_sop (), // (terminated)
+ .data_src_eop (), // (terminated)
+ .data_src_valid (), // (terminated)
+ .data_src_ready (1'b1), // (terminated)
+ .data_src_data (), // (terminated)
+ .data_src_empty (), // (terminated)
+ .data_src_error (), // (terminated)
+ .pauselen_src_valid (), // (terminated)
+ .pauselen_src_data (), // (terminated)
+ .pfc_pause_quanta_src_valid (), // (terminated)
+ .pfc_pause_quanta_src_data (), // (terminated)
+ .pfc_status_src_valid (), // (terminated)
+ .pfc_status_src_data (), // (terminated)
+ .pktinfo_src_valid (), // (terminated)
+ .pktinfo_src_data () // (terminated)
+ );
+
+ ip_stratixiv_mac_10g_tx_st_error_adapter_stat tx_st_error_adapter_stat (
+ .clk (tx_clk_clk), // clk.clk
+ .reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
+ .in_valid (tx_eth_frame_decoder_avalon_st_rxstatus_src_valid), // in.valid
+ .in_data (tx_eth_frame_decoder_avalon_st_rxstatus_src_data), // .data
+ .in_error (tx_eth_frame_decoder_avalon_st_rxstatus_src_error), // .error
+ .out_valid (tx_st_error_adapter_stat_out_valid), // out.valid
+ .out_data (tx_st_error_adapter_stat_out_data), // .data
+ .out_error (tx_st_error_adapter_stat_out_error) // .error
+ );
+
+ ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_in tx_st_timing_adapter_splitter_status_in (
+ .clk (tx_clk_clk), // clk.clk
+ .reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
+ .in_valid (tx_st_error_adapter_stat_out_valid), // in.valid
+ .in_data (tx_st_error_adapter_stat_out_data), // .data
+ .in_error (tx_st_error_adapter_stat_out_error), // .error
+ .out_valid (tx_st_timing_adapter_splitter_status_in_out_valid), // out.valid
+ .out_data (tx_st_timing_adapter_splitter_status_in_out_data), // .data
+ .out_error (tx_st_timing_adapter_splitter_status_in_out_error), // .error
+ .out_ready (tx_st_timing_adapter_splitter_status_in_out_ready) // .ready
+ );
+
+ ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_output tx_st_timing_adapter_splitter_status_output (
+ .clk (tx_clk_clk), // clk.clk
+ .reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
+ .in_ready (tx_st_status_splitter_out1_ready), // in.ready
+ .in_valid (tx_st_status_splitter_out1_valid), // .valid
+ .in_data (tx_st_status_splitter_out1_data), // .data
+ .in_error (tx_st_status_splitter_out1_error), // .error
+ .out_valid (avalon_st_txstatus_valid), // out.valid
+ .out_data (avalon_st_txstatus_data), // .data
+ .out_error (avalon_st_txstatus_error) // .error
+ );
+
+ altera_avalon_st_splitter #(
+ .NUMBER_OF_OUTPUTS (2),
+ .QUALIFY_VALID_OUT (1),
+ .USE_PACKETS (0),
+ .DATA_WIDTH (40),
+ .CHANNEL_WIDTH (1),
+ .ERROR_WIDTH (7),
+ .BITS_PER_SYMBOL (40),
+ .EMPTY_WIDTH (1)
+ ) tx_st_status_splitter (
+ .clk (tx_clk_clk), // clk.clk
+ .in0_ready (tx_st_timing_adapter_splitter_status_in_out_ready), // in.ready
+ .in0_valid (tx_st_timing_adapter_splitter_status_in_out_valid), // .valid
+ .in0_error (tx_st_timing_adapter_splitter_status_in_out_error), // .error
+ .in0_data (tx_st_timing_adapter_splitter_status_in_out_data), // .data
+ .out0_ready (tx_st_status_splitter_out0_ready), // out0.ready
+ .out0_valid (tx_st_status_splitter_out0_valid), // .valid
+ .out0_error (tx_st_status_splitter_out0_error), // .error
+ .out0_data (tx_st_status_splitter_out0_data), // .data
+ .out1_ready (tx_st_status_splitter_out1_ready), // out1.ready
+ .out1_valid (tx_st_status_splitter_out1_valid), // .valid
+ .out1_error (tx_st_status_splitter_out1_error), // .error
+ .out1_data (tx_st_status_splitter_out1_data), // .data
+ .in0_startofpacket (1'b0), // (terminated)
+ .in0_endofpacket (1'b0), // (terminated)
+ .in0_empty (1'b0), // (terminated)
+ .in0_channel (1'b0), // (terminated)
+ .out0_startofpacket (), // (terminated)
+ .out0_endofpacket (), // (terminated)
+ .out0_empty (), // (terminated)
+ .out0_channel (), // (terminated)
+ .out1_startofpacket (), // (terminated)
+ .out1_endofpacket (), // (terminated)
+ .out1_empty (), // (terminated)
+ .out1_channel (), // (terminated)
+ .out2_ready (1'b1), // (terminated)
+ .out2_valid (), // (terminated)
+ .out2_startofpacket (), // (terminated)
+ .out2_endofpacket (), // (terminated)
+ .out2_empty (), // (terminated)
+ .out2_channel (), // (terminated)
+ .out2_error (), // (terminated)
+ .out2_data (), // (terminated)
+ .out3_ready (1'b1), // (terminated)
+ .out3_valid (), // (terminated)
+ .out3_startofpacket (), // (terminated)
+ .out3_endofpacket (), // (terminated)
+ .out3_empty (), // (terminated)
+ .out3_channel (), // (terminated)
+ .out3_error (), // (terminated)
+ .out3_data (), // (terminated)
+ .out4_ready (1'b1), // (terminated)
+ .out4_valid (), // (terminated)
+ .out4_startofpacket (), // (terminated)
+ .out4_endofpacket (), // (terminated)
+ .out4_empty (), // (terminated)
+ .out4_channel (), // (terminated)
+ .out4_error (), // (terminated)
+ .out4_data (), // (terminated)
+ .out5_ready (1'b1), // (terminated)
+ .out5_valid (), // (terminated)
+ .out5_startofpacket (), // (terminated)
+ .out5_endofpacket (), // (terminated)
+ .out5_empty (), // (terminated)
+ .out5_channel (), // (terminated)
+ .out5_error (), // (terminated)
+ .out5_data (), // (terminated)
+ .out6_ready (1'b1), // (terminated)
+ .out6_valid (), // (terminated)
+ .out6_startofpacket (), // (terminated)
+ .out6_endofpacket (), // (terminated)
+ .out6_empty (), // (terminated)
+ .out6_channel (), // (terminated)
+ .out6_error (), // (terminated)
+ .out6_data (), // (terminated)
+ .out7_ready (1'b1), // (terminated)
+ .out7_valid (), // (terminated)
+ .out7_startofpacket (), // (terminated)
+ .out7_endofpacket (), // (terminated)
+ .out7_empty (), // (terminated)
+ .out7_channel (), // (terminated)
+ .out7_error (), // (terminated)
+ .out7_data (), // (terminated)
+ .out8_ready (1'b1), // (terminated)
+ .out8_valid (), // (terminated)
+ .out8_startofpacket (), // (terminated)
+ .out8_endofpacket (), // (terminated)
+ .out8_empty (), // (terminated)
+ .out8_channel (), // (terminated)
+ .out8_error (), // (terminated)
+ .out8_data (), // (terminated)
+ .out9_ready (1'b1), // (terminated)
+ .out9_valid (), // (terminated)
+ .out9_startofpacket (), // (terminated)
+ .out9_endofpacket (), // (terminated)
+ .out9_empty (), // (terminated)
+ .out9_channel (), // (terminated)
+ .out9_error (), // (terminated)
+ .out9_data (), // (terminated)
+ .out10_ready (1'b1), // (terminated)
+ .out10_valid (), // (terminated)
+ .out10_startofpacket (), // (terminated)
+ .out10_endofpacket (), // (terminated)
+ .out10_empty (), // (terminated)
+ .out10_channel (), // (terminated)
+ .out10_error (), // (terminated)
+ .out10_data (), // (terminated)
+ .out11_ready (1'b1), // (terminated)
+ .out11_valid (), // (terminated)
+ .out11_startofpacket (), // (terminated)
+ .out11_endofpacket (), // (terminated)
+ .out11_empty (), // (terminated)
+ .out11_channel (), // (terminated)
+ .out11_error (), // (terminated)
+ .out11_data (), // (terminated)
+ .out12_ready (1'b1), // (terminated)
+ .out12_valid (), // (terminated)
+ .out12_startofpacket (), // (terminated)
+ .out12_endofpacket (), // (terminated)
+ .out12_empty (), // (terminated)
+ .out12_channel (), // (terminated)
+ .out12_error (), // (terminated)
+ .out12_data (), // (terminated)
+ .out13_ready (1'b1), // (terminated)
+ .out13_valid (), // (terminated)
+ .out13_startofpacket (), // (terminated)
+ .out13_endofpacket (), // (terminated)
+ .out13_empty (), // (terminated)
+ .out13_channel (), // (terminated)
+ .out13_error (), // (terminated)
+ .out13_data (), // (terminated)
+ .out14_ready (1'b1), // (terminated)
+ .out14_valid (), // (terminated)
+ .out14_startofpacket (), // (terminated)
+ .out14_endofpacket (), // (terminated)
+ .out14_empty (), // (terminated)
+ .out14_channel (), // (terminated)
+ .out14_error (), // (terminated)
+ .out14_data (), // (terminated)
+ .out15_ready (1'b1), // (terminated)
+ .out15_valid (), // (terminated)
+ .out15_startofpacket (), // (terminated)
+ .out15_endofpacket (), // (terminated)
+ .out15_empty (), // (terminated)
+ .out15_channel (), // (terminated)
+ .out15_error (), // (terminated)
+ .out15_data () // (terminated)
+ );
+
+ ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_output tx_st_timing_adapter_splitter_status_statistics (
+ .clk (tx_clk_clk), // clk.clk
+ .reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
+ .in_ready (tx_st_status_splitter_out0_ready), // in.ready
+ .in_valid (tx_st_status_splitter_out0_valid), // .valid
+ .in_data (tx_st_status_splitter_out0_data), // .data
+ .in_error (tx_st_status_splitter_out0_error), // .error
+ .out_valid (tx_st_timing_adapter_splitter_status_statistics_out_valid), // out.valid
+ .out_data (tx_st_timing_adapter_splitter_status_statistics_out_data), // .data
+ .out_error (tx_st_timing_adapter_splitter_status_statistics_out_error) // .error
+ );
+
+ altera_eth_10gmem_statistics_collector #(
+ .ENABLE_PFC (0)
+ ) tx_eth_statistics_collector (
+ .clk (tx_clk_clk), // clock_reset.clk
+ .reset (rst_controller_001_reset_out_reset), // clock_reset_reset.reset
+ .csr_read (tx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_read), // csr.read
+ .csr_address (tx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_address), // .address
+ .csr_readdata (tx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_readdata), // .readdata
+ .csr_write (tx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_write), // .write
+ .csr_writedata (tx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_writedata), // .writedata
+ .stat_sink_valid (tx_st_timing_adapter_splitter_status_statistics_out_valid), // avalon_st_sink_data.valid
+ .stat_sink_data (tx_st_timing_adapter_splitter_status_statistics_out_data), // .data
+ .stat_sink_error (tx_st_timing_adapter_splitter_status_statistics_out_error) // .error
+ );
+
+ altera_eth_packet_formatter #(
+ .ERROR_WIDTH (3)
+ ) tx_eth_packet_formatter (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .data_sink_data (tx_st_splitter_1_out1_data), // data_sink.data
+ .data_sink_sop (tx_st_splitter_1_out1_startofpacket), // .startofpacket
+ .data_sink_eop (tx_st_splitter_1_out1_endofpacket), // .endofpacket
+ .data_sink_empty (tx_st_splitter_1_out1_empty), // .empty
+ .data_sink_error (tx_st_splitter_1_out1_error), // .error
+ .data_sink_valid (tx_st_splitter_1_out1_valid), // .valid
+ .data_sink_ready (tx_st_splitter_1_out1_ready), // .ready
+ .data_src_data (tx_eth_packet_formatter_data_src_data), // data_src.data
+ .data_src_sop (tx_eth_packet_formatter_data_src_startofpacket), // .startofpacket
+ .data_src_eop (tx_eth_packet_formatter_data_src_endofpacket), // .endofpacket
+ .data_src_empty (tx_eth_packet_formatter_data_src_empty), // .empty
+ .data_src_valid (tx_eth_packet_formatter_data_src_valid), // .valid
+ .data_src_ready (tx_eth_packet_formatter_data_src_ready), // .ready
+ .data_sink_data_preamble (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
+ .data_sink_valid_preamble (1'b0), // (terminated)
+ .data_sink_ready_preamble () // (terminated)
+ );
+
+ altera_eth_xgmii_termination tx_eth_xgmii_termination (
+ .clk (tx_clk_clk), // clock_reset.clk
+ .reset (rst_controller_001_reset_out_reset), // clock_reset_reset.reset
+ .xgmii_src_data (tx_eth_xgmii_termination_avalon_streaming_source_data), // avalon_streaming_source.data
+ .data_sink_sop (tx_eth_packet_formatter_data_src_startofpacket), // avalon_streaming_sink.startofpacket
+ .data_sink_eop (tx_eth_packet_formatter_data_src_endofpacket), // .endofpacket
+ .data_sink_valid (tx_eth_packet_formatter_data_src_valid), // .valid
+ .data_sink_data (tx_eth_packet_formatter_data_src_data), // .data
+ .data_sink_empty (tx_eth_packet_formatter_data_src_empty), // .empty
+ .data_sink_ready (tx_eth_packet_formatter_data_src_ready) // .ready
+ );
+
+ altera_eth_link_fault_generation tx_eth_link_fault_generation (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .mii_sink_data (tx_eth_xgmii_termination_avalon_streaming_source_data), // mii_sink.data
+ .mii_src_data (xgmii_tx_data), // mii_src.data
+ .link_fault_sink_data (rxtx_timing_adapter_link_fault_status_tx_out_data) // link_fault_sink.data
+ );
+
+ altera_avalon_mm_bridge #(
+ .DATA_WIDTH (32),
+ .SYMBOL_WIDTH (8),
+ .ADDRESS_WIDTH (14),
+ .BURSTCOUNT_WIDTH (1),
+ .PIPELINE_COMMAND (0),
+ .PIPELINE_RESPONSE (0)
+ ) rx_bridge (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // reset.reset
+ .s0_waitrequest (rx_bridge_s0_translator_avalon_anti_slave_0_waitrequest), // s0.waitrequest
+ .s0_readdata (rx_bridge_s0_translator_avalon_anti_slave_0_readdata), // .readdata
+ .s0_readdatavalid (rx_bridge_s0_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid
+ .s0_burstcount (rx_bridge_s0_translator_avalon_anti_slave_0_burstcount), // .burstcount
+ .s0_writedata (rx_bridge_s0_translator_avalon_anti_slave_0_writedata), // .writedata
+ .s0_address (rx_bridge_s0_translator_avalon_anti_slave_0_address), // .address
+ .s0_write (rx_bridge_s0_translator_avalon_anti_slave_0_write), // .write
+ .s0_read (rx_bridge_s0_translator_avalon_anti_slave_0_read), // .read
+ .s0_byteenable (rx_bridge_s0_translator_avalon_anti_slave_0_byteenable), // .byteenable
+ .s0_debugaccess (rx_bridge_s0_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
+ .m0_waitrequest (rx_bridge_m0_waitrequest), // m0.waitrequest
+ .m0_readdata (rx_bridge_m0_readdata), // .readdata
+ .m0_readdatavalid (rx_bridge_m0_readdatavalid), // .readdatavalid
+ .m0_burstcount (rx_bridge_m0_burstcount), // .burstcount
+ .m0_writedata (rx_bridge_m0_writedata), // .writedata
+ .m0_address (rx_bridge_m0_address), // .address
+ .m0_write (rx_bridge_m0_write), // .write
+ .m0_read (rx_bridge_m0_read), // .read
+ .m0_byteenable (rx_bridge_m0_byteenable), // .byteenable
+ .m0_debugaccess (rx_bridge_m0_debugaccess) // .debugaccess
+ );
+
+ ip_stratixiv_mac_10g_rx_st_timing_adapter_interface_conversion rx_st_timing_adapter_interface_conversion (
+ .clk (rx_clk_clk), // clk.clk
+ .reset_n (~rst_controller_002_reset_out_reset), // reset.reset_n
+ .in_data (xgmii_rx_data), // in.data
+ .out_data (rx_st_timing_adapter_interface_conversion_out_data), // out.data
+ .out_ready (rx_st_timing_adapter_interface_conversion_out_ready), // .ready
+ .out_valid (rx_st_timing_adapter_interface_conversion_out_valid) // .valid
+ );
+
+ altera_avalon_st_splitter #(
+ .NUMBER_OF_OUTPUTS (2),
+ .QUALIFY_VALID_OUT (1),
+ .USE_PACKETS (0),
+ .DATA_WIDTH (72),
+ .CHANNEL_WIDTH (1),
+ .ERROR_WIDTH (1),
+ .BITS_PER_SYMBOL (9),
+ .EMPTY_WIDTH (3)
+ ) rx_st_splitter_xgmii (
+ .clk (rx_clk_clk), // clk.clk
+ .in0_ready (rx_st_timing_adapter_interface_conversion_out_ready), // in.ready
+ .in0_valid (rx_st_timing_adapter_interface_conversion_out_valid), // .valid
+ .in0_data (rx_st_timing_adapter_interface_conversion_out_data), // .data
+ .out0_ready (rx_st_splitter_xgmii_out0_ready), // out0.ready
+ .out0_valid (rx_st_splitter_xgmii_out0_valid), // .valid
+ .out0_data (rx_st_splitter_xgmii_out0_data), // .data
+ .out1_ready (rx_st_splitter_xgmii_out1_ready), // out1.ready
+ .out1_valid (rx_st_splitter_xgmii_out1_valid), // .valid
+ .out1_data (rx_st_splitter_xgmii_out1_data), // .data
+ .in0_startofpacket (1'b0), // (terminated)
+ .in0_endofpacket (1'b0), // (terminated)
+ .in0_empty (3'b000), // (terminated)
+ .in0_channel (1'b0), // (terminated)
+ .in0_error (1'b0), // (terminated)
+ .out0_startofpacket (), // (terminated)
+ .out0_endofpacket (), // (terminated)
+ .out0_empty (), // (terminated)
+ .out0_channel (), // (terminated)
+ .out0_error (), // (terminated)
+ .out1_startofpacket (), // (terminated)
+ .out1_endofpacket (), // (terminated)
+ .out1_empty (), // (terminated)
+ .out1_channel (), // (terminated)
+ .out1_error (), // (terminated)
+ .out2_ready (1'b1), // (terminated)
+ .out2_valid (), // (terminated)
+ .out2_startofpacket (), // (terminated)
+ .out2_endofpacket (), // (terminated)
+ .out2_empty (), // (terminated)
+ .out2_channel (), // (terminated)
+ .out2_error (), // (terminated)
+ .out2_data (), // (terminated)
+ .out3_ready (1'b1), // (terminated)
+ .out3_valid (), // (terminated)
+ .out3_startofpacket (), // (terminated)
+ .out3_endofpacket (), // (terminated)
+ .out3_empty (), // (terminated)
+ .out3_channel (), // (terminated)
+ .out3_error (), // (terminated)
+ .out3_data (), // (terminated)
+ .out4_ready (1'b1), // (terminated)
+ .out4_valid (), // (terminated)
+ .out4_startofpacket (), // (terminated)
+ .out4_endofpacket (), // (terminated)
+ .out4_empty (), // (terminated)
+ .out4_channel (), // (terminated)
+ .out4_error (), // (terminated)
+ .out4_data (), // (terminated)
+ .out5_ready (1'b1), // (terminated)
+ .out5_valid (), // (terminated)
+ .out5_startofpacket (), // (terminated)
+ .out5_endofpacket (), // (terminated)
+ .out5_empty (), // (terminated)
+ .out5_channel (), // (terminated)
+ .out5_error (), // (terminated)
+ .out5_data (), // (terminated)
+ .out6_ready (1'b1), // (terminated)
+ .out6_valid (), // (terminated)
+ .out6_startofpacket (), // (terminated)
+ .out6_endofpacket (), // (terminated)
+ .out6_empty (), // (terminated)
+ .out6_channel (), // (terminated)
+ .out6_error (), // (terminated)
+ .out6_data (), // (terminated)
+ .out7_ready (1'b1), // (terminated)
+ .out7_valid (), // (terminated)
+ .out7_startofpacket (), // (terminated)
+ .out7_endofpacket (), // (terminated)
+ .out7_empty (), // (terminated)
+ .out7_channel (), // (terminated)
+ .out7_error (), // (terminated)
+ .out7_data (), // (terminated)
+ .out8_ready (1'b1), // (terminated)
+ .out8_valid (), // (terminated)
+ .out8_startofpacket (), // (terminated)
+ .out8_endofpacket (), // (terminated)
+ .out8_empty (), // (terminated)
+ .out8_channel (), // (terminated)
+ .out8_error (), // (terminated)
+ .out8_data (), // (terminated)
+ .out9_ready (1'b1), // (terminated)
+ .out9_valid (), // (terminated)
+ .out9_startofpacket (), // (terminated)
+ .out9_endofpacket (), // (terminated)
+ .out9_empty (), // (terminated)
+ .out9_channel (), // (terminated)
+ .out9_error (), // (terminated)
+ .out9_data (), // (terminated)
+ .out10_ready (1'b1), // (terminated)
+ .out10_valid (), // (terminated)
+ .out10_startofpacket (), // (terminated)
+ .out10_endofpacket (), // (terminated)
+ .out10_empty (), // (terminated)
+ .out10_channel (), // (terminated)
+ .out10_error (), // (terminated)
+ .out10_data (), // (terminated)
+ .out11_ready (1'b1), // (terminated)
+ .out11_valid (), // (terminated)
+ .out11_startofpacket (), // (terminated)
+ .out11_endofpacket (), // (terminated)
+ .out11_empty (), // (terminated)
+ .out11_channel (), // (terminated)
+ .out11_error (), // (terminated)
+ .out11_data (), // (terminated)
+ .out12_ready (1'b1), // (terminated)
+ .out12_valid (), // (terminated)
+ .out12_startofpacket (), // (terminated)
+ .out12_endofpacket (), // (terminated)
+ .out12_empty (), // (terminated)
+ .out12_channel (), // (terminated)
+ .out12_error (), // (terminated)
+ .out12_data (), // (terminated)
+ .out13_ready (1'b1), // (terminated)
+ .out13_valid (), // (terminated)
+ .out13_startofpacket (), // (terminated)
+ .out13_endofpacket (), // (terminated)
+ .out13_empty (), // (terminated)
+ .out13_channel (), // (terminated)
+ .out13_error (), // (terminated)
+ .out13_data (), // (terminated)
+ .out14_ready (1'b1), // (terminated)
+ .out14_valid (), // (terminated)
+ .out14_startofpacket (), // (terminated)
+ .out14_endofpacket (), // (terminated)
+ .out14_empty (), // (terminated)
+ .out14_channel (), // (terminated)
+ .out14_error (), // (terminated)
+ .out14_data (), // (terminated)
+ .out15_ready (1'b1), // (terminated)
+ .out15_valid (), // (terminated)
+ .out15_startofpacket (), // (terminated)
+ .out15_endofpacket (), // (terminated)
+ .out15_empty (), // (terminated)
+ .out15_channel (), // (terminated)
+ .out15_error (), // (terminated)
+ .out15_data () // (terminated)
+ );
+
+ ip_stratixiv_mac_10g_rx_st_timing_adapter_lane_decoder rx_st_timing_adapter_lane_decoder (
+ .clk (rx_clk_clk), // clk.clk
+ .reset_n (~rst_controller_002_reset_out_reset), // reset.reset_n
+ .in_ready (rx_st_splitter_xgmii_out0_ready), // in.ready
+ .in_valid (rx_st_splitter_xgmii_out0_valid), // .valid
+ .in_data (rx_st_splitter_xgmii_out0_data), // .data
+ .out_data (rx_st_timing_adapter_lane_decoder_out_data) // out.data
+ );
+
+ ip_stratixiv_mac_10g_rx_st_timing_adapter_lane_decoder rx_st_timing_adapter_link_fault_detection (
+ .clk (rx_clk_clk), // clk.clk
+ .reset_n (~rst_controller_002_reset_out_reset), // reset.reset_n
+ .in_ready (rx_st_splitter_xgmii_out1_ready), // in.ready
+ .in_valid (rx_st_splitter_xgmii_out1_valid), // .valid
+ .in_data (rx_st_splitter_xgmii_out1_data), // .data
+ .out_data (rx_st_timing_adapter_link_fault_detection_out_data) // out.data
+ );
+
+ altera_eth_link_fault_detection rx_eth_link_fault_detection (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .mii_sink_data (rx_st_timing_adapter_link_fault_detection_out_data), // mii_sink.data
+ .link_fault_src_data (rx_eth_link_fault_detection_link_fault_src_data) // link_fault_src.data
+ );
+
+ altera_eth_lane_decoder rx_eth_lane_decoder (
+ .clk (rx_clk_clk), // clock_reset.clk
+ .reset (rst_controller_002_reset_out_reset), // clock_reset_reset.reset
+ .xgmii_sink_data (rx_st_timing_adapter_lane_decoder_out_data), // avalon_streaming_sink.data
+ .rxdata_src_eop (rx_eth_lane_decoder_avalon_streaming_source_endofpacket), // avalon_streaming_source.endofpacket
+ .rxdata_src_sop (rx_eth_lane_decoder_avalon_streaming_source_startofpacket), // .startofpacket
+ .rxdata_src_valid (rx_eth_lane_decoder_avalon_streaming_source_valid), // .valid
+ .rxdata_src_data (rx_eth_lane_decoder_avalon_streaming_source_data), // .data
+ .rxdata_src_empty (rx_eth_lane_decoder_avalon_streaming_source_empty), // .empty
+ .rxdata_src_error (rx_eth_lane_decoder_avalon_streaming_source_error), // .error
+ .csr_read (rx_eth_lane_decoder_csr_translator_avalon_anti_slave_0_read), // csr.read
+ .csr_write (rx_eth_lane_decoder_csr_translator_avalon_anti_slave_0_write), // .write
+ .csr_address (rx_eth_lane_decoder_csr_translator_avalon_anti_slave_0_address), // .address
+ .csr_writedata (rx_eth_lane_decoder_csr_translator_avalon_anti_slave_0_writedata), // .writedata
+ .csr_readdata (rx_eth_lane_decoder_csr_translator_avalon_anti_slave_0_readdata), // .readdata
+ .preamble_valid (), // (terminated)
+ .preamble_bytes () // (terminated)
+ );
+
+ altera_eth_pkt_backpressure_control #(
+ .BITSPERSYMBOL (8),
+ .SYMBOLSPERBEAT (8),
+ .ERROR_WIDTH (1),
+ .USE_READY (0)
+ ) rx_eth_pkt_backpressure_control (
+ .clk (rx_clk_clk), // clock_reset.clk
+ .reset (rst_controller_002_reset_out_reset), // clock_reset_reset.reset
+ .csr_write (rx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_write), // csr.write
+ .csr_read (rx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_read), // .read
+ .csr_address (rx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_address), // .address
+ .csr_writedata (rx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_writedata), // .writedata
+ .csr_readdata (rx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_readdata), // .readdata
+ .data_src_sop (rx_eth_pkt_backpressure_control_avalon_st_source_data_startofpacket), // avalon_st_source_data.startofpacket
+ .data_src_eop (rx_eth_pkt_backpressure_control_avalon_st_source_data_endofpacket), // .endofpacket
+ .data_src_valid (rx_eth_pkt_backpressure_control_avalon_st_source_data_valid), // .valid
+ .data_src_data (rx_eth_pkt_backpressure_control_avalon_st_source_data_data), // .data
+ .data_src_empty (rx_eth_pkt_backpressure_control_avalon_st_source_data_empty), // .empty
+ .data_src_error (rx_eth_pkt_backpressure_control_avalon_st_source_data_error), // .error
+ .data_sink_sop (rx_eth_lane_decoder_avalon_streaming_source_startofpacket), // avalon_st_sink_data.startofpacket
+ .data_sink_eop (rx_eth_lane_decoder_avalon_streaming_source_endofpacket), // .endofpacket
+ .data_sink_valid (rx_eth_lane_decoder_avalon_streaming_source_valid), // .valid
+ .data_sink_data (rx_eth_lane_decoder_avalon_streaming_source_data), // .data
+ .data_sink_empty (rx_eth_lane_decoder_avalon_streaming_source_empty), // .empty
+ .data_sink_error (rx_eth_lane_decoder_avalon_streaming_source_error), // .error
+ .data_src_ready (1'b1), // (terminated)
+ .data_sink_ready (), // (terminated)
+ .pausebeats_sink_valid (1'b0), // (terminated)
+ .pausebeats_sink_data (32'b00000000000000000000000000000000) // (terminated)
+ );
+
+ ip_stratixiv_mac_10g_rx_st_timing_adapter_frame_status_in rx_st_timing_adapter_frame_status_in (
+ .clk (rx_clk_clk), // clk.clk
+ .reset_n (~rst_controller_002_reset_out_reset), // reset.reset_n
+ .in_valid (rx_eth_pkt_backpressure_control_avalon_st_source_data_valid), // in.valid
+ .in_data (rx_eth_pkt_backpressure_control_avalon_st_source_data_data), // .data
+ .in_error (rx_eth_pkt_backpressure_control_avalon_st_source_data_error), // .error
+ .in_startofpacket (rx_eth_pkt_backpressure_control_avalon_st_source_data_startofpacket), // .startofpacket
+ .in_endofpacket (rx_eth_pkt_backpressure_control_avalon_st_source_data_endofpacket), // .endofpacket
+ .in_empty (rx_eth_pkt_backpressure_control_avalon_st_source_data_empty), // .empty
+ .out_valid (rx_st_timing_adapter_frame_status_in_out_valid), // out.valid
+ .out_data (rx_st_timing_adapter_frame_status_in_out_data), // .data
+ .out_error (rx_st_timing_adapter_frame_status_in_out_error), // .error
+ .out_startofpacket (rx_st_timing_adapter_frame_status_in_out_startofpacket), // .startofpacket
+ .out_endofpacket (rx_st_timing_adapter_frame_status_in_out_endofpacket), // .endofpacket
+ .out_empty (rx_st_timing_adapter_frame_status_in_out_empty), // .empty
+ .out_ready (rx_st_timing_adapter_frame_status_in_out_ready) // .ready
+ );
+
+ altera_avalon_st_splitter #(
+ .NUMBER_OF_OUTPUTS (2),
+ .QUALIFY_VALID_OUT (1),
+ .USE_PACKETS (1),
+ .DATA_WIDTH (64),
+ .CHANNEL_WIDTH (1),
+ .ERROR_WIDTH (1),
+ .BITS_PER_SYMBOL (8),
+ .EMPTY_WIDTH (3)
+ ) rx_st_frame_status_splitter (
+ .clk (rx_clk_clk), // clk.clk
+ .in0_ready (rx_st_timing_adapter_frame_status_in_out_ready), // in.ready
+ .in0_valid (rx_st_timing_adapter_frame_status_in_out_valid), // .valid
+ .in0_startofpacket (rx_st_timing_adapter_frame_status_in_out_startofpacket), // .startofpacket
+ .in0_endofpacket (rx_st_timing_adapter_frame_status_in_out_endofpacket), // .endofpacket
+ .in0_empty (rx_st_timing_adapter_frame_status_in_out_empty), // .empty
+ .in0_error (rx_st_timing_adapter_frame_status_in_out_error), // .error
+ .in0_data (rx_st_timing_adapter_frame_status_in_out_data), // .data
+ .out0_ready (rx_st_frame_status_splitter_out0_ready), // out0.ready
+ .out0_valid (rx_st_frame_status_splitter_out0_valid), // .valid
+ .out0_startofpacket (rx_st_frame_status_splitter_out0_startofpacket), // .startofpacket
+ .out0_endofpacket (rx_st_frame_status_splitter_out0_endofpacket), // .endofpacket
+ .out0_empty (rx_st_frame_status_splitter_out0_empty), // .empty
+ .out0_error (rx_st_frame_status_splitter_out0_error), // .error
+ .out0_data (rx_st_frame_status_splitter_out0_data), // .data
+ .out1_ready (rx_st_frame_status_splitter_out1_ready), // out1.ready
+ .out1_valid (rx_st_frame_status_splitter_out1_valid), // .valid
+ .out1_startofpacket (rx_st_frame_status_splitter_out1_startofpacket), // .startofpacket
+ .out1_endofpacket (rx_st_frame_status_splitter_out1_endofpacket), // .endofpacket
+ .out1_empty (rx_st_frame_status_splitter_out1_empty), // .empty
+ .out1_error (rx_st_frame_status_splitter_out1_error), // .error
+ .out1_data (rx_st_frame_status_splitter_out1_data), // .data
+ .in0_channel (1'b0), // (terminated)
+ .out0_channel (), // (terminated)
+ .out1_channel (), // (terminated)
+ .out2_ready (1'b1), // (terminated)
+ .out2_valid (), // (terminated)
+ .out2_startofpacket (), // (terminated)
+ .out2_endofpacket (), // (terminated)
+ .out2_empty (), // (terminated)
+ .out2_channel (), // (terminated)
+ .out2_error (), // (terminated)
+ .out2_data (), // (terminated)
+ .out3_ready (1'b1), // (terminated)
+ .out3_valid (), // (terminated)
+ .out3_startofpacket (), // (terminated)
+ .out3_endofpacket (), // (terminated)
+ .out3_empty (), // (terminated)
+ .out3_channel (), // (terminated)
+ .out3_error (), // (terminated)
+ .out3_data (), // (terminated)
+ .out4_ready (1'b1), // (terminated)
+ .out4_valid (), // (terminated)
+ .out4_startofpacket (), // (terminated)
+ .out4_endofpacket (), // (terminated)
+ .out4_empty (), // (terminated)
+ .out4_channel (), // (terminated)
+ .out4_error (), // (terminated)
+ .out4_data (), // (terminated)
+ .out5_ready (1'b1), // (terminated)
+ .out5_valid (), // (terminated)
+ .out5_startofpacket (), // (terminated)
+ .out5_endofpacket (), // (terminated)
+ .out5_empty (), // (terminated)
+ .out5_channel (), // (terminated)
+ .out5_error (), // (terminated)
+ .out5_data (), // (terminated)
+ .out6_ready (1'b1), // (terminated)
+ .out6_valid (), // (terminated)
+ .out6_startofpacket (), // (terminated)
+ .out6_endofpacket (), // (terminated)
+ .out6_empty (), // (terminated)
+ .out6_channel (), // (terminated)
+ .out6_error (), // (terminated)
+ .out6_data (), // (terminated)
+ .out7_ready (1'b1), // (terminated)
+ .out7_valid (), // (terminated)
+ .out7_startofpacket (), // (terminated)
+ .out7_endofpacket (), // (terminated)
+ .out7_empty (), // (terminated)
+ .out7_channel (), // (terminated)
+ .out7_error (), // (terminated)
+ .out7_data (), // (terminated)
+ .out8_ready (1'b1), // (terminated)
+ .out8_valid (), // (terminated)
+ .out8_startofpacket (), // (terminated)
+ .out8_endofpacket (), // (terminated)
+ .out8_empty (), // (terminated)
+ .out8_channel (), // (terminated)
+ .out8_error (), // (terminated)
+ .out8_data (), // (terminated)
+ .out9_ready (1'b1), // (terminated)
+ .out9_valid (), // (terminated)
+ .out9_startofpacket (), // (terminated)
+ .out9_endofpacket (), // (terminated)
+ .out9_empty (), // (terminated)
+ .out9_channel (), // (terminated)
+ .out9_error (), // (terminated)
+ .out9_data (), // (terminated)
+ .out10_ready (1'b1), // (terminated)
+ .out10_valid (), // (terminated)
+ .out10_startofpacket (), // (terminated)
+ .out10_endofpacket (), // (terminated)
+ .out10_empty (), // (terminated)
+ .out10_channel (), // (terminated)
+ .out10_error (), // (terminated)
+ .out10_data (), // (terminated)
+ .out11_ready (1'b1), // (terminated)
+ .out11_valid (), // (terminated)
+ .out11_startofpacket (), // (terminated)
+ .out11_endofpacket (), // (terminated)
+ .out11_empty (), // (terminated)
+ .out11_channel (), // (terminated)
+ .out11_error (), // (terminated)
+ .out11_data (), // (terminated)
+ .out12_ready (1'b1), // (terminated)
+ .out12_valid (), // (terminated)
+ .out12_startofpacket (), // (terminated)
+ .out12_endofpacket (), // (terminated)
+ .out12_empty (), // (terminated)
+ .out12_channel (), // (terminated)
+ .out12_error (), // (terminated)
+ .out12_data (), // (terminated)
+ .out13_ready (1'b1), // (terminated)
+ .out13_valid (), // (terminated)
+ .out13_startofpacket (), // (terminated)
+ .out13_endofpacket (), // (terminated)
+ .out13_empty (), // (terminated)
+ .out13_channel (), // (terminated)
+ .out13_error (), // (terminated)
+ .out13_data (), // (terminated)
+ .out14_ready (1'b1), // (terminated)
+ .out14_valid (), // (terminated)
+ .out14_startofpacket (), // (terminated)
+ .out14_endofpacket (), // (terminated)
+ .out14_empty (), // (terminated)
+ .out14_channel (), // (terminated)
+ .out14_error (), // (terminated)
+ .out14_data (), // (terminated)
+ .out15_ready (1'b1), // (terminated)
+ .out15_valid (), // (terminated)
+ .out15_startofpacket (), // (terminated)
+ .out15_endofpacket (), // (terminated)
+ .out15_empty (), // (terminated)
+ .out15_channel (), // (terminated)
+ .out15_error (), // (terminated)
+ .out15_data () // (terminated)
+ );
+
+ altera_eth_frame_decoder #(
+ .BITSPERSYMBOL (8),
+ .SYMBOLSPERBEAT (8),
+ .ERROR_WIDTH (1),
+ .ENABLE_SUPP_ADDR (1),
+ .ENABLE_PFC (0),
+ .PFC_PRIORITY_NUM (8)
+ ) rx_eth_frame_decoder (
+ .clk (rx_clk_clk), // clock_reset.clk
+ .reset (rst_controller_002_reset_out_reset), // clock_reset_reset.reset
+ .csr_readdata (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_readdata), // avalom_mm_csr.readdata
+ .csr_write (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_write), // .write
+ .csr_read (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_read), // .read
+ .csr_address (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_address), // .address
+ .csr_writedata (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_writedata), // .writedata
+ .data_sink_sop (rx_timing_adapter_frame_status_out_frame_decoder_out_startofpacket), // avalon_st_data_sink.startofpacket
+ .data_sink_eop (rx_timing_adapter_frame_status_out_frame_decoder_out_endofpacket), // .endofpacket
+ .data_sink_valid (rx_timing_adapter_frame_status_out_frame_decoder_out_valid), // .valid
+ .data_sink_data (rx_timing_adapter_frame_status_out_frame_decoder_out_data), // .data
+ .data_sink_empty (rx_timing_adapter_frame_status_out_frame_decoder_out_empty), // .empty
+ .data_sink_error (rx_timing_adapter_frame_status_out_frame_decoder_out_error), // .error
+ .data_src_sop (rx_eth_frame_decoder_avalon_st_data_src_startofpacket), // avalon_st_data_src.startofpacket
+ .data_src_eop (rx_eth_frame_decoder_avalon_st_data_src_endofpacket), // .endofpacket
+ .data_src_valid (rx_eth_frame_decoder_avalon_st_data_src_valid), // .valid
+ .data_src_data (rx_eth_frame_decoder_avalon_st_data_src_data), // .data
+ .data_src_empty (rx_eth_frame_decoder_avalon_st_data_src_empty), // .empty
+ .data_src_error (rx_eth_frame_decoder_avalon_st_data_src_error), // .error
+ .pauselen_src_valid (rx_eth_frame_decoder_avalon_st_pauselen_src_valid), // avalon_st_pauselen_src.valid
+ .pauselen_src_data (rx_eth_frame_decoder_avalon_st_pauselen_src_data), // .data
+ .rxstatus_src_valid (rx_eth_frame_decoder_avalon_st_rxstatus_src_valid), // avalon_st_rxstatus_src.valid
+ .rxstatus_src_data (rx_eth_frame_decoder_avalon_st_rxstatus_src_data), // .data
+ .rxstatus_src_error (rx_eth_frame_decoder_avalon_st_rxstatus_src_error), // .error
+ .pktinfo_src_valid (rx_eth_frame_decoder_avalon_st_pktinfo_src_valid), // avalon_st_pktinfo_src.valid
+ .pktinfo_src_data (rx_eth_frame_decoder_avalon_st_pktinfo_src_data), // .data
+ .data_sink_ready (), // (terminated)
+ .data_src_ready (1'b1), // (terminated)
+ .pfc_pause_quanta_src_valid (), // (terminated)
+ .pfc_pause_quanta_src_data (), // (terminated)
+ .pfc_status_src_valid (), // (terminated)
+ .pfc_status_src_data () // (terminated)
+ );
+
+ altera_eth_crc #(
+ .BITSPERSYMBOL (8),
+ .SYMBOLSPERBEAT (8),
+ .ERROR_WIDTH (1),
+ .MODE_CHECKER_0_INSERTER_1 (0)
+ ) rx_eth_crc_checker (
+ .clk (rx_clk_clk), // clock_reset.clk
+ .reset (rst_controller_002_reset_out_reset), // clock_reset_reset.reset
+ .csr_write (rx_eth_crc_checker_csr_translator_avalon_anti_slave_0_write), // csr.write
+ .csr_read (rx_eth_crc_checker_csr_translator_avalon_anti_slave_0_read), // .read
+ .csr_address (rx_eth_crc_checker_csr_translator_avalon_anti_slave_0_address), // .address
+ .csr_writedata (rx_eth_crc_checker_csr_translator_avalon_anti_slave_0_writedata), // .writedata
+ .csr_readdata (rx_eth_crc_checker_csr_translator_avalon_anti_slave_0_readdata), // .readdata
+ .data_sink_sop (rx_timing_adapter_frame_status_out_crc_checker_out_startofpacket), // avalon_streaming_sink.startofpacket
+ .data_sink_eop (rx_timing_adapter_frame_status_out_crc_checker_out_endofpacket), // .endofpacket
+ .data_sink_valid (rx_timing_adapter_frame_status_out_crc_checker_out_valid), // .valid
+ .data_sink_data (rx_timing_adapter_frame_status_out_crc_checker_out_data), // .data
+ .data_sink_empty (rx_timing_adapter_frame_status_out_crc_checker_out_empty), // .empty
+ .data_sink_error (rx_timing_adapter_frame_status_out_crc_checker_out_error), // .error
+ .data_src_sop (rx_eth_crc_checker_avalon_streaming_source_startofpacket), // avalon_streaming_source.startofpacket
+ .data_src_eop (rx_eth_crc_checker_avalon_streaming_source_endofpacket), // .endofpacket
+ .data_src_valid (rx_eth_crc_checker_avalon_streaming_source_valid), // .valid
+ .data_src_data (rx_eth_crc_checker_avalon_streaming_source_data), // .data
+ .data_src_empty (rx_eth_crc_checker_avalon_streaming_source_empty), // .empty
+ .data_src_error (rx_eth_crc_checker_avalon_streaming_source_error), // .error
+ .data_sink_ready (), // (terminated)
+ .data_src_ready (1'b1) // (terminated)
+ );
+
+ ip_stratixiv_mac_10g_rx_timing_adapter_frame_status_out_frame_decoder rx_timing_adapter_frame_status_out_frame_decoder (
+ .clk (rx_clk_clk), // clk.clk
+ .reset_n (~rst_controller_002_reset_out_reset), // reset.reset_n
+ .in_ready (rx_st_frame_status_splitter_out0_ready), // in.ready
+ .in_valid (rx_st_frame_status_splitter_out0_valid), // .valid
+ .in_data (rx_st_frame_status_splitter_out0_data), // .data
+ .in_error (rx_st_frame_status_splitter_out0_error), // .error
+ .in_startofpacket (rx_st_frame_status_splitter_out0_startofpacket), // .startofpacket
+ .in_endofpacket (rx_st_frame_status_splitter_out0_endofpacket), // .endofpacket
+ .in_empty (rx_st_frame_status_splitter_out0_empty), // .empty
+ .out_valid (rx_timing_adapter_frame_status_out_frame_decoder_out_valid), // out.valid
+ .out_data (rx_timing_adapter_frame_status_out_frame_decoder_out_data), // .data
+ .out_error (rx_timing_adapter_frame_status_out_frame_decoder_out_error), // .error
+ .out_startofpacket (rx_timing_adapter_frame_status_out_frame_decoder_out_startofpacket), // .startofpacket
+ .out_endofpacket (rx_timing_adapter_frame_status_out_frame_decoder_out_endofpacket), // .endofpacket
+ .out_empty (rx_timing_adapter_frame_status_out_frame_decoder_out_empty) // .empty
+ );
+
+ ip_stratixiv_mac_10g_rx_timing_adapter_frame_status_out_frame_decoder rx_timing_adapter_frame_status_out_crc_checker (
+ .clk (rx_clk_clk), // clk.clk
+ .reset_n (~rst_controller_002_reset_out_reset), // reset.reset_n
+ .in_ready (rx_st_frame_status_splitter_out1_ready), // in.ready
+ .in_valid (rx_st_frame_status_splitter_out1_valid), // .valid
+ .in_data (rx_st_frame_status_splitter_out1_data), // .data
+ .in_error (rx_st_frame_status_splitter_out1_error), // .error
+ .in_startofpacket (rx_st_frame_status_splitter_out1_startofpacket), // .startofpacket
+ .in_endofpacket (rx_st_frame_status_splitter_out1_endofpacket), // .endofpacket
+ .in_empty (rx_st_frame_status_splitter_out1_empty), // .empty
+ .out_valid (rx_timing_adapter_frame_status_out_crc_checker_out_valid), // out.valid
+ .out_data (rx_timing_adapter_frame_status_out_crc_checker_out_data), // .data
+ .out_error (rx_timing_adapter_frame_status_out_crc_checker_out_error), // .error
+ .out_startofpacket (rx_timing_adapter_frame_status_out_crc_checker_out_startofpacket), // .startofpacket
+ .out_endofpacket (rx_timing_adapter_frame_status_out_crc_checker_out_endofpacket), // .endofpacket
+ .out_empty (rx_timing_adapter_frame_status_out_crc_checker_out_empty) // .empty
+ );
+
+ altera_eth_frame_status_merger rx_eth_frame_status_merger (
+ .clk (rx_clk_clk), // clock_reset.clk
+ .reset (rst_controller_002_reset_out_reset), // clock_reset_reset.reset
+ .frame_decoder_data_sink_sop (rx_eth_frame_decoder_avalon_st_data_src_startofpacket), // frame_decoder_data_sink.startofpacket
+ .frame_decoder_data_sink_eop (rx_eth_frame_decoder_avalon_st_data_src_endofpacket), // .endofpacket
+ .frame_decoder_data_sink_valid (rx_eth_frame_decoder_avalon_st_data_src_valid), // .valid
+ .frame_decoder_data_sink_data (rx_eth_frame_decoder_avalon_st_data_src_data), // .data
+ .frame_decoder_data_sink_empty (rx_eth_frame_decoder_avalon_st_data_src_empty), // .empty
+ .frame_decoder_data_sink_error (rx_eth_frame_decoder_avalon_st_data_src_error), // .error
+ .crc_checker_data_sink_sop (rx_eth_crc_checker_avalon_streaming_source_startofpacket), // crc_checker_data_sink.startofpacket
+ .crc_checker_data_sink_eop (rx_eth_crc_checker_avalon_streaming_source_endofpacket), // .endofpacket
+ .crc_checker_data_sink_valid (rx_eth_crc_checker_avalon_streaming_source_valid), // .valid
+ .crc_checker_data_sink_data (rx_eth_crc_checker_avalon_streaming_source_data), // .data
+ .crc_checker_data_sink_empty (rx_eth_crc_checker_avalon_streaming_source_empty), // .empty
+ .crc_checker_data_sink_error (rx_eth_crc_checker_avalon_streaming_source_error), // .error
+ .data_src_sop (rx_eth_frame_status_merger_data_src_startofpacket), // data_src.startofpacket
+ .data_src_eop (rx_eth_frame_status_merger_data_src_endofpacket), // .endofpacket
+ .data_src_valid (rx_eth_frame_status_merger_data_src_valid), // .valid
+ .data_src_data (rx_eth_frame_status_merger_data_src_data), // .data
+ .data_src_empty (rx_eth_frame_status_merger_data_src_empty), // .empty
+ .data_src_error (rx_eth_frame_status_merger_data_src_error), // .error
+ .pauselen_sink_valid (rx_eth_frame_decoder_avalon_st_pauselen_src_valid), // pauselen_sink.valid
+ .pauselen_sink_data (rx_eth_frame_decoder_avalon_st_pauselen_src_data), // .data
+ .pauselen_src_valid (rx_eth_frame_status_merger_pauselen_src_valid), // pauselen_src.valid
+ .pauselen_src_data (rx_eth_frame_status_merger_pauselen_src_data), // .data
+ .rxstatus_sink_valid (rx_eth_frame_decoder_avalon_st_rxstatus_src_valid), // rxstatus_sink.valid
+ .rxstatus_sink_data (rx_eth_frame_decoder_avalon_st_rxstatus_src_data), // .data
+ .rxstatus_sink_error (rx_eth_frame_decoder_avalon_st_rxstatus_src_error), // .error
+ .rxstatus_src_valid (rx_eth_frame_status_merger_rxstatus_src_valid), // rxstatus_src.valid
+ .rxstatus_src_data (rx_eth_frame_status_merger_rxstatus_src_data), // .data
+ .rxstatus_src_error (rx_eth_frame_status_merger_rxstatus_src_error), // .error
+ .pfc_pause_quanta_sink_valid (1'b0), // (terminated)
+ .pfc_pause_quanta_sink_data (136'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
+ .pfc_pause_quanta_src_valid (), // (terminated)
+ .pfc_pause_quanta_src_data () // (terminated)
+ );
+
+ altera_eth_crc_pad_rem #(
+ .BITSPERSYMBOL (8),
+ .SYMBOLSPERBEAT (8),
+ .ERRORWIDTH (5)
+ ) rx_eth_crc_pad_rem (
+ .clk (rx_clk_clk), // clock_reset.clk
+ .reset (rst_controller_002_reset_out_reset), // clock_reset_reset.reset
+ .csr_read (rx_eth_crc_pad_rem_csr_translator_avalon_anti_slave_0_read), // csr.read
+ .csr_write (rx_eth_crc_pad_rem_csr_translator_avalon_anti_slave_0_write), // .write
+ .csr_address (rx_eth_crc_pad_rem_csr_translator_avalon_anti_slave_0_address), // .address
+ .csr_writedata (rx_eth_crc_pad_rem_csr_translator_avalon_anti_slave_0_writedata), // .writedata
+ .csr_readdata (rx_eth_crc_pad_rem_csr_translator_avalon_anti_slave_0_readdata), // .readdata
+ .data_sink_sop (rx_eth_frame_status_merger_data_src_startofpacket), // avalon_streaming_sink_data.startofpacket
+ .data_sink_eop (rx_eth_frame_status_merger_data_src_endofpacket), // .endofpacket
+ .data_sink_valid (rx_eth_frame_status_merger_data_src_valid), // .valid
+ .data_sink_data (rx_eth_frame_status_merger_data_src_data), // .data
+ .data_sink_empty (rx_eth_frame_status_merger_data_src_empty), // .empty
+ .data_sink_error (rx_eth_frame_status_merger_data_src_error), // .error
+ .status_sink_valid (rx_eth_frame_decoder_avalon_st_pktinfo_src_valid), // avalon_streaming_sink_status.valid
+ .status_sink_data (rx_eth_frame_decoder_avalon_st_pktinfo_src_data), // .data
+ .data_source_sop (rx_eth_crc_pad_rem_avalon_streaming_source_data_startofpacket), // avalon_streaming_source_data.startofpacket
+ .data_source_eop (rx_eth_crc_pad_rem_avalon_streaming_source_data_endofpacket), // .endofpacket
+ .data_source_valid (rx_eth_crc_pad_rem_avalon_streaming_source_data_valid), // .valid
+ .data_source_data (rx_eth_crc_pad_rem_avalon_streaming_source_data_data), // .data
+ .data_source_empty (rx_eth_crc_pad_rem_avalon_streaming_source_data_empty), // .empty
+ .data_source_error (rx_eth_crc_pad_rem_avalon_streaming_source_data_error) // .error
+ );
+
+ altera_eth_packet_overflow_control #(
+ .BITSPERSYMBOL (8),
+ .SYMBOLSPERBEAT (8),
+ .ERROR_WIDTH (5)
+ ) rx_eth_packet_overflow_control (
+ .clk (rx_clk_clk), // clock_reset.clk
+ .reset (rst_controller_002_reset_out_reset), // clock_reset_reset.reset
+ .data_sink_sop (rx_eth_crc_pad_rem_avalon_streaming_source_data_startofpacket), // avalon_streaming_sink.startofpacket
+ .data_sink_eop (rx_eth_crc_pad_rem_avalon_streaming_source_data_endofpacket), // .endofpacket
+ .data_sink_valid (rx_eth_crc_pad_rem_avalon_streaming_source_data_valid), // .valid
+ .data_sink_empty (rx_eth_crc_pad_rem_avalon_streaming_source_data_empty), // .empty
+ .data_sink_error (rx_eth_crc_pad_rem_avalon_streaming_source_data_error), // .error
+ .data_sink_data (rx_eth_crc_pad_rem_avalon_streaming_source_data_data), // .data
+ .data_src_sop (avalon_st_rx_startofpacket), // avalon_streaming_source.startofpacket
+ .data_src_eop (avalon_st_rx_endofpacket), // .endofpacket
+ .data_src_valid (avalon_st_rx_valid), // .valid
+ .data_src_ready (avalon_st_rx_ready), // .ready
+ .data_src_data (avalon_st_rx_data), // .data
+ .data_src_empty (avalon_st_rx_empty), // .empty
+ .data_src_error (avalon_st_rx_error), // .error
+ .csr_address (rx_eth_packet_overflow_control_csr_translator_avalon_anti_slave_0_address), // csr.address
+ .csr_read (rx_eth_packet_overflow_control_csr_translator_avalon_anti_slave_0_read), // .read
+ .csr_readdata (rx_eth_packet_overflow_control_csr_translator_avalon_anti_slave_0_readdata) // .readdata
+ );
+
+ altera_avalon_st_delay #(
+ .NUMBER_OF_DELAY_CLOCKS (2),
+ .DATA_WIDTH (40),
+ .BITS_PER_SYMBOL (40),
+ .USE_PACKETS (0),
+ .USE_CHANNEL (0),
+ .CHANNEL_WIDTH (1),
+ .USE_ERROR (1),
+ .ERROR_WIDTH (7)
+ ) rx_st_status_output_delay (
+ .in0_valid (rx_st_timing_adapter_splitter_status_output_out_valid), // in.valid
+ .in0_data (rx_st_timing_adapter_splitter_status_output_out_data), // .data
+ .in0_error (rx_st_timing_adapter_splitter_status_output_out_error), // .error
+ .out0_valid (avalon_st_rxstatus_valid), // out.valid
+ .out0_data (avalon_st_rxstatus_data), // .data
+ .out0_error (avalon_st_rxstatus_error), // .error
+ .clk (rx_clk_clk), // clk.clk
+ .reset_n (~rst_controller_002_reset_out_reset), // clk_reset.reset_n
+ .in0_startofpacket (1'b0), // (terminated)
+ .in0_endofpacket (1'b0), // (terminated)
+ .out0_startofpacket (), // (terminated)
+ .out0_endofpacket (), // (terminated)
+ .in0_empty (1'b0), // (terminated)
+ .out0_empty (), // (terminated)
+ .in0_channel (1'b0), // (terminated)
+ .out0_channel () // (terminated)
+ );
+
+ ip_stratixiv_mac_10g_rx_st_error_adapter_stat rx_st_error_adapter_stat (
+ .clk (rx_clk_clk), // clk.clk
+ .reset_n (~rst_controller_002_reset_out_reset), // reset.reset_n
+ .in_valid (rx_eth_frame_status_merger_rxstatus_src_valid), // in.valid
+ .in_data (rx_eth_frame_status_merger_rxstatus_src_data), // .data
+ .in_error (rx_eth_frame_status_merger_rxstatus_src_error), // .error
+ .out_valid (rx_st_error_adapter_stat_out_valid), // out.valid
+ .out_data (rx_st_error_adapter_stat_out_data), // .data
+ .out_error (rx_st_error_adapter_stat_out_error) // .error
+ );
+
+ ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_in rx_st_timing_adapter_splitter_status_in (
+ .clk (rx_clk_clk), // clk.clk
+ .reset_n (~rst_controller_002_reset_out_reset), // reset.reset_n
+ .in_valid (rx_st_error_adapter_stat_out_valid), // in.valid
+ .in_data (rx_st_error_adapter_stat_out_data), // .data
+ .in_error (rx_st_error_adapter_stat_out_error), // .error
+ .out_valid (rx_st_timing_adapter_splitter_status_in_out_valid), // out.valid
+ .out_data (rx_st_timing_adapter_splitter_status_in_out_data), // .data
+ .out_error (rx_st_timing_adapter_splitter_status_in_out_error), // .error
+ .out_ready (rx_st_timing_adapter_splitter_status_in_out_ready) // .ready
+ );
+
+ altera_avalon_st_splitter #(
+ .NUMBER_OF_OUTPUTS (2),
+ .QUALIFY_VALID_OUT (1),
+ .USE_PACKETS (0),
+ .DATA_WIDTH (40),
+ .CHANNEL_WIDTH (1),
+ .ERROR_WIDTH (7),
+ .BITS_PER_SYMBOL (40),
+ .EMPTY_WIDTH (1)
+ ) rx_st_status_splitter (
+ .clk (rx_clk_clk), // clk.clk
+ .in0_ready (rx_st_timing_adapter_splitter_status_in_out_ready), // in.ready
+ .in0_valid (rx_st_timing_adapter_splitter_status_in_out_valid), // .valid
+ .in0_error (rx_st_timing_adapter_splitter_status_in_out_error), // .error
+ .in0_data (rx_st_timing_adapter_splitter_status_in_out_data), // .data
+ .out0_ready (rx_st_status_splitter_out0_ready), // out0.ready
+ .out0_valid (rx_st_status_splitter_out0_valid), // .valid
+ .out0_error (rx_st_status_splitter_out0_error), // .error
+ .out0_data (rx_st_status_splitter_out0_data), // .data
+ .out1_ready (rx_st_status_splitter_out1_ready), // out1.ready
+ .out1_valid (rx_st_status_splitter_out1_valid), // .valid
+ .out1_error (rx_st_status_splitter_out1_error), // .error
+ .out1_data (rx_st_status_splitter_out1_data), // .data
+ .in0_startofpacket (1'b0), // (terminated)
+ .in0_endofpacket (1'b0), // (terminated)
+ .in0_empty (1'b0), // (terminated)
+ .in0_channel (1'b0), // (terminated)
+ .out0_startofpacket (), // (terminated)
+ .out0_endofpacket (), // (terminated)
+ .out0_empty (), // (terminated)
+ .out0_channel (), // (terminated)
+ .out1_startofpacket (), // (terminated)
+ .out1_endofpacket (), // (terminated)
+ .out1_empty (), // (terminated)
+ .out1_channel (), // (terminated)
+ .out2_ready (1'b1), // (terminated)
+ .out2_valid (), // (terminated)
+ .out2_startofpacket (), // (terminated)
+ .out2_endofpacket (), // (terminated)
+ .out2_empty (), // (terminated)
+ .out2_channel (), // (terminated)
+ .out2_error (), // (terminated)
+ .out2_data (), // (terminated)
+ .out3_ready (1'b1), // (terminated)
+ .out3_valid (), // (terminated)
+ .out3_startofpacket (), // (terminated)
+ .out3_endofpacket (), // (terminated)
+ .out3_empty (), // (terminated)
+ .out3_channel (), // (terminated)
+ .out3_error (), // (terminated)
+ .out3_data (), // (terminated)
+ .out4_ready (1'b1), // (terminated)
+ .out4_valid (), // (terminated)
+ .out4_startofpacket (), // (terminated)
+ .out4_endofpacket (), // (terminated)
+ .out4_empty (), // (terminated)
+ .out4_channel (), // (terminated)
+ .out4_error (), // (terminated)
+ .out4_data (), // (terminated)
+ .out5_ready (1'b1), // (terminated)
+ .out5_valid (), // (terminated)
+ .out5_startofpacket (), // (terminated)
+ .out5_endofpacket (), // (terminated)
+ .out5_empty (), // (terminated)
+ .out5_channel (), // (terminated)
+ .out5_error (), // (terminated)
+ .out5_data (), // (terminated)
+ .out6_ready (1'b1), // (terminated)
+ .out6_valid (), // (terminated)
+ .out6_startofpacket (), // (terminated)
+ .out6_endofpacket (), // (terminated)
+ .out6_empty (), // (terminated)
+ .out6_channel (), // (terminated)
+ .out6_error (), // (terminated)
+ .out6_data (), // (terminated)
+ .out7_ready (1'b1), // (terminated)
+ .out7_valid (), // (terminated)
+ .out7_startofpacket (), // (terminated)
+ .out7_endofpacket (), // (terminated)
+ .out7_empty (), // (terminated)
+ .out7_channel (), // (terminated)
+ .out7_error (), // (terminated)
+ .out7_data (), // (terminated)
+ .out8_ready (1'b1), // (terminated)
+ .out8_valid (), // (terminated)
+ .out8_startofpacket (), // (terminated)
+ .out8_endofpacket (), // (terminated)
+ .out8_empty (), // (terminated)
+ .out8_channel (), // (terminated)
+ .out8_error (), // (terminated)
+ .out8_data (), // (terminated)
+ .out9_ready (1'b1), // (terminated)
+ .out9_valid (), // (terminated)
+ .out9_startofpacket (), // (terminated)
+ .out9_endofpacket (), // (terminated)
+ .out9_empty (), // (terminated)
+ .out9_channel (), // (terminated)
+ .out9_error (), // (terminated)
+ .out9_data (), // (terminated)
+ .out10_ready (1'b1), // (terminated)
+ .out10_valid (), // (terminated)
+ .out10_startofpacket (), // (terminated)
+ .out10_endofpacket (), // (terminated)
+ .out10_empty (), // (terminated)
+ .out10_channel (), // (terminated)
+ .out10_error (), // (terminated)
+ .out10_data (), // (terminated)
+ .out11_ready (1'b1), // (terminated)
+ .out11_valid (), // (terminated)
+ .out11_startofpacket (), // (terminated)
+ .out11_endofpacket (), // (terminated)
+ .out11_empty (), // (terminated)
+ .out11_channel (), // (terminated)
+ .out11_error (), // (terminated)
+ .out11_data (), // (terminated)
+ .out12_ready (1'b1), // (terminated)
+ .out12_valid (), // (terminated)
+ .out12_startofpacket (), // (terminated)
+ .out12_endofpacket (), // (terminated)
+ .out12_empty (), // (terminated)
+ .out12_channel (), // (terminated)
+ .out12_error (), // (terminated)
+ .out12_data (), // (terminated)
+ .out13_ready (1'b1), // (terminated)
+ .out13_valid (), // (terminated)
+ .out13_startofpacket (), // (terminated)
+ .out13_endofpacket (), // (terminated)
+ .out13_empty (), // (terminated)
+ .out13_channel (), // (terminated)
+ .out13_error (), // (terminated)
+ .out13_data (), // (terminated)
+ .out14_ready (1'b1), // (terminated)
+ .out14_valid (), // (terminated)
+ .out14_startofpacket (), // (terminated)
+ .out14_endofpacket (), // (terminated)
+ .out14_empty (), // (terminated)
+ .out14_channel (), // (terminated)
+ .out14_error (), // (terminated)
+ .out14_data (), // (terminated)
+ .out15_ready (1'b1), // (terminated)
+ .out15_valid (), // (terminated)
+ .out15_startofpacket (), // (terminated)
+ .out15_endofpacket (), // (terminated)
+ .out15_empty (), // (terminated)
+ .out15_channel (), // (terminated)
+ .out15_error (), // (terminated)
+ .out15_data () // (terminated)
+ );
+
+ ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_output rx_st_timing_adapter_splitter_status_statistics (
+ .clk (rx_clk_clk), // clk.clk
+ .reset_n (~rst_controller_002_reset_out_reset), // reset.reset_n
+ .in_ready (rx_st_status_splitter_out0_ready), // in.ready
+ .in_valid (rx_st_status_splitter_out0_valid), // .valid
+ .in_data (rx_st_status_splitter_out0_data), // .data
+ .in_error (rx_st_status_splitter_out0_error), // .error
+ .out_valid (rx_st_timing_adapter_splitter_status_statistics_out_valid), // out.valid
+ .out_data (rx_st_timing_adapter_splitter_status_statistics_out_data), // .data
+ .out_error (rx_st_timing_adapter_splitter_status_statistics_out_error) // .error
+ );
+
+ ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_output rx_st_timing_adapter_splitter_status_output (
+ .clk (rx_clk_clk), // clk.clk
+ .reset_n (~rst_controller_002_reset_out_reset), // reset.reset_n
+ .in_ready (rx_st_status_splitter_out1_ready), // in.ready
+ .in_valid (rx_st_status_splitter_out1_valid), // .valid
+ .in_data (rx_st_status_splitter_out1_data), // .data
+ .in_error (rx_st_status_splitter_out1_error), // .error
+ .out_valid (rx_st_timing_adapter_splitter_status_output_out_valid), // out.valid
+ .out_data (rx_st_timing_adapter_splitter_status_output_out_data), // .data
+ .out_error (rx_st_timing_adapter_splitter_status_output_out_error) // .error
+ );
+
+ altera_avalon_st_delay #(
+ .NUMBER_OF_DELAY_CLOCKS (1),
+ .DATA_WIDTH (40),
+ .BITS_PER_SYMBOL (40),
+ .USE_PACKETS (0),
+ .USE_CHANNEL (0),
+ .CHANNEL_WIDTH (1),
+ .USE_ERROR (1),
+ .ERROR_WIDTH (7)
+ ) rx_st_status_statistics_delay (
+ .in0_valid (rx_st_timing_adapter_splitter_status_statistics_out_valid), // in.valid
+ .in0_data (rx_st_timing_adapter_splitter_status_statistics_out_data), // .data
+ .in0_error (rx_st_timing_adapter_splitter_status_statistics_out_error), // .error
+ .out0_valid (rx_st_status_statistics_delay_out_valid), // out.valid
+ .out0_data (rx_st_status_statistics_delay_out_data), // .data
+ .out0_error (rx_st_status_statistics_delay_out_error), // .error
+ .clk (rx_clk_clk), // clk.clk
+ .reset_n (~rst_controller_002_reset_out_reset), // clk_reset.reset_n
+ .in0_startofpacket (1'b0), // (terminated)
+ .in0_endofpacket (1'b0), // (terminated)
+ .out0_startofpacket (), // (terminated)
+ .out0_endofpacket (), // (terminated)
+ .in0_empty (1'b0), // (terminated)
+ .out0_empty (), // (terminated)
+ .in0_channel (1'b0), // (terminated)
+ .out0_channel () // (terminated)
+ );
+
+ altera_eth_10gmem_statistics_collector #(
+ .ENABLE_PFC (0)
+ ) rx_eth_statistics_collector (
+ .clk (rx_clk_clk), // clock_reset.clk
+ .reset (rst_controller_002_reset_out_reset), // clock_reset_reset.reset
+ .csr_read (rx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_read), // csr.read
+ .csr_address (rx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_address), // .address
+ .csr_readdata (rx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_readdata), // .readdata
+ .csr_write (rx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_write), // .write
+ .csr_writedata (rx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_writedata), // .writedata
+ .stat_sink_valid (rx_st_status_statistics_delay_out_valid), // avalon_st_sink_data.valid
+ .stat_sink_data (rx_st_status_statistics_delay_out_data), // .data
+ .stat_sink_error (rx_st_status_statistics_delay_out_error) // .error
+ );
+
+ ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_rx txrx_timing_adapter_link_fault_status_rx (
+ .clk (rx_clk_clk), // clk.clk
+ .reset_n (~rst_controller_002_reset_out_reset), // reset.reset_n
+ .in_data (rx_eth_link_fault_detection_link_fault_src_data), // in.data
+ .out_data (txrx_timing_adapter_link_fault_status_rx_out_data), // out.data
+ .out_ready (txrx_timing_adapter_link_fault_status_rx_out_ready), // .ready
+ .out_valid (txrx_timing_adapter_link_fault_status_rx_out_valid) // .valid
+ );
+
+ altera_avalon_st_splitter #(
+ .NUMBER_OF_OUTPUTS (2),
+ .QUALIFY_VALID_OUT (0),
+ .USE_PACKETS (0),
+ .DATA_WIDTH (2),
+ .CHANNEL_WIDTH (1),
+ .ERROR_WIDTH (1),
+ .BITS_PER_SYMBOL (2),
+ .EMPTY_WIDTH (1)
+ ) txrx_st_splitter_link_fault_status (
+ .clk (rx_clk_clk), // clk.clk
+ .in0_ready (txrx_timing_adapter_link_fault_status_rx_out_ready), // in.ready
+ .in0_valid (txrx_timing_adapter_link_fault_status_rx_out_valid), // .valid
+ .in0_data (txrx_timing_adapter_link_fault_status_rx_out_data), // .data
+ .out0_ready (txrx_st_splitter_link_fault_status_out0_ready), // out0.ready
+ .out0_valid (txrx_st_splitter_link_fault_status_out0_valid), // .valid
+ .out0_data (txrx_st_splitter_link_fault_status_out0_data), // .data
+ .out1_ready (txrx_st_splitter_link_fault_status_out1_ready), // out1.ready
+ .out1_valid (txrx_st_splitter_link_fault_status_out1_valid), // .valid
+ .out1_data (txrx_st_splitter_link_fault_status_out1_data), // .data
+ .in0_startofpacket (1'b0), // (terminated)
+ .in0_endofpacket (1'b0), // (terminated)
+ .in0_empty (1'b0), // (terminated)
+ .in0_channel (1'b0), // (terminated)
+ .in0_error (1'b0), // (terminated)
+ .out0_startofpacket (), // (terminated)
+ .out0_endofpacket (), // (terminated)
+ .out0_empty (), // (terminated)
+ .out0_channel (), // (terminated)
+ .out0_error (), // (terminated)
+ .out1_startofpacket (), // (terminated)
+ .out1_endofpacket (), // (terminated)
+ .out1_empty (), // (terminated)
+ .out1_channel (), // (terminated)
+ .out1_error (), // (terminated)
+ .out2_ready (1'b1), // (terminated)
+ .out2_valid (), // (terminated)
+ .out2_startofpacket (), // (terminated)
+ .out2_endofpacket (), // (terminated)
+ .out2_empty (), // (terminated)
+ .out2_channel (), // (terminated)
+ .out2_error (), // (terminated)
+ .out2_data (), // (terminated)
+ .out3_ready (1'b1), // (terminated)
+ .out3_valid (), // (terminated)
+ .out3_startofpacket (), // (terminated)
+ .out3_endofpacket (), // (terminated)
+ .out3_empty (), // (terminated)
+ .out3_channel (), // (terminated)
+ .out3_error (), // (terminated)
+ .out3_data (), // (terminated)
+ .out4_ready (1'b1), // (terminated)
+ .out4_valid (), // (terminated)
+ .out4_startofpacket (), // (terminated)
+ .out4_endofpacket (), // (terminated)
+ .out4_empty (), // (terminated)
+ .out4_channel (), // (terminated)
+ .out4_error (), // (terminated)
+ .out4_data (), // (terminated)
+ .out5_ready (1'b1), // (terminated)
+ .out5_valid (), // (terminated)
+ .out5_startofpacket (), // (terminated)
+ .out5_endofpacket (), // (terminated)
+ .out5_empty (), // (terminated)
+ .out5_channel (), // (terminated)
+ .out5_error (), // (terminated)
+ .out5_data (), // (terminated)
+ .out6_ready (1'b1), // (terminated)
+ .out6_valid (), // (terminated)
+ .out6_startofpacket (), // (terminated)
+ .out6_endofpacket (), // (terminated)
+ .out6_empty (), // (terminated)
+ .out6_channel (), // (terminated)
+ .out6_error (), // (terminated)
+ .out6_data (), // (terminated)
+ .out7_ready (1'b1), // (terminated)
+ .out7_valid (), // (terminated)
+ .out7_startofpacket (), // (terminated)
+ .out7_endofpacket (), // (terminated)
+ .out7_empty (), // (terminated)
+ .out7_channel (), // (terminated)
+ .out7_error (), // (terminated)
+ .out7_data (), // (terminated)
+ .out8_ready (1'b1), // (terminated)
+ .out8_valid (), // (terminated)
+ .out8_startofpacket (), // (terminated)
+ .out8_endofpacket (), // (terminated)
+ .out8_empty (), // (terminated)
+ .out8_channel (), // (terminated)
+ .out8_error (), // (terminated)
+ .out8_data (), // (terminated)
+ .out9_ready (1'b1), // (terminated)
+ .out9_valid (), // (terminated)
+ .out9_startofpacket (), // (terminated)
+ .out9_endofpacket (), // (terminated)
+ .out9_empty (), // (terminated)
+ .out9_channel (), // (terminated)
+ .out9_error (), // (terminated)
+ .out9_data (), // (terminated)
+ .out10_ready (1'b1), // (terminated)
+ .out10_valid (), // (terminated)
+ .out10_startofpacket (), // (terminated)
+ .out10_endofpacket (), // (terminated)
+ .out10_empty (), // (terminated)
+ .out10_channel (), // (terminated)
+ .out10_error (), // (terminated)
+ .out10_data (), // (terminated)
+ .out11_ready (1'b1), // (terminated)
+ .out11_valid (), // (terminated)
+ .out11_startofpacket (), // (terminated)
+ .out11_endofpacket (), // (terminated)
+ .out11_empty (), // (terminated)
+ .out11_channel (), // (terminated)
+ .out11_error (), // (terminated)
+ .out11_data (), // (terminated)
+ .out12_ready (1'b1), // (terminated)
+ .out12_valid (), // (terminated)
+ .out12_startofpacket (), // (terminated)
+ .out12_endofpacket (), // (terminated)
+ .out12_empty (), // (terminated)
+ .out12_channel (), // (terminated)
+ .out12_error (), // (terminated)
+ .out12_data (), // (terminated)
+ .out13_ready (1'b1), // (terminated)
+ .out13_valid (), // (terminated)
+ .out13_startofpacket (), // (terminated)
+ .out13_endofpacket (), // (terminated)
+ .out13_empty (), // (terminated)
+ .out13_channel (), // (terminated)
+ .out13_error (), // (terminated)
+ .out13_data (), // (terminated)
+ .out14_ready (1'b1), // (terminated)
+ .out14_valid (), // (terminated)
+ .out14_startofpacket (), // (terminated)
+ .out14_endofpacket (), // (terminated)
+ .out14_empty (), // (terminated)
+ .out14_channel (), // (terminated)
+ .out14_error (), // (terminated)
+ .out14_data (), // (terminated)
+ .out15_ready (1'b1), // (terminated)
+ .out15_valid (), // (terminated)
+ .out15_startofpacket (), // (terminated)
+ .out15_endofpacket (), // (terminated)
+ .out15_empty (), // (terminated)
+ .out15_channel (), // (terminated)
+ .out15_error (), // (terminated)
+ .out15_data () // (terminated)
+ );
+
+ ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_export txrx_timing_adapter_link_fault_status_export (
+ .clk (rx_clk_clk), // clk.clk
+ .reset_n (~rst_controller_002_reset_out_reset), // reset.reset_n
+ .in_ready (txrx_st_splitter_link_fault_status_out0_ready), // in.ready
+ .in_valid (txrx_st_splitter_link_fault_status_out0_valid), // .valid
+ .in_data (txrx_st_splitter_link_fault_status_out0_data), // .data
+ .out_data (link_fault_status_xgmii_rx_data) // out.data
+ );
+
+ altera_avalon_dc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (2),
+ .FIFO_DEPTH (16),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (0),
+ .USE_IN_FILL_LEVEL (0),
+ .USE_OUT_FILL_LEVEL (0),
+ .WR_SYNC_DEPTH (2),
+ .RD_SYNC_DEPTH (2)
+ ) rxtx_dc_fifo_link_fault_status (
+ .in_clk (rx_clk_clk), // in_clk.clk
+ .in_reset_n (~rst_controller_002_reset_out_reset), // in_clk_reset.reset_n
+ .out_clk (tx_clk_clk), // out_clk.clk
+ .out_reset_n (~rst_controller_001_reset_out_reset), // out_clk_reset.reset_n
+ .in_data (txrx_st_splitter_link_fault_status_out1_data), // in.data
+ .in_valid (txrx_st_splitter_link_fault_status_out1_valid), // .valid
+ .in_ready (txrx_st_splitter_link_fault_status_out1_ready), // .ready
+ .out_data (rxtx_dc_fifo_link_fault_status_out_data), // out.data
+ .out_valid (rxtx_dc_fifo_link_fault_status_out_valid), // .valid
+ .out_ready (rxtx_dc_fifo_link_fault_status_out_ready) // .ready
+ );
+
+ ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_export rxtx_timing_adapter_link_fault_status_tx (
+ .clk (tx_clk_clk), // clk.clk
+ .reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
+ .in_ready (rxtx_dc_fifo_link_fault_status_out_ready), // in.ready
+ .in_valid (rxtx_dc_fifo_link_fault_status_out_valid), // .valid
+ .in_data (rxtx_dc_fifo_link_fault_status_out_data), // .data
+ .out_data (rxtx_timing_adapter_link_fault_status_tx_out_data) // out.data
+ );
+
+ ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_rx rxtx_timing_adapter_pauselen_rx (
+ .clk (rx_clk_clk), // clk.clk
+ .reset_n (~rst_controller_002_reset_out_reset), // reset.reset_n
+ .in_valid (rx_eth_frame_status_merger_pauselen_src_valid), // in.valid
+ .in_data (rx_eth_frame_status_merger_pauselen_src_data), // .data
+ .out_valid (rxtx_timing_adapter_pauselen_rx_out_valid), // out.valid
+ .out_data (rxtx_timing_adapter_pauselen_rx_out_data), // .data
+ .out_ready (rxtx_timing_adapter_pauselen_rx_out_ready) // .ready
+ );
+
+ altera_avalon_dc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (16),
+ .FIFO_DEPTH (16),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (0),
+ .USE_IN_FILL_LEVEL (0),
+ .USE_OUT_FILL_LEVEL (0),
+ .WR_SYNC_DEPTH (2),
+ .RD_SYNC_DEPTH (2)
+ ) rxtx_dc_fifo_pauselen (
+ .in_clk (rx_clk_clk), // in_clk.clk
+ .in_reset_n (~rst_controller_002_reset_out_reset), // in_clk_reset.reset_n
+ .out_clk (tx_clk_clk), // out_clk.clk
+ .out_reset_n (~rst_controller_001_reset_out_reset), // out_clk_reset.reset_n
+ .in_data (rxtx_timing_adapter_pauselen_rx_out_data), // in.data
+ .in_valid (rxtx_timing_adapter_pauselen_rx_out_valid), // .valid
+ .in_ready (rxtx_timing_adapter_pauselen_rx_out_ready), // .ready
+ .out_data (rxtx_dc_fifo_pauselen_out_data), // out.data
+ .out_valid (rxtx_dc_fifo_pauselen_out_valid), // .valid
+ .out_ready (rxtx_dc_fifo_pauselen_out_ready) // .ready
+ );
+
+ ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_tx rxtx_timing_adapter_pauselen_tx (
+ .clk (tx_clk_clk), // clk.clk
+ .reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
+ .in_ready (rxtx_dc_fifo_pauselen_out_ready), // in.ready
+ .in_valid (rxtx_dc_fifo_pauselen_out_valid), // .valid
+ .in_data (rxtx_dc_fifo_pauselen_out_data), // .data
+ .out_valid (rxtx_timing_adapter_pauselen_tx_out_valid), // out.valid
+ .out_data (rxtx_timing_adapter_pauselen_tx_out_data) // .data
+ );
+
+ altera_merlin_master_translator #(
+ .AV_ADDRESS_W (15),
+ .AV_DATA_W (32),
+ .AV_BURSTCOUNT_W (3),
+ .AV_BYTEENABLE_W (4),
+ .UAV_ADDRESS_W (15),
+ .UAV_BURSTCOUNT_W (3),
+ .USE_READ (1),
+ .USE_WRITE (1),
+ .USE_BEGINBURSTTRANSFER (0),
+ .USE_BEGINTRANSFER (0),
+ .USE_CHIPSELECT (0),
+ .USE_BURSTCOUNT (1),
+ .USE_READDATAVALID (1),
+ .USE_WAITREQUEST (1),
+ .AV_SYMBOLS_PER_WORD (4),
+ .AV_ADDRESS_SYMBOLS (1),
+ .AV_BURSTCOUNT_SYMBOLS (1),
+ .AV_CONSTANT_BURST_BEHAVIOR (0),
+ .UAV_CONSTANT_BURST_BEHAVIOR (0),
+ .AV_LINEWRAPBURSTS (0),
+ .AV_REGISTERINCOMINGSIGNALS (0)
+ ) merlin_master_translator_avalon_universal_master_0_translator (
+ .clk (csr_clk_clk), // clk.clk
+ .reset (rst_controller_reset_out_reset), // reset.reset
+ .uav_address (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
+ .uav_burstcount (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_burstcount), // .burstcount
+ .uav_read (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_read), // .read
+ .uav_write (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_write), // .write
+ .uav_waitrequest (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
+ .uav_readdatavalid (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
+ .uav_byteenable (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_byteenable), // .byteenable
+ .uav_readdata (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_readdata), // .readdata
+ .uav_writedata (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_writedata), // .writedata
+ .uav_lock (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_lock), // .lock
+ .uav_debugaccess (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
+ .av_address (merlin_master_translator_avalon_universal_master_0_address), // avalon_anti_master_0.address
+ .av_waitrequest (merlin_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
+ .av_burstcount (merlin_master_translator_avalon_universal_master_0_burstcount), // .burstcount
+ .av_byteenable (merlin_master_translator_avalon_universal_master_0_byteenable), // .byteenable
+ .av_read (merlin_master_translator_avalon_universal_master_0_read), // .read
+ .av_readdata (merlin_master_translator_avalon_universal_master_0_readdata), // .readdata
+ .av_readdatavalid (merlin_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
+ .av_write (merlin_master_translator_avalon_universal_master_0_write), // .write
+ .av_writedata (merlin_master_translator_avalon_universal_master_0_writedata), // .writedata
+ .av_lock (merlin_master_translator_avalon_universal_master_0_lock), // .lock
+ .av_debugaccess (merlin_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
+ .av_beginbursttransfer (1'b0), // (terminated)
+ .av_begintransfer (1'b0), // (terminated)
+ .av_chipselect (1'b0), // (terminated)
+ .uav_clken (), // (terminated)
+ .av_clken (1'b1) // (terminated)
+ );
+
+ altera_merlin_slave_translator #(
+ .AV_ADDRESS_W (14),
+ .AV_DATA_W (32),
+ .UAV_DATA_W (32),
+ .AV_BURSTCOUNT_W (1),
+ .AV_BYTEENABLE_W (4),
+ .UAV_BYTEENABLE_W (4),
+ .UAV_ADDRESS_W (15),
+ .UAV_BURSTCOUNT_W (3),
+ .AV_READLATENCY (0),
+ .USE_READDATAVALID (1),
+ .USE_WAITREQUEST (1),
+ .USE_UAV_CLKEN (0),
+ .AV_SYMBOLS_PER_WORD (4),
+ .AV_ADDRESS_SYMBOLS (1),
+ .AV_BURSTCOUNT_SYMBOLS (0),
+ .AV_CONSTANT_BURST_BEHAVIOR (0),
+ .UAV_CONSTANT_BURST_BEHAVIOR (0),
+ .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+ .CHIPSELECT_THROUGH_READLATENCY (0),
+ .AV_READ_WAIT_CYCLES (0),
+ .AV_WRITE_WAIT_CYCLES (0),
+ .AV_SETUP_WAIT_CYCLES (0),
+ .AV_DATA_HOLD_CYCLES (0)
+ ) tx_bridge_s0_translator (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // reset.reset
+ .uav_address (tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
+ .uav_burstcount (tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .uav_read (tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .uav_write (tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .uav_waitrequest (tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .uav_readdatavalid (tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .uav_byteenable (tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .uav_readdata (tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .uav_writedata (tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .uav_lock (tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .uav_debugaccess (tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .av_address (tx_bridge_s0_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
+ .av_write (tx_bridge_s0_translator_avalon_anti_slave_0_write), // .write
+ .av_read (tx_bridge_s0_translator_avalon_anti_slave_0_read), // .read
+ .av_readdata (tx_bridge_s0_translator_avalon_anti_slave_0_readdata), // .readdata
+ .av_writedata (tx_bridge_s0_translator_avalon_anti_slave_0_writedata), // .writedata
+ .av_burstcount (tx_bridge_s0_translator_avalon_anti_slave_0_burstcount), // .burstcount
+ .av_byteenable (tx_bridge_s0_translator_avalon_anti_slave_0_byteenable), // .byteenable
+ .av_readdatavalid (tx_bridge_s0_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid
+ .av_waitrequest (tx_bridge_s0_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
+ .av_debugaccess (tx_bridge_s0_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
+ .av_begintransfer (), // (terminated)
+ .av_beginbursttransfer (), // (terminated)
+ .av_writebyteenable (), // (terminated)
+ .av_lock (), // (terminated)
+ .av_chipselect (), // (terminated)
+ .av_clken (), // (terminated)
+ .uav_clken (1'b0), // (terminated)
+ .av_outputenable () // (terminated)
+ );
+
+ altera_merlin_slave_translator #(
+ .AV_ADDRESS_W (14),
+ .AV_DATA_W (32),
+ .UAV_DATA_W (32),
+ .AV_BURSTCOUNT_W (1),
+ .AV_BYTEENABLE_W (4),
+ .UAV_BYTEENABLE_W (4),
+ .UAV_ADDRESS_W (15),
+ .UAV_BURSTCOUNT_W (3),
+ .AV_READLATENCY (0),
+ .USE_READDATAVALID (1),
+ .USE_WAITREQUEST (1),
+ .USE_UAV_CLKEN (0),
+ .AV_SYMBOLS_PER_WORD (4),
+ .AV_ADDRESS_SYMBOLS (1),
+ .AV_BURSTCOUNT_SYMBOLS (0),
+ .AV_CONSTANT_BURST_BEHAVIOR (0),
+ .UAV_CONSTANT_BURST_BEHAVIOR (0),
+ .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+ .CHIPSELECT_THROUGH_READLATENCY (0),
+ .AV_READ_WAIT_CYCLES (0),
+ .AV_WRITE_WAIT_CYCLES (0),
+ .AV_SETUP_WAIT_CYCLES (0),
+ .AV_DATA_HOLD_CYCLES (0)
+ ) rx_bridge_s0_translator (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // reset.reset
+ .uav_address (rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
+ .uav_burstcount (rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .uav_read (rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .uav_write (rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .uav_waitrequest (rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .uav_readdatavalid (rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .uav_byteenable (rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .uav_readdata (rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .uav_writedata (rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .uav_lock (rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .uav_debugaccess (rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .av_address (rx_bridge_s0_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
+ .av_write (rx_bridge_s0_translator_avalon_anti_slave_0_write), // .write
+ .av_read (rx_bridge_s0_translator_avalon_anti_slave_0_read), // .read
+ .av_readdata (rx_bridge_s0_translator_avalon_anti_slave_0_readdata), // .readdata
+ .av_writedata (rx_bridge_s0_translator_avalon_anti_slave_0_writedata), // .writedata
+ .av_burstcount (rx_bridge_s0_translator_avalon_anti_slave_0_burstcount), // .burstcount
+ .av_byteenable (rx_bridge_s0_translator_avalon_anti_slave_0_byteenable), // .byteenable
+ .av_readdatavalid (rx_bridge_s0_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid
+ .av_waitrequest (rx_bridge_s0_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
+ .av_debugaccess (rx_bridge_s0_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
+ .av_begintransfer (), // (terminated)
+ .av_beginbursttransfer (), // (terminated)
+ .av_writebyteenable (), // (terminated)
+ .av_lock (), // (terminated)
+ .av_chipselect (), // (terminated)
+ .av_clken (), // (terminated)
+ .uav_clken (1'b0), // (terminated)
+ .av_outputenable () // (terminated)
+ );
+
+ altera_merlin_master_translator #(
+ .AV_ADDRESS_W (14),
+ .AV_DATA_W (32),
+ .AV_BURSTCOUNT_W (1),
+ .AV_BYTEENABLE_W (4),
+ .UAV_ADDRESS_W (14),
+ .UAV_BURSTCOUNT_W (3),
+ .USE_READ (1),
+ .USE_WRITE (1),
+ .USE_BEGINBURSTTRANSFER (0),
+ .USE_BEGINTRANSFER (0),
+ .USE_CHIPSELECT (0),
+ .USE_BURSTCOUNT (1),
+ .USE_READDATAVALID (1),
+ .USE_WAITREQUEST (1),
+ .AV_SYMBOLS_PER_WORD (4),
+ .AV_ADDRESS_SYMBOLS (1),
+ .AV_BURSTCOUNT_SYMBOLS (0),
+ .AV_CONSTANT_BURST_BEHAVIOR (0),
+ .UAV_CONSTANT_BURST_BEHAVIOR (0),
+ .AV_LINEWRAPBURSTS (0),
+ .AV_REGISTERINCOMINGSIGNALS (0)
+ ) tx_bridge_m0_translator (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // reset.reset
+ .uav_address (tx_bridge_m0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
+ .uav_burstcount (tx_bridge_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
+ .uav_read (tx_bridge_m0_translator_avalon_universal_master_0_read), // .read
+ .uav_write (tx_bridge_m0_translator_avalon_universal_master_0_write), // .write
+ .uav_waitrequest (tx_bridge_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
+ .uav_readdatavalid (tx_bridge_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
+ .uav_byteenable (tx_bridge_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
+ .uav_readdata (tx_bridge_m0_translator_avalon_universal_master_0_readdata), // .readdata
+ .uav_writedata (tx_bridge_m0_translator_avalon_universal_master_0_writedata), // .writedata
+ .uav_lock (tx_bridge_m0_translator_avalon_universal_master_0_lock), // .lock
+ .uav_debugaccess (tx_bridge_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
+ .av_address (tx_bridge_m0_address), // avalon_anti_master_0.address
+ .av_waitrequest (tx_bridge_m0_waitrequest), // .waitrequest
+ .av_burstcount (tx_bridge_m0_burstcount), // .burstcount
+ .av_byteenable (tx_bridge_m0_byteenable), // .byteenable
+ .av_read (tx_bridge_m0_read), // .read
+ .av_readdata (tx_bridge_m0_readdata), // .readdata
+ .av_readdatavalid (tx_bridge_m0_readdatavalid), // .readdatavalid
+ .av_write (tx_bridge_m0_write), // .write
+ .av_writedata (tx_bridge_m0_writedata), // .writedata
+ .av_debugaccess (tx_bridge_m0_debugaccess), // .debugaccess
+ .av_beginbursttransfer (1'b0), // (terminated)
+ .av_begintransfer (1'b0), // (terminated)
+ .av_chipselect (1'b0), // (terminated)
+ .av_lock (1'b0), // (terminated)
+ .uav_clken (), // (terminated)
+ .av_clken (1'b1) // (terminated)
+ );
+
+ altera_merlin_slave_translator #(
+ .AV_ADDRESS_W (1),
+ .AV_DATA_W (32),
+ .UAV_DATA_W (32),
+ .AV_BURSTCOUNT_W (1),
+ .AV_BYTEENABLE_W (4),
+ .UAV_BYTEENABLE_W (4),
+ .UAV_ADDRESS_W (14),
+ .UAV_BURSTCOUNT_W (3),
+ .AV_READLATENCY (1),
+ .USE_READDATAVALID (0),
+ .USE_WAITREQUEST (0),
+ .USE_UAV_CLKEN (0),
+ .AV_SYMBOLS_PER_WORD (4),
+ .AV_ADDRESS_SYMBOLS (0),
+ .AV_BURSTCOUNT_SYMBOLS (0),
+ .AV_CONSTANT_BURST_BEHAVIOR (0),
+ .UAV_CONSTANT_BURST_BEHAVIOR (0),
+ .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+ .CHIPSELECT_THROUGH_READLATENCY (0),
+ .AV_READ_WAIT_CYCLES (0),
+ .AV_WRITE_WAIT_CYCLES (0),
+ .AV_SETUP_WAIT_CYCLES (0),
+ .AV_DATA_HOLD_CYCLES (0)
+ ) tx_eth_pkt_backpressure_control_csr_translator (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // reset.reset
+ .uav_address (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
+ .uav_burstcount (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .uav_read (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .uav_write (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .uav_waitrequest (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .uav_readdatavalid (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .uav_byteenable (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .uav_readdata (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .uav_writedata (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .uav_lock (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .uav_debugaccess (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .av_address (tx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
+ .av_write (tx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_write), // .write
+ .av_read (tx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_read), // .read
+ .av_readdata (tx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_readdata), // .readdata
+ .av_writedata (tx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_writedata), // .writedata
+ .av_begintransfer (), // (terminated)
+ .av_beginbursttransfer (), // (terminated)
+ .av_burstcount (), // (terminated)
+ .av_byteenable (), // (terminated)
+ .av_readdatavalid (1'b0), // (terminated)
+ .av_waitrequest (1'b0), // (terminated)
+ .av_writebyteenable (), // (terminated)
+ .av_lock (), // (terminated)
+ .av_chipselect (), // (terminated)
+ .av_clken (), // (terminated)
+ .uav_clken (1'b0), // (terminated)
+ .av_debugaccess (), // (terminated)
+ .av_outputenable () // (terminated)
+ );
+
+ altera_merlin_slave_translator #(
+ .AV_ADDRESS_W (1),
+ .AV_DATA_W (32),
+ .UAV_DATA_W (32),
+ .AV_BURSTCOUNT_W (1),
+ .AV_BYTEENABLE_W (4),
+ .UAV_BYTEENABLE_W (4),
+ .UAV_ADDRESS_W (14),
+ .UAV_BURSTCOUNT_W (3),
+ .AV_READLATENCY (1),
+ .USE_READDATAVALID (0),
+ .USE_WAITREQUEST (0),
+ .USE_UAV_CLKEN (0),
+ .AV_SYMBOLS_PER_WORD (4),
+ .AV_ADDRESS_SYMBOLS (0),
+ .AV_BURSTCOUNT_SYMBOLS (0),
+ .AV_CONSTANT_BURST_BEHAVIOR (0),
+ .UAV_CONSTANT_BURST_BEHAVIOR (0),
+ .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+ .CHIPSELECT_THROUGH_READLATENCY (0),
+ .AV_READ_WAIT_CYCLES (0),
+ .AV_WRITE_WAIT_CYCLES (0),
+ .AV_SETUP_WAIT_CYCLES (0),
+ .AV_DATA_HOLD_CYCLES (0)
+ ) tx_eth_pad_inserter_csr_translator (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // reset.reset
+ .uav_address (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
+ .uav_burstcount (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .uav_read (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .uav_write (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .uav_waitrequest (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .uav_readdatavalid (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .uav_byteenable (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .uav_readdata (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .uav_writedata (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .uav_lock (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .uav_debugaccess (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .av_address (tx_eth_pad_inserter_csr_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
+ .av_write (tx_eth_pad_inserter_csr_translator_avalon_anti_slave_0_write), // .write
+ .av_read (tx_eth_pad_inserter_csr_translator_avalon_anti_slave_0_read), // .read
+ .av_readdata (tx_eth_pad_inserter_csr_translator_avalon_anti_slave_0_readdata), // .readdata
+ .av_writedata (tx_eth_pad_inserter_csr_translator_avalon_anti_slave_0_writedata), // .writedata
+ .av_begintransfer (), // (terminated)
+ .av_beginbursttransfer (), // (terminated)
+ .av_burstcount (), // (terminated)
+ .av_byteenable (), // (terminated)
+ .av_readdatavalid (1'b0), // (terminated)
+ .av_waitrequest (1'b0), // (terminated)
+ .av_writebyteenable (), // (terminated)
+ .av_lock (), // (terminated)
+ .av_chipselect (), // (terminated)
+ .av_clken (), // (terminated)
+ .uav_clken (1'b0), // (terminated)
+ .av_debugaccess (), // (terminated)
+ .av_outputenable () // (terminated)
+ );
+
+ altera_merlin_slave_translator #(
+ .AV_ADDRESS_W (1),
+ .AV_DATA_W (32),
+ .UAV_DATA_W (32),
+ .AV_BURSTCOUNT_W (1),
+ .AV_BYTEENABLE_W (4),
+ .UAV_BYTEENABLE_W (4),
+ .UAV_ADDRESS_W (14),
+ .UAV_BURSTCOUNT_W (3),
+ .AV_READLATENCY (1),
+ .USE_READDATAVALID (0),
+ .USE_WAITREQUEST (0),
+ .USE_UAV_CLKEN (0),
+ .AV_SYMBOLS_PER_WORD (4),
+ .AV_ADDRESS_SYMBOLS (0),
+ .AV_BURSTCOUNT_SYMBOLS (0),
+ .AV_CONSTANT_BURST_BEHAVIOR (0),
+ .UAV_CONSTANT_BURST_BEHAVIOR (0),
+ .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+ .CHIPSELECT_THROUGH_READLATENCY (0),
+ .AV_READ_WAIT_CYCLES (0),
+ .AV_WRITE_WAIT_CYCLES (0),
+ .AV_SETUP_WAIT_CYCLES (0),
+ .AV_DATA_HOLD_CYCLES (0)
+ ) tx_eth_crc_inserter_csr_translator (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // reset.reset
+ .uav_address (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
+ .uav_burstcount (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .uav_read (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .uav_write (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .uav_waitrequest (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .uav_readdatavalid (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .uav_byteenable (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .uav_readdata (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .uav_writedata (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .uav_lock (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .uav_debugaccess (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .av_address (tx_eth_crc_inserter_csr_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
+ .av_write (tx_eth_crc_inserter_csr_translator_avalon_anti_slave_0_write), // .write
+ .av_read (tx_eth_crc_inserter_csr_translator_avalon_anti_slave_0_read), // .read
+ .av_readdata (tx_eth_crc_inserter_csr_translator_avalon_anti_slave_0_readdata), // .readdata
+ .av_writedata (tx_eth_crc_inserter_csr_translator_avalon_anti_slave_0_writedata), // .writedata
+ .av_begintransfer (), // (terminated)
+ .av_beginbursttransfer (), // (terminated)
+ .av_burstcount (), // (terminated)
+ .av_byteenable (), // (terminated)
+ .av_readdatavalid (1'b0), // (terminated)
+ .av_waitrequest (1'b0), // (terminated)
+ .av_writebyteenable (), // (terminated)
+ .av_lock (), // (terminated)
+ .av_chipselect (), // (terminated)
+ .av_clken (), // (terminated)
+ .uav_clken (1'b0), // (terminated)
+ .av_debugaccess (), // (terminated)
+ .av_outputenable () // (terminated)
+ );
+
+ altera_merlin_slave_translator #(
+ .AV_ADDRESS_W (2),
+ .AV_DATA_W (32),
+ .UAV_DATA_W (32),
+ .AV_BURSTCOUNT_W (1),
+ .AV_BYTEENABLE_W (4),
+ .UAV_BYTEENABLE_W (4),
+ .UAV_ADDRESS_W (14),
+ .UAV_BURSTCOUNT_W (3),
+ .AV_READLATENCY (1),
+ .USE_READDATAVALID (0),
+ .USE_WAITREQUEST (0),
+ .USE_UAV_CLKEN (0),
+ .AV_SYMBOLS_PER_WORD (4),
+ .AV_ADDRESS_SYMBOLS (0),
+ .AV_BURSTCOUNT_SYMBOLS (0),
+ .AV_CONSTANT_BURST_BEHAVIOR (0),
+ .UAV_CONSTANT_BURST_BEHAVIOR (0),
+ .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+ .CHIPSELECT_THROUGH_READLATENCY (0),
+ .AV_READ_WAIT_CYCLES (0),
+ .AV_WRITE_WAIT_CYCLES (0),
+ .AV_SETUP_WAIT_CYCLES (0),
+ .AV_DATA_HOLD_CYCLES (0)
+ ) tx_eth_pause_ctrl_gen_csr_translator (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // reset.reset
+ .uav_address (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
+ .uav_burstcount (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .uav_read (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .uav_write (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .uav_waitrequest (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .uav_readdatavalid (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .uav_byteenable (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .uav_readdata (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .uav_writedata (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .uav_lock (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .uav_debugaccess (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .av_address (tx_eth_pause_ctrl_gen_csr_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
+ .av_write (tx_eth_pause_ctrl_gen_csr_translator_avalon_anti_slave_0_write), // .write
+ .av_read (tx_eth_pause_ctrl_gen_csr_translator_avalon_anti_slave_0_read), // .read
+ .av_readdata (tx_eth_pause_ctrl_gen_csr_translator_avalon_anti_slave_0_readdata), // .readdata
+ .av_writedata (tx_eth_pause_ctrl_gen_csr_translator_avalon_anti_slave_0_writedata), // .writedata
+ .av_begintransfer (), // (terminated)
+ .av_beginbursttransfer (), // (terminated)
+ .av_burstcount (), // (terminated)
+ .av_byteenable (), // (terminated)
+ .av_readdatavalid (1'b0), // (terminated)
+ .av_waitrequest (1'b0), // (terminated)
+ .av_writebyteenable (), // (terminated)
+ .av_lock (), // (terminated)
+ .av_chipselect (), // (terminated)
+ .av_clken (), // (terminated)
+ .uav_clken (1'b0), // (terminated)
+ .av_debugaccess (), // (terminated)
+ .av_outputenable () // (terminated)
+ );
+
+ altera_merlin_slave_translator #(
+ .AV_ADDRESS_W (2),
+ .AV_DATA_W (32),
+ .UAV_DATA_W (32),
+ .AV_BURSTCOUNT_W (1),
+ .AV_BYTEENABLE_W (4),
+ .UAV_BYTEENABLE_W (4),
+ .UAV_ADDRESS_W (14),
+ .UAV_BURSTCOUNT_W (3),
+ .AV_READLATENCY (1),
+ .USE_READDATAVALID (0),
+ .USE_WAITREQUEST (0),
+ .USE_UAV_CLKEN (0),
+ .AV_SYMBOLS_PER_WORD (4),
+ .AV_ADDRESS_SYMBOLS (0),
+ .AV_BURSTCOUNT_SYMBOLS (0),
+ .AV_CONSTANT_BURST_BEHAVIOR (0),
+ .UAV_CONSTANT_BURST_BEHAVIOR (0),
+ .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+ .CHIPSELECT_THROUGH_READLATENCY (0),
+ .AV_READ_WAIT_CYCLES (0),
+ .AV_WRITE_WAIT_CYCLES (0),
+ .AV_SETUP_WAIT_CYCLES (0),
+ .AV_DATA_HOLD_CYCLES (0)
+ ) tx_eth_address_inserter_csr_translator (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // reset.reset
+ .uav_address (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
+ .uav_burstcount (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .uav_read (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .uav_write (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .uav_waitrequest (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .uav_readdatavalid (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .uav_byteenable (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .uav_readdata (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .uav_writedata (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .uav_lock (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .uav_debugaccess (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .av_address (tx_eth_address_inserter_csr_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
+ .av_write (tx_eth_address_inserter_csr_translator_avalon_anti_slave_0_write), // .write
+ .av_read (tx_eth_address_inserter_csr_translator_avalon_anti_slave_0_read), // .read
+ .av_readdata (tx_eth_address_inserter_csr_translator_avalon_anti_slave_0_readdata), // .readdata
+ .av_writedata (tx_eth_address_inserter_csr_translator_avalon_anti_slave_0_writedata), // .writedata
+ .av_begintransfer (), // (terminated)
+ .av_beginbursttransfer (), // (terminated)
+ .av_burstcount (), // (terminated)
+ .av_byteenable (), // (terminated)
+ .av_readdatavalid (1'b0), // (terminated)
+ .av_waitrequest (1'b0), // (terminated)
+ .av_writebyteenable (), // (terminated)
+ .av_lock (), // (terminated)
+ .av_chipselect (), // (terminated)
+ .av_clken (), // (terminated)
+ .uav_clken (1'b0), // (terminated)
+ .av_debugaccess (), // (terminated)
+ .av_outputenable () // (terminated)
+ );
+
+ altera_merlin_slave_translator #(
+ .AV_ADDRESS_W (1),
+ .AV_DATA_W (32),
+ .UAV_DATA_W (32),
+ .AV_BURSTCOUNT_W (1),
+ .AV_BYTEENABLE_W (4),
+ .UAV_BYTEENABLE_W (4),
+ .UAV_ADDRESS_W (14),
+ .UAV_BURSTCOUNT_W (3),
+ .AV_READLATENCY (1),
+ .USE_READDATAVALID (0),
+ .USE_WAITREQUEST (0),
+ .USE_UAV_CLKEN (0),
+ .AV_SYMBOLS_PER_WORD (4),
+ .AV_ADDRESS_SYMBOLS (0),
+ .AV_BURSTCOUNT_SYMBOLS (0),
+ .AV_CONSTANT_BURST_BEHAVIOR (0),
+ .UAV_CONSTANT_BURST_BEHAVIOR (0),
+ .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+ .CHIPSELECT_THROUGH_READLATENCY (0),
+ .AV_READ_WAIT_CYCLES (0),
+ .AV_WRITE_WAIT_CYCLES (0),
+ .AV_SETUP_WAIT_CYCLES (0),
+ .AV_DATA_HOLD_CYCLES (0)
+ ) tx_eth_packet_underflow_control_avalon_slave_0_translator (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // reset.reset
+ .uav_address (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
+ .uav_burstcount (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .uav_read (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .uav_write (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .uav_waitrequest (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .uav_readdatavalid (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .uav_byteenable (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .uav_readdata (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .uav_writedata (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .uav_lock (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .uav_debugaccess (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .av_address (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
+ .av_read (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_anti_slave_0_read), // .read
+ .av_readdata (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_anti_slave_0_readdata), // .readdata
+ .av_write (), // (terminated)
+ .av_writedata (), // (terminated)
+ .av_begintransfer (), // (terminated)
+ .av_beginbursttransfer (), // (terminated)
+ .av_burstcount (), // (terminated)
+ .av_byteenable (), // (terminated)
+ .av_readdatavalid (1'b0), // (terminated)
+ .av_waitrequest (1'b0), // (terminated)
+ .av_writebyteenable (), // (terminated)
+ .av_lock (), // (terminated)
+ .av_chipselect (), // (terminated)
+ .av_clken (), // (terminated)
+ .uav_clken (1'b0), // (terminated)
+ .av_debugaccess (), // (terminated)
+ .av_outputenable () // (terminated)
+ );
+
+ altera_merlin_slave_translator #(
+ .AV_ADDRESS_W (5),
+ .AV_DATA_W (32),
+ .UAV_DATA_W (32),
+ .AV_BURSTCOUNT_W (1),
+ .AV_BYTEENABLE_W (4),
+ .UAV_BYTEENABLE_W (4),
+ .UAV_ADDRESS_W (14),
+ .UAV_BURSTCOUNT_W (3),
+ .AV_READLATENCY (1),
+ .USE_READDATAVALID (0),
+ .USE_WAITREQUEST (0),
+ .USE_UAV_CLKEN (0),
+ .AV_SYMBOLS_PER_WORD (4),
+ .AV_ADDRESS_SYMBOLS (0),
+ .AV_BURSTCOUNT_SYMBOLS (0),
+ .AV_CONSTANT_BURST_BEHAVIOR (0),
+ .UAV_CONSTANT_BURST_BEHAVIOR (0),
+ .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+ .CHIPSELECT_THROUGH_READLATENCY (0),
+ .AV_READ_WAIT_CYCLES (0),
+ .AV_WRITE_WAIT_CYCLES (0),
+ .AV_SETUP_WAIT_CYCLES (0),
+ .AV_DATA_HOLD_CYCLES (0)
+ ) tx_eth_frame_decoder_avalom_mm_csr_translator (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // reset.reset
+ .uav_address (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
+ .uav_burstcount (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .uav_read (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .uav_write (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .uav_waitrequest (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .uav_readdatavalid (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .uav_byteenable (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .uav_readdata (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .uav_writedata (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .uav_lock (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .uav_debugaccess (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .av_address (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
+ .av_write (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_write), // .write
+ .av_read (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_read), // .read
+ .av_readdata (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_readdata), // .readdata
+ .av_writedata (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_writedata), // .writedata
+ .av_begintransfer (), // (terminated)
+ .av_beginbursttransfer (), // (terminated)
+ .av_burstcount (), // (terminated)
+ .av_byteenable (), // (terminated)
+ .av_readdatavalid (1'b0), // (terminated)
+ .av_waitrequest (1'b0), // (terminated)
+ .av_writebyteenable (), // (terminated)
+ .av_lock (), // (terminated)
+ .av_chipselect (), // (terminated)
+ .av_clken (), // (terminated)
+ .uav_clken (1'b0), // (terminated)
+ .av_debugaccess (), // (terminated)
+ .av_outputenable () // (terminated)
+ );
+
+ altera_merlin_slave_translator #(
+ .AV_ADDRESS_W (6),
+ .AV_DATA_W (32),
+ .UAV_DATA_W (32),
+ .AV_BURSTCOUNT_W (1),
+ .AV_BYTEENABLE_W (4),
+ .UAV_BYTEENABLE_W (4),
+ .UAV_ADDRESS_W (14),
+ .UAV_BURSTCOUNT_W (3),
+ .AV_READLATENCY (2),
+ .USE_READDATAVALID (0),
+ .USE_WAITREQUEST (0),
+ .USE_UAV_CLKEN (0),
+ .AV_SYMBOLS_PER_WORD (4),
+ .AV_ADDRESS_SYMBOLS (0),
+ .AV_BURSTCOUNT_SYMBOLS (0),
+ .AV_CONSTANT_BURST_BEHAVIOR (0),
+ .UAV_CONSTANT_BURST_BEHAVIOR (0),
+ .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+ .CHIPSELECT_THROUGH_READLATENCY (0),
+ .AV_READ_WAIT_CYCLES (0),
+ .AV_WRITE_WAIT_CYCLES (0),
+ .AV_SETUP_WAIT_CYCLES (0),
+ .AV_DATA_HOLD_CYCLES (0)
+ ) tx_eth_statistics_collector_csr_translator (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // reset.reset
+ .uav_address (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
+ .uav_burstcount (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .uav_read (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .uav_write (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .uav_waitrequest (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .uav_readdatavalid (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .uav_byteenable (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .uav_readdata (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .uav_writedata (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .uav_lock (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .uav_debugaccess (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .av_address (tx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
+ .av_write (tx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_write), // .write
+ .av_read (tx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_read), // .read
+ .av_readdata (tx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_readdata), // .readdata
+ .av_writedata (tx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_writedata), // .writedata
+ .av_begintransfer (), // (terminated)
+ .av_beginbursttransfer (), // (terminated)
+ .av_burstcount (), // (terminated)
+ .av_byteenable (), // (terminated)
+ .av_readdatavalid (1'b0), // (terminated)
+ .av_waitrequest (1'b0), // (terminated)
+ .av_writebyteenable (), // (terminated)
+ .av_lock (), // (terminated)
+ .av_chipselect (), // (terminated)
+ .av_clken (), // (terminated)
+ .uav_clken (1'b0), // (terminated)
+ .av_debugaccess (), // (terminated)
+ .av_outputenable () // (terminated)
+ );
+
+ altera_merlin_master_translator #(
+ .AV_ADDRESS_W (14),
+ .AV_DATA_W (32),
+ .AV_BURSTCOUNT_W (1),
+ .AV_BYTEENABLE_W (4),
+ .UAV_ADDRESS_W (14),
+ .UAV_BURSTCOUNT_W (3),
+ .USE_READ (1),
+ .USE_WRITE (1),
+ .USE_BEGINBURSTTRANSFER (0),
+ .USE_BEGINTRANSFER (0),
+ .USE_CHIPSELECT (0),
+ .USE_BURSTCOUNT (1),
+ .USE_READDATAVALID (1),
+ .USE_WAITREQUEST (1),
+ .AV_SYMBOLS_PER_WORD (4),
+ .AV_ADDRESS_SYMBOLS (1),
+ .AV_BURSTCOUNT_SYMBOLS (0),
+ .AV_CONSTANT_BURST_BEHAVIOR (0),
+ .UAV_CONSTANT_BURST_BEHAVIOR (0),
+ .AV_LINEWRAPBURSTS (0),
+ .AV_REGISTERINCOMINGSIGNALS (0)
+ ) rx_bridge_m0_translator (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // reset.reset
+ .uav_address (rx_bridge_m0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
+ .uav_burstcount (rx_bridge_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
+ .uav_read (rx_bridge_m0_translator_avalon_universal_master_0_read), // .read
+ .uav_write (rx_bridge_m0_translator_avalon_universal_master_0_write), // .write
+ .uav_waitrequest (rx_bridge_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
+ .uav_readdatavalid (rx_bridge_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
+ .uav_byteenable (rx_bridge_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
+ .uav_readdata (rx_bridge_m0_translator_avalon_universal_master_0_readdata), // .readdata
+ .uav_writedata (rx_bridge_m0_translator_avalon_universal_master_0_writedata), // .writedata
+ .uav_lock (rx_bridge_m0_translator_avalon_universal_master_0_lock), // .lock
+ .uav_debugaccess (rx_bridge_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
+ .av_address (rx_bridge_m0_address), // avalon_anti_master_0.address
+ .av_waitrequest (rx_bridge_m0_waitrequest), // .waitrequest
+ .av_burstcount (rx_bridge_m0_burstcount), // .burstcount
+ .av_byteenable (rx_bridge_m0_byteenable), // .byteenable
+ .av_read (rx_bridge_m0_read), // .read
+ .av_readdata (rx_bridge_m0_readdata), // .readdata
+ .av_readdatavalid (rx_bridge_m0_readdatavalid), // .readdatavalid
+ .av_write (rx_bridge_m0_write), // .write
+ .av_writedata (rx_bridge_m0_writedata), // .writedata
+ .av_debugaccess (rx_bridge_m0_debugaccess), // .debugaccess
+ .av_beginbursttransfer (1'b0), // (terminated)
+ .av_begintransfer (1'b0), // (terminated)
+ .av_chipselect (1'b0), // (terminated)
+ .av_lock (1'b0), // (terminated)
+ .uav_clken (), // (terminated)
+ .av_clken (1'b1) // (terminated)
+ );
+
+ altera_merlin_slave_translator #(
+ .AV_ADDRESS_W (1),
+ .AV_DATA_W (32),
+ .UAV_DATA_W (32),
+ .AV_BURSTCOUNT_W (1),
+ .AV_BYTEENABLE_W (4),
+ .UAV_BYTEENABLE_W (4),
+ .UAV_ADDRESS_W (14),
+ .UAV_BURSTCOUNT_W (3),
+ .AV_READLATENCY (1),
+ .USE_READDATAVALID (0),
+ .USE_WAITREQUEST (0),
+ .USE_UAV_CLKEN (0),
+ .AV_SYMBOLS_PER_WORD (4),
+ .AV_ADDRESS_SYMBOLS (0),
+ .AV_BURSTCOUNT_SYMBOLS (0),
+ .AV_CONSTANT_BURST_BEHAVIOR (0),
+ .UAV_CONSTANT_BURST_BEHAVIOR (0),
+ .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+ .CHIPSELECT_THROUGH_READLATENCY (0),
+ .AV_READ_WAIT_CYCLES (0),
+ .AV_WRITE_WAIT_CYCLES (0),
+ .AV_SETUP_WAIT_CYCLES (0),
+ .AV_DATA_HOLD_CYCLES (0)
+ ) rx_eth_pkt_backpressure_control_csr_translator (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // reset.reset
+ .uav_address (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
+ .uav_burstcount (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .uav_read (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .uav_write (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .uav_waitrequest (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .uav_readdatavalid (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .uav_byteenable (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .uav_readdata (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .uav_writedata (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .uav_lock (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .uav_debugaccess (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .av_address (rx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
+ .av_write (rx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_write), // .write
+ .av_read (rx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_read), // .read
+ .av_readdata (rx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_readdata), // .readdata
+ .av_writedata (rx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_writedata), // .writedata
+ .av_begintransfer (), // (terminated)
+ .av_beginbursttransfer (), // (terminated)
+ .av_burstcount (), // (terminated)
+ .av_byteenable (), // (terminated)
+ .av_readdatavalid (1'b0), // (terminated)
+ .av_waitrequest (1'b0), // (terminated)
+ .av_writebyteenable (), // (terminated)
+ .av_lock (), // (terminated)
+ .av_chipselect (), // (terminated)
+ .av_clken (), // (terminated)
+ .uav_clken (1'b0), // (terminated)
+ .av_debugaccess (), // (terminated)
+ .av_outputenable () // (terminated)
+ );
+
+ altera_merlin_slave_translator #(
+ .AV_ADDRESS_W (2),
+ .AV_DATA_W (32),
+ .UAV_DATA_W (32),
+ .AV_BURSTCOUNT_W (1),
+ .AV_BYTEENABLE_W (4),
+ .UAV_BYTEENABLE_W (4),
+ .UAV_ADDRESS_W (14),
+ .UAV_BURSTCOUNT_W (3),
+ .AV_READLATENCY (1),
+ .USE_READDATAVALID (0),
+ .USE_WAITREQUEST (0),
+ .USE_UAV_CLKEN (0),
+ .AV_SYMBOLS_PER_WORD (4),
+ .AV_ADDRESS_SYMBOLS (0),
+ .AV_BURSTCOUNT_SYMBOLS (0),
+ .AV_CONSTANT_BURST_BEHAVIOR (0),
+ .UAV_CONSTANT_BURST_BEHAVIOR (0),
+ .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+ .CHIPSELECT_THROUGH_READLATENCY (0),
+ .AV_READ_WAIT_CYCLES (0),
+ .AV_WRITE_WAIT_CYCLES (0),
+ .AV_SETUP_WAIT_CYCLES (0),
+ .AV_DATA_HOLD_CYCLES (0)
+ ) rx_eth_crc_pad_rem_csr_translator (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // reset.reset
+ .uav_address (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
+ .uav_burstcount (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .uav_read (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .uav_write (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .uav_waitrequest (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .uav_readdatavalid (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .uav_byteenable (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .uav_readdata (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .uav_writedata (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .uav_lock (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .uav_debugaccess (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .av_address (rx_eth_crc_pad_rem_csr_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
+ .av_write (rx_eth_crc_pad_rem_csr_translator_avalon_anti_slave_0_write), // .write
+ .av_read (rx_eth_crc_pad_rem_csr_translator_avalon_anti_slave_0_read), // .read
+ .av_readdata (rx_eth_crc_pad_rem_csr_translator_avalon_anti_slave_0_readdata), // .readdata
+ .av_writedata (rx_eth_crc_pad_rem_csr_translator_avalon_anti_slave_0_writedata), // .writedata
+ .av_begintransfer (), // (terminated)
+ .av_beginbursttransfer (), // (terminated)
+ .av_burstcount (), // (terminated)
+ .av_byteenable (), // (terminated)
+ .av_readdatavalid (1'b0), // (terminated)
+ .av_waitrequest (1'b0), // (terminated)
+ .av_writebyteenable (), // (terminated)
+ .av_lock (), // (terminated)
+ .av_chipselect (), // (terminated)
+ .av_clken (), // (terminated)
+ .uav_clken (1'b0), // (terminated)
+ .av_debugaccess (), // (terminated)
+ .av_outputenable () // (terminated)
+ );
+
+ altera_merlin_slave_translator #(
+ .AV_ADDRESS_W (1),
+ .AV_DATA_W (32),
+ .UAV_DATA_W (32),
+ .AV_BURSTCOUNT_W (1),
+ .AV_BYTEENABLE_W (4),
+ .UAV_BYTEENABLE_W (4),
+ .UAV_ADDRESS_W (14),
+ .UAV_BURSTCOUNT_W (3),
+ .AV_READLATENCY (1),
+ .USE_READDATAVALID (0),
+ .USE_WAITREQUEST (0),
+ .USE_UAV_CLKEN (0),
+ .AV_SYMBOLS_PER_WORD (4),
+ .AV_ADDRESS_SYMBOLS (0),
+ .AV_BURSTCOUNT_SYMBOLS (0),
+ .AV_CONSTANT_BURST_BEHAVIOR (0),
+ .UAV_CONSTANT_BURST_BEHAVIOR (0),
+ .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+ .CHIPSELECT_THROUGH_READLATENCY (0),
+ .AV_READ_WAIT_CYCLES (0),
+ .AV_WRITE_WAIT_CYCLES (0),
+ .AV_SETUP_WAIT_CYCLES (0),
+ .AV_DATA_HOLD_CYCLES (0)
+ ) rx_eth_crc_checker_csr_translator (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // reset.reset
+ .uav_address (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
+ .uav_burstcount (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .uav_read (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .uav_write (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .uav_waitrequest (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .uav_readdatavalid (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .uav_byteenable (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .uav_readdata (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .uav_writedata (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .uav_lock (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .uav_debugaccess (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .av_address (rx_eth_crc_checker_csr_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
+ .av_write (rx_eth_crc_checker_csr_translator_avalon_anti_slave_0_write), // .write
+ .av_read (rx_eth_crc_checker_csr_translator_avalon_anti_slave_0_read), // .read
+ .av_readdata (rx_eth_crc_checker_csr_translator_avalon_anti_slave_0_readdata), // .readdata
+ .av_writedata (rx_eth_crc_checker_csr_translator_avalon_anti_slave_0_writedata), // .writedata
+ .av_begintransfer (), // (terminated)
+ .av_beginbursttransfer (), // (terminated)
+ .av_burstcount (), // (terminated)
+ .av_byteenable (), // (terminated)
+ .av_readdatavalid (1'b0), // (terminated)
+ .av_waitrequest (1'b0), // (terminated)
+ .av_writebyteenable (), // (terminated)
+ .av_lock (), // (terminated)
+ .av_chipselect (), // (terminated)
+ .av_clken (), // (terminated)
+ .uav_clken (1'b0), // (terminated)
+ .av_debugaccess (), // (terminated)
+ .av_outputenable () // (terminated)
+ );
+
+ altera_merlin_slave_translator #(
+ .AV_ADDRESS_W (5),
+ .AV_DATA_W (32),
+ .UAV_DATA_W (32),
+ .AV_BURSTCOUNT_W (1),
+ .AV_BYTEENABLE_W (4),
+ .UAV_BYTEENABLE_W (4),
+ .UAV_ADDRESS_W (14),
+ .UAV_BURSTCOUNT_W (3),
+ .AV_READLATENCY (1),
+ .USE_READDATAVALID (0),
+ .USE_WAITREQUEST (0),
+ .USE_UAV_CLKEN (0),
+ .AV_SYMBOLS_PER_WORD (4),
+ .AV_ADDRESS_SYMBOLS (0),
+ .AV_BURSTCOUNT_SYMBOLS (0),
+ .AV_CONSTANT_BURST_BEHAVIOR (0),
+ .UAV_CONSTANT_BURST_BEHAVIOR (0),
+ .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+ .CHIPSELECT_THROUGH_READLATENCY (0),
+ .AV_READ_WAIT_CYCLES (0),
+ .AV_WRITE_WAIT_CYCLES (0),
+ .AV_SETUP_WAIT_CYCLES (0),
+ .AV_DATA_HOLD_CYCLES (0)
+ ) rx_eth_frame_decoder_avalom_mm_csr_translator (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // reset.reset
+ .uav_address (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
+ .uav_burstcount (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .uav_read (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .uav_write (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .uav_waitrequest (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .uav_readdatavalid (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .uav_byteenable (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .uav_readdata (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .uav_writedata (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .uav_lock (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .uav_debugaccess (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .av_address (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
+ .av_write (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_write), // .write
+ .av_read (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_read), // .read
+ .av_readdata (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_readdata), // .readdata
+ .av_writedata (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_writedata), // .writedata
+ .av_begintransfer (), // (terminated)
+ .av_beginbursttransfer (), // (terminated)
+ .av_burstcount (), // (terminated)
+ .av_byteenable (), // (terminated)
+ .av_readdatavalid (1'b0), // (terminated)
+ .av_waitrequest (1'b0), // (terminated)
+ .av_writebyteenable (), // (terminated)
+ .av_lock (), // (terminated)
+ .av_chipselect (), // (terminated)
+ .av_clken (), // (terminated)
+ .uav_clken (1'b0), // (terminated)
+ .av_debugaccess (), // (terminated)
+ .av_outputenable () // (terminated)
+ );
+
+ altera_merlin_slave_translator #(
+ .AV_ADDRESS_W (2),
+ .AV_DATA_W (32),
+ .UAV_DATA_W (32),
+ .AV_BURSTCOUNT_W (1),
+ .AV_BYTEENABLE_W (4),
+ .UAV_BYTEENABLE_W (4),
+ .UAV_ADDRESS_W (14),
+ .UAV_BURSTCOUNT_W (3),
+ .AV_READLATENCY (1),
+ .USE_READDATAVALID (0),
+ .USE_WAITREQUEST (0),
+ .USE_UAV_CLKEN (0),
+ .AV_SYMBOLS_PER_WORD (4),
+ .AV_ADDRESS_SYMBOLS (0),
+ .AV_BURSTCOUNT_SYMBOLS (0),
+ .AV_CONSTANT_BURST_BEHAVIOR (0),
+ .UAV_CONSTANT_BURST_BEHAVIOR (0),
+ .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+ .CHIPSELECT_THROUGH_READLATENCY (0),
+ .AV_READ_WAIT_CYCLES (0),
+ .AV_WRITE_WAIT_CYCLES (0),
+ .AV_SETUP_WAIT_CYCLES (0),
+ .AV_DATA_HOLD_CYCLES (0)
+ ) rx_eth_packet_overflow_control_csr_translator (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // reset.reset
+ .uav_address (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
+ .uav_burstcount (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .uav_read (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .uav_write (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .uav_waitrequest (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .uav_readdatavalid (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .uav_byteenable (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .uav_readdata (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .uav_writedata (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .uav_lock (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .uav_debugaccess (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .av_address (rx_eth_packet_overflow_control_csr_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
+ .av_read (rx_eth_packet_overflow_control_csr_translator_avalon_anti_slave_0_read), // .read
+ .av_readdata (rx_eth_packet_overflow_control_csr_translator_avalon_anti_slave_0_readdata), // .readdata
+ .av_write (), // (terminated)
+ .av_writedata (), // (terminated)
+ .av_begintransfer (), // (terminated)
+ .av_beginbursttransfer (), // (terminated)
+ .av_burstcount (), // (terminated)
+ .av_byteenable (), // (terminated)
+ .av_readdatavalid (1'b0), // (terminated)
+ .av_waitrequest (1'b0), // (terminated)
+ .av_writebyteenable (), // (terminated)
+ .av_lock (), // (terminated)
+ .av_chipselect (), // (terminated)
+ .av_clken (), // (terminated)
+ .uav_clken (1'b0), // (terminated)
+ .av_debugaccess (), // (terminated)
+ .av_outputenable () // (terminated)
+ );
+
+ altera_merlin_slave_translator #(
+ .AV_ADDRESS_W (6),
+ .AV_DATA_W (32),
+ .UAV_DATA_W (32),
+ .AV_BURSTCOUNT_W (1),
+ .AV_BYTEENABLE_W (4),
+ .UAV_BYTEENABLE_W (4),
+ .UAV_ADDRESS_W (14),
+ .UAV_BURSTCOUNT_W (3),
+ .AV_READLATENCY (2),
+ .USE_READDATAVALID (0),
+ .USE_WAITREQUEST (0),
+ .USE_UAV_CLKEN (0),
+ .AV_SYMBOLS_PER_WORD (4),
+ .AV_ADDRESS_SYMBOLS (0),
+ .AV_BURSTCOUNT_SYMBOLS (0),
+ .AV_CONSTANT_BURST_BEHAVIOR (0),
+ .UAV_CONSTANT_BURST_BEHAVIOR (0),
+ .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+ .CHIPSELECT_THROUGH_READLATENCY (0),
+ .AV_READ_WAIT_CYCLES (0),
+ .AV_WRITE_WAIT_CYCLES (0),
+ .AV_SETUP_WAIT_CYCLES (0),
+ .AV_DATA_HOLD_CYCLES (0)
+ ) rx_eth_statistics_collector_csr_translator (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // reset.reset
+ .uav_address (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
+ .uav_burstcount (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .uav_read (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .uav_write (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .uav_waitrequest (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .uav_readdatavalid (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .uav_byteenable (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .uav_readdata (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .uav_writedata (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .uav_lock (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .uav_debugaccess (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .av_address (rx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
+ .av_write (rx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_write), // .write
+ .av_read (rx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_read), // .read
+ .av_readdata (rx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_readdata), // .readdata
+ .av_writedata (rx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_writedata), // .writedata
+ .av_begintransfer (), // (terminated)
+ .av_beginbursttransfer (), // (terminated)
+ .av_burstcount (), // (terminated)
+ .av_byteenable (), // (terminated)
+ .av_readdatavalid (1'b0), // (terminated)
+ .av_waitrequest (1'b0), // (terminated)
+ .av_writebyteenable (), // (terminated)
+ .av_lock (), // (terminated)
+ .av_chipselect (), // (terminated)
+ .av_clken (), // (terminated)
+ .uav_clken (1'b0), // (terminated)
+ .av_debugaccess (), // (terminated)
+ .av_outputenable () // (terminated)
+ );
+
+ altera_merlin_slave_translator #(
+ .AV_ADDRESS_W (1),
+ .AV_DATA_W (32),
+ .UAV_DATA_W (32),
+ .AV_BURSTCOUNT_W (1),
+ .AV_BYTEENABLE_W (4),
+ .UAV_BYTEENABLE_W (4),
+ .UAV_ADDRESS_W (14),
+ .UAV_BURSTCOUNT_W (3),
+ .AV_READLATENCY (1),
+ .USE_READDATAVALID (0),
+ .USE_WAITREQUEST (0),
+ .USE_UAV_CLKEN (0),
+ .AV_SYMBOLS_PER_WORD (4),
+ .AV_ADDRESS_SYMBOLS (0),
+ .AV_BURSTCOUNT_SYMBOLS (0),
+ .AV_CONSTANT_BURST_BEHAVIOR (0),
+ .UAV_CONSTANT_BURST_BEHAVIOR (0),
+ .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+ .CHIPSELECT_THROUGH_READLATENCY (0),
+ .AV_READ_WAIT_CYCLES (0),
+ .AV_WRITE_WAIT_CYCLES (0),
+ .AV_SETUP_WAIT_CYCLES (0),
+ .AV_DATA_HOLD_CYCLES (0)
+ ) rx_eth_lane_decoder_csr_translator (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // reset.reset
+ .uav_address (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
+ .uav_burstcount (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .uav_read (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .uav_write (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .uav_waitrequest (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .uav_readdatavalid (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .uav_byteenable (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .uav_readdata (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .uav_writedata (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .uav_lock (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .uav_debugaccess (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .av_address (rx_eth_lane_decoder_csr_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
+ .av_write (rx_eth_lane_decoder_csr_translator_avalon_anti_slave_0_write), // .write
+ .av_read (rx_eth_lane_decoder_csr_translator_avalon_anti_slave_0_read), // .read
+ .av_readdata (rx_eth_lane_decoder_csr_translator_avalon_anti_slave_0_readdata), // .readdata
+ .av_writedata (rx_eth_lane_decoder_csr_translator_avalon_anti_slave_0_writedata), // .writedata
+ .av_begintransfer (), // (terminated)
+ .av_beginbursttransfer (), // (terminated)
+ .av_burstcount (), // (terminated)
+ .av_byteenable (), // (terminated)
+ .av_readdatavalid (1'b0), // (terminated)
+ .av_waitrequest (1'b0), // (terminated)
+ .av_writebyteenable (), // (terminated)
+ .av_lock (), // (terminated)
+ .av_chipselect (), // (terminated)
+ .av_clken (), // (terminated)
+ .uav_clken (1'b0), // (terminated)
+ .av_debugaccess (), // (terminated)
+ .av_outputenable () // (terminated)
+ );
+
+ altera_merlin_slave_agent #(
+ .PKT_DATA_H (31),
+ .PKT_DATA_L (0),
+ .PKT_BEGIN_BURST (62),
+ .PKT_SYMBOL_W (8),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32),
+ .PKT_ADDR_H (50),
+ .PKT_ADDR_L (36),
+ .PKT_TRANS_COMPRESSED_READ (51),
+ .PKT_TRANS_POSTED (52),
+ .PKT_TRANS_WRITE (53),
+ .PKT_TRANS_READ (54),
+ .PKT_TRANS_LOCK (55),
+ .PKT_SRC_ID_H (63),
+ .PKT_SRC_ID_L (63),
+ .PKT_DEST_ID_H (64),
+ .PKT_DEST_ID_L (64),
+ .PKT_BURSTWRAP_H (61),
+ .PKT_BURSTWRAP_L (59),
+ .PKT_BYTE_CNT_H (58),
+ .PKT_BYTE_CNT_L (56),
+ .PKT_PROTECTION_H (65),
+ .PKT_PROTECTION_L (65),
+ .ST_CHANNEL_W (2),
+ .ST_DATA_W (66),
+ .AVS_BURSTCOUNT_W (3),
+ .SUPPRESS_0_BYTEEN_CMD (0),
+ .PREVENT_FIFO_OVERFLOW (1)
+ ) rx_bridge_s0_translator_avalon_universal_slave_0_agent (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .m0_address (rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
+ .m0_burstcount (rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .m0_byteenable (rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .m0_debugaccess (rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .m0_lock (rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .m0_readdata (rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .m0_readdatavalid (rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .m0_read (rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .m0_waitrequest (rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .m0_writedata (rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .m0_write (rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .rp_endofpacket (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
+ .rp_ready (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
+ .rp_valid (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .rp_data (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .rp_startofpacket (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .cp_ready (crosser_001_out_ready), // cp.ready
+ .cp_valid (crosser_001_out_valid), // .valid
+ .cp_data (crosser_001_out_data), // .data
+ .cp_startofpacket (crosser_001_out_startofpacket), // .startofpacket
+ .cp_endofpacket (crosser_001_out_endofpacket), // .endofpacket
+ .cp_channel (crosser_001_out_channel), // .channel
+ .rf_sink_ready (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
+ .rf_sink_valid (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .rf_sink_startofpacket (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .rf_sink_endofpacket (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .rf_sink_data (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
+ .rf_source_ready (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
+ .rf_source_valid (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .rf_source_startofpacket (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .rf_source_endofpacket (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .rf_source_data (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
+ .rdata_fifo_sink_ready (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
+ .rdata_fifo_sink_valid (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid
+ .rdata_fifo_sink_data (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // .data
+ .rdata_fifo_src_ready (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
+ .rdata_fifo_src_valid (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_src_data (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
+ );
+
+ altera_avalon_sc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (67),
+ .FIFO_DEPTH (2),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (1),
+ .USE_FILL_LEVEL (0),
+ .EMPTY_LATENCY (1),
+ .USE_MEMORY_BLOCKS (0),
+ .USE_STORE_FORWARD (0),
+ .USE_ALMOST_FULL_IF (0),
+ .USE_ALMOST_EMPTY_IF (0)
+ ) rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .in_data (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
+ .in_valid (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .in_ready (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
+ .in_startofpacket (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .in_endofpacket (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .out_data (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
+ .out_valid (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .out_ready (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
+ .out_startofpacket (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .out_endofpacket (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .csr_address (2'b00), // (terminated)
+ .csr_read (1'b0), // (terminated)
+ .csr_write (1'b0), // (terminated)
+ .csr_readdata (), // (terminated)
+ .csr_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .almost_full_data (), // (terminated)
+ .almost_empty_data (), // (terminated)
+ .in_empty (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_error (), // (terminated)
+ .in_channel (1'b0), // (terminated)
+ .out_channel () // (terminated)
+ );
+
+ altera_avalon_sc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (32),
+ .FIFO_DEPTH (2),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (0),
+ .USE_FILL_LEVEL (0),
+ .EMPTY_LATENCY (0),
+ .USE_MEMORY_BLOCKS (0),
+ .USE_STORE_FORWARD (0),
+ .USE_ALMOST_FULL_IF (0),
+ .USE_ALMOST_EMPTY_IF (0)
+ ) rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .in_data (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // in.data
+ .in_valid (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .in_ready (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // .ready
+ .out_data (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // out.data
+ .out_valid (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid
+ .out_ready (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // .ready
+ .csr_address (2'b00), // (terminated)
+ .csr_read (1'b0), // (terminated)
+ .csr_write (1'b0), // (terminated)
+ .csr_readdata (), // (terminated)
+ .csr_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .almost_full_data (), // (terminated)
+ .almost_empty_data (), // (terminated)
+ .in_startofpacket (1'b0), // (terminated)
+ .in_endofpacket (1'b0), // (terminated)
+ .out_startofpacket (), // (terminated)
+ .out_endofpacket (), // (terminated)
+ .in_empty (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_error (), // (terminated)
+ .in_channel (1'b0), // (terminated)
+ .out_channel () // (terminated)
+ );
+
+ altera_merlin_slave_agent #(
+ .PKT_DATA_H (31),
+ .PKT_DATA_L (0),
+ .PKT_BEGIN_BURST (62),
+ .PKT_SYMBOL_W (8),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32),
+ .PKT_ADDR_H (50),
+ .PKT_ADDR_L (36),
+ .PKT_TRANS_COMPRESSED_READ (51),
+ .PKT_TRANS_POSTED (52),
+ .PKT_TRANS_WRITE (53),
+ .PKT_TRANS_READ (54),
+ .PKT_TRANS_LOCK (55),
+ .PKT_SRC_ID_H (63),
+ .PKT_SRC_ID_L (63),
+ .PKT_DEST_ID_H (64),
+ .PKT_DEST_ID_L (64),
+ .PKT_BURSTWRAP_H (61),
+ .PKT_BURSTWRAP_L (59),
+ .PKT_BYTE_CNT_H (58),
+ .PKT_BYTE_CNT_L (56),
+ .PKT_PROTECTION_H (65),
+ .PKT_PROTECTION_L (65),
+ .ST_CHANNEL_W (2),
+ .ST_DATA_W (66),
+ .AVS_BURSTCOUNT_W (3),
+ .SUPPRESS_0_BYTEEN_CMD (0),
+ .PREVENT_FIFO_OVERFLOW (1)
+ ) tx_bridge_s0_translator_avalon_universal_slave_0_agent (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .m0_address (tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
+ .m0_burstcount (tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .m0_byteenable (tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .m0_debugaccess (tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .m0_lock (tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .m0_readdata (tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .m0_readdatavalid (tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .m0_read (tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .m0_waitrequest (tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .m0_writedata (tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .m0_write (tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .rp_endofpacket (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
+ .rp_ready (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
+ .rp_valid (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .rp_data (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .rp_startofpacket (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .cp_ready (crosser_out_ready), // cp.ready
+ .cp_valid (crosser_out_valid), // .valid
+ .cp_data (crosser_out_data), // .data
+ .cp_startofpacket (crosser_out_startofpacket), // .startofpacket
+ .cp_endofpacket (crosser_out_endofpacket), // .endofpacket
+ .cp_channel (crosser_out_channel), // .channel
+ .rf_sink_ready (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
+ .rf_sink_valid (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .rf_sink_startofpacket (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .rf_sink_endofpacket (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .rf_sink_data (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
+ .rf_source_ready (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
+ .rf_source_valid (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .rf_source_startofpacket (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .rf_source_endofpacket (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .rf_source_data (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
+ .rdata_fifo_sink_ready (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
+ .rdata_fifo_sink_valid (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid
+ .rdata_fifo_sink_data (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // .data
+ .rdata_fifo_src_ready (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
+ .rdata_fifo_src_valid (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_src_data (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
+ );
+
+ altera_avalon_sc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (67),
+ .FIFO_DEPTH (2),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (1),
+ .USE_FILL_LEVEL (0),
+ .EMPTY_LATENCY (1),
+ .USE_MEMORY_BLOCKS (0),
+ .USE_STORE_FORWARD (0),
+ .USE_ALMOST_FULL_IF (0),
+ .USE_ALMOST_EMPTY_IF (0)
+ ) tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .in_data (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
+ .in_valid (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .in_ready (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
+ .in_startofpacket (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .in_endofpacket (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .out_data (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
+ .out_valid (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .out_ready (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
+ .out_startofpacket (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .out_endofpacket (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .csr_address (2'b00), // (terminated)
+ .csr_read (1'b0), // (terminated)
+ .csr_write (1'b0), // (terminated)
+ .csr_readdata (), // (terminated)
+ .csr_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .almost_full_data (), // (terminated)
+ .almost_empty_data (), // (terminated)
+ .in_empty (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_error (), // (terminated)
+ .in_channel (1'b0), // (terminated)
+ .out_channel () // (terminated)
+ );
+
+ altera_avalon_sc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (32),
+ .FIFO_DEPTH (2),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (0),
+ .USE_FILL_LEVEL (0),
+ .EMPTY_LATENCY (0),
+ .USE_MEMORY_BLOCKS (0),
+ .USE_STORE_FORWARD (0),
+ .USE_ALMOST_FULL_IF (0),
+ .USE_ALMOST_EMPTY_IF (0)
+ ) tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .in_data (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // in.data
+ .in_valid (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .in_ready (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // .ready
+ .out_data (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // out.data
+ .out_valid (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid
+ .out_ready (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // .ready
+ .csr_address (2'b00), // (terminated)
+ .csr_read (1'b0), // (terminated)
+ .csr_write (1'b0), // (terminated)
+ .csr_readdata (), // (terminated)
+ .csr_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .almost_full_data (), // (terminated)
+ .almost_empty_data (), // (terminated)
+ .in_startofpacket (1'b0), // (terminated)
+ .in_endofpacket (1'b0), // (terminated)
+ .out_startofpacket (), // (terminated)
+ .out_endofpacket (), // (terminated)
+ .in_empty (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_error (), // (terminated)
+ .in_channel (1'b0), // (terminated)
+ .out_channel () // (terminated)
+ );
+
+ altera_merlin_master_agent #(
+ .PKT_PROTECTION_H (65),
+ .PKT_PROTECTION_L (65),
+ .PKT_BEGIN_BURST (62),
+ .PKT_BURSTWRAP_H (61),
+ .PKT_BURSTWRAP_L (59),
+ .PKT_BYTE_CNT_H (58),
+ .PKT_BYTE_CNT_L (56),
+ .PKT_ADDR_H (50),
+ .PKT_ADDR_L (36),
+ .PKT_TRANS_COMPRESSED_READ (51),
+ .PKT_TRANS_POSTED (52),
+ .PKT_TRANS_WRITE (53),
+ .PKT_TRANS_READ (54),
+ .PKT_TRANS_LOCK (55),
+ .PKT_DATA_H (31),
+ .PKT_DATA_L (0),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32),
+ .PKT_SRC_ID_H (63),
+ .PKT_SRC_ID_L (63),
+ .PKT_DEST_ID_H (64),
+ .PKT_DEST_ID_L (64),
+ .ST_DATA_W (66),
+ .ST_CHANNEL_W (2),
+ .AV_BURSTCOUNT_W (3),
+ .SUPPRESS_0_BYTEEN_RSP (0),
+ .ID (0),
+ .BURSTWRAP_VALUE (7)
+ ) merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent (
+ .clk (csr_clk_clk), // clk.clk
+ .reset (rst_controller_reset_out_reset), // clk_reset.reset
+ .av_address (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_address), // av.address
+ .av_write (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_write), // .write
+ .av_read (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_read), // .read
+ .av_writedata (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_writedata), // .writedata
+ .av_readdata (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_readdata), // .readdata
+ .av_waitrequest (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
+ .av_readdatavalid (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
+ .av_byteenable (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_byteenable), // .byteenable
+ .av_burstcount (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_burstcount), // .burstcount
+ .av_debugaccess (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
+ .av_lock (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_lock), // .lock
+ .cp_valid (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
+ .cp_data (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent_cp_data), // .data
+ .cp_startofpacket (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
+ .cp_endofpacket (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
+ .cp_ready (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent_cp_ready), // .ready
+ .rp_valid (limiter_rsp_src_valid), // rp.valid
+ .rp_data (limiter_rsp_src_data), // .data
+ .rp_channel (limiter_rsp_src_channel), // .channel
+ .rp_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket
+ .rp_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket
+ .rp_ready (limiter_rsp_src_ready) // .ready
+ );
+
+ altera_merlin_slave_agent #(
+ .PKT_DATA_H (31),
+ .PKT_DATA_L (0),
+ .PKT_BEGIN_BURST (61),
+ .PKT_SYMBOL_W (8),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32),
+ .PKT_ADDR_H (49),
+ .PKT_ADDR_L (36),
+ .PKT_TRANS_COMPRESSED_READ (50),
+ .PKT_TRANS_POSTED (51),
+ .PKT_TRANS_WRITE (52),
+ .PKT_TRANS_READ (53),
+ .PKT_TRANS_LOCK (54),
+ .PKT_SRC_ID_H (64),
+ .PKT_SRC_ID_L (62),
+ .PKT_DEST_ID_H (67),
+ .PKT_DEST_ID_L (65),
+ .PKT_BURSTWRAP_H (60),
+ .PKT_BURSTWRAP_L (58),
+ .PKT_BYTE_CNT_H (57),
+ .PKT_BYTE_CNT_L (55),
+ .PKT_PROTECTION_H (68),
+ .PKT_PROTECTION_L (68),
+ .ST_CHANNEL_W (8),
+ .ST_DATA_W (69),
+ .AVS_BURSTCOUNT_W (3),
+ .SUPPRESS_0_BYTEEN_CMD (0),
+ .PREVENT_FIFO_OVERFLOW (1)
+ ) tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .m0_address (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
+ .m0_burstcount (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .m0_byteenable (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .m0_debugaccess (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .m0_lock (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .m0_readdata (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .m0_readdatavalid (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .m0_read (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .m0_waitrequest (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .m0_writedata (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .m0_write (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .rp_endofpacket (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
+ .rp_ready (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
+ .rp_valid (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .rp_data (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .rp_startofpacket (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .cp_ready (cmd_xbar_demux_001_src0_ready), // cp.ready
+ .cp_valid (cmd_xbar_demux_001_src0_valid), // .valid
+ .cp_data (cmd_xbar_demux_001_src0_data), // .data
+ .cp_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
+ .cp_endofpacket (cmd_xbar_demux_001_src0_endofpacket), // .endofpacket
+ .cp_channel (cmd_xbar_demux_001_src0_channel), // .channel
+ .rf_sink_ready (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
+ .rf_sink_valid (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .rf_sink_startofpacket (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .rf_sink_endofpacket (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .rf_sink_data (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
+ .rf_source_ready (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
+ .rf_source_valid (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .rf_source_startofpacket (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .rf_source_endofpacket (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .rf_source_data (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
+ .rdata_fifo_sink_ready (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
+ .rdata_fifo_sink_valid (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_sink_data (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
+ .rdata_fifo_src_ready (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
+ .rdata_fifo_src_valid (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_src_data (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
+ );
+
+ altera_avalon_sc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (70),
+ .FIFO_DEPTH (2),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (1),
+ .USE_FILL_LEVEL (0),
+ .EMPTY_LATENCY (1),
+ .USE_MEMORY_BLOCKS (0),
+ .USE_STORE_FORWARD (0),
+ .USE_ALMOST_FULL_IF (0),
+ .USE_ALMOST_EMPTY_IF (0)
+ ) tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .in_data (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
+ .in_valid (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .in_ready (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
+ .in_startofpacket (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .in_endofpacket (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .out_data (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
+ .out_valid (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .out_ready (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
+ .out_startofpacket (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .out_endofpacket (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .csr_address (2'b00), // (terminated)
+ .csr_read (1'b0), // (terminated)
+ .csr_write (1'b0), // (terminated)
+ .csr_readdata (), // (terminated)
+ .csr_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .almost_full_data (), // (terminated)
+ .almost_empty_data (), // (terminated)
+ .in_empty (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_error (), // (terminated)
+ .in_channel (1'b0), // (terminated)
+ .out_channel () // (terminated)
+ );
+
+ altera_merlin_slave_agent #(
+ .PKT_DATA_H (31),
+ .PKT_DATA_L (0),
+ .PKT_BEGIN_BURST (61),
+ .PKT_SYMBOL_W (8),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32),
+ .PKT_ADDR_H (49),
+ .PKT_ADDR_L (36),
+ .PKT_TRANS_COMPRESSED_READ (50),
+ .PKT_TRANS_POSTED (51),
+ .PKT_TRANS_WRITE (52),
+ .PKT_TRANS_READ (53),
+ .PKT_TRANS_LOCK (54),
+ .PKT_SRC_ID_H (64),
+ .PKT_SRC_ID_L (62),
+ .PKT_DEST_ID_H (67),
+ .PKT_DEST_ID_L (65),
+ .PKT_BURSTWRAP_H (60),
+ .PKT_BURSTWRAP_L (58),
+ .PKT_BYTE_CNT_H (57),
+ .PKT_BYTE_CNT_L (55),
+ .PKT_PROTECTION_H (68),
+ .PKT_PROTECTION_L (68),
+ .ST_CHANNEL_W (8),
+ .ST_DATA_W (69),
+ .AVS_BURSTCOUNT_W (3),
+ .SUPPRESS_0_BYTEEN_CMD (0),
+ .PREVENT_FIFO_OVERFLOW (1)
+ ) tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .m0_address (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
+ .m0_burstcount (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .m0_byteenable (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .m0_debugaccess (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .m0_lock (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .m0_readdata (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .m0_readdatavalid (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .m0_read (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .m0_waitrequest (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .m0_writedata (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .m0_write (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .rp_endofpacket (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
+ .rp_ready (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
+ .rp_valid (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .rp_data (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .rp_startofpacket (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .cp_ready (cmd_xbar_demux_001_src3_ready), // cp.ready
+ .cp_valid (cmd_xbar_demux_001_src3_valid), // .valid
+ .cp_data (cmd_xbar_demux_001_src3_data), // .data
+ .cp_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket
+ .cp_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket
+ .cp_channel (cmd_xbar_demux_001_src3_channel), // .channel
+ .rf_sink_ready (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
+ .rf_sink_valid (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .rf_sink_startofpacket (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .rf_sink_endofpacket (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .rf_sink_data (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
+ .rf_source_ready (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
+ .rf_source_valid (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .rf_source_startofpacket (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .rf_source_endofpacket (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .rf_source_data (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
+ .rdata_fifo_sink_ready (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
+ .rdata_fifo_sink_valid (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_sink_data (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
+ .rdata_fifo_src_ready (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
+ .rdata_fifo_src_valid (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_src_data (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
+ );
+
+ altera_avalon_sc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (70),
+ .FIFO_DEPTH (2),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (1),
+ .USE_FILL_LEVEL (0),
+ .EMPTY_LATENCY (1),
+ .USE_MEMORY_BLOCKS (0),
+ .USE_STORE_FORWARD (0),
+ .USE_ALMOST_FULL_IF (0),
+ .USE_ALMOST_EMPTY_IF (0)
+ ) tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .in_data (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
+ .in_valid (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .in_ready (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
+ .in_startofpacket (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .in_endofpacket (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .out_data (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
+ .out_valid (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .out_ready (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
+ .out_startofpacket (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .out_endofpacket (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .csr_address (2'b00), // (terminated)
+ .csr_read (1'b0), // (terminated)
+ .csr_write (1'b0), // (terminated)
+ .csr_readdata (), // (terminated)
+ .csr_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .almost_full_data (), // (terminated)
+ .almost_empty_data (), // (terminated)
+ .in_empty (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_error (), // (terminated)
+ .in_channel (1'b0), // (terminated)
+ .out_channel () // (terminated)
+ );
+
+ altera_merlin_slave_agent #(
+ .PKT_DATA_H (31),
+ .PKT_DATA_L (0),
+ .PKT_BEGIN_BURST (61),
+ .PKT_SYMBOL_W (8),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32),
+ .PKT_ADDR_H (49),
+ .PKT_ADDR_L (36),
+ .PKT_TRANS_COMPRESSED_READ (50),
+ .PKT_TRANS_POSTED (51),
+ .PKT_TRANS_WRITE (52),
+ .PKT_TRANS_READ (53),
+ .PKT_TRANS_LOCK (54),
+ .PKT_SRC_ID_H (64),
+ .PKT_SRC_ID_L (62),
+ .PKT_DEST_ID_H (67),
+ .PKT_DEST_ID_L (65),
+ .PKT_BURSTWRAP_H (60),
+ .PKT_BURSTWRAP_L (58),
+ .PKT_BYTE_CNT_H (57),
+ .PKT_BYTE_CNT_L (55),
+ .PKT_PROTECTION_H (68),
+ .PKT_PROTECTION_L (68),
+ .ST_CHANNEL_W (8),
+ .ST_DATA_W (69),
+ .AVS_BURSTCOUNT_W (3),
+ .SUPPRESS_0_BYTEEN_CMD (0),
+ .PREVENT_FIFO_OVERFLOW (1)
+ ) tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .m0_address (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
+ .m0_burstcount (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .m0_byteenable (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .m0_debugaccess (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .m0_lock (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .m0_readdata (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .m0_readdatavalid (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .m0_read (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .m0_waitrequest (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .m0_writedata (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .m0_write (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .rp_endofpacket (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
+ .rp_ready (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
+ .rp_valid (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .rp_data (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .rp_startofpacket (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .cp_ready (cmd_xbar_demux_001_src6_ready), // cp.ready
+ .cp_valid (cmd_xbar_demux_001_src6_valid), // .valid
+ .cp_data (cmd_xbar_demux_001_src6_data), // .data
+ .cp_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket
+ .cp_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket
+ .cp_channel (cmd_xbar_demux_001_src6_channel), // .channel
+ .rf_sink_ready (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
+ .rf_sink_valid (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .rf_sink_startofpacket (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .rf_sink_endofpacket (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .rf_sink_data (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
+ .rf_source_ready (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
+ .rf_source_valid (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .rf_source_startofpacket (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .rf_source_endofpacket (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .rf_source_data (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
+ .rdata_fifo_sink_ready (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
+ .rdata_fifo_sink_valid (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_sink_data (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
+ .rdata_fifo_src_ready (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
+ .rdata_fifo_src_valid (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_src_data (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
+ );
+
+ altera_avalon_sc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (70),
+ .FIFO_DEPTH (2),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (1),
+ .USE_FILL_LEVEL (0),
+ .EMPTY_LATENCY (1),
+ .USE_MEMORY_BLOCKS (0),
+ .USE_STORE_FORWARD (0),
+ .USE_ALMOST_FULL_IF (0),
+ .USE_ALMOST_EMPTY_IF (0)
+ ) tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .in_data (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
+ .in_valid (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .in_ready (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
+ .in_startofpacket (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .in_endofpacket (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .out_data (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
+ .out_valid (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .out_ready (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
+ .out_startofpacket (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .out_endofpacket (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .csr_address (2'b00), // (terminated)
+ .csr_read (1'b0), // (terminated)
+ .csr_write (1'b0), // (terminated)
+ .csr_readdata (), // (terminated)
+ .csr_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .almost_full_data (), // (terminated)
+ .almost_empty_data (), // (terminated)
+ .in_empty (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_error (), // (terminated)
+ .in_channel (1'b0), // (terminated)
+ .out_channel () // (terminated)
+ );
+
+ altera_merlin_slave_agent #(
+ .PKT_DATA_H (31),
+ .PKT_DATA_L (0),
+ .PKT_BEGIN_BURST (61),
+ .PKT_SYMBOL_W (8),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32),
+ .PKT_ADDR_H (49),
+ .PKT_ADDR_L (36),
+ .PKT_TRANS_COMPRESSED_READ (50),
+ .PKT_TRANS_POSTED (51),
+ .PKT_TRANS_WRITE (52),
+ .PKT_TRANS_READ (53),
+ .PKT_TRANS_LOCK (54),
+ .PKT_SRC_ID_H (64),
+ .PKT_SRC_ID_L (62),
+ .PKT_DEST_ID_H (67),
+ .PKT_DEST_ID_L (65),
+ .PKT_BURSTWRAP_H (60),
+ .PKT_BURSTWRAP_L (58),
+ .PKT_BYTE_CNT_H (57),
+ .PKT_BYTE_CNT_L (55),
+ .PKT_PROTECTION_H (68),
+ .PKT_PROTECTION_L (68),
+ .ST_CHANNEL_W (8),
+ .ST_DATA_W (69),
+ .AVS_BURSTCOUNT_W (3),
+ .SUPPRESS_0_BYTEEN_CMD (0),
+ .PREVENT_FIFO_OVERFLOW (1)
+ ) tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .m0_address (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
+ .m0_burstcount (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .m0_byteenable (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .m0_debugaccess (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .m0_lock (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .m0_readdata (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .m0_readdatavalid (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .m0_read (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .m0_waitrequest (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .m0_writedata (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .m0_write (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .rp_endofpacket (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
+ .rp_ready (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
+ .rp_valid (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .rp_data (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .rp_startofpacket (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .cp_ready (cmd_xbar_demux_001_src7_ready), // cp.ready
+ .cp_valid (cmd_xbar_demux_001_src7_valid), // .valid
+ .cp_data (cmd_xbar_demux_001_src7_data), // .data
+ .cp_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket
+ .cp_endofpacket (cmd_xbar_demux_001_src7_endofpacket), // .endofpacket
+ .cp_channel (cmd_xbar_demux_001_src7_channel), // .channel
+ .rf_sink_ready (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
+ .rf_sink_valid (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .rf_sink_startofpacket (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .rf_sink_endofpacket (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .rf_sink_data (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
+ .rf_source_ready (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
+ .rf_source_valid (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .rf_source_startofpacket (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .rf_source_endofpacket (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .rf_source_data (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
+ .rdata_fifo_sink_ready (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
+ .rdata_fifo_sink_valid (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_sink_data (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
+ .rdata_fifo_src_ready (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
+ .rdata_fifo_src_valid (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_src_data (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
+ );
+
+ altera_avalon_sc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (70),
+ .FIFO_DEPTH (3),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (1),
+ .USE_FILL_LEVEL (0),
+ .EMPTY_LATENCY (1),
+ .USE_MEMORY_BLOCKS (0),
+ .USE_STORE_FORWARD (0),
+ .USE_ALMOST_FULL_IF (0),
+ .USE_ALMOST_EMPTY_IF (0)
+ ) tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .in_data (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
+ .in_valid (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .in_ready (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
+ .in_startofpacket (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .in_endofpacket (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .out_data (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
+ .out_valid (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .out_ready (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
+ .out_startofpacket (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .out_endofpacket (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .csr_address (2'b00), // (terminated)
+ .csr_read (1'b0), // (terminated)
+ .csr_write (1'b0), // (terminated)
+ .csr_readdata (), // (terminated)
+ .csr_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .almost_full_data (), // (terminated)
+ .almost_empty_data (), // (terminated)
+ .in_empty (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_error (), // (terminated)
+ .in_channel (1'b0), // (terminated)
+ .out_channel () // (terminated)
+ );
+
+ altera_merlin_master_agent #(
+ .PKT_PROTECTION_H (68),
+ .PKT_PROTECTION_L (68),
+ .PKT_BEGIN_BURST (61),
+ .PKT_BURSTWRAP_H (60),
+ .PKT_BURSTWRAP_L (58),
+ .PKT_BYTE_CNT_H (57),
+ .PKT_BYTE_CNT_L (55),
+ .PKT_ADDR_H (49),
+ .PKT_ADDR_L (36),
+ .PKT_TRANS_COMPRESSED_READ (50),
+ .PKT_TRANS_POSTED (51),
+ .PKT_TRANS_WRITE (52),
+ .PKT_TRANS_READ (53),
+ .PKT_TRANS_LOCK (54),
+ .PKT_DATA_H (31),
+ .PKT_DATA_L (0),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32),
+ .PKT_SRC_ID_H (64),
+ .PKT_SRC_ID_L (62),
+ .PKT_DEST_ID_H (67),
+ .PKT_DEST_ID_L (65),
+ .ST_DATA_W (69),
+ .ST_CHANNEL_W (8),
+ .AV_BURSTCOUNT_W (3),
+ .SUPPRESS_0_BYTEEN_RSP (0),
+ .ID (0),
+ .BURSTWRAP_VALUE (7)
+ ) tx_bridge_m0_translator_avalon_universal_master_0_agent (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .av_address (tx_bridge_m0_translator_avalon_universal_master_0_address), // av.address
+ .av_write (tx_bridge_m0_translator_avalon_universal_master_0_write), // .write
+ .av_read (tx_bridge_m0_translator_avalon_universal_master_0_read), // .read
+ .av_writedata (tx_bridge_m0_translator_avalon_universal_master_0_writedata), // .writedata
+ .av_readdata (tx_bridge_m0_translator_avalon_universal_master_0_readdata), // .readdata
+ .av_waitrequest (tx_bridge_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
+ .av_readdatavalid (tx_bridge_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
+ .av_byteenable (tx_bridge_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
+ .av_burstcount (tx_bridge_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
+ .av_debugaccess (tx_bridge_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
+ .av_lock (tx_bridge_m0_translator_avalon_universal_master_0_lock), // .lock
+ .cp_valid (tx_bridge_m0_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
+ .cp_data (tx_bridge_m0_translator_avalon_universal_master_0_agent_cp_data), // .data
+ .cp_startofpacket (tx_bridge_m0_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
+ .cp_endofpacket (tx_bridge_m0_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
+ .cp_ready (tx_bridge_m0_translator_avalon_universal_master_0_agent_cp_ready), // .ready
+ .rp_valid (limiter_001_rsp_src_valid), // rp.valid
+ .rp_data (limiter_001_rsp_src_data), // .data
+ .rp_channel (limiter_001_rsp_src_channel), // .channel
+ .rp_startofpacket (limiter_001_rsp_src_startofpacket), // .startofpacket
+ .rp_endofpacket (limiter_001_rsp_src_endofpacket), // .endofpacket
+ .rp_ready (limiter_001_rsp_src_ready) // .ready
+ );
+
+ altera_merlin_slave_agent #(
+ .PKT_DATA_H (31),
+ .PKT_DATA_L (0),
+ .PKT_BEGIN_BURST (61),
+ .PKT_SYMBOL_W (8),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32),
+ .PKT_ADDR_H (49),
+ .PKT_ADDR_L (36),
+ .PKT_TRANS_COMPRESSED_READ (50),
+ .PKT_TRANS_POSTED (51),
+ .PKT_TRANS_WRITE (52),
+ .PKT_TRANS_READ (53),
+ .PKT_TRANS_LOCK (54),
+ .PKT_SRC_ID_H (64),
+ .PKT_SRC_ID_L (62),
+ .PKT_DEST_ID_H (67),
+ .PKT_DEST_ID_L (65),
+ .PKT_BURSTWRAP_H (60),
+ .PKT_BURSTWRAP_L (58),
+ .PKT_BYTE_CNT_H (57),
+ .PKT_BYTE_CNT_L (55),
+ .PKT_PROTECTION_H (68),
+ .PKT_PROTECTION_L (68),
+ .ST_CHANNEL_W (8),
+ .ST_DATA_W (69),
+ .AVS_BURSTCOUNT_W (3),
+ .SUPPRESS_0_BYTEEN_CMD (0),
+ .PREVENT_FIFO_OVERFLOW (1)
+ ) tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .m0_address (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
+ .m0_burstcount (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .m0_byteenable (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .m0_debugaccess (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .m0_lock (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .m0_readdata (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .m0_readdatavalid (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .m0_read (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .m0_waitrequest (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .m0_writedata (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .m0_write (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .rp_endofpacket (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
+ .rp_ready (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
+ .rp_valid (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .rp_data (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .rp_startofpacket (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .cp_ready (cmd_xbar_demux_001_src5_ready), // cp.ready
+ .cp_valid (cmd_xbar_demux_001_src5_valid), // .valid
+ .cp_data (cmd_xbar_demux_001_src5_data), // .data
+ .cp_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket
+ .cp_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket
+ .cp_channel (cmd_xbar_demux_001_src5_channel), // .channel
+ .rf_sink_ready (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
+ .rf_sink_valid (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .rf_sink_startofpacket (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .rf_sink_endofpacket (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .rf_sink_data (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
+ .rf_source_ready (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
+ .rf_source_valid (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .rf_source_startofpacket (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .rf_source_endofpacket (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .rf_source_data (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
+ .rdata_fifo_sink_ready (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
+ .rdata_fifo_sink_valid (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_sink_data (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
+ .rdata_fifo_src_ready (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
+ .rdata_fifo_src_valid (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_src_data (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
+ );
+
+ altera_avalon_sc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (70),
+ .FIFO_DEPTH (2),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (1),
+ .USE_FILL_LEVEL (0),
+ .EMPTY_LATENCY (1),
+ .USE_MEMORY_BLOCKS (0),
+ .USE_STORE_FORWARD (0),
+ .USE_ALMOST_FULL_IF (0),
+ .USE_ALMOST_EMPTY_IF (0)
+ ) tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .in_data (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
+ .in_valid (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .in_ready (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
+ .in_startofpacket (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .in_endofpacket (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .out_data (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
+ .out_valid (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .out_ready (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
+ .out_startofpacket (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .out_endofpacket (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .csr_address (2'b00), // (terminated)
+ .csr_read (1'b0), // (terminated)
+ .csr_write (1'b0), // (terminated)
+ .csr_readdata (), // (terminated)
+ .csr_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .almost_full_data (), // (terminated)
+ .almost_empty_data (), // (terminated)
+ .in_empty (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_error (), // (terminated)
+ .in_channel (1'b0), // (terminated)
+ .out_channel () // (terminated)
+ );
+
+ altera_merlin_slave_agent #(
+ .PKT_DATA_H (31),
+ .PKT_DATA_L (0),
+ .PKT_BEGIN_BURST (61),
+ .PKT_SYMBOL_W (8),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32),
+ .PKT_ADDR_H (49),
+ .PKT_ADDR_L (36),
+ .PKT_TRANS_COMPRESSED_READ (50),
+ .PKT_TRANS_POSTED (51),
+ .PKT_TRANS_WRITE (52),
+ .PKT_TRANS_READ (53),
+ .PKT_TRANS_LOCK (54),
+ .PKT_SRC_ID_H (64),
+ .PKT_SRC_ID_L (62),
+ .PKT_DEST_ID_H (67),
+ .PKT_DEST_ID_L (65),
+ .PKT_BURSTWRAP_H (60),
+ .PKT_BURSTWRAP_L (58),
+ .PKT_BYTE_CNT_H (57),
+ .PKT_BYTE_CNT_L (55),
+ .PKT_PROTECTION_H (68),
+ .PKT_PROTECTION_L (68),
+ .ST_CHANNEL_W (8),
+ .ST_DATA_W (69),
+ .AVS_BURSTCOUNT_W (3),
+ .SUPPRESS_0_BYTEEN_CMD (0),
+ .PREVENT_FIFO_OVERFLOW (1)
+ ) tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .m0_address (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
+ .m0_burstcount (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .m0_byteenable (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .m0_debugaccess (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .m0_lock (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .m0_readdata (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .m0_readdatavalid (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .m0_read (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .m0_waitrequest (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .m0_writedata (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .m0_write (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .rp_endofpacket (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
+ .rp_ready (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
+ .rp_valid (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .rp_data (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .rp_startofpacket (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .cp_ready (cmd_xbar_demux_001_src4_ready), // cp.ready
+ .cp_valid (cmd_xbar_demux_001_src4_valid), // .valid
+ .cp_data (cmd_xbar_demux_001_src4_data), // .data
+ .cp_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket
+ .cp_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket
+ .cp_channel (cmd_xbar_demux_001_src4_channel), // .channel
+ .rf_sink_ready (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
+ .rf_sink_valid (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .rf_sink_startofpacket (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .rf_sink_endofpacket (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .rf_sink_data (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
+ .rf_source_ready (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
+ .rf_source_valid (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .rf_source_startofpacket (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .rf_source_endofpacket (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .rf_source_data (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
+ .rdata_fifo_sink_ready (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
+ .rdata_fifo_sink_valid (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_sink_data (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
+ .rdata_fifo_src_ready (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
+ .rdata_fifo_src_valid (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_src_data (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
+ );
+
+ altera_avalon_sc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (70),
+ .FIFO_DEPTH (2),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (1),
+ .USE_FILL_LEVEL (0),
+ .EMPTY_LATENCY (1),
+ .USE_MEMORY_BLOCKS (0),
+ .USE_STORE_FORWARD (0),
+ .USE_ALMOST_FULL_IF (0),
+ .USE_ALMOST_EMPTY_IF (0)
+ ) tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .in_data (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
+ .in_valid (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .in_ready (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
+ .in_startofpacket (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .in_endofpacket (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .out_data (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
+ .out_valid (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .out_ready (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
+ .out_startofpacket (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .out_endofpacket (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .csr_address (2'b00), // (terminated)
+ .csr_read (1'b0), // (terminated)
+ .csr_write (1'b0), // (terminated)
+ .csr_readdata (), // (terminated)
+ .csr_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .almost_full_data (), // (terminated)
+ .almost_empty_data (), // (terminated)
+ .in_empty (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_error (), // (terminated)
+ .in_channel (1'b0), // (terminated)
+ .out_channel () // (terminated)
+ );
+
+ altera_merlin_slave_agent #(
+ .PKT_DATA_H (31),
+ .PKT_DATA_L (0),
+ .PKT_BEGIN_BURST (61),
+ .PKT_SYMBOL_W (8),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32),
+ .PKT_ADDR_H (49),
+ .PKT_ADDR_L (36),
+ .PKT_TRANS_COMPRESSED_READ (50),
+ .PKT_TRANS_POSTED (51),
+ .PKT_TRANS_WRITE (52),
+ .PKT_TRANS_READ (53),
+ .PKT_TRANS_LOCK (54),
+ .PKT_SRC_ID_H (64),
+ .PKT_SRC_ID_L (62),
+ .PKT_DEST_ID_H (67),
+ .PKT_DEST_ID_L (65),
+ .PKT_BURSTWRAP_H (60),
+ .PKT_BURSTWRAP_L (58),
+ .PKT_BYTE_CNT_H (57),
+ .PKT_BYTE_CNT_L (55),
+ .PKT_PROTECTION_H (68),
+ .PKT_PROTECTION_L (68),
+ .ST_CHANNEL_W (8),
+ .ST_DATA_W (69),
+ .AVS_BURSTCOUNT_W (3),
+ .SUPPRESS_0_BYTEEN_CMD (0),
+ .PREVENT_FIFO_OVERFLOW (1)
+ ) tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .m0_address (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
+ .m0_burstcount (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .m0_byteenable (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .m0_debugaccess (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .m0_lock (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .m0_readdata (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .m0_readdatavalid (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .m0_read (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .m0_waitrequest (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .m0_writedata (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .m0_write (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .rp_endofpacket (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
+ .rp_ready (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
+ .rp_valid (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .rp_data (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .rp_startofpacket (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .cp_ready (cmd_xbar_demux_001_src1_ready), // cp.ready
+ .cp_valid (cmd_xbar_demux_001_src1_valid), // .valid
+ .cp_data (cmd_xbar_demux_001_src1_data), // .data
+ .cp_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
+ .cp_endofpacket (cmd_xbar_demux_001_src1_endofpacket), // .endofpacket
+ .cp_channel (cmd_xbar_demux_001_src1_channel), // .channel
+ .rf_sink_ready (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
+ .rf_sink_valid (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .rf_sink_startofpacket (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .rf_sink_endofpacket (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .rf_sink_data (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
+ .rf_source_ready (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
+ .rf_source_valid (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .rf_source_startofpacket (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .rf_source_endofpacket (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .rf_source_data (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
+ .rdata_fifo_sink_ready (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
+ .rdata_fifo_sink_valid (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_sink_data (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
+ .rdata_fifo_src_ready (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
+ .rdata_fifo_src_valid (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_src_data (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
+ );
+
+ altera_avalon_sc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (70),
+ .FIFO_DEPTH (2),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (1),
+ .USE_FILL_LEVEL (0),
+ .EMPTY_LATENCY (1),
+ .USE_MEMORY_BLOCKS (0),
+ .USE_STORE_FORWARD (0),
+ .USE_ALMOST_FULL_IF (0),
+ .USE_ALMOST_EMPTY_IF (0)
+ ) tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .in_data (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
+ .in_valid (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .in_ready (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
+ .in_startofpacket (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .in_endofpacket (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .out_data (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
+ .out_valid (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .out_ready (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
+ .out_startofpacket (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .out_endofpacket (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .csr_address (2'b00), // (terminated)
+ .csr_read (1'b0), // (terminated)
+ .csr_write (1'b0), // (terminated)
+ .csr_readdata (), // (terminated)
+ .csr_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .almost_full_data (), // (terminated)
+ .almost_empty_data (), // (terminated)
+ .in_empty (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_error (), // (terminated)
+ .in_channel (1'b0), // (terminated)
+ .out_channel () // (terminated)
+ );
+
+ altera_merlin_slave_agent #(
+ .PKT_DATA_H (31),
+ .PKT_DATA_L (0),
+ .PKT_BEGIN_BURST (61),
+ .PKT_SYMBOL_W (8),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32),
+ .PKT_ADDR_H (49),
+ .PKT_ADDR_L (36),
+ .PKT_TRANS_COMPRESSED_READ (50),
+ .PKT_TRANS_POSTED (51),
+ .PKT_TRANS_WRITE (52),
+ .PKT_TRANS_READ (53),
+ .PKT_TRANS_LOCK (54),
+ .PKT_SRC_ID_H (64),
+ .PKT_SRC_ID_L (62),
+ .PKT_DEST_ID_H (67),
+ .PKT_DEST_ID_L (65),
+ .PKT_BURSTWRAP_H (60),
+ .PKT_BURSTWRAP_L (58),
+ .PKT_BYTE_CNT_H (57),
+ .PKT_BYTE_CNT_L (55),
+ .PKT_PROTECTION_H (68),
+ .PKT_PROTECTION_L (68),
+ .ST_CHANNEL_W (8),
+ .ST_DATA_W (69),
+ .AVS_BURSTCOUNT_W (3),
+ .SUPPRESS_0_BYTEEN_CMD (0),
+ .PREVENT_FIFO_OVERFLOW (1)
+ ) tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .m0_address (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
+ .m0_burstcount (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .m0_byteenable (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .m0_debugaccess (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .m0_lock (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .m0_readdata (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .m0_readdatavalid (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .m0_read (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .m0_waitrequest (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .m0_writedata (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .m0_write (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .rp_endofpacket (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
+ .rp_ready (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
+ .rp_valid (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .rp_data (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .rp_startofpacket (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .cp_ready (cmd_xbar_demux_001_src2_ready), // cp.ready
+ .cp_valid (cmd_xbar_demux_001_src2_valid), // .valid
+ .cp_data (cmd_xbar_demux_001_src2_data), // .data
+ .cp_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket
+ .cp_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket
+ .cp_channel (cmd_xbar_demux_001_src2_channel), // .channel
+ .rf_sink_ready (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
+ .rf_sink_valid (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .rf_sink_startofpacket (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .rf_sink_endofpacket (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .rf_sink_data (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
+ .rf_source_ready (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
+ .rf_source_valid (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .rf_source_startofpacket (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .rf_source_endofpacket (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .rf_source_data (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
+ .rdata_fifo_sink_ready (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
+ .rdata_fifo_sink_valid (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_sink_data (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
+ .rdata_fifo_src_ready (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
+ .rdata_fifo_src_valid (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_src_data (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
+ );
+
+ altera_avalon_sc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (70),
+ .FIFO_DEPTH (2),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (1),
+ .USE_FILL_LEVEL (0),
+ .EMPTY_LATENCY (1),
+ .USE_MEMORY_BLOCKS (0),
+ .USE_STORE_FORWARD (0),
+ .USE_ALMOST_FULL_IF (0),
+ .USE_ALMOST_EMPTY_IF (0)
+ ) tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .in_data (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
+ .in_valid (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .in_ready (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
+ .in_startofpacket (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .in_endofpacket (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .out_data (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
+ .out_valid (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .out_ready (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
+ .out_startofpacket (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .out_endofpacket (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .csr_address (2'b00), // (terminated)
+ .csr_read (1'b0), // (terminated)
+ .csr_write (1'b0), // (terminated)
+ .csr_readdata (), // (terminated)
+ .csr_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .almost_full_data (), // (terminated)
+ .almost_empty_data (), // (terminated)
+ .in_empty (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_error (), // (terminated)
+ .in_channel (1'b0), // (terminated)
+ .out_channel () // (terminated)
+ );
+
+ altera_merlin_slave_agent #(
+ .PKT_DATA_H (31),
+ .PKT_DATA_L (0),
+ .PKT_BEGIN_BURST (61),
+ .PKT_SYMBOL_W (8),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32),
+ .PKT_ADDR_H (49),
+ .PKT_ADDR_L (36),
+ .PKT_TRANS_COMPRESSED_READ (50),
+ .PKT_TRANS_POSTED (51),
+ .PKT_TRANS_WRITE (52),
+ .PKT_TRANS_READ (53),
+ .PKT_TRANS_LOCK (54),
+ .PKT_SRC_ID_H (64),
+ .PKT_SRC_ID_L (62),
+ .PKT_DEST_ID_H (67),
+ .PKT_DEST_ID_L (65),
+ .PKT_BURSTWRAP_H (60),
+ .PKT_BURSTWRAP_L (58),
+ .PKT_BYTE_CNT_H (57),
+ .PKT_BYTE_CNT_L (55),
+ .PKT_PROTECTION_H (68),
+ .PKT_PROTECTION_L (68),
+ .ST_CHANNEL_W (7),
+ .ST_DATA_W (69),
+ .AVS_BURSTCOUNT_W (3),
+ .SUPPRESS_0_BYTEEN_CMD (0),
+ .PREVENT_FIFO_OVERFLOW (1)
+ ) rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .m0_address (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
+ .m0_burstcount (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .m0_byteenable (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .m0_debugaccess (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .m0_lock (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .m0_readdata (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .m0_readdatavalid (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .m0_read (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .m0_waitrequest (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .m0_writedata (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .m0_write (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .rp_endofpacket (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
+ .rp_ready (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
+ .rp_valid (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .rp_data (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .rp_startofpacket (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .cp_ready (cmd_xbar_demux_002_src1_ready), // cp.ready
+ .cp_valid (cmd_xbar_demux_002_src1_valid), // .valid
+ .cp_data (cmd_xbar_demux_002_src1_data), // .data
+ .cp_startofpacket (cmd_xbar_demux_002_src1_startofpacket), // .startofpacket
+ .cp_endofpacket (cmd_xbar_demux_002_src1_endofpacket), // .endofpacket
+ .cp_channel (cmd_xbar_demux_002_src1_channel), // .channel
+ .rf_sink_ready (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
+ .rf_sink_valid (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .rf_sink_startofpacket (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .rf_sink_endofpacket (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .rf_sink_data (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
+ .rf_source_ready (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
+ .rf_source_valid (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .rf_source_startofpacket (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .rf_source_endofpacket (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .rf_source_data (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
+ .rdata_fifo_sink_ready (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
+ .rdata_fifo_sink_valid (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_sink_data (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
+ .rdata_fifo_src_ready (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
+ .rdata_fifo_src_valid (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_src_data (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
+ );
+
+ altera_avalon_sc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (70),
+ .FIFO_DEPTH (2),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (1),
+ .USE_FILL_LEVEL (0),
+ .EMPTY_LATENCY (1),
+ .USE_MEMORY_BLOCKS (0),
+ .USE_STORE_FORWARD (0),
+ .USE_ALMOST_FULL_IF (0),
+ .USE_ALMOST_EMPTY_IF (0)
+ ) rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .in_data (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
+ .in_valid (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .in_ready (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
+ .in_startofpacket (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .in_endofpacket (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .out_data (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
+ .out_valid (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .out_ready (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
+ .out_startofpacket (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .out_endofpacket (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .csr_address (2'b00), // (terminated)
+ .csr_read (1'b0), // (terminated)
+ .csr_write (1'b0), // (terminated)
+ .csr_readdata (), // (terminated)
+ .csr_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .almost_full_data (), // (terminated)
+ .almost_empty_data (), // (terminated)
+ .in_empty (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_error (), // (terminated)
+ .in_channel (1'b0), // (terminated)
+ .out_channel () // (terminated)
+ );
+
+ altera_merlin_slave_agent #(
+ .PKT_DATA_H (31),
+ .PKT_DATA_L (0),
+ .PKT_BEGIN_BURST (61),
+ .PKT_SYMBOL_W (8),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32),
+ .PKT_ADDR_H (49),
+ .PKT_ADDR_L (36),
+ .PKT_TRANS_COMPRESSED_READ (50),
+ .PKT_TRANS_POSTED (51),
+ .PKT_TRANS_WRITE (52),
+ .PKT_TRANS_READ (53),
+ .PKT_TRANS_LOCK (54),
+ .PKT_SRC_ID_H (64),
+ .PKT_SRC_ID_L (62),
+ .PKT_DEST_ID_H (67),
+ .PKT_DEST_ID_L (65),
+ .PKT_BURSTWRAP_H (60),
+ .PKT_BURSTWRAP_L (58),
+ .PKT_BYTE_CNT_H (57),
+ .PKT_BYTE_CNT_L (55),
+ .PKT_PROTECTION_H (68),
+ .PKT_PROTECTION_L (68),
+ .ST_CHANNEL_W (7),
+ .ST_DATA_W (69),
+ .AVS_BURSTCOUNT_W (3),
+ .SUPPRESS_0_BYTEEN_CMD (0),
+ .PREVENT_FIFO_OVERFLOW (1)
+ ) rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .m0_address (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
+ .m0_burstcount (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .m0_byteenable (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .m0_debugaccess (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .m0_lock (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .m0_readdata (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .m0_readdatavalid (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .m0_read (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .m0_waitrequest (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .m0_writedata (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .m0_write (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .rp_endofpacket (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
+ .rp_ready (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
+ .rp_valid (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .rp_data (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .rp_startofpacket (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .cp_ready (cmd_xbar_demux_002_src0_ready), // cp.ready
+ .cp_valid (cmd_xbar_demux_002_src0_valid), // .valid
+ .cp_data (cmd_xbar_demux_002_src0_data), // .data
+ .cp_startofpacket (cmd_xbar_demux_002_src0_startofpacket), // .startofpacket
+ .cp_endofpacket (cmd_xbar_demux_002_src0_endofpacket), // .endofpacket
+ .cp_channel (cmd_xbar_demux_002_src0_channel), // .channel
+ .rf_sink_ready (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
+ .rf_sink_valid (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .rf_sink_startofpacket (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .rf_sink_endofpacket (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .rf_sink_data (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
+ .rf_source_ready (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
+ .rf_source_valid (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .rf_source_startofpacket (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .rf_source_endofpacket (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .rf_source_data (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
+ .rdata_fifo_sink_ready (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
+ .rdata_fifo_sink_valid (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_sink_data (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
+ .rdata_fifo_src_ready (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
+ .rdata_fifo_src_valid (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_src_data (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
+ );
+
+ altera_avalon_sc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (70),
+ .FIFO_DEPTH (2),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (1),
+ .USE_FILL_LEVEL (0),
+ .EMPTY_LATENCY (1),
+ .USE_MEMORY_BLOCKS (0),
+ .USE_STORE_FORWARD (0),
+ .USE_ALMOST_FULL_IF (0),
+ .USE_ALMOST_EMPTY_IF (0)
+ ) rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .in_data (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
+ .in_valid (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .in_ready (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
+ .in_startofpacket (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .in_endofpacket (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .out_data (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
+ .out_valid (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .out_ready (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
+ .out_startofpacket (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .out_endofpacket (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .csr_address (2'b00), // (terminated)
+ .csr_read (1'b0), // (terminated)
+ .csr_write (1'b0), // (terminated)
+ .csr_readdata (), // (terminated)
+ .csr_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .almost_full_data (), // (terminated)
+ .almost_empty_data (), // (terminated)
+ .in_empty (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_error (), // (terminated)
+ .in_channel (1'b0), // (terminated)
+ .out_channel () // (terminated)
+ );
+
+ altera_merlin_slave_agent #(
+ .PKT_DATA_H (31),
+ .PKT_DATA_L (0),
+ .PKT_BEGIN_BURST (61),
+ .PKT_SYMBOL_W (8),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32),
+ .PKT_ADDR_H (49),
+ .PKT_ADDR_L (36),
+ .PKT_TRANS_COMPRESSED_READ (50),
+ .PKT_TRANS_POSTED (51),
+ .PKT_TRANS_WRITE (52),
+ .PKT_TRANS_READ (53),
+ .PKT_TRANS_LOCK (54),
+ .PKT_SRC_ID_H (64),
+ .PKT_SRC_ID_L (62),
+ .PKT_DEST_ID_H (67),
+ .PKT_DEST_ID_L (65),
+ .PKT_BURSTWRAP_H (60),
+ .PKT_BURSTWRAP_L (58),
+ .PKT_BYTE_CNT_H (57),
+ .PKT_BYTE_CNT_L (55),
+ .PKT_PROTECTION_H (68),
+ .PKT_PROTECTION_L (68),
+ .ST_CHANNEL_W (7),
+ .ST_DATA_W (69),
+ .AVS_BURSTCOUNT_W (3),
+ .SUPPRESS_0_BYTEEN_CMD (0),
+ .PREVENT_FIFO_OVERFLOW (1)
+ ) rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .m0_address (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
+ .m0_burstcount (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .m0_byteenable (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .m0_debugaccess (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .m0_lock (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .m0_readdata (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .m0_readdatavalid (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .m0_read (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .m0_waitrequest (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .m0_writedata (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .m0_write (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .rp_endofpacket (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
+ .rp_ready (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
+ .rp_valid (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .rp_data (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .rp_startofpacket (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .cp_ready (cmd_xbar_demux_002_src4_ready), // cp.ready
+ .cp_valid (cmd_xbar_demux_002_src4_valid), // .valid
+ .cp_data (cmd_xbar_demux_002_src4_data), // .data
+ .cp_startofpacket (cmd_xbar_demux_002_src4_startofpacket), // .startofpacket
+ .cp_endofpacket (cmd_xbar_demux_002_src4_endofpacket), // .endofpacket
+ .cp_channel (cmd_xbar_demux_002_src4_channel), // .channel
+ .rf_sink_ready (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
+ .rf_sink_valid (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .rf_sink_startofpacket (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .rf_sink_endofpacket (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .rf_sink_data (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
+ .rf_source_ready (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
+ .rf_source_valid (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .rf_source_startofpacket (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .rf_source_endofpacket (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .rf_source_data (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
+ .rdata_fifo_sink_ready (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
+ .rdata_fifo_sink_valid (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_sink_data (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
+ .rdata_fifo_src_ready (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
+ .rdata_fifo_src_valid (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_src_data (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
+ );
+
+ altera_avalon_sc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (70),
+ .FIFO_DEPTH (2),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (1),
+ .USE_FILL_LEVEL (0),
+ .EMPTY_LATENCY (1),
+ .USE_MEMORY_BLOCKS (0),
+ .USE_STORE_FORWARD (0),
+ .USE_ALMOST_FULL_IF (0),
+ .USE_ALMOST_EMPTY_IF (0)
+ ) rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .in_data (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
+ .in_valid (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .in_ready (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
+ .in_startofpacket (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .in_endofpacket (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .out_data (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
+ .out_valid (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .out_ready (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
+ .out_startofpacket (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .out_endofpacket (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .csr_address (2'b00), // (terminated)
+ .csr_read (1'b0), // (terminated)
+ .csr_write (1'b0), // (terminated)
+ .csr_readdata (), // (terminated)
+ .csr_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .almost_full_data (), // (terminated)
+ .almost_empty_data (), // (terminated)
+ .in_empty (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_error (), // (terminated)
+ .in_channel (1'b0), // (terminated)
+ .out_channel () // (terminated)
+ );
+
+ altera_merlin_master_agent #(
+ .PKT_PROTECTION_H (68),
+ .PKT_PROTECTION_L (68),
+ .PKT_BEGIN_BURST (61),
+ .PKT_BURSTWRAP_H (60),
+ .PKT_BURSTWRAP_L (58),
+ .PKT_BYTE_CNT_H (57),
+ .PKT_BYTE_CNT_L (55),
+ .PKT_ADDR_H (49),
+ .PKT_ADDR_L (36),
+ .PKT_TRANS_COMPRESSED_READ (50),
+ .PKT_TRANS_POSTED (51),
+ .PKT_TRANS_WRITE (52),
+ .PKT_TRANS_READ (53),
+ .PKT_TRANS_LOCK (54),
+ .PKT_DATA_H (31),
+ .PKT_DATA_L (0),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32),
+ .PKT_SRC_ID_H (64),
+ .PKT_SRC_ID_L (62),
+ .PKT_DEST_ID_H (67),
+ .PKT_DEST_ID_L (65),
+ .ST_DATA_W (69),
+ .ST_CHANNEL_W (7),
+ .AV_BURSTCOUNT_W (3),
+ .SUPPRESS_0_BYTEEN_RSP (0),
+ .ID (0),
+ .BURSTWRAP_VALUE (7)
+ ) rx_bridge_m0_translator_avalon_universal_master_0_agent (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .av_address (rx_bridge_m0_translator_avalon_universal_master_0_address), // av.address
+ .av_write (rx_bridge_m0_translator_avalon_universal_master_0_write), // .write
+ .av_read (rx_bridge_m0_translator_avalon_universal_master_0_read), // .read
+ .av_writedata (rx_bridge_m0_translator_avalon_universal_master_0_writedata), // .writedata
+ .av_readdata (rx_bridge_m0_translator_avalon_universal_master_0_readdata), // .readdata
+ .av_waitrequest (rx_bridge_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
+ .av_readdatavalid (rx_bridge_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
+ .av_byteenable (rx_bridge_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
+ .av_burstcount (rx_bridge_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
+ .av_debugaccess (rx_bridge_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
+ .av_lock (rx_bridge_m0_translator_avalon_universal_master_0_lock), // .lock
+ .cp_valid (rx_bridge_m0_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
+ .cp_data (rx_bridge_m0_translator_avalon_universal_master_0_agent_cp_data), // .data
+ .cp_startofpacket (rx_bridge_m0_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
+ .cp_endofpacket (rx_bridge_m0_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
+ .cp_ready (rx_bridge_m0_translator_avalon_universal_master_0_agent_cp_ready), // .ready
+ .rp_valid (limiter_002_rsp_src_valid), // rp.valid
+ .rp_data (limiter_002_rsp_src_data), // .data
+ .rp_channel (limiter_002_rsp_src_channel), // .channel
+ .rp_startofpacket (limiter_002_rsp_src_startofpacket), // .startofpacket
+ .rp_endofpacket (limiter_002_rsp_src_endofpacket), // .endofpacket
+ .rp_ready (limiter_002_rsp_src_ready) // .ready
+ );
+
+ altera_merlin_slave_agent #(
+ .PKT_DATA_H (31),
+ .PKT_DATA_L (0),
+ .PKT_BEGIN_BURST (61),
+ .PKT_SYMBOL_W (8),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32),
+ .PKT_ADDR_H (49),
+ .PKT_ADDR_L (36),
+ .PKT_TRANS_COMPRESSED_READ (50),
+ .PKT_TRANS_POSTED (51),
+ .PKT_TRANS_WRITE (52),
+ .PKT_TRANS_READ (53),
+ .PKT_TRANS_LOCK (54),
+ .PKT_SRC_ID_H (64),
+ .PKT_SRC_ID_L (62),
+ .PKT_DEST_ID_H (67),
+ .PKT_DEST_ID_L (65),
+ .PKT_BURSTWRAP_H (60),
+ .PKT_BURSTWRAP_L (58),
+ .PKT_BYTE_CNT_H (57),
+ .PKT_BYTE_CNT_L (55),
+ .PKT_PROTECTION_H (68),
+ .PKT_PROTECTION_L (68),
+ .ST_CHANNEL_W (7),
+ .ST_DATA_W (69),
+ .AVS_BURSTCOUNT_W (3),
+ .SUPPRESS_0_BYTEEN_CMD (0),
+ .PREVENT_FIFO_OVERFLOW (1)
+ ) rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .m0_address (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
+ .m0_burstcount (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .m0_byteenable (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .m0_debugaccess (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .m0_lock (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .m0_readdata (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .m0_readdatavalid (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .m0_read (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .m0_waitrequest (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .m0_writedata (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .m0_write (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .rp_endofpacket (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
+ .rp_ready (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
+ .rp_valid (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .rp_data (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .rp_startofpacket (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .cp_ready (cmd_xbar_demux_002_src5_ready), // cp.ready
+ .cp_valid (cmd_xbar_demux_002_src5_valid), // .valid
+ .cp_data (cmd_xbar_demux_002_src5_data), // .data
+ .cp_startofpacket (cmd_xbar_demux_002_src5_startofpacket), // .startofpacket
+ .cp_endofpacket (cmd_xbar_demux_002_src5_endofpacket), // .endofpacket
+ .cp_channel (cmd_xbar_demux_002_src5_channel), // .channel
+ .rf_sink_ready (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
+ .rf_sink_valid (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .rf_sink_startofpacket (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .rf_sink_endofpacket (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .rf_sink_data (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
+ .rf_source_ready (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
+ .rf_source_valid (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .rf_source_startofpacket (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .rf_source_endofpacket (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .rf_source_data (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
+ .rdata_fifo_sink_ready (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
+ .rdata_fifo_sink_valid (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_sink_data (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
+ .rdata_fifo_src_ready (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
+ .rdata_fifo_src_valid (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_src_data (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
+ );
+
+ altera_avalon_sc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (70),
+ .FIFO_DEPTH (3),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (1),
+ .USE_FILL_LEVEL (0),
+ .EMPTY_LATENCY (1),
+ .USE_MEMORY_BLOCKS (0),
+ .USE_STORE_FORWARD (0),
+ .USE_ALMOST_FULL_IF (0),
+ .USE_ALMOST_EMPTY_IF (0)
+ ) rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .in_data (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
+ .in_valid (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .in_ready (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
+ .in_startofpacket (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .in_endofpacket (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .out_data (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
+ .out_valid (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .out_ready (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
+ .out_startofpacket (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .out_endofpacket (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .csr_address (2'b00), // (terminated)
+ .csr_read (1'b0), // (terminated)
+ .csr_write (1'b0), // (terminated)
+ .csr_readdata (), // (terminated)
+ .csr_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .almost_full_data (), // (terminated)
+ .almost_empty_data (), // (terminated)
+ .in_empty (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_error (), // (terminated)
+ .in_channel (1'b0), // (terminated)
+ .out_channel () // (terminated)
+ );
+
+ altera_merlin_slave_agent #(
+ .PKT_DATA_H (31),
+ .PKT_DATA_L (0),
+ .PKT_BEGIN_BURST (61),
+ .PKT_SYMBOL_W (8),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32),
+ .PKT_ADDR_H (49),
+ .PKT_ADDR_L (36),
+ .PKT_TRANS_COMPRESSED_READ (50),
+ .PKT_TRANS_POSTED (51),
+ .PKT_TRANS_WRITE (52),
+ .PKT_TRANS_READ (53),
+ .PKT_TRANS_LOCK (54),
+ .PKT_SRC_ID_H (64),
+ .PKT_SRC_ID_L (62),
+ .PKT_DEST_ID_H (67),
+ .PKT_DEST_ID_L (65),
+ .PKT_BURSTWRAP_H (60),
+ .PKT_BURSTWRAP_L (58),
+ .PKT_BYTE_CNT_H (57),
+ .PKT_BYTE_CNT_L (55),
+ .PKT_PROTECTION_H (68),
+ .PKT_PROTECTION_L (68),
+ .ST_CHANNEL_W (7),
+ .ST_DATA_W (69),
+ .AVS_BURSTCOUNT_W (3),
+ .SUPPRESS_0_BYTEEN_CMD (0),
+ .PREVENT_FIFO_OVERFLOW (1)
+ ) rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .m0_address (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
+ .m0_burstcount (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .m0_byteenable (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .m0_debugaccess (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .m0_lock (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .m0_readdata (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .m0_readdatavalid (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .m0_read (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .m0_waitrequest (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .m0_writedata (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .m0_write (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .rp_endofpacket (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
+ .rp_ready (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
+ .rp_valid (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .rp_data (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .rp_startofpacket (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .cp_ready (cmd_xbar_demux_002_src6_ready), // cp.ready
+ .cp_valid (cmd_xbar_demux_002_src6_valid), // .valid
+ .cp_data (cmd_xbar_demux_002_src6_data), // .data
+ .cp_startofpacket (cmd_xbar_demux_002_src6_startofpacket), // .startofpacket
+ .cp_endofpacket (cmd_xbar_demux_002_src6_endofpacket), // .endofpacket
+ .cp_channel (cmd_xbar_demux_002_src6_channel), // .channel
+ .rf_sink_ready (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
+ .rf_sink_valid (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .rf_sink_startofpacket (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .rf_sink_endofpacket (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .rf_sink_data (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
+ .rf_source_ready (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
+ .rf_source_valid (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .rf_source_startofpacket (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .rf_source_endofpacket (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .rf_source_data (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
+ .rdata_fifo_sink_ready (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
+ .rdata_fifo_sink_valid (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_sink_data (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
+ .rdata_fifo_src_ready (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
+ .rdata_fifo_src_valid (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_src_data (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
+ );
+
+ altera_avalon_sc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (70),
+ .FIFO_DEPTH (2),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (1),
+ .USE_FILL_LEVEL (0),
+ .EMPTY_LATENCY (1),
+ .USE_MEMORY_BLOCKS (0),
+ .USE_STORE_FORWARD (0),
+ .USE_ALMOST_FULL_IF (0),
+ .USE_ALMOST_EMPTY_IF (0)
+ ) rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .in_data (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
+ .in_valid (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .in_ready (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
+ .in_startofpacket (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .in_endofpacket (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .out_data (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
+ .out_valid (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .out_ready (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
+ .out_startofpacket (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .out_endofpacket (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .csr_address (2'b00), // (terminated)
+ .csr_read (1'b0), // (terminated)
+ .csr_write (1'b0), // (terminated)
+ .csr_readdata (), // (terminated)
+ .csr_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .almost_full_data (), // (terminated)
+ .almost_empty_data (), // (terminated)
+ .in_empty (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_error (), // (terminated)
+ .in_channel (1'b0), // (terminated)
+ .out_channel () // (terminated)
+ );
+
+ altera_merlin_slave_agent #(
+ .PKT_DATA_H (31),
+ .PKT_DATA_L (0),
+ .PKT_BEGIN_BURST (61),
+ .PKT_SYMBOL_W (8),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32),
+ .PKT_ADDR_H (49),
+ .PKT_ADDR_L (36),
+ .PKT_TRANS_COMPRESSED_READ (50),
+ .PKT_TRANS_POSTED (51),
+ .PKT_TRANS_WRITE (52),
+ .PKT_TRANS_READ (53),
+ .PKT_TRANS_LOCK (54),
+ .PKT_SRC_ID_H (64),
+ .PKT_SRC_ID_L (62),
+ .PKT_DEST_ID_H (67),
+ .PKT_DEST_ID_L (65),
+ .PKT_BURSTWRAP_H (60),
+ .PKT_BURSTWRAP_L (58),
+ .PKT_BYTE_CNT_H (57),
+ .PKT_BYTE_CNT_L (55),
+ .PKT_PROTECTION_H (68),
+ .PKT_PROTECTION_L (68),
+ .ST_CHANNEL_W (7),
+ .ST_DATA_W (69),
+ .AVS_BURSTCOUNT_W (3),
+ .SUPPRESS_0_BYTEEN_CMD (0),
+ .PREVENT_FIFO_OVERFLOW (1)
+ ) rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .m0_address (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
+ .m0_burstcount (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .m0_byteenable (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .m0_debugaccess (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .m0_lock (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .m0_readdata (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .m0_readdatavalid (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .m0_read (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .m0_waitrequest (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .m0_writedata (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .m0_write (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .rp_endofpacket (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
+ .rp_ready (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
+ .rp_valid (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .rp_data (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .rp_startofpacket (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .cp_ready (cmd_xbar_demux_002_src2_ready), // cp.ready
+ .cp_valid (cmd_xbar_demux_002_src2_valid), // .valid
+ .cp_data (cmd_xbar_demux_002_src2_data), // .data
+ .cp_startofpacket (cmd_xbar_demux_002_src2_startofpacket), // .startofpacket
+ .cp_endofpacket (cmd_xbar_demux_002_src2_endofpacket), // .endofpacket
+ .cp_channel (cmd_xbar_demux_002_src2_channel), // .channel
+ .rf_sink_ready (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
+ .rf_sink_valid (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .rf_sink_startofpacket (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .rf_sink_endofpacket (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .rf_sink_data (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
+ .rf_source_ready (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
+ .rf_source_valid (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .rf_source_startofpacket (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .rf_source_endofpacket (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .rf_source_data (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
+ .rdata_fifo_sink_ready (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
+ .rdata_fifo_sink_valid (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_sink_data (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
+ .rdata_fifo_src_ready (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
+ .rdata_fifo_src_valid (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_src_data (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
+ );
+
+ altera_avalon_sc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (70),
+ .FIFO_DEPTH (2),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (1),
+ .USE_FILL_LEVEL (0),
+ .EMPTY_LATENCY (1),
+ .USE_MEMORY_BLOCKS (0),
+ .USE_STORE_FORWARD (0),
+ .USE_ALMOST_FULL_IF (0),
+ .USE_ALMOST_EMPTY_IF (0)
+ ) rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .in_data (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
+ .in_valid (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .in_ready (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
+ .in_startofpacket (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .in_endofpacket (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .out_data (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
+ .out_valid (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .out_ready (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
+ .out_startofpacket (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .out_endofpacket (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .csr_address (2'b00), // (terminated)
+ .csr_read (1'b0), // (terminated)
+ .csr_write (1'b0), // (terminated)
+ .csr_readdata (), // (terminated)
+ .csr_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .almost_full_data (), // (terminated)
+ .almost_empty_data (), // (terminated)
+ .in_empty (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_error (), // (terminated)
+ .in_channel (1'b0), // (terminated)
+ .out_channel () // (terminated)
+ );
+
+ altera_merlin_slave_agent #(
+ .PKT_DATA_H (31),
+ .PKT_DATA_L (0),
+ .PKT_BEGIN_BURST (61),
+ .PKT_SYMBOL_W (8),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32),
+ .PKT_ADDR_H (49),
+ .PKT_ADDR_L (36),
+ .PKT_TRANS_COMPRESSED_READ (50),
+ .PKT_TRANS_POSTED (51),
+ .PKT_TRANS_WRITE (52),
+ .PKT_TRANS_READ (53),
+ .PKT_TRANS_LOCK (54),
+ .PKT_SRC_ID_H (64),
+ .PKT_SRC_ID_L (62),
+ .PKT_DEST_ID_H (67),
+ .PKT_DEST_ID_L (65),
+ .PKT_BURSTWRAP_H (60),
+ .PKT_BURSTWRAP_L (58),
+ .PKT_BYTE_CNT_H (57),
+ .PKT_BYTE_CNT_L (55),
+ .PKT_PROTECTION_H (68),
+ .PKT_PROTECTION_L (68),
+ .ST_CHANNEL_W (7),
+ .ST_DATA_W (69),
+ .AVS_BURSTCOUNT_W (3),
+ .SUPPRESS_0_BYTEEN_CMD (0),
+ .PREVENT_FIFO_OVERFLOW (1)
+ ) rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .m0_address (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
+ .m0_burstcount (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
+ .m0_byteenable (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
+ .m0_debugaccess (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
+ .m0_lock (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
+ .m0_readdata (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
+ .m0_readdatavalid (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
+ .m0_read (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
+ .m0_waitrequest (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
+ .m0_writedata (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
+ .m0_write (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
+ .rp_endofpacket (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
+ .rp_ready (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
+ .rp_valid (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .rp_data (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .rp_startofpacket (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .cp_ready (cmd_xbar_demux_002_src3_ready), // cp.ready
+ .cp_valid (cmd_xbar_demux_002_src3_valid), // .valid
+ .cp_data (cmd_xbar_demux_002_src3_data), // .data
+ .cp_startofpacket (cmd_xbar_demux_002_src3_startofpacket), // .startofpacket
+ .cp_endofpacket (cmd_xbar_demux_002_src3_endofpacket), // .endofpacket
+ .cp_channel (cmd_xbar_demux_002_src3_channel), // .channel
+ .rf_sink_ready (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
+ .rf_sink_valid (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .rf_sink_startofpacket (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .rf_sink_endofpacket (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .rf_sink_data (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
+ .rf_source_ready (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
+ .rf_source_valid (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .rf_source_startofpacket (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .rf_source_endofpacket (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .rf_source_data (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
+ .rdata_fifo_sink_ready (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
+ .rdata_fifo_sink_valid (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_sink_data (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
+ .rdata_fifo_src_ready (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
+ .rdata_fifo_src_valid (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_src_data (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
+ );
+
+ altera_avalon_sc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (70),
+ .FIFO_DEPTH (2),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (1),
+ .USE_FILL_LEVEL (0),
+ .EMPTY_LATENCY (1),
+ .USE_MEMORY_BLOCKS (0),
+ .USE_STORE_FORWARD (0),
+ .USE_ALMOST_FULL_IF (0),
+ .USE_ALMOST_EMPTY_IF (0)
+ ) rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .in_data (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
+ .in_valid (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
+ .in_ready (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
+ .in_startofpacket (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
+ .in_endofpacket (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
+ .out_data (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
+ .out_valid (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
+ .out_ready (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
+ .out_startofpacket (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .out_endofpacket (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .csr_address (2'b00), // (terminated)
+ .csr_read (1'b0), // (terminated)
+ .csr_write (1'b0), // (terminated)
+ .csr_readdata (), // (terminated)
+ .csr_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .almost_full_data (), // (terminated)
+ .almost_empty_data (), // (terminated)
+ .in_empty (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_error (), // (terminated)
+ .in_channel (1'b0), // (terminated)
+ .out_channel () // (terminated)
+ );
+
+ ip_stratixiv_mac_10g_addr_router addr_router (
+ .sink_ready (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
+ .sink_valid (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent_cp_valid), // .valid
+ .sink_data (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent_cp_data), // .data
+ .sink_startofpacket (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
+ .sink_endofpacket (merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
+ .clk (csr_clk_clk), // clk.clk
+ .reset (rst_controller_reset_out_reset), // clk_reset.reset
+ .src_ready (addr_router_src_ready), // src.ready
+ .src_valid (addr_router_src_valid), // .valid
+ .src_data (addr_router_src_data), // .data
+ .src_channel (addr_router_src_channel), // .channel
+ .src_startofpacket (addr_router_src_startofpacket), // .startofpacket
+ .src_endofpacket (addr_router_src_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_id_router id_router (
+ .sink_ready (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
+ .sink_valid (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .sink_data (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .sink_startofpacket (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .sink_endofpacket (tx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .src_ready (id_router_src_ready), // src.ready
+ .src_valid (id_router_src_valid), // .valid
+ .src_data (id_router_src_data), // .data
+ .src_channel (id_router_src_channel), // .channel
+ .src_startofpacket (id_router_src_startofpacket), // .startofpacket
+ .src_endofpacket (id_router_src_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_id_router id_router_001 (
+ .sink_ready (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
+ .sink_valid (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .sink_data (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .sink_startofpacket (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .sink_endofpacket (rx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .src_ready (id_router_001_src_ready), // src.ready
+ .src_valid (id_router_001_src_valid), // .valid
+ .src_data (id_router_001_src_data), // .data
+ .src_channel (id_router_001_src_channel), // .channel
+ .src_startofpacket (id_router_001_src_startofpacket), // .startofpacket
+ .src_endofpacket (id_router_001_src_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_addr_router_001 addr_router_001 (
+ .sink_ready (tx_bridge_m0_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
+ .sink_valid (tx_bridge_m0_translator_avalon_universal_master_0_agent_cp_valid), // .valid
+ .sink_data (tx_bridge_m0_translator_avalon_universal_master_0_agent_cp_data), // .data
+ .sink_startofpacket (tx_bridge_m0_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
+ .sink_endofpacket (tx_bridge_m0_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .src_ready (addr_router_001_src_ready), // src.ready
+ .src_valid (addr_router_001_src_valid), // .valid
+ .src_data (addr_router_001_src_data), // .data
+ .src_channel (addr_router_001_src_channel), // .channel
+ .src_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
+ .src_endofpacket (addr_router_001_src_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_id_router_002 id_router_002 (
+ .sink_ready (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
+ .sink_valid (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .sink_data (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .sink_startofpacket (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .sink_endofpacket (tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .src_ready (id_router_002_src_ready), // src.ready
+ .src_valid (id_router_002_src_valid), // .valid
+ .src_data (id_router_002_src_data), // .data
+ .src_channel (id_router_002_src_channel), // .channel
+ .src_startofpacket (id_router_002_src_startofpacket), // .startofpacket
+ .src_endofpacket (id_router_002_src_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_id_router_002 id_router_003 (
+ .sink_ready (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
+ .sink_valid (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .sink_data (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .sink_startofpacket (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .sink_endofpacket (tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .src_ready (id_router_003_src_ready), // src.ready
+ .src_valid (id_router_003_src_valid), // .valid
+ .src_data (id_router_003_src_data), // .data
+ .src_channel (id_router_003_src_channel), // .channel
+ .src_startofpacket (id_router_003_src_startofpacket), // .startofpacket
+ .src_endofpacket (id_router_003_src_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_id_router_002 id_router_004 (
+ .sink_ready (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
+ .sink_valid (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .sink_data (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .sink_startofpacket (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .sink_endofpacket (tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .src_ready (id_router_004_src_ready), // src.ready
+ .src_valid (id_router_004_src_valid), // .valid
+ .src_data (id_router_004_src_data), // .data
+ .src_channel (id_router_004_src_channel), // .channel
+ .src_startofpacket (id_router_004_src_startofpacket), // .startofpacket
+ .src_endofpacket (id_router_004_src_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_id_router_002 id_router_005 (
+ .sink_ready (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
+ .sink_valid (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .sink_data (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .sink_startofpacket (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .sink_endofpacket (tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .src_ready (id_router_005_src_ready), // src.ready
+ .src_valid (id_router_005_src_valid), // .valid
+ .src_data (id_router_005_src_data), // .data
+ .src_channel (id_router_005_src_channel), // .channel
+ .src_startofpacket (id_router_005_src_startofpacket), // .startofpacket
+ .src_endofpacket (id_router_005_src_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_id_router_002 id_router_006 (
+ .sink_ready (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
+ .sink_valid (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .sink_data (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .sink_startofpacket (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .sink_endofpacket (tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .src_ready (id_router_006_src_ready), // src.ready
+ .src_valid (id_router_006_src_valid), // .valid
+ .src_data (id_router_006_src_data), // .data
+ .src_channel (id_router_006_src_channel), // .channel
+ .src_startofpacket (id_router_006_src_startofpacket), // .startofpacket
+ .src_endofpacket (id_router_006_src_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_id_router_002 id_router_007 (
+ .sink_ready (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
+ .sink_valid (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .sink_data (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .sink_startofpacket (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .sink_endofpacket (tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .src_ready (id_router_007_src_ready), // src.ready
+ .src_valid (id_router_007_src_valid), // .valid
+ .src_data (id_router_007_src_data), // .data
+ .src_channel (id_router_007_src_channel), // .channel
+ .src_startofpacket (id_router_007_src_startofpacket), // .startofpacket
+ .src_endofpacket (id_router_007_src_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_id_router_002 id_router_008 (
+ .sink_ready (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
+ .sink_valid (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .sink_data (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .sink_startofpacket (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .sink_endofpacket (tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .src_ready (id_router_008_src_ready), // src.ready
+ .src_valid (id_router_008_src_valid), // .valid
+ .src_data (id_router_008_src_data), // .data
+ .src_channel (id_router_008_src_channel), // .channel
+ .src_startofpacket (id_router_008_src_startofpacket), // .startofpacket
+ .src_endofpacket (id_router_008_src_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_id_router_002 id_router_009 (
+ .sink_ready (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
+ .sink_valid (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .sink_data (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .sink_startofpacket (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .sink_endofpacket (tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .src_ready (id_router_009_src_ready), // src.ready
+ .src_valid (id_router_009_src_valid), // .valid
+ .src_data (id_router_009_src_data), // .data
+ .src_channel (id_router_009_src_channel), // .channel
+ .src_startofpacket (id_router_009_src_startofpacket), // .startofpacket
+ .src_endofpacket (id_router_009_src_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_addr_router_002 addr_router_002 (
+ .sink_ready (rx_bridge_m0_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
+ .sink_valid (rx_bridge_m0_translator_avalon_universal_master_0_agent_cp_valid), // .valid
+ .sink_data (rx_bridge_m0_translator_avalon_universal_master_0_agent_cp_data), // .data
+ .sink_startofpacket (rx_bridge_m0_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
+ .sink_endofpacket (rx_bridge_m0_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .src_ready (addr_router_002_src_ready), // src.ready
+ .src_valid (addr_router_002_src_valid), // .valid
+ .src_data (addr_router_002_src_data), // .data
+ .src_channel (addr_router_002_src_channel), // .channel
+ .src_startofpacket (addr_router_002_src_startofpacket), // .startofpacket
+ .src_endofpacket (addr_router_002_src_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_id_router_010 id_router_010 (
+ .sink_ready (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
+ .sink_valid (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .sink_data (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .sink_startofpacket (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .sink_endofpacket (rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .src_ready (id_router_010_src_ready), // src.ready
+ .src_valid (id_router_010_src_valid), // .valid
+ .src_data (id_router_010_src_data), // .data
+ .src_channel (id_router_010_src_channel), // .channel
+ .src_startofpacket (id_router_010_src_startofpacket), // .startofpacket
+ .src_endofpacket (id_router_010_src_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_id_router_010 id_router_011 (
+ .sink_ready (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
+ .sink_valid (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .sink_data (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .sink_startofpacket (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .sink_endofpacket (rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .src_ready (id_router_011_src_ready), // src.ready
+ .src_valid (id_router_011_src_valid), // .valid
+ .src_data (id_router_011_src_data), // .data
+ .src_channel (id_router_011_src_channel), // .channel
+ .src_startofpacket (id_router_011_src_startofpacket), // .startofpacket
+ .src_endofpacket (id_router_011_src_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_id_router_010 id_router_012 (
+ .sink_ready (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
+ .sink_valid (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .sink_data (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .sink_startofpacket (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .sink_endofpacket (rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .src_ready (id_router_012_src_ready), // src.ready
+ .src_valid (id_router_012_src_valid), // .valid
+ .src_data (id_router_012_src_data), // .data
+ .src_channel (id_router_012_src_channel), // .channel
+ .src_startofpacket (id_router_012_src_startofpacket), // .startofpacket
+ .src_endofpacket (id_router_012_src_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_id_router_010 id_router_013 (
+ .sink_ready (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
+ .sink_valid (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .sink_data (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .sink_startofpacket (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .sink_endofpacket (rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .src_ready (id_router_013_src_ready), // src.ready
+ .src_valid (id_router_013_src_valid), // .valid
+ .src_data (id_router_013_src_data), // .data
+ .src_channel (id_router_013_src_channel), // .channel
+ .src_startofpacket (id_router_013_src_startofpacket), // .startofpacket
+ .src_endofpacket (id_router_013_src_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_id_router_010 id_router_014 (
+ .sink_ready (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
+ .sink_valid (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .sink_data (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .sink_startofpacket (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .sink_endofpacket (rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .src_ready (id_router_014_src_ready), // src.ready
+ .src_valid (id_router_014_src_valid), // .valid
+ .src_data (id_router_014_src_data), // .data
+ .src_channel (id_router_014_src_channel), // .channel
+ .src_startofpacket (id_router_014_src_startofpacket), // .startofpacket
+ .src_endofpacket (id_router_014_src_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_id_router_010 id_router_015 (
+ .sink_ready (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
+ .sink_valid (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .sink_data (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .sink_startofpacket (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .sink_endofpacket (rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .src_ready (id_router_015_src_ready), // src.ready
+ .src_valid (id_router_015_src_valid), // .valid
+ .src_data (id_router_015_src_data), // .data
+ .src_channel (id_router_015_src_channel), // .channel
+ .src_startofpacket (id_router_015_src_startofpacket), // .startofpacket
+ .src_endofpacket (id_router_015_src_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_id_router_010 id_router_016 (
+ .sink_ready (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
+ .sink_valid (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
+ .sink_data (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
+ .sink_startofpacket (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
+ .sink_endofpacket (rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .src_ready (id_router_016_src_ready), // src.ready
+ .src_valid (id_router_016_src_valid), // .valid
+ .src_data (id_router_016_src_data), // .data
+ .src_channel (id_router_016_src_channel), // .channel
+ .src_startofpacket (id_router_016_src_startofpacket), // .startofpacket
+ .src_endofpacket (id_router_016_src_endofpacket) // .endofpacket
+ );
+
+ altera_merlin_traffic_limiter #(
+ .PKT_DEST_ID_H (64),
+ .PKT_DEST_ID_L (64),
+ .PKT_TRANS_POSTED (52),
+ .MAX_OUTSTANDING_RESPONSES (5),
+ .PIPELINED (0),
+ .ST_DATA_W (66),
+ .ST_CHANNEL_W (2),
+ .VALID_WIDTH (2),
+ .ENFORCE_ORDER (1),
+ .PKT_BYTE_CNT_H (58),
+ .PKT_BYTE_CNT_L (56),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32)
+ ) limiter (
+ .clk (csr_clk_clk), // clk.clk
+ .reset (rst_controller_reset_out_reset), // clk_reset.reset
+ .cmd_sink_ready (addr_router_src_ready), // cmd_sink.ready
+ .cmd_sink_valid (addr_router_src_valid), // .valid
+ .cmd_sink_data (addr_router_src_data), // .data
+ .cmd_sink_channel (addr_router_src_channel), // .channel
+ .cmd_sink_startofpacket (addr_router_src_startofpacket), // .startofpacket
+ .cmd_sink_endofpacket (addr_router_src_endofpacket), // .endofpacket
+ .cmd_src_ready (limiter_cmd_src_ready), // cmd_src.ready
+ .cmd_src_data (limiter_cmd_src_data), // .data
+ .cmd_src_channel (limiter_cmd_src_channel), // .channel
+ .cmd_src_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket
+ .cmd_src_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket
+ .rsp_sink_ready (rsp_xbar_mux_src_ready), // rsp_sink.ready
+ .rsp_sink_valid (rsp_xbar_mux_src_valid), // .valid
+ .rsp_sink_channel (rsp_xbar_mux_src_channel), // .channel
+ .rsp_sink_data (rsp_xbar_mux_src_data), // .data
+ .rsp_sink_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
+ .rsp_sink_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
+ .rsp_src_ready (limiter_rsp_src_ready), // rsp_src.ready
+ .rsp_src_valid (limiter_rsp_src_valid), // .valid
+ .rsp_src_data (limiter_rsp_src_data), // .data
+ .rsp_src_channel (limiter_rsp_src_channel), // .channel
+ .rsp_src_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket
+ .rsp_src_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket
+ .cmd_src_valid (limiter_cmd_valid_data) // cmd_valid.data
+ );
+
+ altera_merlin_traffic_limiter #(
+ .PKT_DEST_ID_H (67),
+ .PKT_DEST_ID_L (65),
+ .PKT_TRANS_POSTED (51),
+ .MAX_OUTSTANDING_RESPONSES (2),
+ .PIPELINED (0),
+ .ST_DATA_W (69),
+ .ST_CHANNEL_W (8),
+ .VALID_WIDTH (8),
+ .ENFORCE_ORDER (1),
+ .PKT_BYTE_CNT_H (57),
+ .PKT_BYTE_CNT_L (55),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32)
+ ) limiter_001 (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .cmd_sink_ready (addr_router_001_src_ready), // cmd_sink.ready
+ .cmd_sink_valid (addr_router_001_src_valid), // .valid
+ .cmd_sink_data (addr_router_001_src_data), // .data
+ .cmd_sink_channel (addr_router_001_src_channel), // .channel
+ .cmd_sink_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
+ .cmd_sink_endofpacket (addr_router_001_src_endofpacket), // .endofpacket
+ .cmd_src_ready (limiter_001_cmd_src_ready), // cmd_src.ready
+ .cmd_src_data (limiter_001_cmd_src_data), // .data
+ .cmd_src_channel (limiter_001_cmd_src_channel), // .channel
+ .cmd_src_startofpacket (limiter_001_cmd_src_startofpacket), // .startofpacket
+ .cmd_src_endofpacket (limiter_001_cmd_src_endofpacket), // .endofpacket
+ .rsp_sink_ready (rsp_xbar_mux_001_src_ready), // rsp_sink.ready
+ .rsp_sink_valid (rsp_xbar_mux_001_src_valid), // .valid
+ .rsp_sink_channel (rsp_xbar_mux_001_src_channel), // .channel
+ .rsp_sink_data (rsp_xbar_mux_001_src_data), // .data
+ .rsp_sink_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
+ .rsp_sink_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
+ .rsp_src_ready (limiter_001_rsp_src_ready), // rsp_src.ready
+ .rsp_src_valid (limiter_001_rsp_src_valid), // .valid
+ .rsp_src_data (limiter_001_rsp_src_data), // .data
+ .rsp_src_channel (limiter_001_rsp_src_channel), // .channel
+ .rsp_src_startofpacket (limiter_001_rsp_src_startofpacket), // .startofpacket
+ .rsp_src_endofpacket (limiter_001_rsp_src_endofpacket), // .endofpacket
+ .cmd_src_valid (limiter_001_cmd_valid_data) // cmd_valid.data
+ );
+
+ altera_merlin_traffic_limiter #(
+ .PKT_DEST_ID_H (67),
+ .PKT_DEST_ID_L (65),
+ .PKT_TRANS_POSTED (51),
+ .MAX_OUTSTANDING_RESPONSES (2),
+ .PIPELINED (0),
+ .ST_DATA_W (69),
+ .ST_CHANNEL_W (7),
+ .VALID_WIDTH (7),
+ .ENFORCE_ORDER (1),
+ .PKT_BYTE_CNT_H (57),
+ .PKT_BYTE_CNT_L (55),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32)
+ ) limiter_002 (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .cmd_sink_ready (addr_router_002_src_ready), // cmd_sink.ready
+ .cmd_sink_valid (addr_router_002_src_valid), // .valid
+ .cmd_sink_data (addr_router_002_src_data), // .data
+ .cmd_sink_channel (addr_router_002_src_channel), // .channel
+ .cmd_sink_startofpacket (addr_router_002_src_startofpacket), // .startofpacket
+ .cmd_sink_endofpacket (addr_router_002_src_endofpacket), // .endofpacket
+ .cmd_src_ready (limiter_002_cmd_src_ready), // cmd_src.ready
+ .cmd_src_data (limiter_002_cmd_src_data), // .data
+ .cmd_src_channel (limiter_002_cmd_src_channel), // .channel
+ .cmd_src_startofpacket (limiter_002_cmd_src_startofpacket), // .startofpacket
+ .cmd_src_endofpacket (limiter_002_cmd_src_endofpacket), // .endofpacket
+ .rsp_sink_ready (rsp_xbar_mux_002_src_ready), // rsp_sink.ready
+ .rsp_sink_valid (rsp_xbar_mux_002_src_valid), // .valid
+ .rsp_sink_channel (rsp_xbar_mux_002_src_channel), // .channel
+ .rsp_sink_data (rsp_xbar_mux_002_src_data), // .data
+ .rsp_sink_startofpacket (rsp_xbar_mux_002_src_startofpacket), // .startofpacket
+ .rsp_sink_endofpacket (rsp_xbar_mux_002_src_endofpacket), // .endofpacket
+ .rsp_src_ready (limiter_002_rsp_src_ready), // rsp_src.ready
+ .rsp_src_valid (limiter_002_rsp_src_valid), // .valid
+ .rsp_src_data (limiter_002_rsp_src_data), // .data
+ .rsp_src_channel (limiter_002_rsp_src_channel), // .channel
+ .rsp_src_startofpacket (limiter_002_rsp_src_startofpacket), // .startofpacket
+ .rsp_src_endofpacket (limiter_002_rsp_src_endofpacket), // .endofpacket
+ .cmd_src_valid (limiter_002_cmd_valid_data) // cmd_valid.data
+ );
+
+ altera_reset_controller #(
+ .NUM_RESET_INPUTS (1),
+ .OUTPUT_RESET_SYNC_EDGES ("deassert"),
+ .SYNC_DEPTH (2)
+ ) rst_controller (
+ .reset_in0 (~csr_reset_reset_n), // reset_in0.reset
+ .clk (csr_clk_clk), // clk.clk
+ .reset_out (rst_controller_reset_out_reset), // reset_out.reset
+ .reset_in1 (1'b0), // (terminated)
+ .reset_in2 (1'b0), // (terminated)
+ .reset_in3 (1'b0), // (terminated)
+ .reset_in4 (1'b0), // (terminated)
+ .reset_in5 (1'b0), // (terminated)
+ .reset_in6 (1'b0), // (terminated)
+ .reset_in7 (1'b0), // (terminated)
+ .reset_in8 (1'b0), // (terminated)
+ .reset_in9 (1'b0), // (terminated)
+ .reset_in10 (1'b0), // (terminated)
+ .reset_in11 (1'b0), // (terminated)
+ .reset_in12 (1'b0), // (terminated)
+ .reset_in13 (1'b0), // (terminated)
+ .reset_in14 (1'b0), // (terminated)
+ .reset_in15 (1'b0) // (terminated)
+ );
+
+ altera_reset_controller #(
+ .NUM_RESET_INPUTS (1),
+ .OUTPUT_RESET_SYNC_EDGES ("deassert"),
+ .SYNC_DEPTH (2)
+ ) rst_controller_001 (
+ .reset_in0 (~tx_reset_reset_n), // reset_in0.reset
+ .clk (tx_clk_clk), // clk.clk
+ .reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
+ .reset_in1 (1'b0), // (terminated)
+ .reset_in2 (1'b0), // (terminated)
+ .reset_in3 (1'b0), // (terminated)
+ .reset_in4 (1'b0), // (terminated)
+ .reset_in5 (1'b0), // (terminated)
+ .reset_in6 (1'b0), // (terminated)
+ .reset_in7 (1'b0), // (terminated)
+ .reset_in8 (1'b0), // (terminated)
+ .reset_in9 (1'b0), // (terminated)
+ .reset_in10 (1'b0), // (terminated)
+ .reset_in11 (1'b0), // (terminated)
+ .reset_in12 (1'b0), // (terminated)
+ .reset_in13 (1'b0), // (terminated)
+ .reset_in14 (1'b0), // (terminated)
+ .reset_in15 (1'b0) // (terminated)
+ );
+
+ altera_reset_controller #(
+ .NUM_RESET_INPUTS (1),
+ .OUTPUT_RESET_SYNC_EDGES ("deassert"),
+ .SYNC_DEPTH (2)
+ ) rst_controller_002 (
+ .reset_in0 (~rx_reset_reset_n), // reset_in0.reset
+ .clk (rx_clk_clk), // clk.clk
+ .reset_out (rst_controller_002_reset_out_reset), // reset_out.reset
+ .reset_in1 (1'b0), // (terminated)
+ .reset_in2 (1'b0), // (terminated)
+ .reset_in3 (1'b0), // (terminated)
+ .reset_in4 (1'b0), // (terminated)
+ .reset_in5 (1'b0), // (terminated)
+ .reset_in6 (1'b0), // (terminated)
+ .reset_in7 (1'b0), // (terminated)
+ .reset_in8 (1'b0), // (terminated)
+ .reset_in9 (1'b0), // (terminated)
+ .reset_in10 (1'b0), // (terminated)
+ .reset_in11 (1'b0), // (terminated)
+ .reset_in12 (1'b0), // (terminated)
+ .reset_in13 (1'b0), // (terminated)
+ .reset_in14 (1'b0), // (terminated)
+ .reset_in15 (1'b0) // (terminated)
+ );
+
+ ip_stratixiv_mac_10g_cmd_xbar_demux cmd_xbar_demux (
+ .clk (csr_clk_clk), // clk.clk
+ .reset (rst_controller_reset_out_reset), // clk_reset.reset
+ .sink_ready (limiter_cmd_src_ready), // sink.ready
+ .sink_channel (limiter_cmd_src_channel), // .channel
+ .sink_data (limiter_cmd_src_data), // .data
+ .sink_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket
+ .sink_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket
+ .sink_valid (limiter_cmd_valid_data), // sink_valid.data
+ .src0_ready (cmd_xbar_demux_src0_ready), // src0.ready
+ .src0_valid (cmd_xbar_demux_src0_valid), // .valid
+ .src0_data (cmd_xbar_demux_src0_data), // .data
+ .src0_channel (cmd_xbar_demux_src0_channel), // .channel
+ .src0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
+ .src1_ready (cmd_xbar_demux_src1_ready), // src1.ready
+ .src1_valid (cmd_xbar_demux_src1_valid), // .valid
+ .src1_data (cmd_xbar_demux_src1_data), // .data
+ .src1_channel (cmd_xbar_demux_src1_channel), // .channel
+ .src1_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
+ .src1_endofpacket (cmd_xbar_demux_src1_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_rsp_xbar_demux rsp_xbar_demux (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .sink_ready (id_router_src_ready), // sink.ready
+ .sink_channel (id_router_src_channel), // .channel
+ .sink_data (id_router_src_data), // .data
+ .sink_startofpacket (id_router_src_startofpacket), // .startofpacket
+ .sink_endofpacket (id_router_src_endofpacket), // .endofpacket
+ .sink_valid (id_router_src_valid), // .valid
+ .src0_ready (rsp_xbar_demux_src0_ready), // src0.ready
+ .src0_valid (rsp_xbar_demux_src0_valid), // .valid
+ .src0_data (rsp_xbar_demux_src0_data), // .data
+ .src0_channel (rsp_xbar_demux_src0_channel), // .channel
+ .src0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (rsp_xbar_demux_src0_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_rsp_xbar_demux rsp_xbar_demux_001 (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .sink_ready (id_router_001_src_ready), // sink.ready
+ .sink_channel (id_router_001_src_channel), // .channel
+ .sink_data (id_router_001_src_data), // .data
+ .sink_startofpacket (id_router_001_src_startofpacket), // .startofpacket
+ .sink_endofpacket (id_router_001_src_endofpacket), // .endofpacket
+ .sink_valid (id_router_001_src_valid), // .valid
+ .src0_ready (rsp_xbar_demux_001_src0_ready), // src0.ready
+ .src0_valid (rsp_xbar_demux_001_src0_valid), // .valid
+ .src0_data (rsp_xbar_demux_001_src0_data), // .data
+ .src0_channel (rsp_xbar_demux_001_src0_channel), // .channel
+ .src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (rsp_xbar_demux_001_src0_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_rsp_xbar_mux rsp_xbar_mux (
+ .clk (csr_clk_clk), // clk.clk
+ .reset (rst_controller_reset_out_reset), // clk_reset.reset
+ .src_ready (rsp_xbar_mux_src_ready), // src.ready
+ .src_valid (rsp_xbar_mux_src_valid), // .valid
+ .src_data (rsp_xbar_mux_src_data), // .data
+ .src_channel (rsp_xbar_mux_src_channel), // .channel
+ .src_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
+ .src_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
+ .sink0_ready (crosser_002_out_ready), // sink0.ready
+ .sink0_valid (crosser_002_out_valid), // .valid
+ .sink0_channel (crosser_002_out_channel), // .channel
+ .sink0_data (crosser_002_out_data), // .data
+ .sink0_startofpacket (crosser_002_out_startofpacket), // .startofpacket
+ .sink0_endofpacket (crosser_002_out_endofpacket), // .endofpacket
+ .sink1_ready (crosser_003_out_ready), // sink1.ready
+ .sink1_valid (crosser_003_out_valid), // .valid
+ .sink1_channel (crosser_003_out_channel), // .channel
+ .sink1_data (crosser_003_out_data), // .data
+ .sink1_startofpacket (crosser_003_out_startofpacket), // .startofpacket
+ .sink1_endofpacket (crosser_003_out_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_cmd_xbar_demux_001 cmd_xbar_demux_001 (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .sink_ready (limiter_001_cmd_src_ready), // sink.ready
+ .sink_channel (limiter_001_cmd_src_channel), // .channel
+ .sink_data (limiter_001_cmd_src_data), // .data
+ .sink_startofpacket (limiter_001_cmd_src_startofpacket), // .startofpacket
+ .sink_endofpacket (limiter_001_cmd_src_endofpacket), // .endofpacket
+ .sink_valid (limiter_001_cmd_valid_data), // sink_valid.data
+ .src0_ready (cmd_xbar_demux_001_src0_ready), // src0.ready
+ .src0_valid (cmd_xbar_demux_001_src0_valid), // .valid
+ .src0_data (cmd_xbar_demux_001_src0_data), // .data
+ .src0_channel (cmd_xbar_demux_001_src0_channel), // .channel
+ .src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (cmd_xbar_demux_001_src0_endofpacket), // .endofpacket
+ .src1_ready (cmd_xbar_demux_001_src1_ready), // src1.ready
+ .src1_valid (cmd_xbar_demux_001_src1_valid), // .valid
+ .src1_data (cmd_xbar_demux_001_src1_data), // .data
+ .src1_channel (cmd_xbar_demux_001_src1_channel), // .channel
+ .src1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
+ .src1_endofpacket (cmd_xbar_demux_001_src1_endofpacket), // .endofpacket
+ .src2_ready (cmd_xbar_demux_001_src2_ready), // src2.ready
+ .src2_valid (cmd_xbar_demux_001_src2_valid), // .valid
+ .src2_data (cmd_xbar_demux_001_src2_data), // .data
+ .src2_channel (cmd_xbar_demux_001_src2_channel), // .channel
+ .src2_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket
+ .src2_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket
+ .src3_ready (cmd_xbar_demux_001_src3_ready), // src3.ready
+ .src3_valid (cmd_xbar_demux_001_src3_valid), // .valid
+ .src3_data (cmd_xbar_demux_001_src3_data), // .data
+ .src3_channel (cmd_xbar_demux_001_src3_channel), // .channel
+ .src3_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket
+ .src3_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket
+ .src4_ready (cmd_xbar_demux_001_src4_ready), // src4.ready
+ .src4_valid (cmd_xbar_demux_001_src4_valid), // .valid
+ .src4_data (cmd_xbar_demux_001_src4_data), // .data
+ .src4_channel (cmd_xbar_demux_001_src4_channel), // .channel
+ .src4_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket
+ .src4_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket
+ .src5_ready (cmd_xbar_demux_001_src5_ready), // src5.ready
+ .src5_valid (cmd_xbar_demux_001_src5_valid), // .valid
+ .src5_data (cmd_xbar_demux_001_src5_data), // .data
+ .src5_channel (cmd_xbar_demux_001_src5_channel), // .channel
+ .src5_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket
+ .src5_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket
+ .src6_ready (cmd_xbar_demux_001_src6_ready), // src6.ready
+ .src6_valid (cmd_xbar_demux_001_src6_valid), // .valid
+ .src6_data (cmd_xbar_demux_001_src6_data), // .data
+ .src6_channel (cmd_xbar_demux_001_src6_channel), // .channel
+ .src6_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket
+ .src6_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket
+ .src7_ready (cmd_xbar_demux_001_src7_ready), // src7.ready
+ .src7_valid (cmd_xbar_demux_001_src7_valid), // .valid
+ .src7_data (cmd_xbar_demux_001_src7_data), // .data
+ .src7_channel (cmd_xbar_demux_001_src7_channel), // .channel
+ .src7_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket
+ .src7_endofpacket (cmd_xbar_demux_001_src7_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_rsp_xbar_demux_002 rsp_xbar_demux_002 (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .sink_ready (id_router_002_src_ready), // sink.ready
+ .sink_channel (id_router_002_src_channel), // .channel
+ .sink_data (id_router_002_src_data), // .data
+ .sink_startofpacket (id_router_002_src_startofpacket), // .startofpacket
+ .sink_endofpacket (id_router_002_src_endofpacket), // .endofpacket
+ .sink_valid (id_router_002_src_valid), // .valid
+ .src0_ready (rsp_xbar_demux_002_src0_ready), // src0.ready
+ .src0_valid (rsp_xbar_demux_002_src0_valid), // .valid
+ .src0_data (rsp_xbar_demux_002_src0_data), // .data
+ .src0_channel (rsp_xbar_demux_002_src0_channel), // .channel
+ .src0_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (rsp_xbar_demux_002_src0_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_rsp_xbar_demux_002 rsp_xbar_demux_003 (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .sink_ready (id_router_003_src_ready), // sink.ready
+ .sink_channel (id_router_003_src_channel), // .channel
+ .sink_data (id_router_003_src_data), // .data
+ .sink_startofpacket (id_router_003_src_startofpacket), // .startofpacket
+ .sink_endofpacket (id_router_003_src_endofpacket), // .endofpacket
+ .sink_valid (id_router_003_src_valid), // .valid
+ .src0_ready (rsp_xbar_demux_003_src0_ready), // src0.ready
+ .src0_valid (rsp_xbar_demux_003_src0_valid), // .valid
+ .src0_data (rsp_xbar_demux_003_src0_data), // .data
+ .src0_channel (rsp_xbar_demux_003_src0_channel), // .channel
+ .src0_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (rsp_xbar_demux_003_src0_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_rsp_xbar_demux_002 rsp_xbar_demux_004 (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .sink_ready (id_router_004_src_ready), // sink.ready
+ .sink_channel (id_router_004_src_channel), // .channel
+ .sink_data (id_router_004_src_data), // .data
+ .sink_startofpacket (id_router_004_src_startofpacket), // .startofpacket
+ .sink_endofpacket (id_router_004_src_endofpacket), // .endofpacket
+ .sink_valid (id_router_004_src_valid), // .valid
+ .src0_ready (rsp_xbar_demux_004_src0_ready), // src0.ready
+ .src0_valid (rsp_xbar_demux_004_src0_valid), // .valid
+ .src0_data (rsp_xbar_demux_004_src0_data), // .data
+ .src0_channel (rsp_xbar_demux_004_src0_channel), // .channel
+ .src0_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (rsp_xbar_demux_004_src0_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_rsp_xbar_demux_002 rsp_xbar_demux_005 (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .sink_ready (id_router_005_src_ready), // sink.ready
+ .sink_channel (id_router_005_src_channel), // .channel
+ .sink_data (id_router_005_src_data), // .data
+ .sink_startofpacket (id_router_005_src_startofpacket), // .startofpacket
+ .sink_endofpacket (id_router_005_src_endofpacket), // .endofpacket
+ .sink_valid (id_router_005_src_valid), // .valid
+ .src0_ready (rsp_xbar_demux_005_src0_ready), // src0.ready
+ .src0_valid (rsp_xbar_demux_005_src0_valid), // .valid
+ .src0_data (rsp_xbar_demux_005_src0_data), // .data
+ .src0_channel (rsp_xbar_demux_005_src0_channel), // .channel
+ .src0_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (rsp_xbar_demux_005_src0_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_rsp_xbar_demux_002 rsp_xbar_demux_006 (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .sink_ready (id_router_006_src_ready), // sink.ready
+ .sink_channel (id_router_006_src_channel), // .channel
+ .sink_data (id_router_006_src_data), // .data
+ .sink_startofpacket (id_router_006_src_startofpacket), // .startofpacket
+ .sink_endofpacket (id_router_006_src_endofpacket), // .endofpacket
+ .sink_valid (id_router_006_src_valid), // .valid
+ .src0_ready (rsp_xbar_demux_006_src0_ready), // src0.ready
+ .src0_valid (rsp_xbar_demux_006_src0_valid), // .valid
+ .src0_data (rsp_xbar_demux_006_src0_data), // .data
+ .src0_channel (rsp_xbar_demux_006_src0_channel), // .channel
+ .src0_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (rsp_xbar_demux_006_src0_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_rsp_xbar_demux_002 rsp_xbar_demux_007 (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .sink_ready (id_router_007_src_ready), // sink.ready
+ .sink_channel (id_router_007_src_channel), // .channel
+ .sink_data (id_router_007_src_data), // .data
+ .sink_startofpacket (id_router_007_src_startofpacket), // .startofpacket
+ .sink_endofpacket (id_router_007_src_endofpacket), // .endofpacket
+ .sink_valid (id_router_007_src_valid), // .valid
+ .src0_ready (rsp_xbar_demux_007_src0_ready), // src0.ready
+ .src0_valid (rsp_xbar_demux_007_src0_valid), // .valid
+ .src0_data (rsp_xbar_demux_007_src0_data), // .data
+ .src0_channel (rsp_xbar_demux_007_src0_channel), // .channel
+ .src0_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (rsp_xbar_demux_007_src0_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_rsp_xbar_demux_002 rsp_xbar_demux_008 (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .sink_ready (id_router_008_src_ready), // sink.ready
+ .sink_channel (id_router_008_src_channel), // .channel
+ .sink_data (id_router_008_src_data), // .data
+ .sink_startofpacket (id_router_008_src_startofpacket), // .startofpacket
+ .sink_endofpacket (id_router_008_src_endofpacket), // .endofpacket
+ .sink_valid (id_router_008_src_valid), // .valid
+ .src0_ready (rsp_xbar_demux_008_src0_ready), // src0.ready
+ .src0_valid (rsp_xbar_demux_008_src0_valid), // .valid
+ .src0_data (rsp_xbar_demux_008_src0_data), // .data
+ .src0_channel (rsp_xbar_demux_008_src0_channel), // .channel
+ .src0_startofpacket (rsp_xbar_demux_008_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (rsp_xbar_demux_008_src0_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_rsp_xbar_demux_002 rsp_xbar_demux_009 (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .sink_ready (id_router_009_src_ready), // sink.ready
+ .sink_channel (id_router_009_src_channel), // .channel
+ .sink_data (id_router_009_src_data), // .data
+ .sink_startofpacket (id_router_009_src_startofpacket), // .startofpacket
+ .sink_endofpacket (id_router_009_src_endofpacket), // .endofpacket
+ .sink_valid (id_router_009_src_valid), // .valid
+ .src0_ready (rsp_xbar_demux_009_src0_ready), // src0.ready
+ .src0_valid (rsp_xbar_demux_009_src0_valid), // .valid
+ .src0_data (rsp_xbar_demux_009_src0_data), // .data
+ .src0_channel (rsp_xbar_demux_009_src0_channel), // .channel
+ .src0_startofpacket (rsp_xbar_demux_009_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (rsp_xbar_demux_009_src0_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_rsp_xbar_mux_001 rsp_xbar_mux_001 (
+ .clk (tx_clk_clk), // clk.clk
+ .reset (rst_controller_001_reset_out_reset), // clk_reset.reset
+ .src_ready (rsp_xbar_mux_001_src_ready), // src.ready
+ .src_valid (rsp_xbar_mux_001_src_valid), // .valid
+ .src_data (rsp_xbar_mux_001_src_data), // .data
+ .src_channel (rsp_xbar_mux_001_src_channel), // .channel
+ .src_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
+ .src_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
+ .sink0_ready (rsp_xbar_demux_002_src0_ready), // sink0.ready
+ .sink0_valid (rsp_xbar_demux_002_src0_valid), // .valid
+ .sink0_channel (rsp_xbar_demux_002_src0_channel), // .channel
+ .sink0_data (rsp_xbar_demux_002_src0_data), // .data
+ .sink0_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket
+ .sink0_endofpacket (rsp_xbar_demux_002_src0_endofpacket), // .endofpacket
+ .sink1_ready (rsp_xbar_demux_003_src0_ready), // sink1.ready
+ .sink1_valid (rsp_xbar_demux_003_src0_valid), // .valid
+ .sink1_channel (rsp_xbar_demux_003_src0_channel), // .channel
+ .sink1_data (rsp_xbar_demux_003_src0_data), // .data
+ .sink1_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket
+ .sink1_endofpacket (rsp_xbar_demux_003_src0_endofpacket), // .endofpacket
+ .sink2_ready (rsp_xbar_demux_004_src0_ready), // sink2.ready
+ .sink2_valid (rsp_xbar_demux_004_src0_valid), // .valid
+ .sink2_channel (rsp_xbar_demux_004_src0_channel), // .channel
+ .sink2_data (rsp_xbar_demux_004_src0_data), // .data
+ .sink2_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket
+ .sink2_endofpacket (rsp_xbar_demux_004_src0_endofpacket), // .endofpacket
+ .sink3_ready (rsp_xbar_demux_005_src0_ready), // sink3.ready
+ .sink3_valid (rsp_xbar_demux_005_src0_valid), // .valid
+ .sink3_channel (rsp_xbar_demux_005_src0_channel), // .channel
+ .sink3_data (rsp_xbar_demux_005_src0_data), // .data
+ .sink3_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket
+ .sink3_endofpacket (rsp_xbar_demux_005_src0_endofpacket), // .endofpacket
+ .sink4_ready (rsp_xbar_demux_006_src0_ready), // sink4.ready
+ .sink4_valid (rsp_xbar_demux_006_src0_valid), // .valid
+ .sink4_channel (rsp_xbar_demux_006_src0_channel), // .channel
+ .sink4_data (rsp_xbar_demux_006_src0_data), // .data
+ .sink4_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket
+ .sink4_endofpacket (rsp_xbar_demux_006_src0_endofpacket), // .endofpacket
+ .sink5_ready (rsp_xbar_demux_007_src0_ready), // sink5.ready
+ .sink5_valid (rsp_xbar_demux_007_src0_valid), // .valid
+ .sink5_channel (rsp_xbar_demux_007_src0_channel), // .channel
+ .sink5_data (rsp_xbar_demux_007_src0_data), // .data
+ .sink5_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket
+ .sink5_endofpacket (rsp_xbar_demux_007_src0_endofpacket), // .endofpacket
+ .sink6_ready (rsp_xbar_demux_008_src0_ready), // sink6.ready
+ .sink6_valid (rsp_xbar_demux_008_src0_valid), // .valid
+ .sink6_channel (rsp_xbar_demux_008_src0_channel), // .channel
+ .sink6_data (rsp_xbar_demux_008_src0_data), // .data
+ .sink6_startofpacket (rsp_xbar_demux_008_src0_startofpacket), // .startofpacket
+ .sink6_endofpacket (rsp_xbar_demux_008_src0_endofpacket), // .endofpacket
+ .sink7_ready (rsp_xbar_demux_009_src0_ready), // sink7.ready
+ .sink7_valid (rsp_xbar_demux_009_src0_valid), // .valid
+ .sink7_channel (rsp_xbar_demux_009_src0_channel), // .channel
+ .sink7_data (rsp_xbar_demux_009_src0_data), // .data
+ .sink7_startofpacket (rsp_xbar_demux_009_src0_startofpacket), // .startofpacket
+ .sink7_endofpacket (rsp_xbar_demux_009_src0_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_cmd_xbar_demux_002 cmd_xbar_demux_002 (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .sink_ready (limiter_002_cmd_src_ready), // sink.ready
+ .sink_channel (limiter_002_cmd_src_channel), // .channel
+ .sink_data (limiter_002_cmd_src_data), // .data
+ .sink_startofpacket (limiter_002_cmd_src_startofpacket), // .startofpacket
+ .sink_endofpacket (limiter_002_cmd_src_endofpacket), // .endofpacket
+ .sink_valid (limiter_002_cmd_valid_data), // sink_valid.data
+ .src0_ready (cmd_xbar_demux_002_src0_ready), // src0.ready
+ .src0_valid (cmd_xbar_demux_002_src0_valid), // .valid
+ .src0_data (cmd_xbar_demux_002_src0_data), // .data
+ .src0_channel (cmd_xbar_demux_002_src0_channel), // .channel
+ .src0_startofpacket (cmd_xbar_demux_002_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (cmd_xbar_demux_002_src0_endofpacket), // .endofpacket
+ .src1_ready (cmd_xbar_demux_002_src1_ready), // src1.ready
+ .src1_valid (cmd_xbar_demux_002_src1_valid), // .valid
+ .src1_data (cmd_xbar_demux_002_src1_data), // .data
+ .src1_channel (cmd_xbar_demux_002_src1_channel), // .channel
+ .src1_startofpacket (cmd_xbar_demux_002_src1_startofpacket), // .startofpacket
+ .src1_endofpacket (cmd_xbar_demux_002_src1_endofpacket), // .endofpacket
+ .src2_ready (cmd_xbar_demux_002_src2_ready), // src2.ready
+ .src2_valid (cmd_xbar_demux_002_src2_valid), // .valid
+ .src2_data (cmd_xbar_demux_002_src2_data), // .data
+ .src2_channel (cmd_xbar_demux_002_src2_channel), // .channel
+ .src2_startofpacket (cmd_xbar_demux_002_src2_startofpacket), // .startofpacket
+ .src2_endofpacket (cmd_xbar_demux_002_src2_endofpacket), // .endofpacket
+ .src3_ready (cmd_xbar_demux_002_src3_ready), // src3.ready
+ .src3_valid (cmd_xbar_demux_002_src3_valid), // .valid
+ .src3_data (cmd_xbar_demux_002_src3_data), // .data
+ .src3_channel (cmd_xbar_demux_002_src3_channel), // .channel
+ .src3_startofpacket (cmd_xbar_demux_002_src3_startofpacket), // .startofpacket
+ .src3_endofpacket (cmd_xbar_demux_002_src3_endofpacket), // .endofpacket
+ .src4_ready (cmd_xbar_demux_002_src4_ready), // src4.ready
+ .src4_valid (cmd_xbar_demux_002_src4_valid), // .valid
+ .src4_data (cmd_xbar_demux_002_src4_data), // .data
+ .src4_channel (cmd_xbar_demux_002_src4_channel), // .channel
+ .src4_startofpacket (cmd_xbar_demux_002_src4_startofpacket), // .startofpacket
+ .src4_endofpacket (cmd_xbar_demux_002_src4_endofpacket), // .endofpacket
+ .src5_ready (cmd_xbar_demux_002_src5_ready), // src5.ready
+ .src5_valid (cmd_xbar_demux_002_src5_valid), // .valid
+ .src5_data (cmd_xbar_demux_002_src5_data), // .data
+ .src5_channel (cmd_xbar_demux_002_src5_channel), // .channel
+ .src5_startofpacket (cmd_xbar_demux_002_src5_startofpacket), // .startofpacket
+ .src5_endofpacket (cmd_xbar_demux_002_src5_endofpacket), // .endofpacket
+ .src6_ready (cmd_xbar_demux_002_src6_ready), // src6.ready
+ .src6_valid (cmd_xbar_demux_002_src6_valid), // .valid
+ .src6_data (cmd_xbar_demux_002_src6_data), // .data
+ .src6_channel (cmd_xbar_demux_002_src6_channel), // .channel
+ .src6_startofpacket (cmd_xbar_demux_002_src6_startofpacket), // .startofpacket
+ .src6_endofpacket (cmd_xbar_demux_002_src6_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_rsp_xbar_demux_010 rsp_xbar_demux_010 (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .sink_ready (id_router_010_src_ready), // sink.ready
+ .sink_channel (id_router_010_src_channel), // .channel
+ .sink_data (id_router_010_src_data), // .data
+ .sink_startofpacket (id_router_010_src_startofpacket), // .startofpacket
+ .sink_endofpacket (id_router_010_src_endofpacket), // .endofpacket
+ .sink_valid (id_router_010_src_valid), // .valid
+ .src0_ready (rsp_xbar_demux_010_src0_ready), // src0.ready
+ .src0_valid (rsp_xbar_demux_010_src0_valid), // .valid
+ .src0_data (rsp_xbar_demux_010_src0_data), // .data
+ .src0_channel (rsp_xbar_demux_010_src0_channel), // .channel
+ .src0_startofpacket (rsp_xbar_demux_010_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (rsp_xbar_demux_010_src0_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_rsp_xbar_demux_010 rsp_xbar_demux_011 (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .sink_ready (id_router_011_src_ready), // sink.ready
+ .sink_channel (id_router_011_src_channel), // .channel
+ .sink_data (id_router_011_src_data), // .data
+ .sink_startofpacket (id_router_011_src_startofpacket), // .startofpacket
+ .sink_endofpacket (id_router_011_src_endofpacket), // .endofpacket
+ .sink_valid (id_router_011_src_valid), // .valid
+ .src0_ready (rsp_xbar_demux_011_src0_ready), // src0.ready
+ .src0_valid (rsp_xbar_demux_011_src0_valid), // .valid
+ .src0_data (rsp_xbar_demux_011_src0_data), // .data
+ .src0_channel (rsp_xbar_demux_011_src0_channel), // .channel
+ .src0_startofpacket (rsp_xbar_demux_011_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (rsp_xbar_demux_011_src0_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_rsp_xbar_demux_010 rsp_xbar_demux_012 (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .sink_ready (id_router_012_src_ready), // sink.ready
+ .sink_channel (id_router_012_src_channel), // .channel
+ .sink_data (id_router_012_src_data), // .data
+ .sink_startofpacket (id_router_012_src_startofpacket), // .startofpacket
+ .sink_endofpacket (id_router_012_src_endofpacket), // .endofpacket
+ .sink_valid (id_router_012_src_valid), // .valid
+ .src0_ready (rsp_xbar_demux_012_src0_ready), // src0.ready
+ .src0_valid (rsp_xbar_demux_012_src0_valid), // .valid
+ .src0_data (rsp_xbar_demux_012_src0_data), // .data
+ .src0_channel (rsp_xbar_demux_012_src0_channel), // .channel
+ .src0_startofpacket (rsp_xbar_demux_012_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (rsp_xbar_demux_012_src0_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_rsp_xbar_demux_010 rsp_xbar_demux_013 (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .sink_ready (id_router_013_src_ready), // sink.ready
+ .sink_channel (id_router_013_src_channel), // .channel
+ .sink_data (id_router_013_src_data), // .data
+ .sink_startofpacket (id_router_013_src_startofpacket), // .startofpacket
+ .sink_endofpacket (id_router_013_src_endofpacket), // .endofpacket
+ .sink_valid (id_router_013_src_valid), // .valid
+ .src0_ready (rsp_xbar_demux_013_src0_ready), // src0.ready
+ .src0_valid (rsp_xbar_demux_013_src0_valid), // .valid
+ .src0_data (rsp_xbar_demux_013_src0_data), // .data
+ .src0_channel (rsp_xbar_demux_013_src0_channel), // .channel
+ .src0_startofpacket (rsp_xbar_demux_013_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (rsp_xbar_demux_013_src0_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_rsp_xbar_demux_010 rsp_xbar_demux_014 (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .sink_ready (id_router_014_src_ready), // sink.ready
+ .sink_channel (id_router_014_src_channel), // .channel
+ .sink_data (id_router_014_src_data), // .data
+ .sink_startofpacket (id_router_014_src_startofpacket), // .startofpacket
+ .sink_endofpacket (id_router_014_src_endofpacket), // .endofpacket
+ .sink_valid (id_router_014_src_valid), // .valid
+ .src0_ready (rsp_xbar_demux_014_src0_ready), // src0.ready
+ .src0_valid (rsp_xbar_demux_014_src0_valid), // .valid
+ .src0_data (rsp_xbar_demux_014_src0_data), // .data
+ .src0_channel (rsp_xbar_demux_014_src0_channel), // .channel
+ .src0_startofpacket (rsp_xbar_demux_014_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (rsp_xbar_demux_014_src0_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_rsp_xbar_demux_010 rsp_xbar_demux_015 (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .sink_ready (id_router_015_src_ready), // sink.ready
+ .sink_channel (id_router_015_src_channel), // .channel
+ .sink_data (id_router_015_src_data), // .data
+ .sink_startofpacket (id_router_015_src_startofpacket), // .startofpacket
+ .sink_endofpacket (id_router_015_src_endofpacket), // .endofpacket
+ .sink_valid (id_router_015_src_valid), // .valid
+ .src0_ready (rsp_xbar_demux_015_src0_ready), // src0.ready
+ .src0_valid (rsp_xbar_demux_015_src0_valid), // .valid
+ .src0_data (rsp_xbar_demux_015_src0_data), // .data
+ .src0_channel (rsp_xbar_demux_015_src0_channel), // .channel
+ .src0_startofpacket (rsp_xbar_demux_015_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (rsp_xbar_demux_015_src0_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_rsp_xbar_demux_010 rsp_xbar_demux_016 (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .sink_ready (id_router_016_src_ready), // sink.ready
+ .sink_channel (id_router_016_src_channel), // .channel
+ .sink_data (id_router_016_src_data), // .data
+ .sink_startofpacket (id_router_016_src_startofpacket), // .startofpacket
+ .sink_endofpacket (id_router_016_src_endofpacket), // .endofpacket
+ .sink_valid (id_router_016_src_valid), // .valid
+ .src0_ready (rsp_xbar_demux_016_src0_ready), // src0.ready
+ .src0_valid (rsp_xbar_demux_016_src0_valid), // .valid
+ .src0_data (rsp_xbar_demux_016_src0_data), // .data
+ .src0_channel (rsp_xbar_demux_016_src0_channel), // .channel
+ .src0_startofpacket (rsp_xbar_demux_016_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (rsp_xbar_demux_016_src0_endofpacket) // .endofpacket
+ );
+
+ ip_stratixiv_mac_10g_rsp_xbar_mux_002 rsp_xbar_mux_002 (
+ .clk (rx_clk_clk), // clk.clk
+ .reset (rst_controller_002_reset_out_reset), // clk_reset.reset
+ .src_ready (rsp_xbar_mux_002_src_ready), // src.ready
+ .src_valid (rsp_xbar_mux_002_src_valid), // .valid
+ .src_data (rsp_xbar_mux_002_src_data), // .data
+ .src_channel (rsp_xbar_mux_002_src_channel), // .channel
+ .src_startofpacket (rsp_xbar_mux_002_src_startofpacket), // .startofpacket
+ .src_endofpacket (rsp_xbar_mux_002_src_endofpacket), // .endofpacket
+ .sink0_ready (rsp_xbar_demux_010_src0_ready), // sink0.ready
+ .sink0_valid (rsp_xbar_demux_010_src0_valid), // .valid
+ .sink0_channel (rsp_xbar_demux_010_src0_channel), // .channel
+ .sink0_data (rsp_xbar_demux_010_src0_data), // .data
+ .sink0_startofpacket (rsp_xbar_demux_010_src0_startofpacket), // .startofpacket
+ .sink0_endofpacket (rsp_xbar_demux_010_src0_endofpacket), // .endofpacket
+ .sink1_ready (rsp_xbar_demux_011_src0_ready), // sink1.ready
+ .sink1_valid (rsp_xbar_demux_011_src0_valid), // .valid
+ .sink1_channel (rsp_xbar_demux_011_src0_channel), // .channel
+ .sink1_data (rsp_xbar_demux_011_src0_data), // .data
+ .sink1_startofpacket (rsp_xbar_demux_011_src0_startofpacket), // .startofpacket
+ .sink1_endofpacket (rsp_xbar_demux_011_src0_endofpacket), // .endofpacket
+ .sink2_ready (rsp_xbar_demux_012_src0_ready), // sink2.ready
+ .sink2_valid (rsp_xbar_demux_012_src0_valid), // .valid
+ .sink2_channel (rsp_xbar_demux_012_src0_channel), // .channel
+ .sink2_data (rsp_xbar_demux_012_src0_data), // .data
+ .sink2_startofpacket (rsp_xbar_demux_012_src0_startofpacket), // .startofpacket
+ .sink2_endofpacket (rsp_xbar_demux_012_src0_endofpacket), // .endofpacket
+ .sink3_ready (rsp_xbar_demux_013_src0_ready), // sink3.ready
+ .sink3_valid (rsp_xbar_demux_013_src0_valid), // .valid
+ .sink3_channel (rsp_xbar_demux_013_src0_channel), // .channel
+ .sink3_data (rsp_xbar_demux_013_src0_data), // .data
+ .sink3_startofpacket (rsp_xbar_demux_013_src0_startofpacket), // .startofpacket
+ .sink3_endofpacket (rsp_xbar_demux_013_src0_endofpacket), // .endofpacket
+ .sink4_ready (rsp_xbar_demux_014_src0_ready), // sink4.ready
+ .sink4_valid (rsp_xbar_demux_014_src0_valid), // .valid
+ .sink4_channel (rsp_xbar_demux_014_src0_channel), // .channel
+ .sink4_data (rsp_xbar_demux_014_src0_data), // .data
+ .sink4_startofpacket (rsp_xbar_demux_014_src0_startofpacket), // .startofpacket
+ .sink4_endofpacket (rsp_xbar_demux_014_src0_endofpacket), // .endofpacket
+ .sink5_ready (rsp_xbar_demux_015_src0_ready), // sink5.ready
+ .sink5_valid (rsp_xbar_demux_015_src0_valid), // .valid
+ .sink5_channel (rsp_xbar_demux_015_src0_channel), // .channel
+ .sink5_data (rsp_xbar_demux_015_src0_data), // .data
+ .sink5_startofpacket (rsp_xbar_demux_015_src0_startofpacket), // .startofpacket
+ .sink5_endofpacket (rsp_xbar_demux_015_src0_endofpacket), // .endofpacket
+ .sink6_ready (rsp_xbar_demux_016_src0_ready), // sink6.ready
+ .sink6_valid (rsp_xbar_demux_016_src0_valid), // .valid
+ .sink6_channel (rsp_xbar_demux_016_src0_channel), // .channel
+ .sink6_data (rsp_xbar_demux_016_src0_data), // .data
+ .sink6_startofpacket (rsp_xbar_demux_016_src0_startofpacket), // .startofpacket
+ .sink6_endofpacket (rsp_xbar_demux_016_src0_endofpacket) // .endofpacket
+ );
+
+ altera_avalon_st_handshake_clock_crosser #(
+ .DATA_WIDTH (66),
+ .BITS_PER_SYMBOL (66),
+ .USE_PACKETS (1),
+ .USE_CHANNEL (1),
+ .CHANNEL_WIDTH (2),
+ .USE_ERROR (0),
+ .ERROR_WIDTH (1),
+ .VALID_SYNC_DEPTH (2),
+ .READY_SYNC_DEPTH (2),
+ .USE_OUTPUT_PIPELINE (0)
+ ) crosser (
+ .in_clk (csr_clk_clk), // in_clk.clk
+ .in_reset (rst_controller_reset_out_reset), // in_clk_reset.reset
+ .out_clk (tx_clk_clk), // out_clk.clk
+ .out_reset (rst_controller_001_reset_out_reset), // out_clk_reset.reset
+ .in_ready (cmd_xbar_demux_src0_ready), // in.ready
+ .in_valid (cmd_xbar_demux_src0_valid), // .valid
+ .in_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
+ .in_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
+ .in_channel (cmd_xbar_demux_src0_channel), // .channel
+ .in_data (cmd_xbar_demux_src0_data), // .data
+ .out_ready (crosser_out_ready), // out.ready
+ .out_valid (crosser_out_valid), // .valid
+ .out_startofpacket (crosser_out_startofpacket), // .startofpacket
+ .out_endofpacket (crosser_out_endofpacket), // .endofpacket
+ .out_channel (crosser_out_channel), // .channel
+ .out_data (crosser_out_data), // .data
+ .in_empty (1'b0), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .out_error () // (terminated)
+ );
+
+ altera_avalon_st_handshake_clock_crosser #(
+ .DATA_WIDTH (66),
+ .BITS_PER_SYMBOL (66),
+ .USE_PACKETS (1),
+ .USE_CHANNEL (1),
+ .CHANNEL_WIDTH (2),
+ .USE_ERROR (0),
+ .ERROR_WIDTH (1),
+ .VALID_SYNC_DEPTH (2),
+ .READY_SYNC_DEPTH (2),
+ .USE_OUTPUT_PIPELINE (0)
+ ) crosser_001 (
+ .in_clk (csr_clk_clk), // in_clk.clk
+ .in_reset (rst_controller_reset_out_reset), // in_clk_reset.reset
+ .out_clk (rx_clk_clk), // out_clk.clk
+ .out_reset (rst_controller_002_reset_out_reset), // out_clk_reset.reset
+ .in_ready (cmd_xbar_demux_src1_ready), // in.ready
+ .in_valid (cmd_xbar_demux_src1_valid), // .valid
+ .in_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
+ .in_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket
+ .in_channel (cmd_xbar_demux_src1_channel), // .channel
+ .in_data (cmd_xbar_demux_src1_data), // .data
+ .out_ready (crosser_001_out_ready), // out.ready
+ .out_valid (crosser_001_out_valid), // .valid
+ .out_startofpacket (crosser_001_out_startofpacket), // .startofpacket
+ .out_endofpacket (crosser_001_out_endofpacket), // .endofpacket
+ .out_channel (crosser_001_out_channel), // .channel
+ .out_data (crosser_001_out_data), // .data
+ .in_empty (1'b0), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .out_error () // (terminated)
+ );
+
+ altera_avalon_st_handshake_clock_crosser #(
+ .DATA_WIDTH (66),
+ .BITS_PER_SYMBOL (66),
+ .USE_PACKETS (1),
+ .USE_CHANNEL (1),
+ .CHANNEL_WIDTH (2),
+ .USE_ERROR (0),
+ .ERROR_WIDTH (1),
+ .VALID_SYNC_DEPTH (2),
+ .READY_SYNC_DEPTH (2),
+ .USE_OUTPUT_PIPELINE (0)
+ ) crosser_002 (
+ .in_clk (tx_clk_clk), // in_clk.clk
+ .in_reset (rst_controller_001_reset_out_reset), // in_clk_reset.reset
+ .out_clk (csr_clk_clk), // out_clk.clk
+ .out_reset (rst_controller_reset_out_reset), // out_clk_reset.reset
+ .in_ready (rsp_xbar_demux_src0_ready), // in.ready
+ .in_valid (rsp_xbar_demux_src0_valid), // .valid
+ .in_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
+ .in_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
+ .in_channel (rsp_xbar_demux_src0_channel), // .channel
+ .in_data (rsp_xbar_demux_src0_data), // .data
+ .out_ready (crosser_002_out_ready), // out.ready
+ .out_valid (crosser_002_out_valid), // .valid
+ .out_startofpacket (crosser_002_out_startofpacket), // .startofpacket
+ .out_endofpacket (crosser_002_out_endofpacket), // .endofpacket
+ .out_channel (crosser_002_out_channel), // .channel
+ .out_data (crosser_002_out_data), // .data
+ .in_empty (1'b0), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .out_error () // (terminated)
+ );
+
+ altera_avalon_st_handshake_clock_crosser #(
+ .DATA_WIDTH (66),
+ .BITS_PER_SYMBOL (66),
+ .USE_PACKETS (1),
+ .USE_CHANNEL (1),
+ .CHANNEL_WIDTH (2),
+ .USE_ERROR (0),
+ .ERROR_WIDTH (1),
+ .VALID_SYNC_DEPTH (2),
+ .READY_SYNC_DEPTH (2),
+ .USE_OUTPUT_PIPELINE (0)
+ ) crosser_003 (
+ .in_clk (rx_clk_clk), // in_clk.clk
+ .in_reset (rst_controller_002_reset_out_reset), // in_clk_reset.reset
+ .out_clk (csr_clk_clk), // out_clk.clk
+ .out_reset (rst_controller_reset_out_reset), // out_clk_reset.reset
+ .in_ready (rsp_xbar_demux_001_src0_ready), // in.ready
+ .in_valid (rsp_xbar_demux_001_src0_valid), // .valid
+ .in_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
+ .in_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket
+ .in_channel (rsp_xbar_demux_001_src0_channel), // .channel
+ .in_data (rsp_xbar_demux_001_src0_data), // .data
+ .out_ready (crosser_003_out_ready), // out.ready
+ .out_valid (crosser_003_out_valid), // .valid
+ .out_startofpacket (crosser_003_out_startofpacket), // .startofpacket
+ .out_endofpacket (crosser_003_out_endofpacket), // .endofpacket
+ .out_channel (crosser_003_out_channel), // .channel
+ .out_data (crosser_003_out_data), // .data
+ .in_empty (1'b0), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .out_error () // (terminated)
+ );
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_addr_router.sv b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_addr_router.sv
new file mode 100644
index 0000000000000000000000000000000000000000..26f387f5f8eb9fe43d571edea3df9fdb9c42bd03
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_addr_router.sv
@@ -0,0 +1,185 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/rel/11.1sp2/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2011/11/10 $
+// $Author: max $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module ip_stratixiv_mac_10g_addr_router_default_decode
+ #(
+ parameter DEFAULT_CHANNEL = 1,
+ DEFAULT_DESTID = 1
+ )
+ (output [64 - 64 : 0] default_destination_id,
+ output [2-1 : 0] default_src_channel
+ );
+
+ assign default_destination_id =
+ DEFAULT_DESTID[64 - 64 : 0];
+ generate begin : default_decode
+ if (DEFAULT_CHANNEL == -1)
+ assign default_src_channel = '0;
+ else
+ assign default_src_channel = 2'b1 << DEFAULT_CHANNEL;
+ end endgenerate
+
+endmodule
+
+
+module ip_stratixiv_mac_10g_addr_router
+(
+ // -------------------
+ // Clock & Reset
+ // -------------------
+ input clk,
+ input reset,
+
+ // -------------------
+ // Command Sink (Input)
+ // -------------------
+ input sink_valid,
+ input [66-1 : 0] sink_data,
+ input sink_startofpacket,
+ input sink_endofpacket,
+ output sink_ready,
+
+ // -------------------
+ // Command Source (Output)
+ // -------------------
+ output src_valid,
+ output reg [66-1 : 0] src_data,
+ output reg [2-1 : 0] src_channel,
+ output src_startofpacket,
+ output src_endofpacket,
+ input src_ready
+);
+
+ // -------------------------------------------------------
+ // Local parameters and variables
+ // -------------------------------------------------------
+ localparam PKT_ADDR_H = 50;
+ localparam PKT_ADDR_L = 36;
+ localparam PKT_DEST_ID_H = 64;
+ localparam PKT_DEST_ID_L = 64;
+ localparam ST_DATA_W = 66;
+ localparam ST_CHANNEL_W = 2;
+ localparam DECODER_TYPE = 0;
+
+ localparam PKT_TRANS_WRITE = 53;
+ localparam PKT_TRANS_READ = 54;
+
+ localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+ localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+
+ // -------------------------------------------------------
+ // Figure out the number of bits to mask off for each slave span
+ // during address decoding
+ // -------------------------------------------------------
+ localparam PAD0 = log2ceil(32'h4000 - 32'h0);
+ localparam PAD1 = log2ceil(32'h8000 - 32'h4000);
+
+ // -------------------------------------------------------
+ // Work out which address bits are significant based on the
+ // address range of the slaves. If the required width is too
+ // large or too small, we use the address field width instead.
+ // -------------------------------------------------------
+ localparam ADDR_RANGE = 32'h8000;
+ localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+ localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+ (RANGE_ADDR_WIDTH == 0) ?
+ PKT_ADDR_H :
+ PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+ localparam RG = RANGE_ADDR_WIDTH-1;
+
+ wire [PKT_ADDR_W-1 : 0] address = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
+
+ // -------------------------------------------------------
+ // Pass almost everything through, untouched
+ // -------------------------------------------------------
+ assign sink_ready = src_ready;
+ assign src_valid = sink_valid;
+ assign src_startofpacket = sink_startofpacket;
+ assign src_endofpacket = sink_endofpacket;
+
+ wire [PKT_DEST_ID_W-1:0] default_destid;
+ wire [2-1 : 0] default_src_channel;
+
+
+
+
+ ip_stratixiv_mac_10g_addr_router_default_decode the_default_decode(
+ .default_destination_id (default_destid),
+ .default_src_channel (default_src_channel)
+ );
+
+ always @* begin
+ src_data = sink_data;
+ src_channel = default_src_channel;
+
+ src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
+ // --------------------------------------------------
+ // Address Decoder
+ // Sets the channel and destination ID based on the address
+ // --------------------------------------------------
+
+ // ( 0x0 .. 0x4000 )
+ if ( {address[RG:PAD0],{PAD0{1'b0}}} == 'h0 ) begin
+ src_channel = 2'b10;
+ src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
+ end
+
+ // ( 0x4000 .. 0x8000 )
+ if ( {address[RG:PAD1],{PAD1{1'b0}}} == 'h4000 ) begin
+ src_channel = 2'b01;
+ src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
+ end
+ end
+
+ // --------------------------------------------------
+ // Ceil(log2()) function
+ // --------------------------------------------------
+ function integer log2ceil;
+ input reg[63:0] val;
+ reg [63:0] i;
+
+ begin
+ i = 1;
+ log2ceil = 0;
+
+ while (i < val) begin
+ log2ceil = log2ceil + 1;
+ i = i << 1;
+ end
+ end
+ endfunction
+
+endmodule
+
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_addr_router_001.sv b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_addr_router_001.sv
new file mode 100644
index 0000000000000000000000000000000000000000..d81c07ba91f24b6187bcec20ef2b6bf1ddcf7bb2
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_addr_router_001.sv
@@ -0,0 +1,227 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/rel/11.1sp2/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2011/11/10 $
+// $Author: max $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module ip_stratixiv_mac_10g_addr_router_001_default_decode
+ #(
+ parameter DEFAULT_CHANNEL = 7,
+ DEFAULT_DESTID = 7
+ )
+ (output [67 - 65 : 0] default_destination_id,
+ output [8-1 : 0] default_src_channel
+ );
+
+ assign default_destination_id =
+ DEFAULT_DESTID[67 - 65 : 0];
+ generate begin : default_decode
+ if (DEFAULT_CHANNEL == -1)
+ assign default_src_channel = '0;
+ else
+ assign default_src_channel = 8'b1 << DEFAULT_CHANNEL;
+ end endgenerate
+
+endmodule
+
+
+module ip_stratixiv_mac_10g_addr_router_001
+(
+ // -------------------
+ // Clock & Reset
+ // -------------------
+ input clk,
+ input reset,
+
+ // -------------------
+ // Command Sink (Input)
+ // -------------------
+ input sink_valid,
+ input [69-1 : 0] sink_data,
+ input sink_startofpacket,
+ input sink_endofpacket,
+ output sink_ready,
+
+ // -------------------
+ // Command Source (Output)
+ // -------------------
+ output src_valid,
+ output reg [69-1 : 0] src_data,
+ output reg [8-1 : 0] src_channel,
+ output src_startofpacket,
+ output src_endofpacket,
+ input src_ready
+);
+
+ // -------------------------------------------------------
+ // Local parameters and variables
+ // -------------------------------------------------------
+ localparam PKT_ADDR_H = 49;
+ localparam PKT_ADDR_L = 36;
+ localparam PKT_DEST_ID_H = 67;
+ localparam PKT_DEST_ID_L = 65;
+ localparam ST_DATA_W = 69;
+ localparam ST_CHANNEL_W = 8;
+ localparam DECODER_TYPE = 0;
+
+ localparam PKT_TRANS_WRITE = 52;
+ localparam PKT_TRANS_READ = 53;
+
+ localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+ localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+
+ // -------------------------------------------------------
+ // Figure out the number of bits to mask off for each slave span
+ // during address decoding
+ // -------------------------------------------------------
+ localparam PAD0 = log2ceil(32'h8 - 32'h0);
+ localparam PAD1 = log2ceil(32'h108 - 32'h100);
+ localparam PAD2 = log2ceil(32'h208 - 32'h200);
+ localparam PAD3 = log2ceil(32'h308 - 32'h300);
+ localparam PAD4 = log2ceil(32'h510 - 32'h500);
+ localparam PAD5 = log2ceil(32'h810 - 32'h800);
+ localparam PAD6 = log2ceil(32'h2080 - 32'h2000);
+ localparam PAD7 = log2ceil(32'h3100 - 32'h3000);
+
+ // -------------------------------------------------------
+ // Work out which address bits are significant based on the
+ // address range of the slaves. If the required width is too
+ // large or too small, we use the address field width instead.
+ // -------------------------------------------------------
+ localparam ADDR_RANGE = 32'h3100;
+ localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+ localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+ (RANGE_ADDR_WIDTH == 0) ?
+ PKT_ADDR_H :
+ PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+ localparam RG = RANGE_ADDR_WIDTH-1;
+
+ wire [PKT_ADDR_W-1 : 0] address = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
+
+ // -------------------------------------------------------
+ // Pass almost everything through, untouched
+ // -------------------------------------------------------
+ assign sink_ready = src_ready;
+ assign src_valid = sink_valid;
+ assign src_startofpacket = sink_startofpacket;
+ assign src_endofpacket = sink_endofpacket;
+
+ wire [PKT_DEST_ID_W-1:0] default_destid;
+ wire [8-1 : 0] default_src_channel;
+
+
+
+
+ ip_stratixiv_mac_10g_addr_router_001_default_decode the_default_decode(
+ .default_destination_id (default_destid),
+ .default_src_channel (default_src_channel)
+ );
+
+ always @* begin
+ src_data = sink_data;
+ src_channel = default_src_channel;
+
+ src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
+ // --------------------------------------------------
+ // Address Decoder
+ // Sets the channel and destination ID based on the address
+ // --------------------------------------------------
+
+ // ( 0x0 .. 0x8 )
+ if ( {address[RG:PAD0],{PAD0{1'b0}}} == 'h0 ) begin
+ src_channel = 8'b00000001;
+ src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
+ end
+
+ // ( 0x100 .. 0x108 )
+ if ( {address[RG:PAD1],{PAD1{1'b0}}} == 'h100 ) begin
+ src_channel = 8'b00000010;
+ src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
+ end
+
+ // ( 0x200 .. 0x208 )
+ if ( {address[RG:PAD2],{PAD2{1'b0}}} == 'h200 ) begin
+ src_channel = 8'b00000100;
+ src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
+ end
+
+ // ( 0x300 .. 0x308 )
+ if ( {address[RG:PAD3],{PAD3{1'b0}}} == 'h300 ) begin
+ src_channel = 8'b00100000;
+ src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
+ end
+
+ // ( 0x500 .. 0x510 )
+ if ( {address[RG:PAD4],{PAD4{1'b0}}} == 'h500 ) begin
+ src_channel = 8'b00001000;
+ src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
+ end
+
+ // ( 0x800 .. 0x810 )
+ if ( {address[RG:PAD5],{PAD5{1'b0}}} == 'h800 ) begin
+ src_channel = 8'b00010000;
+ src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
+ end
+
+ // ( 0x2000 .. 0x2080 )
+ if ( {address[RG:PAD6],{PAD6{1'b0}}} == 'h2000 ) begin
+ src_channel = 8'b01000000;
+ src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6;
+ end
+
+ // ( 0x3000 .. 0x3100 )
+ if ( {address[RG:PAD7],{PAD7{1'b0}}} == 'h3000 ) begin
+ src_channel = 8'b10000000;
+ src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 7;
+ end
+ end
+
+ // --------------------------------------------------
+ // Ceil(log2()) function
+ // --------------------------------------------------
+ function integer log2ceil;
+ input reg[63:0] val;
+ reg [63:0] i;
+
+ begin
+ i = 1;
+ log2ceil = 0;
+
+ while (i < val) begin
+ log2ceil = log2ceil + 1;
+ i = i << 1;
+ end
+ end
+ endfunction
+
+endmodule
+
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_addr_router_002.sv b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_addr_router_002.sv
new file mode 100644
index 0000000000000000000000000000000000000000..ffc5d0eb76f5e121e1781cdc9335bcfeb6601412
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_addr_router_002.sv
@@ -0,0 +1,220 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/rel/11.1sp2/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2011/11/10 $
+// $Author: max $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module ip_stratixiv_mac_10g_addr_router_002_default_decode
+ #(
+ parameter DEFAULT_CHANNEL = 5,
+ DEFAULT_DESTID = 5
+ )
+ (output [67 - 65 : 0] default_destination_id,
+ output [7-1 : 0] default_src_channel
+ );
+
+ assign default_destination_id =
+ DEFAULT_DESTID[67 - 65 : 0];
+ generate begin : default_decode
+ if (DEFAULT_CHANNEL == -1)
+ assign default_src_channel = '0;
+ else
+ assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
+ end endgenerate
+
+endmodule
+
+
+module ip_stratixiv_mac_10g_addr_router_002
+(
+ // -------------------
+ // Clock & Reset
+ // -------------------
+ input clk,
+ input reset,
+
+ // -------------------
+ // Command Sink (Input)
+ // -------------------
+ input sink_valid,
+ input [69-1 : 0] sink_data,
+ input sink_startofpacket,
+ input sink_endofpacket,
+ output sink_ready,
+
+ // -------------------
+ // Command Source (Output)
+ // -------------------
+ output src_valid,
+ output reg [69-1 : 0] src_data,
+ output reg [7-1 : 0] src_channel,
+ output src_startofpacket,
+ output src_endofpacket,
+ input src_ready
+);
+
+ // -------------------------------------------------------
+ // Local parameters and variables
+ // -------------------------------------------------------
+ localparam PKT_ADDR_H = 49;
+ localparam PKT_ADDR_L = 36;
+ localparam PKT_DEST_ID_H = 67;
+ localparam PKT_DEST_ID_L = 65;
+ localparam ST_DATA_W = 69;
+ localparam ST_CHANNEL_W = 7;
+ localparam DECODER_TYPE = 0;
+
+ localparam PKT_TRANS_WRITE = 52;
+ localparam PKT_TRANS_READ = 53;
+
+ localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+ localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+
+ // -------------------------------------------------------
+ // Figure out the number of bits to mask off for each slave span
+ // during address decoding
+ // -------------------------------------------------------
+ localparam PAD0 = log2ceil(32'h8 - 32'h0);
+ localparam PAD1 = log2ceil(32'h110 - 32'h100);
+ localparam PAD2 = log2ceil(32'h208 - 32'h200);
+ localparam PAD3 = log2ceil(32'h310 - 32'h300);
+ localparam PAD4 = log2ceil(32'h508 - 32'h500);
+ localparam PAD5 = log2ceil(32'h2080 - 32'h2000);
+ localparam PAD6 = log2ceil(32'h3100 - 32'h3000);
+
+ // -------------------------------------------------------
+ // Work out which address bits are significant based on the
+ // address range of the slaves. If the required width is too
+ // large or too small, we use the address field width instead.
+ // -------------------------------------------------------
+ localparam ADDR_RANGE = 32'h3100;
+ localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+ localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+ (RANGE_ADDR_WIDTH == 0) ?
+ PKT_ADDR_H :
+ PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+ localparam RG = RANGE_ADDR_WIDTH-1;
+
+ wire [PKT_ADDR_W-1 : 0] address = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
+
+ // -------------------------------------------------------
+ // Pass almost everything through, untouched
+ // -------------------------------------------------------
+ assign sink_ready = src_ready;
+ assign src_valid = sink_valid;
+ assign src_startofpacket = sink_startofpacket;
+ assign src_endofpacket = sink_endofpacket;
+
+ wire [PKT_DEST_ID_W-1:0] default_destid;
+ wire [7-1 : 0] default_src_channel;
+
+
+
+
+ ip_stratixiv_mac_10g_addr_router_002_default_decode the_default_decode(
+ .default_destination_id (default_destid),
+ .default_src_channel (default_src_channel)
+ );
+
+ always @* begin
+ src_data = sink_data;
+ src_channel = default_src_channel;
+
+ src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
+ // --------------------------------------------------
+ // Address Decoder
+ // Sets the channel and destination ID based on the address
+ // --------------------------------------------------
+
+ // ( 0x0 .. 0x8 )
+ if ( {address[RG:PAD0],{PAD0{1'b0}}} == 'h0 ) begin
+ src_channel = 7'b0000001;
+ src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
+ end
+
+ // ( 0x100 .. 0x110 )
+ if ( {address[RG:PAD1],{PAD1{1'b0}}} == 'h100 ) begin
+ src_channel = 7'b0000010;
+ src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
+ end
+
+ // ( 0x200 .. 0x208 )
+ if ( {address[RG:PAD2],{PAD2{1'b0}}} == 'h200 ) begin
+ src_channel = 7'b0000100;
+ src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
+ end
+
+ // ( 0x300 .. 0x310 )
+ if ( {address[RG:PAD3],{PAD3{1'b0}}} == 'h300 ) begin
+ src_channel = 7'b0010000;
+ src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
+ end
+
+ // ( 0x500 .. 0x508 )
+ if ( {address[RG:PAD4],{PAD4{1'b0}}} == 'h500 ) begin
+ src_channel = 7'b1000000;
+ src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6;
+ end
+
+ // ( 0x2000 .. 0x2080 )
+ if ( {address[RG:PAD5],{PAD5{1'b0}}} == 'h2000 ) begin
+ src_channel = 7'b0001000;
+ src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
+ end
+
+ // ( 0x3000 .. 0x3100 )
+ if ( {address[RG:PAD6],{PAD6{1'b0}}} == 'h3000 ) begin
+ src_channel = 7'b0100000;
+ src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
+ end
+ end
+
+ // --------------------------------------------------
+ // Ceil(log2()) function
+ // --------------------------------------------------
+ function integer log2ceil;
+ input reg[63:0] val;
+ reg [63:0] i;
+
+ begin
+ i = 1;
+ log2ceil = 0;
+
+ while (i < val) begin
+ log2ceil = log2ceil + 1;
+ i = i << 1;
+ end
+ end
+ endfunction
+
+endmodule
+
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_cmd_xbar_demux.sv b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_cmd_xbar_demux.sv
new file mode 100644
index 0000000000000000000000000000000000000000..cee516f85d15d5e813ae9bf2beef7d3088ed4a27
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_cmd_xbar_demux.sv
@@ -0,0 +1,115 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/rel/11.1sp2/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2011/11/10 $
+// $Author: max $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+// output_name: ip_stratixiv_mac_10g_cmd_xbar_demux
+// ST_DATA_W: 66
+// ST_CHANNEL_W: 2
+// NUM_OUTPUTS: 2
+// VALID_WIDTH: 2
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module ip_stratixiv_mac_10g_cmd_xbar_demux
+(
+ // -------------------
+ // Sink
+ // -------------------
+ input [2-1 : 0] sink_valid,
+ input [66-1 : 0] sink_data, // ST_DATA_W=66
+ input [2-1 : 0] sink_channel, // ST_CHANNEL_W=2
+ input sink_startofpacket,
+ input sink_endofpacket,
+ output sink_ready,
+
+ // -------------------
+ // Sources
+ // -------------------
+ output reg src0_valid,
+ output reg [66-1 : 0] src0_data, // ST_DATA_W=66
+ output reg [2-1 : 0] src0_channel, // ST_CHANNEL_W=2
+ output reg src0_startofpacket,
+ output reg src0_endofpacket,
+ input src0_ready,
+
+ output reg src1_valid,
+ output reg [66-1 : 0] src1_data, // ST_DATA_W=66
+ output reg [2-1 : 0] src1_channel, // ST_CHANNEL_W=2
+ output reg src1_startofpacket,
+ output reg src1_endofpacket,
+ input src1_ready,
+
+
+ // -------------------
+ // Clock & Reset
+ // -------------------
+ (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+ input clk,
+ (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+ input reset
+
+);
+
+ localparam NUM_OUTPUTS = 2;
+ wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+ // -------------------
+ // Demux
+ // -------------------
+ always @* begin
+ src0_data = sink_data;
+ src0_startofpacket = sink_startofpacket;
+ src0_endofpacket = sink_endofpacket;
+ src0_channel = sink_channel >> NUM_OUTPUTS;
+
+ src0_valid = sink_channel[0] && sink_valid[0];
+
+ src1_data = sink_data;
+ src1_startofpacket = sink_startofpacket;
+ src1_endofpacket = sink_endofpacket;
+ src1_channel = sink_channel >> NUM_OUTPUTS;
+
+ src1_valid = sink_channel[1] && sink_valid[1];
+
+ end
+
+ // -------------------
+ // Backpressure
+ // -------------------
+ assign ready_vector[0] = src0_ready;
+ assign ready_vector[1] = src1_ready;
+ assign sink_ready = |(sink_channel & ready_vector);
+
+endmodule
+
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_cmd_xbar_demux_001.sv b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_cmd_xbar_demux_001.sv
new file mode 100644
index 0000000000000000000000000000000000000000..215e875583926eadd2f39c8bbac572404db23509
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_cmd_xbar_demux_001.sv
@@ -0,0 +1,205 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/rel/11.1sp2/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2011/11/10 $
+// $Author: max $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+// output_name: ip_stratixiv_mac_10g_cmd_xbar_demux_001
+// ST_DATA_W: 69
+// ST_CHANNEL_W: 8
+// NUM_OUTPUTS: 8
+// VALID_WIDTH: 8
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module ip_stratixiv_mac_10g_cmd_xbar_demux_001
+(
+ // -------------------
+ // Sink
+ // -------------------
+ input [8-1 : 0] sink_valid,
+ input [69-1 : 0] sink_data, // ST_DATA_W=69
+ input [8-1 : 0] sink_channel, // ST_CHANNEL_W=8
+ input sink_startofpacket,
+ input sink_endofpacket,
+ output sink_ready,
+
+ // -------------------
+ // Sources
+ // -------------------
+ output reg src0_valid,
+ output reg [69-1 : 0] src0_data, // ST_DATA_W=69
+ output reg [8-1 : 0] src0_channel, // ST_CHANNEL_W=8
+ output reg src0_startofpacket,
+ output reg src0_endofpacket,
+ input src0_ready,
+
+ output reg src1_valid,
+ output reg [69-1 : 0] src1_data, // ST_DATA_W=69
+ output reg [8-1 : 0] src1_channel, // ST_CHANNEL_W=8
+ output reg src1_startofpacket,
+ output reg src1_endofpacket,
+ input src1_ready,
+
+ output reg src2_valid,
+ output reg [69-1 : 0] src2_data, // ST_DATA_W=69
+ output reg [8-1 : 0] src2_channel, // ST_CHANNEL_W=8
+ output reg src2_startofpacket,
+ output reg src2_endofpacket,
+ input src2_ready,
+
+ output reg src3_valid,
+ output reg [69-1 : 0] src3_data, // ST_DATA_W=69
+ output reg [8-1 : 0] src3_channel, // ST_CHANNEL_W=8
+ output reg src3_startofpacket,
+ output reg src3_endofpacket,
+ input src3_ready,
+
+ output reg src4_valid,
+ output reg [69-1 : 0] src4_data, // ST_DATA_W=69
+ output reg [8-1 : 0] src4_channel, // ST_CHANNEL_W=8
+ output reg src4_startofpacket,
+ output reg src4_endofpacket,
+ input src4_ready,
+
+ output reg src5_valid,
+ output reg [69-1 : 0] src5_data, // ST_DATA_W=69
+ output reg [8-1 : 0] src5_channel, // ST_CHANNEL_W=8
+ output reg src5_startofpacket,
+ output reg src5_endofpacket,
+ input src5_ready,
+
+ output reg src6_valid,
+ output reg [69-1 : 0] src6_data, // ST_DATA_W=69
+ output reg [8-1 : 0] src6_channel, // ST_CHANNEL_W=8
+ output reg src6_startofpacket,
+ output reg src6_endofpacket,
+ input src6_ready,
+
+ output reg src7_valid,
+ output reg [69-1 : 0] src7_data, // ST_DATA_W=69
+ output reg [8-1 : 0] src7_channel, // ST_CHANNEL_W=8
+ output reg src7_startofpacket,
+ output reg src7_endofpacket,
+ input src7_ready,
+
+
+ // -------------------
+ // Clock & Reset
+ // -------------------
+ (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+ input clk,
+ (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+ input reset
+
+);
+
+ localparam NUM_OUTPUTS = 8;
+ wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+ // -------------------
+ // Demux
+ // -------------------
+ always @* begin
+ src0_data = sink_data;
+ src0_startofpacket = sink_startofpacket;
+ src0_endofpacket = sink_endofpacket;
+ src0_channel = sink_channel >> NUM_OUTPUTS;
+
+ src0_valid = sink_channel[0] && sink_valid[0];
+
+ src1_data = sink_data;
+ src1_startofpacket = sink_startofpacket;
+ src1_endofpacket = sink_endofpacket;
+ src1_channel = sink_channel >> NUM_OUTPUTS;
+
+ src1_valid = sink_channel[1] && sink_valid[1];
+
+ src2_data = sink_data;
+ src2_startofpacket = sink_startofpacket;
+ src2_endofpacket = sink_endofpacket;
+ src2_channel = sink_channel >> NUM_OUTPUTS;
+
+ src2_valid = sink_channel[2] && sink_valid[2];
+
+ src3_data = sink_data;
+ src3_startofpacket = sink_startofpacket;
+ src3_endofpacket = sink_endofpacket;
+ src3_channel = sink_channel >> NUM_OUTPUTS;
+
+ src3_valid = sink_channel[3] && sink_valid[3];
+
+ src4_data = sink_data;
+ src4_startofpacket = sink_startofpacket;
+ src4_endofpacket = sink_endofpacket;
+ src4_channel = sink_channel >> NUM_OUTPUTS;
+
+ src4_valid = sink_channel[4] && sink_valid[4];
+
+ src5_data = sink_data;
+ src5_startofpacket = sink_startofpacket;
+ src5_endofpacket = sink_endofpacket;
+ src5_channel = sink_channel >> NUM_OUTPUTS;
+
+ src5_valid = sink_channel[5] && sink_valid[5];
+
+ src6_data = sink_data;
+ src6_startofpacket = sink_startofpacket;
+ src6_endofpacket = sink_endofpacket;
+ src6_channel = sink_channel >> NUM_OUTPUTS;
+
+ src6_valid = sink_channel[6] && sink_valid[6];
+
+ src7_data = sink_data;
+ src7_startofpacket = sink_startofpacket;
+ src7_endofpacket = sink_endofpacket;
+ src7_channel = sink_channel >> NUM_OUTPUTS;
+
+ src7_valid = sink_channel[7] && sink_valid[7];
+
+ end
+
+ // -------------------
+ // Backpressure
+ // -------------------
+ assign ready_vector[0] = src0_ready;
+ assign ready_vector[1] = src1_ready;
+ assign ready_vector[2] = src2_ready;
+ assign ready_vector[3] = src3_ready;
+ assign ready_vector[4] = src4_ready;
+ assign ready_vector[5] = src5_ready;
+ assign ready_vector[6] = src6_ready;
+ assign ready_vector[7] = src7_ready;
+ assign sink_ready = |(sink_channel & ready_vector);
+
+endmodule
+
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_cmd_xbar_demux_002.sv b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_cmd_xbar_demux_002.sv
new file mode 100644
index 0000000000000000000000000000000000000000..8486ca3ef08344dafd5cf3935d7a01d4b3d1ad35
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_cmd_xbar_demux_002.sv
@@ -0,0 +1,190 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/rel/11.1sp2/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2011/11/10 $
+// $Author: max $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+// output_name: ip_stratixiv_mac_10g_cmd_xbar_demux_002
+// ST_DATA_W: 69
+// ST_CHANNEL_W: 7
+// NUM_OUTPUTS: 7
+// VALID_WIDTH: 7
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module ip_stratixiv_mac_10g_cmd_xbar_demux_002
+(
+ // -------------------
+ // Sink
+ // -------------------
+ input [7-1 : 0] sink_valid,
+ input [69-1 : 0] sink_data, // ST_DATA_W=69
+ input [7-1 : 0] sink_channel, // ST_CHANNEL_W=7
+ input sink_startofpacket,
+ input sink_endofpacket,
+ output sink_ready,
+
+ // -------------------
+ // Sources
+ // -------------------
+ output reg src0_valid,
+ output reg [69-1 : 0] src0_data, // ST_DATA_W=69
+ output reg [7-1 : 0] src0_channel, // ST_CHANNEL_W=7
+ output reg src0_startofpacket,
+ output reg src0_endofpacket,
+ input src0_ready,
+
+ output reg src1_valid,
+ output reg [69-1 : 0] src1_data, // ST_DATA_W=69
+ output reg [7-1 : 0] src1_channel, // ST_CHANNEL_W=7
+ output reg src1_startofpacket,
+ output reg src1_endofpacket,
+ input src1_ready,
+
+ output reg src2_valid,
+ output reg [69-1 : 0] src2_data, // ST_DATA_W=69
+ output reg [7-1 : 0] src2_channel, // ST_CHANNEL_W=7
+ output reg src2_startofpacket,
+ output reg src2_endofpacket,
+ input src2_ready,
+
+ output reg src3_valid,
+ output reg [69-1 : 0] src3_data, // ST_DATA_W=69
+ output reg [7-1 : 0] src3_channel, // ST_CHANNEL_W=7
+ output reg src3_startofpacket,
+ output reg src3_endofpacket,
+ input src3_ready,
+
+ output reg src4_valid,
+ output reg [69-1 : 0] src4_data, // ST_DATA_W=69
+ output reg [7-1 : 0] src4_channel, // ST_CHANNEL_W=7
+ output reg src4_startofpacket,
+ output reg src4_endofpacket,
+ input src4_ready,
+
+ output reg src5_valid,
+ output reg [69-1 : 0] src5_data, // ST_DATA_W=69
+ output reg [7-1 : 0] src5_channel, // ST_CHANNEL_W=7
+ output reg src5_startofpacket,
+ output reg src5_endofpacket,
+ input src5_ready,
+
+ output reg src6_valid,
+ output reg [69-1 : 0] src6_data, // ST_DATA_W=69
+ output reg [7-1 : 0] src6_channel, // ST_CHANNEL_W=7
+ output reg src6_startofpacket,
+ output reg src6_endofpacket,
+ input src6_ready,
+
+
+ // -------------------
+ // Clock & Reset
+ // -------------------
+ (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+ input clk,
+ (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+ input reset
+
+);
+
+ localparam NUM_OUTPUTS = 7;
+ wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+ // -------------------
+ // Demux
+ // -------------------
+ always @* begin
+ src0_data = sink_data;
+ src0_startofpacket = sink_startofpacket;
+ src0_endofpacket = sink_endofpacket;
+ src0_channel = sink_channel >> NUM_OUTPUTS;
+
+ src0_valid = sink_channel[0] && sink_valid[0];
+
+ src1_data = sink_data;
+ src1_startofpacket = sink_startofpacket;
+ src1_endofpacket = sink_endofpacket;
+ src1_channel = sink_channel >> NUM_OUTPUTS;
+
+ src1_valid = sink_channel[1] && sink_valid[1];
+
+ src2_data = sink_data;
+ src2_startofpacket = sink_startofpacket;
+ src2_endofpacket = sink_endofpacket;
+ src2_channel = sink_channel >> NUM_OUTPUTS;
+
+ src2_valid = sink_channel[2] && sink_valid[2];
+
+ src3_data = sink_data;
+ src3_startofpacket = sink_startofpacket;
+ src3_endofpacket = sink_endofpacket;
+ src3_channel = sink_channel >> NUM_OUTPUTS;
+
+ src3_valid = sink_channel[3] && sink_valid[3];
+
+ src4_data = sink_data;
+ src4_startofpacket = sink_startofpacket;
+ src4_endofpacket = sink_endofpacket;
+ src4_channel = sink_channel >> NUM_OUTPUTS;
+
+ src4_valid = sink_channel[4] && sink_valid[4];
+
+ src5_data = sink_data;
+ src5_startofpacket = sink_startofpacket;
+ src5_endofpacket = sink_endofpacket;
+ src5_channel = sink_channel >> NUM_OUTPUTS;
+
+ src5_valid = sink_channel[5] && sink_valid[5];
+
+ src6_data = sink_data;
+ src6_startofpacket = sink_startofpacket;
+ src6_endofpacket = sink_endofpacket;
+ src6_channel = sink_channel >> NUM_OUTPUTS;
+
+ src6_valid = sink_channel[6] && sink_valid[6];
+
+ end
+
+ // -------------------
+ // Backpressure
+ // -------------------
+ assign ready_vector[0] = src0_ready;
+ assign ready_vector[1] = src1_ready;
+ assign ready_vector[2] = src2_ready;
+ assign ready_vector[3] = src3_ready;
+ assign ready_vector[4] = src4_ready;
+ assign ready_vector[5] = src5_ready;
+ assign ready_vector[6] = src6_ready;
+ assign sink_ready = |(sink_channel & ready_vector);
+
+endmodule
+
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_id_router.sv b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_id_router.sv
new file mode 100644
index 0000000000000000000000000000000000000000..280ee5d5b3d0a04b32f811c5c7515a3fcb1f17f4
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_id_router.sv
@@ -0,0 +1,177 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/rel/11.1sp2/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2011/11/10 $
+// $Author: max $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module ip_stratixiv_mac_10g_id_router_default_decode
+ #(
+ parameter DEFAULT_CHANNEL = 0,
+ DEFAULT_DESTID = 0
+ )
+ (output [64 - 64 : 0] default_destination_id,
+ output [2-1 : 0] default_src_channel
+ );
+
+ assign default_destination_id =
+ DEFAULT_DESTID[64 - 64 : 0];
+ generate begin : default_decode
+ if (DEFAULT_CHANNEL == -1)
+ assign default_src_channel = '0;
+ else
+ assign default_src_channel = 2'b1 << DEFAULT_CHANNEL;
+ end endgenerate
+
+endmodule
+
+
+module ip_stratixiv_mac_10g_id_router
+(
+ // -------------------
+ // Clock & Reset
+ // -------------------
+ input clk,
+ input reset,
+
+ // -------------------
+ // Command Sink (Input)
+ // -------------------
+ input sink_valid,
+ input [66-1 : 0] sink_data,
+ input sink_startofpacket,
+ input sink_endofpacket,
+ output sink_ready,
+
+ // -------------------
+ // Command Source (Output)
+ // -------------------
+ output src_valid,
+ output reg [66-1 : 0] src_data,
+ output reg [2-1 : 0] src_channel,
+ output src_startofpacket,
+ output src_endofpacket,
+ input src_ready
+);
+
+ // -------------------------------------------------------
+ // Local parameters and variables
+ // -------------------------------------------------------
+ localparam PKT_ADDR_H = 50;
+ localparam PKT_ADDR_L = 36;
+ localparam PKT_DEST_ID_H = 64;
+ localparam PKT_DEST_ID_L = 64;
+ localparam ST_DATA_W = 66;
+ localparam ST_CHANNEL_W = 2;
+ localparam DECODER_TYPE = 1;
+
+ localparam PKT_TRANS_WRITE = 53;
+ localparam PKT_TRANS_READ = 54;
+
+ localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+ localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+
+ // -------------------------------------------------------
+ // Figure out the number of bits to mask off for each slave span
+ // during address decoding
+ // -------------------------------------------------------
+
+ // -------------------------------------------------------
+ // Work out which address bits are significant based on the
+ // address range of the slaves. If the required width is too
+ // large or too small, we use the address field width instead.
+ // -------------------------------------------------------
+ localparam ADDR_RANGE = 32'h0;
+ localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+ localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+ (RANGE_ADDR_WIDTH == 0) ?
+ PKT_ADDR_H :
+ PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+ localparam RG = RANGE_ADDR_WIDTH-1;
+
+ reg [PKT_DEST_ID_W-1 : 0] destid;
+
+ // -------------------------------------------------------
+ // Pass almost everything through, untouched
+ // -------------------------------------------------------
+ assign sink_ready = src_ready;
+ assign src_valid = sink_valid;
+ assign src_startofpacket = sink_startofpacket;
+ assign src_endofpacket = sink_endofpacket;
+
+ wire [PKT_DEST_ID_W-1:0] default_destid;
+ wire [2-1 : 0] default_src_channel;
+
+
+
+
+ ip_stratixiv_mac_10g_id_router_default_decode the_default_decode(
+ .default_destination_id (default_destid),
+ .default_src_channel (default_src_channel)
+ );
+
+ always @* begin
+ src_data = sink_data;
+ src_channel = default_src_channel;
+
+ // --------------------------------------------------
+ // DestinationID Decoder
+ // Sets the channel based on the destination ID.
+ // --------------------------------------------------
+ destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+
+
+ if (destid == 0 ) begin
+ src_channel = 2'b1;
+ end
+
+ end
+
+ // --------------------------------------------------
+ // Ceil(log2()) function
+ // --------------------------------------------------
+ function integer log2ceil;
+ input reg[63:0] val;
+ reg [63:0] i;
+
+ begin
+ i = 1;
+ log2ceil = 0;
+
+ while (i < val) begin
+ log2ceil = log2ceil + 1;
+ i = i << 1;
+ end
+ end
+ endfunction
+
+endmodule
+
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_id_router_002.sv b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_id_router_002.sv
new file mode 100644
index 0000000000000000000000000000000000000000..3dce56e01f6510070f6b051667d9847e3a9a8bd4
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_id_router_002.sv
@@ -0,0 +1,177 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/rel/11.1sp2/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2011/11/10 $
+// $Author: max $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module ip_stratixiv_mac_10g_id_router_002_default_decode
+ #(
+ parameter DEFAULT_CHANNEL = 0,
+ DEFAULT_DESTID = 0
+ )
+ (output [67 - 65 : 0] default_destination_id,
+ output [8-1 : 0] default_src_channel
+ );
+
+ assign default_destination_id =
+ DEFAULT_DESTID[67 - 65 : 0];
+ generate begin : default_decode
+ if (DEFAULT_CHANNEL == -1)
+ assign default_src_channel = '0;
+ else
+ assign default_src_channel = 8'b1 << DEFAULT_CHANNEL;
+ end endgenerate
+
+endmodule
+
+
+module ip_stratixiv_mac_10g_id_router_002
+(
+ // -------------------
+ // Clock & Reset
+ // -------------------
+ input clk,
+ input reset,
+
+ // -------------------
+ // Command Sink (Input)
+ // -------------------
+ input sink_valid,
+ input [69-1 : 0] sink_data,
+ input sink_startofpacket,
+ input sink_endofpacket,
+ output sink_ready,
+
+ // -------------------
+ // Command Source (Output)
+ // -------------------
+ output src_valid,
+ output reg [69-1 : 0] src_data,
+ output reg [8-1 : 0] src_channel,
+ output src_startofpacket,
+ output src_endofpacket,
+ input src_ready
+);
+
+ // -------------------------------------------------------
+ // Local parameters and variables
+ // -------------------------------------------------------
+ localparam PKT_ADDR_H = 49;
+ localparam PKT_ADDR_L = 36;
+ localparam PKT_DEST_ID_H = 67;
+ localparam PKT_DEST_ID_L = 65;
+ localparam ST_DATA_W = 69;
+ localparam ST_CHANNEL_W = 8;
+ localparam DECODER_TYPE = 1;
+
+ localparam PKT_TRANS_WRITE = 52;
+ localparam PKT_TRANS_READ = 53;
+
+ localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+ localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+
+ // -------------------------------------------------------
+ // Figure out the number of bits to mask off for each slave span
+ // during address decoding
+ // -------------------------------------------------------
+
+ // -------------------------------------------------------
+ // Work out which address bits are significant based on the
+ // address range of the slaves. If the required width is too
+ // large or too small, we use the address field width instead.
+ // -------------------------------------------------------
+ localparam ADDR_RANGE = 32'h0;
+ localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+ localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+ (RANGE_ADDR_WIDTH == 0) ?
+ PKT_ADDR_H :
+ PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+ localparam RG = RANGE_ADDR_WIDTH-1;
+
+ reg [PKT_DEST_ID_W-1 : 0] destid;
+
+ // -------------------------------------------------------
+ // Pass almost everything through, untouched
+ // -------------------------------------------------------
+ assign sink_ready = src_ready;
+ assign src_valid = sink_valid;
+ assign src_startofpacket = sink_startofpacket;
+ assign src_endofpacket = sink_endofpacket;
+
+ wire [PKT_DEST_ID_W-1:0] default_destid;
+ wire [8-1 : 0] default_src_channel;
+
+
+
+
+ ip_stratixiv_mac_10g_id_router_002_default_decode the_default_decode(
+ .default_destination_id (default_destid),
+ .default_src_channel (default_src_channel)
+ );
+
+ always @* begin
+ src_data = sink_data;
+ src_channel = default_src_channel;
+
+ // --------------------------------------------------
+ // DestinationID Decoder
+ // Sets the channel based on the destination ID.
+ // --------------------------------------------------
+ destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+
+
+ if (destid == 0 ) begin
+ src_channel = 8'b1;
+ end
+
+ end
+
+ // --------------------------------------------------
+ // Ceil(log2()) function
+ // --------------------------------------------------
+ function integer log2ceil;
+ input reg[63:0] val;
+ reg [63:0] i;
+
+ begin
+ i = 1;
+ log2ceil = 0;
+
+ while (i < val) begin
+ log2ceil = log2ceil + 1;
+ i = i << 1;
+ end
+ end
+ endfunction
+
+endmodule
+
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_id_router_010.sv b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_id_router_010.sv
new file mode 100644
index 0000000000000000000000000000000000000000..4def9ce307df786e3d6a8cc44d06157b6d968dbd
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_id_router_010.sv
@@ -0,0 +1,177 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/rel/11.1sp2/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2011/11/10 $
+// $Author: max $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module ip_stratixiv_mac_10g_id_router_010_default_decode
+ #(
+ parameter DEFAULT_CHANNEL = 0,
+ DEFAULT_DESTID = 0
+ )
+ (output [67 - 65 : 0] default_destination_id,
+ output [7-1 : 0] default_src_channel
+ );
+
+ assign default_destination_id =
+ DEFAULT_DESTID[67 - 65 : 0];
+ generate begin : default_decode
+ if (DEFAULT_CHANNEL == -1)
+ assign default_src_channel = '0;
+ else
+ assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
+ end endgenerate
+
+endmodule
+
+
+module ip_stratixiv_mac_10g_id_router_010
+(
+ // -------------------
+ // Clock & Reset
+ // -------------------
+ input clk,
+ input reset,
+
+ // -------------------
+ // Command Sink (Input)
+ // -------------------
+ input sink_valid,
+ input [69-1 : 0] sink_data,
+ input sink_startofpacket,
+ input sink_endofpacket,
+ output sink_ready,
+
+ // -------------------
+ // Command Source (Output)
+ // -------------------
+ output src_valid,
+ output reg [69-1 : 0] src_data,
+ output reg [7-1 : 0] src_channel,
+ output src_startofpacket,
+ output src_endofpacket,
+ input src_ready
+);
+
+ // -------------------------------------------------------
+ // Local parameters and variables
+ // -------------------------------------------------------
+ localparam PKT_ADDR_H = 49;
+ localparam PKT_ADDR_L = 36;
+ localparam PKT_DEST_ID_H = 67;
+ localparam PKT_DEST_ID_L = 65;
+ localparam ST_DATA_W = 69;
+ localparam ST_CHANNEL_W = 7;
+ localparam DECODER_TYPE = 1;
+
+ localparam PKT_TRANS_WRITE = 52;
+ localparam PKT_TRANS_READ = 53;
+
+ localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+ localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+
+ // -------------------------------------------------------
+ // Figure out the number of bits to mask off for each slave span
+ // during address decoding
+ // -------------------------------------------------------
+
+ // -------------------------------------------------------
+ // Work out which address bits are significant based on the
+ // address range of the slaves. If the required width is too
+ // large or too small, we use the address field width instead.
+ // -------------------------------------------------------
+ localparam ADDR_RANGE = 32'h0;
+ localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+ localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+ (RANGE_ADDR_WIDTH == 0) ?
+ PKT_ADDR_H :
+ PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+ localparam RG = RANGE_ADDR_WIDTH-1;
+
+ reg [PKT_DEST_ID_W-1 : 0] destid;
+
+ // -------------------------------------------------------
+ // Pass almost everything through, untouched
+ // -------------------------------------------------------
+ assign sink_ready = src_ready;
+ assign src_valid = sink_valid;
+ assign src_startofpacket = sink_startofpacket;
+ assign src_endofpacket = sink_endofpacket;
+
+ wire [PKT_DEST_ID_W-1:0] default_destid;
+ wire [7-1 : 0] default_src_channel;
+
+
+
+
+ ip_stratixiv_mac_10g_id_router_010_default_decode the_default_decode(
+ .default_destination_id (default_destid),
+ .default_src_channel (default_src_channel)
+ );
+
+ always @* begin
+ src_data = sink_data;
+ src_channel = default_src_channel;
+
+ // --------------------------------------------------
+ // DestinationID Decoder
+ // Sets the channel based on the destination ID.
+ // --------------------------------------------------
+ destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+
+
+ if (destid == 0 ) begin
+ src_channel = 7'b1;
+ end
+
+ end
+
+ // --------------------------------------------------
+ // Ceil(log2()) function
+ // --------------------------------------------------
+ function integer log2ceil;
+ input reg[63:0] val;
+ reg [63:0] i;
+
+ begin
+ i = 1;
+ log2ceil = 0;
+
+ while (i < val) begin
+ log2ceil = log2ceil + 1;
+ i = i << 1;
+ end
+ end
+ endfunction
+
+endmodule
+
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rsp_xbar_demux.sv b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rsp_xbar_demux.sv
new file mode 100644
index 0000000000000000000000000000000000000000..a759ce390f5f958b24a611ab2b77149095df4c04
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rsp_xbar_demux.sv
@@ -0,0 +1,100 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/rel/11.1sp2/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2011/11/10 $
+// $Author: max $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+// output_name: ip_stratixiv_mac_10g_rsp_xbar_demux
+// ST_DATA_W: 66
+// ST_CHANNEL_W: 2
+// NUM_OUTPUTS: 1
+// VALID_WIDTH: 1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module ip_stratixiv_mac_10g_rsp_xbar_demux
+(
+ // -------------------
+ // Sink
+ // -------------------
+ input [1-1 : 0] sink_valid,
+ input [66-1 : 0] sink_data, // ST_DATA_W=66
+ input [2-1 : 0] sink_channel, // ST_CHANNEL_W=2
+ input sink_startofpacket,
+ input sink_endofpacket,
+ output sink_ready,
+
+ // -------------------
+ // Sources
+ // -------------------
+ output reg src0_valid,
+ output reg [66-1 : 0] src0_data, // ST_DATA_W=66
+ output reg [2-1 : 0] src0_channel, // ST_CHANNEL_W=2
+ output reg src0_startofpacket,
+ output reg src0_endofpacket,
+ input src0_ready,
+
+
+ // -------------------
+ // Clock & Reset
+ // -------------------
+ (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+ input clk,
+ (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+ input reset
+
+);
+
+ localparam NUM_OUTPUTS = 1;
+ wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+ // -------------------
+ // Demux
+ // -------------------
+ always @* begin
+ src0_data = sink_data;
+ src0_startofpacket = sink_startofpacket;
+ src0_endofpacket = sink_endofpacket;
+ src0_channel = sink_channel >> NUM_OUTPUTS;
+
+ src0_valid = sink_channel[0] && sink_valid;
+
+ end
+
+ // -------------------
+ // Backpressure
+ // -------------------
+ assign ready_vector[0] = src0_ready;
+ assign sink_ready = |(sink_channel & ready_vector);
+
+endmodule
+
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rsp_xbar_demux_002.sv b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rsp_xbar_demux_002.sv
new file mode 100644
index 0000000000000000000000000000000000000000..336bebe584e1476e5abebe4ba74fcb70c5ac2b62
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rsp_xbar_demux_002.sv
@@ -0,0 +1,100 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/rel/11.1sp2/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2011/11/10 $
+// $Author: max $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+// output_name: ip_stratixiv_mac_10g_rsp_xbar_demux_002
+// ST_DATA_W: 69
+// ST_CHANNEL_W: 8
+// NUM_OUTPUTS: 1
+// VALID_WIDTH: 1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module ip_stratixiv_mac_10g_rsp_xbar_demux_002
+(
+ // -------------------
+ // Sink
+ // -------------------
+ input [1-1 : 0] sink_valid,
+ input [69-1 : 0] sink_data, // ST_DATA_W=69
+ input [8-1 : 0] sink_channel, // ST_CHANNEL_W=8
+ input sink_startofpacket,
+ input sink_endofpacket,
+ output sink_ready,
+
+ // -------------------
+ // Sources
+ // -------------------
+ output reg src0_valid,
+ output reg [69-1 : 0] src0_data, // ST_DATA_W=69
+ output reg [8-1 : 0] src0_channel, // ST_CHANNEL_W=8
+ output reg src0_startofpacket,
+ output reg src0_endofpacket,
+ input src0_ready,
+
+
+ // -------------------
+ // Clock & Reset
+ // -------------------
+ (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+ input clk,
+ (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+ input reset
+
+);
+
+ localparam NUM_OUTPUTS = 1;
+ wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+ // -------------------
+ // Demux
+ // -------------------
+ always @* begin
+ src0_data = sink_data;
+ src0_startofpacket = sink_startofpacket;
+ src0_endofpacket = sink_endofpacket;
+ src0_channel = sink_channel >> NUM_OUTPUTS;
+
+ src0_valid = sink_channel[0] && sink_valid;
+
+ end
+
+ // -------------------
+ // Backpressure
+ // -------------------
+ assign ready_vector[0] = src0_ready;
+ assign sink_ready = |(sink_channel & ready_vector);
+
+endmodule
+
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rsp_xbar_demux_010.sv b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rsp_xbar_demux_010.sv
new file mode 100644
index 0000000000000000000000000000000000000000..1d60c922d8a1f68b55a1d4bee471576f0215d3bb
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rsp_xbar_demux_010.sv
@@ -0,0 +1,100 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/rel/11.1sp2/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2011/11/10 $
+// $Author: max $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+// output_name: ip_stratixiv_mac_10g_rsp_xbar_demux_010
+// ST_DATA_W: 69
+// ST_CHANNEL_W: 7
+// NUM_OUTPUTS: 1
+// VALID_WIDTH: 1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module ip_stratixiv_mac_10g_rsp_xbar_demux_010
+(
+ // -------------------
+ // Sink
+ // -------------------
+ input [1-1 : 0] sink_valid,
+ input [69-1 : 0] sink_data, // ST_DATA_W=69
+ input [7-1 : 0] sink_channel, // ST_CHANNEL_W=7
+ input sink_startofpacket,
+ input sink_endofpacket,
+ output sink_ready,
+
+ // -------------------
+ // Sources
+ // -------------------
+ output reg src0_valid,
+ output reg [69-1 : 0] src0_data, // ST_DATA_W=69
+ output reg [7-1 : 0] src0_channel, // ST_CHANNEL_W=7
+ output reg src0_startofpacket,
+ output reg src0_endofpacket,
+ input src0_ready,
+
+
+ // -------------------
+ // Clock & Reset
+ // -------------------
+ (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+ input clk,
+ (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+ input reset
+
+);
+
+ localparam NUM_OUTPUTS = 1;
+ wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+ // -------------------
+ // Demux
+ // -------------------
+ always @* begin
+ src0_data = sink_data;
+ src0_startofpacket = sink_startofpacket;
+ src0_endofpacket = sink_endofpacket;
+ src0_channel = sink_channel >> NUM_OUTPUTS;
+
+ src0_valid = sink_channel[0] && sink_valid;
+
+ end
+
+ // -------------------
+ // Backpressure
+ // -------------------
+ assign ready_vector[0] = src0_ready;
+ assign sink_ready = |(sink_channel & ready_vector);
+
+endmodule
+
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rsp_xbar_mux.sv b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rsp_xbar_mux.sv
new file mode 100644
index 0000000000000000000000000000000000000000..d40f12f5ada431fb1de770370ca0ea963a682cc0
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rsp_xbar_mux.sv
@@ -0,0 +1,328 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/rel/11.1sp2/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2011/11/10 $
+// $Author: max $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+// output_name: ip_stratixiv_mac_10g_rsp_xbar_mux
+// NUM_INPUTS: 2
+// ARBITRATION_SHARES: 1 1
+// ARBITRATION_SCHEME "no-arb"
+// PIPELINE_ARB: 0
+// PKT_TRANS_LOCK: 55 (arbitration locking enabled)
+// ST_DATA_W: 66
+// ST_CHANNEL_W: 2
+// ------------------------------------------
+
+module ip_stratixiv_mac_10g_rsp_xbar_mux
+(
+ // ----------------------
+ // Sinks
+ // ----------------------
+ input sink0_valid,
+ input [66-1 : 0] sink0_data,
+ input [2-1: 0] sink0_channel,
+ input sink0_startofpacket,
+ input sink0_endofpacket,
+ output sink0_ready,
+
+ input sink1_valid,
+ input [66-1 : 0] sink1_data,
+ input [2-1: 0] sink1_channel,
+ input sink1_startofpacket,
+ input sink1_endofpacket,
+ output sink1_ready,
+
+
+ // ----------------------
+ // Source
+ // ----------------------
+ output src_valid,
+ output [66-1 : 0] src_data,
+ output [2-1 : 0] src_channel,
+ output src_startofpacket,
+ output src_endofpacket,
+ input src_ready,
+
+ // ----------------------
+ // Clock & Reset
+ // ----------------------
+ input clk,
+ input reset
+);
+ localparam PAYLOAD_W = 66 + 2 + 2;
+ localparam NUM_INPUTS = 2;
+ localparam SHARE_COUNTER_W = 1;
+ localparam PIPELINE_ARB = 0;
+ localparam ST_DATA_W = 66;
+ localparam ST_CHANNEL_W = 2;
+ localparam PKT_TRANS_LOCK = 55;
+
+ // ------------------------------------------
+ // Signals
+ // ------------------------------------------
+ wire [NUM_INPUTS - 1 : 0] request;
+ wire [NUM_INPUTS - 1 : 0] valid;
+ wire [NUM_INPUTS - 1 : 0] grant;
+ wire [NUM_INPUTS - 1 : 0] next_grant;
+ reg [NUM_INPUTS - 1 : 0] saved_grant;
+ reg [PAYLOAD_W - 1 : 0] src_payload;
+ wire last_cycle;
+ reg packet_in_progress;
+ reg update_grant;
+
+ wire [PAYLOAD_W - 1 : 0] sink0_payload;
+ wire [PAYLOAD_W - 1 : 0] sink1_payload;
+
+ assign valid[0] = sink0_valid;
+ assign valid[1] = sink1_valid;
+
+
+ // ------------------------------------------
+ // ------------------------------------------
+ // Grant Logic & Updates
+ // ------------------------------------------
+ // ------------------------------------------
+ reg [NUM_INPUTS - 1 : 0] lock;
+ always @* begin
+ lock[0] = sink0_data[55];
+ lock[1] = sink1_data[55];
+ end
+
+ assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
+
+ // ------------------------------------------
+ // We're working on a packet at any time valid is high, except
+ // when this is the endofpacket.
+ // ------------------------------------------
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ packet_in_progress <= 1'b0;
+ end
+ else begin
+ if (src_valid)
+ packet_in_progress <= 1'b1;
+ if (last_cycle)
+ packet_in_progress <= 1'b0;
+ end
+ end
+
+
+ // ------------------------------------------
+ // Shares
+ //
+ // Special case: all-equal shares _should_ be optimized into assigning a
+ // constant to next_grant_share.
+ // Special case: all-1's shares _should_ result in the share counter
+ // being optimized away.
+ // ------------------------------------------
+ // Input | arb shares | counter load value
+ // 0 | 1 | 0
+ // 1 | 1 | 0
+ wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
+ wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
+
+ // ------------------------------------------
+ // Choose the share value corresponding to the grant.
+ // ------------------------------------------
+ reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
+ always @* begin
+ next_grant_share =
+ share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
+ share_1 & { SHARE_COUNTER_W {next_grant[1]} };
+ end
+
+ // ------------------------------------------
+ // Flag to indicate first packet of an arb sequence.
+ // ------------------------------------------
+ wire grant_changed = ~packet_in_progress && !(saved_grant & valid);
+ reg first_packet_r;
+ wire first_packet = grant_changed | first_packet_r;
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ first_packet_r <= 1'b0;
+ end
+ else begin
+ if (update_grant)
+ first_packet_r <= 1'b1;
+ else if (last_cycle)
+ first_packet_r <= 1'b0;
+ else if (grant_changed)
+ first_packet_r <= 1'b1;
+ end
+ end
+
+ // ------------------------------------------
+ // Compute the next share-count value.
+ // ------------------------------------------
+ reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
+ reg [SHARE_COUNTER_W - 1 : 0] share_count;
+ reg share_count_zero_flag;
+
+ always @* begin
+ if (first_packet) begin
+ p1_share_count = next_grant_share;
+ end
+ else begin
+ // Update the counter, but don't decrement below 0.
+ p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
+ end
+ end
+
+ // ------------------------------------------
+ // Update the share counter and share-counter=zero flag.
+ // ------------------------------------------
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ share_count <= '0;
+ share_count_zero_flag <= 1'b1;
+ end
+ else begin
+ if (last_cycle) begin
+ share_count <= p1_share_count;
+ share_count_zero_flag <= (p1_share_count == '0);
+ end
+ end
+ end
+
+ // ------------------------------------------
+ // For each input, maintain a final_packet signal which goes active for the
+ // last packet of a full-share packet sequence. Example: if I have 4
+ // shares and I'm continuously requesting, final_packet is active in the
+ // 4th packet.
+ // ------------------------------------------
+ wire final_packet_0 = 1'b1;
+
+ wire final_packet_1 = 1'b1;
+
+
+ // ------------------------------------------
+ // Concatenate all final_packet signals (wire or reg) into a handy vector.
+ // ------------------------------------------
+ wire [NUM_INPUTS - 1 : 0] final_packet = {
+ final_packet_1,
+ final_packet_0
+ };
+
+ // ------------------------------------------
+ // ------------------------------------------
+ wire p1_done = |(final_packet & grant);
+
+ // ------------------------------------------
+ // Flag for the first cycle of packets within an
+ // arb sequence
+ // ------------------------------------------
+ reg first_cycle;
+ always @(posedge clk, posedge reset) begin
+ if (reset)
+ first_cycle <= 0;
+ else
+ first_cycle <= last_cycle && ~p1_done;
+ end
+
+
+ always @* begin
+ update_grant = 0;
+
+ // ------------------------------------------
+ // No arbitration pipeline, update grant whenever
+ // the current arb winner has consumed all shares,
+ // or all requests are low
+ // ------------------------------------------
+ update_grant = (last_cycle && p1_done) || (first_cycle && !valid);
+ update_grant = last_cycle;
+ end
+
+ wire save_grant;
+ assign save_grant = 1;
+ assign grant = next_grant;
+
+ always @(posedge clk, posedge reset) begin
+ if (reset)
+ saved_grant <= '0;
+ else if (save_grant)
+ saved_grant <= next_grant;
+ end
+
+ // ------------------------------------------
+ // ------------------------------------------
+ // Arbitrator
+ // ------------------------------------------
+ // ------------------------------------------
+
+ // ------------------------------------------
+ // Create a request vector that stays high during
+ // the packet
+ // ------------------------------------------
+ assign request = valid;
+
+
+ altera_merlin_arbitrator
+ #(
+ .NUM_REQUESTERS(NUM_INPUTS),
+ .SCHEME ("no-arb"),
+ .PIPELINE (0)
+ ) arb (
+ .clk (clk),
+ .reset (reset),
+ .request (request),
+ .grant (next_grant),
+ .save_top_priority (src_valid),
+ .increment_top_priority (update_grant)
+ );
+
+ // ------------------------------------------
+ // ------------------------------------------
+ // Mux
+ //
+ // Implemented as a sum of products.
+ // ------------------------------------------
+ // ------------------------------------------
+
+ assign sink0_ready = src_ready && grant[0];
+ assign sink1_ready = src_ready && grant[1];
+
+ assign src_valid = |(grant & valid);
+
+ always @* begin
+ src_payload =
+ sink0_payload & {PAYLOAD_W {grant[0]} } |
+ sink1_payload & {PAYLOAD_W {grant[1]} };
+ end
+
+ // ------------------------------------------
+ // Mux Payload Mapping
+ // ------------------------------------------
+
+ assign sink0_payload = {sink0_channel,sink0_data,
+ sink0_startofpacket,sink0_endofpacket};
+ assign sink1_payload = {sink1_channel,sink1_data,
+ sink1_startofpacket,sink1_endofpacket};
+
+ assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
+
+endmodule
+
+
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rsp_xbar_mux_001.sv b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rsp_xbar_mux_001.sv
new file mode 100644
index 0000000000000000000000000000000000000000..42a8ceca87a5cfcc5ebe1f3db78b006c6376ed10
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rsp_xbar_mux_001.sv
@@ -0,0 +1,448 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/rel/11.1sp2/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2011/11/10 $
+// $Author: max $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+// output_name: ip_stratixiv_mac_10g_rsp_xbar_mux_001
+// NUM_INPUTS: 8
+// ARBITRATION_SHARES: 1 1 1 1 1 1 1 1
+// ARBITRATION_SCHEME "no-arb"
+// PIPELINE_ARB: 0
+// PKT_TRANS_LOCK: 54 (arbitration locking enabled)
+// ST_DATA_W: 69
+// ST_CHANNEL_W: 8
+// ------------------------------------------
+
+module ip_stratixiv_mac_10g_rsp_xbar_mux_001
+(
+ // ----------------------
+ // Sinks
+ // ----------------------
+ input sink0_valid,
+ input [69-1 : 0] sink0_data,
+ input [8-1: 0] sink0_channel,
+ input sink0_startofpacket,
+ input sink0_endofpacket,
+ output sink0_ready,
+
+ input sink1_valid,
+ input [69-1 : 0] sink1_data,
+ input [8-1: 0] sink1_channel,
+ input sink1_startofpacket,
+ input sink1_endofpacket,
+ output sink1_ready,
+
+ input sink2_valid,
+ input [69-1 : 0] sink2_data,
+ input [8-1: 0] sink2_channel,
+ input sink2_startofpacket,
+ input sink2_endofpacket,
+ output sink2_ready,
+
+ input sink3_valid,
+ input [69-1 : 0] sink3_data,
+ input [8-1: 0] sink3_channel,
+ input sink3_startofpacket,
+ input sink3_endofpacket,
+ output sink3_ready,
+
+ input sink4_valid,
+ input [69-1 : 0] sink4_data,
+ input [8-1: 0] sink4_channel,
+ input sink4_startofpacket,
+ input sink4_endofpacket,
+ output sink4_ready,
+
+ input sink5_valid,
+ input [69-1 : 0] sink5_data,
+ input [8-1: 0] sink5_channel,
+ input sink5_startofpacket,
+ input sink5_endofpacket,
+ output sink5_ready,
+
+ input sink6_valid,
+ input [69-1 : 0] sink6_data,
+ input [8-1: 0] sink6_channel,
+ input sink6_startofpacket,
+ input sink6_endofpacket,
+ output sink6_ready,
+
+ input sink7_valid,
+ input [69-1 : 0] sink7_data,
+ input [8-1: 0] sink7_channel,
+ input sink7_startofpacket,
+ input sink7_endofpacket,
+ output sink7_ready,
+
+
+ // ----------------------
+ // Source
+ // ----------------------
+ output src_valid,
+ output [69-1 : 0] src_data,
+ output [8-1 : 0] src_channel,
+ output src_startofpacket,
+ output src_endofpacket,
+ input src_ready,
+
+ // ----------------------
+ // Clock & Reset
+ // ----------------------
+ input clk,
+ input reset
+);
+ localparam PAYLOAD_W = 69 + 8 + 2;
+ localparam NUM_INPUTS = 8;
+ localparam SHARE_COUNTER_W = 1;
+ localparam PIPELINE_ARB = 0;
+ localparam ST_DATA_W = 69;
+ localparam ST_CHANNEL_W = 8;
+ localparam PKT_TRANS_LOCK = 54;
+
+ // ------------------------------------------
+ // Signals
+ // ------------------------------------------
+ wire [NUM_INPUTS - 1 : 0] request;
+ wire [NUM_INPUTS - 1 : 0] valid;
+ wire [NUM_INPUTS - 1 : 0] grant;
+ wire [NUM_INPUTS - 1 : 0] next_grant;
+ reg [NUM_INPUTS - 1 : 0] saved_grant;
+ reg [PAYLOAD_W - 1 : 0] src_payload;
+ wire last_cycle;
+ reg packet_in_progress;
+ reg update_grant;
+
+ wire [PAYLOAD_W - 1 : 0] sink0_payload;
+ wire [PAYLOAD_W - 1 : 0] sink1_payload;
+ wire [PAYLOAD_W - 1 : 0] sink2_payload;
+ wire [PAYLOAD_W - 1 : 0] sink3_payload;
+ wire [PAYLOAD_W - 1 : 0] sink4_payload;
+ wire [PAYLOAD_W - 1 : 0] sink5_payload;
+ wire [PAYLOAD_W - 1 : 0] sink6_payload;
+ wire [PAYLOAD_W - 1 : 0] sink7_payload;
+
+ assign valid[0] = sink0_valid;
+ assign valid[1] = sink1_valid;
+ assign valid[2] = sink2_valid;
+ assign valid[3] = sink3_valid;
+ assign valid[4] = sink4_valid;
+ assign valid[5] = sink5_valid;
+ assign valid[6] = sink6_valid;
+ assign valid[7] = sink7_valid;
+
+
+ // ------------------------------------------
+ // ------------------------------------------
+ // Grant Logic & Updates
+ // ------------------------------------------
+ // ------------------------------------------
+ reg [NUM_INPUTS - 1 : 0] lock;
+ always @* begin
+ lock[0] = sink0_data[54];
+ lock[1] = sink1_data[54];
+ lock[2] = sink2_data[54];
+ lock[3] = sink3_data[54];
+ lock[4] = sink4_data[54];
+ lock[5] = sink5_data[54];
+ lock[6] = sink6_data[54];
+ lock[7] = sink7_data[54];
+ end
+
+ assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
+
+ // ------------------------------------------
+ // We're working on a packet at any time valid is high, except
+ // when this is the endofpacket.
+ // ------------------------------------------
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ packet_in_progress <= 1'b0;
+ end
+ else begin
+ if (src_valid)
+ packet_in_progress <= 1'b1;
+ if (last_cycle)
+ packet_in_progress <= 1'b0;
+ end
+ end
+
+
+ // ------------------------------------------
+ // Shares
+ //
+ // Special case: all-equal shares _should_ be optimized into assigning a
+ // constant to next_grant_share.
+ // Special case: all-1's shares _should_ result in the share counter
+ // being optimized away.
+ // ------------------------------------------
+ // Input | arb shares | counter load value
+ // 0 | 1 | 0
+ // 1 | 1 | 0
+ // 2 | 1 | 0
+ // 3 | 1 | 0
+ // 4 | 1 | 0
+ // 5 | 1 | 0
+ // 6 | 1 | 0
+ // 7 | 1 | 0
+ wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
+ wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
+ wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
+ wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
+ wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0;
+ wire [SHARE_COUNTER_W - 1 : 0] share_5 = 1'd0;
+ wire [SHARE_COUNTER_W - 1 : 0] share_6 = 1'd0;
+ wire [SHARE_COUNTER_W - 1 : 0] share_7 = 1'd0;
+
+ // ------------------------------------------
+ // Choose the share value corresponding to the grant.
+ // ------------------------------------------
+ reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
+ always @* begin
+ next_grant_share =
+ share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
+ share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
+ share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
+ share_3 & { SHARE_COUNTER_W {next_grant[3]} } |
+ share_4 & { SHARE_COUNTER_W {next_grant[4]} } |
+ share_5 & { SHARE_COUNTER_W {next_grant[5]} } |
+ share_6 & { SHARE_COUNTER_W {next_grant[6]} } |
+ share_7 & { SHARE_COUNTER_W {next_grant[7]} };
+ end
+
+ // ------------------------------------------
+ // Flag to indicate first packet of an arb sequence.
+ // ------------------------------------------
+ wire grant_changed = ~packet_in_progress && !(saved_grant & valid);
+ reg first_packet_r;
+ wire first_packet = grant_changed | first_packet_r;
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ first_packet_r <= 1'b0;
+ end
+ else begin
+ if (update_grant)
+ first_packet_r <= 1'b1;
+ else if (last_cycle)
+ first_packet_r <= 1'b0;
+ else if (grant_changed)
+ first_packet_r <= 1'b1;
+ end
+ end
+
+ // ------------------------------------------
+ // Compute the next share-count value.
+ // ------------------------------------------
+ reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
+ reg [SHARE_COUNTER_W - 1 : 0] share_count;
+ reg share_count_zero_flag;
+
+ always @* begin
+ if (first_packet) begin
+ p1_share_count = next_grant_share;
+ end
+ else begin
+ // Update the counter, but don't decrement below 0.
+ p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
+ end
+ end
+
+ // ------------------------------------------
+ // Update the share counter and share-counter=zero flag.
+ // ------------------------------------------
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ share_count <= '0;
+ share_count_zero_flag <= 1'b1;
+ end
+ else begin
+ if (last_cycle) begin
+ share_count <= p1_share_count;
+ share_count_zero_flag <= (p1_share_count == '0);
+ end
+ end
+ end
+
+ // ------------------------------------------
+ // For each input, maintain a final_packet signal which goes active for the
+ // last packet of a full-share packet sequence. Example: if I have 4
+ // shares and I'm continuously requesting, final_packet is active in the
+ // 4th packet.
+ // ------------------------------------------
+ wire final_packet_0 = 1'b1;
+
+ wire final_packet_1 = 1'b1;
+
+ wire final_packet_2 = 1'b1;
+
+ wire final_packet_3 = 1'b1;
+
+ wire final_packet_4 = 1'b1;
+
+ wire final_packet_5 = 1'b1;
+
+ wire final_packet_6 = 1'b1;
+
+ wire final_packet_7 = 1'b1;
+
+
+ // ------------------------------------------
+ // Concatenate all final_packet signals (wire or reg) into a handy vector.
+ // ------------------------------------------
+ wire [NUM_INPUTS - 1 : 0] final_packet = {
+ final_packet_7,
+ final_packet_6,
+ final_packet_5,
+ final_packet_4,
+ final_packet_3,
+ final_packet_2,
+ final_packet_1,
+ final_packet_0
+ };
+
+ // ------------------------------------------
+ // ------------------------------------------
+ wire p1_done = |(final_packet & grant);
+
+ // ------------------------------------------
+ // Flag for the first cycle of packets within an
+ // arb sequence
+ // ------------------------------------------
+ reg first_cycle;
+ always @(posedge clk, posedge reset) begin
+ if (reset)
+ first_cycle <= 0;
+ else
+ first_cycle <= last_cycle && ~p1_done;
+ end
+
+
+ always @* begin
+ update_grant = 0;
+
+ // ------------------------------------------
+ // No arbitration pipeline, update grant whenever
+ // the current arb winner has consumed all shares,
+ // or all requests are low
+ // ------------------------------------------
+ update_grant = (last_cycle && p1_done) || (first_cycle && !valid);
+ update_grant = last_cycle;
+ end
+
+ wire save_grant;
+ assign save_grant = 1;
+ assign grant = next_grant;
+
+ always @(posedge clk, posedge reset) begin
+ if (reset)
+ saved_grant <= '0;
+ else if (save_grant)
+ saved_grant <= next_grant;
+ end
+
+ // ------------------------------------------
+ // ------------------------------------------
+ // Arbitrator
+ // ------------------------------------------
+ // ------------------------------------------
+
+ // ------------------------------------------
+ // Create a request vector that stays high during
+ // the packet
+ // ------------------------------------------
+ assign request = valid;
+
+
+ altera_merlin_arbitrator
+ #(
+ .NUM_REQUESTERS(NUM_INPUTS),
+ .SCHEME ("no-arb"),
+ .PIPELINE (0)
+ ) arb (
+ .clk (clk),
+ .reset (reset),
+ .request (request),
+ .grant (next_grant),
+ .save_top_priority (src_valid),
+ .increment_top_priority (update_grant)
+ );
+
+ // ------------------------------------------
+ // ------------------------------------------
+ // Mux
+ //
+ // Implemented as a sum of products.
+ // ------------------------------------------
+ // ------------------------------------------
+
+ assign sink0_ready = src_ready && grant[0];
+ assign sink1_ready = src_ready && grant[1];
+ assign sink2_ready = src_ready && grant[2];
+ assign sink3_ready = src_ready && grant[3];
+ assign sink4_ready = src_ready && grant[4];
+ assign sink5_ready = src_ready && grant[5];
+ assign sink6_ready = src_ready && grant[6];
+ assign sink7_ready = src_ready && grant[7];
+
+ assign src_valid = |(grant & valid);
+
+ always @* begin
+ src_payload =
+ sink0_payload & {PAYLOAD_W {grant[0]} } |
+ sink1_payload & {PAYLOAD_W {grant[1]} } |
+ sink2_payload & {PAYLOAD_W {grant[2]} } |
+ sink3_payload & {PAYLOAD_W {grant[3]} } |
+ sink4_payload & {PAYLOAD_W {grant[4]} } |
+ sink5_payload & {PAYLOAD_W {grant[5]} } |
+ sink6_payload & {PAYLOAD_W {grant[6]} } |
+ sink7_payload & {PAYLOAD_W {grant[7]} };
+ end
+
+ // ------------------------------------------
+ // Mux Payload Mapping
+ // ------------------------------------------
+
+ assign sink0_payload = {sink0_channel,sink0_data,
+ sink0_startofpacket,sink0_endofpacket};
+ assign sink1_payload = {sink1_channel,sink1_data,
+ sink1_startofpacket,sink1_endofpacket};
+ assign sink2_payload = {sink2_channel,sink2_data,
+ sink2_startofpacket,sink2_endofpacket};
+ assign sink3_payload = {sink3_channel,sink3_data,
+ sink3_startofpacket,sink3_endofpacket};
+ assign sink4_payload = {sink4_channel,sink4_data,
+ sink4_startofpacket,sink4_endofpacket};
+ assign sink5_payload = {sink5_channel,sink5_data,
+ sink5_startofpacket,sink5_endofpacket};
+ assign sink6_payload = {sink6_channel,sink6_data,
+ sink6_startofpacket,sink6_endofpacket};
+ assign sink7_payload = {sink7_channel,sink7_data,
+ sink7_startofpacket,sink7_endofpacket};
+
+ assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
+
+endmodule
+
+
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rsp_xbar_mux_002.sv b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rsp_xbar_mux_002.sv
new file mode 100644
index 0000000000000000000000000000000000000000..623598f7941e53285141edf382f8d144e10b4424
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rsp_xbar_mux_002.sv
@@ -0,0 +1,428 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/rel/11.1sp2/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2011/11/10 $
+// $Author: max $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+// output_name: ip_stratixiv_mac_10g_rsp_xbar_mux_002
+// NUM_INPUTS: 7
+// ARBITRATION_SHARES: 1 1 1 1 1 1 1
+// ARBITRATION_SCHEME "no-arb"
+// PIPELINE_ARB: 0
+// PKT_TRANS_LOCK: 54 (arbitration locking enabled)
+// ST_DATA_W: 69
+// ST_CHANNEL_W: 7
+// ------------------------------------------
+
+module ip_stratixiv_mac_10g_rsp_xbar_mux_002
+(
+ // ----------------------
+ // Sinks
+ // ----------------------
+ input sink0_valid,
+ input [69-1 : 0] sink0_data,
+ input [7-1: 0] sink0_channel,
+ input sink0_startofpacket,
+ input sink0_endofpacket,
+ output sink0_ready,
+
+ input sink1_valid,
+ input [69-1 : 0] sink1_data,
+ input [7-1: 0] sink1_channel,
+ input sink1_startofpacket,
+ input sink1_endofpacket,
+ output sink1_ready,
+
+ input sink2_valid,
+ input [69-1 : 0] sink2_data,
+ input [7-1: 0] sink2_channel,
+ input sink2_startofpacket,
+ input sink2_endofpacket,
+ output sink2_ready,
+
+ input sink3_valid,
+ input [69-1 : 0] sink3_data,
+ input [7-1: 0] sink3_channel,
+ input sink3_startofpacket,
+ input sink3_endofpacket,
+ output sink3_ready,
+
+ input sink4_valid,
+ input [69-1 : 0] sink4_data,
+ input [7-1: 0] sink4_channel,
+ input sink4_startofpacket,
+ input sink4_endofpacket,
+ output sink4_ready,
+
+ input sink5_valid,
+ input [69-1 : 0] sink5_data,
+ input [7-1: 0] sink5_channel,
+ input sink5_startofpacket,
+ input sink5_endofpacket,
+ output sink5_ready,
+
+ input sink6_valid,
+ input [69-1 : 0] sink6_data,
+ input [7-1: 0] sink6_channel,
+ input sink6_startofpacket,
+ input sink6_endofpacket,
+ output sink6_ready,
+
+
+ // ----------------------
+ // Source
+ // ----------------------
+ output src_valid,
+ output [69-1 : 0] src_data,
+ output [7-1 : 0] src_channel,
+ output src_startofpacket,
+ output src_endofpacket,
+ input src_ready,
+
+ // ----------------------
+ // Clock & Reset
+ // ----------------------
+ input clk,
+ input reset
+);
+ localparam PAYLOAD_W = 69 + 7 + 2;
+ localparam NUM_INPUTS = 7;
+ localparam SHARE_COUNTER_W = 1;
+ localparam PIPELINE_ARB = 0;
+ localparam ST_DATA_W = 69;
+ localparam ST_CHANNEL_W = 7;
+ localparam PKT_TRANS_LOCK = 54;
+
+ // ------------------------------------------
+ // Signals
+ // ------------------------------------------
+ wire [NUM_INPUTS - 1 : 0] request;
+ wire [NUM_INPUTS - 1 : 0] valid;
+ wire [NUM_INPUTS - 1 : 0] grant;
+ wire [NUM_INPUTS - 1 : 0] next_grant;
+ reg [NUM_INPUTS - 1 : 0] saved_grant;
+ reg [PAYLOAD_W - 1 : 0] src_payload;
+ wire last_cycle;
+ reg packet_in_progress;
+ reg update_grant;
+
+ wire [PAYLOAD_W - 1 : 0] sink0_payload;
+ wire [PAYLOAD_W - 1 : 0] sink1_payload;
+ wire [PAYLOAD_W - 1 : 0] sink2_payload;
+ wire [PAYLOAD_W - 1 : 0] sink3_payload;
+ wire [PAYLOAD_W - 1 : 0] sink4_payload;
+ wire [PAYLOAD_W - 1 : 0] sink5_payload;
+ wire [PAYLOAD_W - 1 : 0] sink6_payload;
+
+ assign valid[0] = sink0_valid;
+ assign valid[1] = sink1_valid;
+ assign valid[2] = sink2_valid;
+ assign valid[3] = sink3_valid;
+ assign valid[4] = sink4_valid;
+ assign valid[5] = sink5_valid;
+ assign valid[6] = sink6_valid;
+
+
+ // ------------------------------------------
+ // ------------------------------------------
+ // Grant Logic & Updates
+ // ------------------------------------------
+ // ------------------------------------------
+ reg [NUM_INPUTS - 1 : 0] lock;
+ always @* begin
+ lock[0] = sink0_data[54];
+ lock[1] = sink1_data[54];
+ lock[2] = sink2_data[54];
+ lock[3] = sink3_data[54];
+ lock[4] = sink4_data[54];
+ lock[5] = sink5_data[54];
+ lock[6] = sink6_data[54];
+ end
+
+ assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
+
+ // ------------------------------------------
+ // We're working on a packet at any time valid is high, except
+ // when this is the endofpacket.
+ // ------------------------------------------
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ packet_in_progress <= 1'b0;
+ end
+ else begin
+ if (src_valid)
+ packet_in_progress <= 1'b1;
+ if (last_cycle)
+ packet_in_progress <= 1'b0;
+ end
+ end
+
+
+ // ------------------------------------------
+ // Shares
+ //
+ // Special case: all-equal shares _should_ be optimized into assigning a
+ // constant to next_grant_share.
+ // Special case: all-1's shares _should_ result in the share counter
+ // being optimized away.
+ // ------------------------------------------
+ // Input | arb shares | counter load value
+ // 0 | 1 | 0
+ // 1 | 1 | 0
+ // 2 | 1 | 0
+ // 3 | 1 | 0
+ // 4 | 1 | 0
+ // 5 | 1 | 0
+ // 6 | 1 | 0
+ wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
+ wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
+ wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
+ wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
+ wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0;
+ wire [SHARE_COUNTER_W - 1 : 0] share_5 = 1'd0;
+ wire [SHARE_COUNTER_W - 1 : 0] share_6 = 1'd0;
+
+ // ------------------------------------------
+ // Choose the share value corresponding to the grant.
+ // ------------------------------------------
+ reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
+ always @* begin
+ next_grant_share =
+ share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
+ share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
+ share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
+ share_3 & { SHARE_COUNTER_W {next_grant[3]} } |
+ share_4 & { SHARE_COUNTER_W {next_grant[4]} } |
+ share_5 & { SHARE_COUNTER_W {next_grant[5]} } |
+ share_6 & { SHARE_COUNTER_W {next_grant[6]} };
+ end
+
+ // ------------------------------------------
+ // Flag to indicate first packet of an arb sequence.
+ // ------------------------------------------
+ wire grant_changed = ~packet_in_progress && !(saved_grant & valid);
+ reg first_packet_r;
+ wire first_packet = grant_changed | first_packet_r;
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ first_packet_r <= 1'b0;
+ end
+ else begin
+ if (update_grant)
+ first_packet_r <= 1'b1;
+ else if (last_cycle)
+ first_packet_r <= 1'b0;
+ else if (grant_changed)
+ first_packet_r <= 1'b1;
+ end
+ end
+
+ // ------------------------------------------
+ // Compute the next share-count value.
+ // ------------------------------------------
+ reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
+ reg [SHARE_COUNTER_W - 1 : 0] share_count;
+ reg share_count_zero_flag;
+
+ always @* begin
+ if (first_packet) begin
+ p1_share_count = next_grant_share;
+ end
+ else begin
+ // Update the counter, but don't decrement below 0.
+ p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
+ end
+ end
+
+ // ------------------------------------------
+ // Update the share counter and share-counter=zero flag.
+ // ------------------------------------------
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ share_count <= '0;
+ share_count_zero_flag <= 1'b1;
+ end
+ else begin
+ if (last_cycle) begin
+ share_count <= p1_share_count;
+ share_count_zero_flag <= (p1_share_count == '0);
+ end
+ end
+ end
+
+ // ------------------------------------------
+ // For each input, maintain a final_packet signal which goes active for the
+ // last packet of a full-share packet sequence. Example: if I have 4
+ // shares and I'm continuously requesting, final_packet is active in the
+ // 4th packet.
+ // ------------------------------------------
+ wire final_packet_0 = 1'b1;
+
+ wire final_packet_1 = 1'b1;
+
+ wire final_packet_2 = 1'b1;
+
+ wire final_packet_3 = 1'b1;
+
+ wire final_packet_4 = 1'b1;
+
+ wire final_packet_5 = 1'b1;
+
+ wire final_packet_6 = 1'b1;
+
+
+ // ------------------------------------------
+ // Concatenate all final_packet signals (wire or reg) into a handy vector.
+ // ------------------------------------------
+ wire [NUM_INPUTS - 1 : 0] final_packet = {
+ final_packet_6,
+ final_packet_5,
+ final_packet_4,
+ final_packet_3,
+ final_packet_2,
+ final_packet_1,
+ final_packet_0
+ };
+
+ // ------------------------------------------
+ // ------------------------------------------
+ wire p1_done = |(final_packet & grant);
+
+ // ------------------------------------------
+ // Flag for the first cycle of packets within an
+ // arb sequence
+ // ------------------------------------------
+ reg first_cycle;
+ always @(posedge clk, posedge reset) begin
+ if (reset)
+ first_cycle <= 0;
+ else
+ first_cycle <= last_cycle && ~p1_done;
+ end
+
+
+ always @* begin
+ update_grant = 0;
+
+ // ------------------------------------------
+ // No arbitration pipeline, update grant whenever
+ // the current arb winner has consumed all shares,
+ // or all requests are low
+ // ------------------------------------------
+ update_grant = (last_cycle && p1_done) || (first_cycle && !valid);
+ update_grant = last_cycle;
+ end
+
+ wire save_grant;
+ assign save_grant = 1;
+ assign grant = next_grant;
+
+ always @(posedge clk, posedge reset) begin
+ if (reset)
+ saved_grant <= '0;
+ else if (save_grant)
+ saved_grant <= next_grant;
+ end
+
+ // ------------------------------------------
+ // ------------------------------------------
+ // Arbitrator
+ // ------------------------------------------
+ // ------------------------------------------
+
+ // ------------------------------------------
+ // Create a request vector that stays high during
+ // the packet
+ // ------------------------------------------
+ assign request = valid;
+
+
+ altera_merlin_arbitrator
+ #(
+ .NUM_REQUESTERS(NUM_INPUTS),
+ .SCHEME ("no-arb"),
+ .PIPELINE (0)
+ ) arb (
+ .clk (clk),
+ .reset (reset),
+ .request (request),
+ .grant (next_grant),
+ .save_top_priority (src_valid),
+ .increment_top_priority (update_grant)
+ );
+
+ // ------------------------------------------
+ // ------------------------------------------
+ // Mux
+ //
+ // Implemented as a sum of products.
+ // ------------------------------------------
+ // ------------------------------------------
+
+ assign sink0_ready = src_ready && grant[0];
+ assign sink1_ready = src_ready && grant[1];
+ assign sink2_ready = src_ready && grant[2];
+ assign sink3_ready = src_ready && grant[3];
+ assign sink4_ready = src_ready && grant[4];
+ assign sink5_ready = src_ready && grant[5];
+ assign sink6_ready = src_ready && grant[6];
+
+ assign src_valid = |(grant & valid);
+
+ always @* begin
+ src_payload =
+ sink0_payload & {PAYLOAD_W {grant[0]} } |
+ sink1_payload & {PAYLOAD_W {grant[1]} } |
+ sink2_payload & {PAYLOAD_W {grant[2]} } |
+ sink3_payload & {PAYLOAD_W {grant[3]} } |
+ sink4_payload & {PAYLOAD_W {grant[4]} } |
+ sink5_payload & {PAYLOAD_W {grant[5]} } |
+ sink6_payload & {PAYLOAD_W {grant[6]} };
+ end
+
+ // ------------------------------------------
+ // Mux Payload Mapping
+ // ------------------------------------------
+
+ assign sink0_payload = {sink0_channel,sink0_data,
+ sink0_startofpacket,sink0_endofpacket};
+ assign sink1_payload = {sink1_channel,sink1_data,
+ sink1_startofpacket,sink1_endofpacket};
+ assign sink2_payload = {sink2_channel,sink2_data,
+ sink2_startofpacket,sink2_endofpacket};
+ assign sink3_payload = {sink3_channel,sink3_data,
+ sink3_startofpacket,sink3_endofpacket};
+ assign sink4_payload = {sink4_channel,sink4_data,
+ sink4_startofpacket,sink4_endofpacket};
+ assign sink5_payload = {sink5_channel,sink5_data,
+ sink5_startofpacket,sink5_endofpacket};
+ assign sink6_payload = {sink6_channel,sink6_data,
+ sink6_startofpacket,sink6_endofpacket};
+
+ assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
+
+endmodule
+
+
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rx_st_error_adapter_stat.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rx_st_error_adapter_stat.v
new file mode 100644
index 0000000000000000000000000000000000000000..89623e862993feeb8c9c859b6638681d48c3ac31
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rx_st_error_adapter_stat.v
@@ -0,0 +1,47 @@
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Error Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+module ip_stratixiv_mac_10g_rx_st_error_adapter_stat (
+
+ // Interface: clk
+ input clk,
+ // Interface: reset
+ input reset_n,
+ // Interface: in
+ input in_valid,
+ input [39: 0] in_data,
+ input [ 4: 0] in_error,
+ // Interface: out
+ output reg out_valid,
+ output reg [39: 0] out_data,
+ output reg [ 6: 0] out_error
+);
+
+
+
+ // ---------------------------------------------------------------------
+ //| Pass-through Mapping
+ // ---------------------------------------------------------------------
+ always @* begin
+ out_valid = in_valid;
+ out_data = in_data;
+
+ end
+
+ // ---------------------------------------------------------------------
+ //| Error Mapping
+ // ---------------------------------------------------------------------
+ always @* begin
+ out_error = 0;
+
+ out_error[0] = in_error[2]; // undersize
+ out_error[1] = in_error[3]; // oversize
+ out_error[2] = in_error[4]; // payload_length
+ out_error[3] = in_error[1]; // crc
+ out_error[6] = in_error[0]; // phy
+
+
+ end
+endmodule
\ No newline at end of file
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rx_st_timing_adapter_frame_status_in.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rx_st_timing_adapter_frame_status_in.v
new file mode 100644
index 0000000000000000000000000000000000000000..8647cfe86e565c71962285bc245f62845246c58c
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rx_st_timing_adapter_frame_status_in.v
@@ -0,0 +1,69 @@
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Timing Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+module ip_stratixiv_mac_10g_rx_st_timing_adapter_frame_status_in (
+
+ // Interface: clk
+ input clk,
+ // Interface: reset
+ input reset_n,
+ // Interface: in
+ input in_valid,
+ input [63: 0] in_data,
+ input in_error,
+ input in_startofpacket,
+ input in_endofpacket,
+ input [ 2: 0] in_empty,
+ // Interface: out
+ output reg out_valid,
+ output reg [63: 0] out_data,
+ output reg out_error,
+ output reg out_startofpacket,
+ output reg out_endofpacket,
+ output reg [ 2: 0] out_empty,
+ input out_ready
+);
+
+
+
+
+ // ---------------------------------------------------------------------
+ //| Signal Declarations
+ // ---------------------------------------------------------------------
+
+ reg [69: 0] in_payload;
+ reg [69: 0] out_payload;
+ reg [ 0: 0] ready;
+ reg in_ready;
+ // synthesis translate_off
+ always @(negedge in_ready) begin
+ $display("%m: The downstream component is backpressuring by deasserting ready, but the upstream component can't be backpressured.");
+ end
+ // synthesis translate_on
+
+
+ // ---------------------------------------------------------------------
+ //| Payload Mapping
+ // ---------------------------------------------------------------------
+ always @* begin
+ in_payload = {in_data,in_error,in_startofpacket,in_endofpacket,in_empty};
+ {out_data,out_error,out_startofpacket,out_endofpacket,out_empty} = out_payload;
+ end
+
+ // ---------------------------------------------------------------------
+ //| Ready & valid signals.
+ // ---------------------------------------------------------------------
+ always @* begin
+ ready[0] = out_ready;
+ out_valid = in_valid;
+ out_payload = in_payload;
+ in_ready = ready[0];
+ end
+
+
+
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rx_st_timing_adapter_interface_conversion.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rx_st_timing_adapter_interface_conversion.v
new file mode 100644
index 0000000000000000000000000000000000000000..340a9fd05ec90626737e56bf1f50b7803d1b24ca
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rx_st_timing_adapter_interface_conversion.v
@@ -0,0 +1,70 @@
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Timing Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+module ip_stratixiv_mac_10g_rx_st_timing_adapter_interface_conversion (
+
+ // Interface: clk
+ input clk,
+ // Interface: reset
+ input reset_n,
+ // Interface: in
+ input [71: 0] in_data,
+ // Interface: out
+ output reg [71: 0] out_data,
+ input out_ready,
+ output reg out_valid
+);
+
+
+
+
+ // ---------------------------------------------------------------------
+ //| Signal Declarations
+ // ---------------------------------------------------------------------
+
+ reg [71: 0] in_payload;
+ reg [71: 0] out_payload;
+ reg [ 0: 0] ready;
+ reg in_ready;
+ // synthesis translate_off
+ always @(negedge in_ready) begin
+ $display("%m: The downstream component is backpressuring by deasserting ready, but the upstream component can't be backpressured.");
+ end
+ // synthesis translate_on
+ reg in_valid;
+ reg [ 0: 0] valid_vector;
+
+
+ // ---------------------------------------------------------------------
+ //| Payload Mapping
+ // ---------------------------------------------------------------------
+ always @* begin
+ in_payload = {in_data};
+ {out_data} = out_payload;
+ end
+
+ // ---------------------------------------------------------------------
+ //| Ready & valid signals.
+ // ---------------------------------------------------------------------
+ always @* begin
+ ready[0] = out_ready;
+ out_valid = in_valid;
+ out_payload = in_payload;
+ in_ready = ready[0];
+ end
+
+
+
+ // ---------------------------------------------------------------------
+ //| Input Valid Generation
+ // ---------------------------------------------------------------------
+ always @* begin
+ valid_vector[0] = in_ready;
+ in_valid = valid_vector[0];
+ end
+
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rx_st_timing_adapter_lane_decoder.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rx_st_timing_adapter_lane_decoder.v
new file mode 100644
index 0000000000000000000000000000000000000000..49c473da29b0b3cd5a246a36e4f2436777c0fbf8
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rx_st_timing_adapter_lane_decoder.v
@@ -0,0 +1,61 @@
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Timing Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+module ip_stratixiv_mac_10g_rx_st_timing_adapter_lane_decoder (
+
+ // Interface: clk
+ input clk,
+ // Interface: reset
+ input reset_n,
+ // Interface: in
+ output reg in_ready,
+ input in_valid,
+ input [71: 0] in_data,
+ // Interface: out
+ output reg [71: 0] out_data
+);
+
+
+
+
+ // ---------------------------------------------------------------------
+ //| Signal Declarations
+ // ---------------------------------------------------------------------
+
+ reg [71: 0] in_payload;
+ reg [71: 0] out_payload;
+ reg [ 0: 0] ready;
+ reg out_ready = 1;
+ reg out_valid;
+ // synthesis translate_off
+ always @(negedge out_valid) begin
+ $display("%m: The downstream component expects valid data, but the upstream component cannot provide it.");
+ end
+ // synthesis translate_on
+
+
+ // ---------------------------------------------------------------------
+ //| Payload Mapping
+ // ---------------------------------------------------------------------
+ always @* begin
+ in_payload = {in_data};
+ {out_data} = out_payload;
+ end
+
+ // ---------------------------------------------------------------------
+ //| Ready & valid signals.
+ // ---------------------------------------------------------------------
+ always @* begin
+ ready[0] = out_ready;
+ out_valid = in_valid;
+ out_payload = in_payload;
+ in_ready = ready[0];
+ end
+
+
+
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rx_timing_adapter_frame_status_out_frame_decoder.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rx_timing_adapter_frame_status_out_frame_decoder.v
new file mode 100644
index 0000000000000000000000000000000000000000..861da7ae39e4b97540c66c4f8a36d77353962419
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rx_timing_adapter_frame_status_out_frame_decoder.v
@@ -0,0 +1,64 @@
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Timing Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+module ip_stratixiv_mac_10g_rx_timing_adapter_frame_status_out_frame_decoder (
+
+ // Interface: clk
+ input clk,
+ // Interface: reset
+ input reset_n,
+ // Interface: in
+ output reg in_ready,
+ input in_valid,
+ input [63: 0] in_data,
+ input in_error,
+ input in_startofpacket,
+ input in_endofpacket,
+ input [ 2: 0] in_empty,
+ // Interface: out
+ output reg out_valid,
+ output reg [63: 0] out_data,
+ output reg out_error,
+ output reg out_startofpacket,
+ output reg out_endofpacket,
+ output reg [ 2: 0] out_empty
+);
+
+
+
+
+ // ---------------------------------------------------------------------
+ //| Signal Declarations
+ // ---------------------------------------------------------------------
+
+ reg [69: 0] in_payload;
+ reg [69: 0] out_payload;
+ reg [ 0: 0] ready;
+ reg out_ready = 1;
+
+
+ // ---------------------------------------------------------------------
+ //| Payload Mapping
+ // ---------------------------------------------------------------------
+ always @* begin
+ in_payload = {in_data,in_error,in_startofpacket,in_endofpacket,in_empty};
+ {out_data,out_error,out_startofpacket,out_endofpacket,out_empty} = out_payload;
+ end
+
+ // ---------------------------------------------------------------------
+ //| Ready & valid signals.
+ // ---------------------------------------------------------------------
+ always @* begin
+ ready[0] = out_ready;
+ out_valid = in_valid;
+ out_payload = in_payload;
+ in_ready = ready[0];
+ end
+
+
+
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_rx.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_rx.v
new file mode 100644
index 0000000000000000000000000000000000000000..5520cf9511a317ea95f776785f1201e1445c51f9
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_rx.v
@@ -0,0 +1,61 @@
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Timing Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+module ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_rx (
+
+ // Interface: clk
+ input clk,
+ // Interface: reset
+ input reset_n,
+ // Interface: in
+ input in_valid,
+ input [15: 0] in_data,
+ // Interface: out
+ output reg out_valid,
+ output reg [15: 0] out_data,
+ input out_ready
+);
+
+
+
+
+ // ---------------------------------------------------------------------
+ //| Signal Declarations
+ // ---------------------------------------------------------------------
+
+ reg [15: 0] in_payload;
+ reg [15: 0] out_payload;
+ reg [ 0: 0] ready;
+ reg in_ready;
+ // synthesis translate_off
+ always @(negedge in_ready) begin
+ $display("%m: The downstream component is backpressuring by deasserting ready, but the upstream component can't be backpressured.");
+ end
+ // synthesis translate_on
+
+
+ // ---------------------------------------------------------------------
+ //| Payload Mapping
+ // ---------------------------------------------------------------------
+ always @* begin
+ in_payload = {in_data};
+ {out_data} = out_payload;
+ end
+
+ // ---------------------------------------------------------------------
+ //| Ready & valid signals.
+ // ---------------------------------------------------------------------
+ always @* begin
+ ready[0] = out_ready;
+ out_valid = in_valid;
+ out_payload = in_payload;
+ in_ready = ready[0];
+ end
+
+
+
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_tx.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_tx.v
new file mode 100644
index 0000000000000000000000000000000000000000..ab9a0efccb57bc0933d334f336e49e7b31e8e15a
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_tx.v
@@ -0,0 +1,56 @@
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Timing Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+module ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_tx (
+
+ // Interface: clk
+ input clk,
+ // Interface: reset
+ input reset_n,
+ // Interface: in
+ output reg in_ready,
+ input in_valid,
+ input [15: 0] in_data,
+ // Interface: out
+ output reg out_valid,
+ output reg [15: 0] out_data
+);
+
+
+
+
+ // ---------------------------------------------------------------------
+ //| Signal Declarations
+ // ---------------------------------------------------------------------
+
+ reg [15: 0] in_payload;
+ reg [15: 0] out_payload;
+ reg [ 0: 0] ready;
+ reg out_ready = 1;
+
+
+ // ---------------------------------------------------------------------
+ //| Payload Mapping
+ // ---------------------------------------------------------------------
+ always @* begin
+ in_payload = {in_data};
+ {out_data} = out_payload;
+ end
+
+ // ---------------------------------------------------------------------
+ //| Ready & valid signals.
+ // ---------------------------------------------------------------------
+ always @* begin
+ ready[0] = out_ready;
+ out_valid = in_valid;
+ out_payload = in_payload;
+ in_ready = ready[0];
+ end
+
+
+
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_tx_st_error_adapter_stat.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_tx_st_error_adapter_stat.v
new file mode 100644
index 0000000000000000000000000000000000000000..bfae38bf162e5e330ed274bfdfe51771998946c6
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_tx_st_error_adapter_stat.v
@@ -0,0 +1,48 @@
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Error Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+module ip_stratixiv_mac_10g_tx_st_error_adapter_stat (
+
+ // Interface: clk
+ input clk,
+ // Interface: reset
+ input reset_n,
+ // Interface: in
+ input in_valid,
+ input [39: 0] in_data,
+ input [ 5: 0] in_error,
+ // Interface: out
+ output reg out_valid,
+ output reg [39: 0] out_data,
+ output reg [ 6: 0] out_error
+);
+
+
+
+ // ---------------------------------------------------------------------
+ //| Pass-through Mapping
+ // ---------------------------------------------------------------------
+ always @* begin
+ out_valid = in_valid;
+ out_data = in_data;
+
+ end
+
+ // ---------------------------------------------------------------------
+ //| Error Mapping
+ // ---------------------------------------------------------------------
+ always @* begin
+ out_error = 0;
+
+ out_error[0] = in_error[3]; // undersize
+ out_error[1] = in_error[4]; // oversize
+ out_error[2] = in_error[5]; // payload_length
+ out_error[3] = in_error[2]; // crc
+ out_error[4] = in_error[1]; // underflow
+ out_error[5] = in_error[0]; // user
+
+
+ end
+endmodule
\ No newline at end of file
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_tx_st_mux_flow_control_user_frame.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_tx_st_mux_flow_control_user_frame.v
new file mode 100644
index 0000000000000000000000000000000000000000..7a54f0dba775b08b37bd15a9c021034fe5918333
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_tx_st_mux_flow_control_user_frame.v
@@ -0,0 +1,216 @@
+// --------------------------------------------------------------------------------
+//| Multiplexer
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+module ip_stratixiv_mac_10g_tx_st_mux_flow_control_user_frame (
+
+ // Interface: clk
+ input clk,
+ // Interface: reset
+ input reset_n,
+ // Interface: in0
+ input in0_valid,
+ output reg in0_ready,
+ input [63: 0] in0_data,
+ input [ 1: 0] in0_error,
+ input in0_startofpacket,
+ input in0_endofpacket,
+ input [ 2: 0] in0_empty,
+ // Interface: in1
+ input in1_valid,
+ output reg in1_ready,
+ input [63: 0] in1_data,
+ input [ 1: 0] in1_error,
+ input in1_startofpacket,
+ input in1_endofpacket,
+ input [ 2: 0] in1_empty,
+ // Interface: out
+ output reg out_channel,
+ output reg out_valid,
+ input out_ready,
+ output reg [63: 0] out_data,
+ output reg [ 1: 0] out_error,
+ output reg out_startofpacket,
+ output reg out_endofpacket,
+ output reg [ 2: 0] out_empty
+);
+
+ // ---------------------------------------------------------------------
+ //| Signal Declarations
+ // ---------------------------------------------------------------------
+ reg [70: 0] in0_payload;
+ reg [70: 0] in1_payload;
+
+ reg decision = 0;
+ reg select = 0;
+ reg selected_endofpacket = 0;
+ reg selected_valid;
+ wire out_valid_wire;
+ wire selected_ready;
+ reg [70: 0] selected_payload;
+ reg packet_in_progress;
+
+ wire out_select;
+ wire [70: 0] out_payload;
+
+ // ---------------------------------------------------------------------
+ //| Input Mapping
+ // ---------------------------------------------------------------------
+ always @* begin
+ in0_payload = {in0_data,in0_empty,in0_endofpacket,in0_error,in0_startofpacket};
+ in1_payload = {in1_data,in1_empty,in1_endofpacket,in1_error,in1_startofpacket};
+ end
+
+ // ---------------------------------------------------------------------
+ //| Scheduling Algorithm
+ // ---------------------------------------------------------------------
+ always @* begin
+
+ decision = 0;
+ case(select)
+ 0 : begin
+ if (in0_valid) decision = 0;
+ if (in1_valid) decision = 1;
+ end
+ 1 : begin
+ if (in1_valid) decision = 1;
+ if (in0_valid) decision = 0;
+ end
+ default : begin // Same as '0', should never get used.
+ if (in0_valid) decision = 0;
+ if (in1_valid) decision = 1;
+ end
+ endcase
+ end
+
+ // ---------------------------------------------------------------------
+ //| Capture Decision
+ // ---------------------------------------------------------------------
+ always @ (negedge reset_n, posedge clk) begin
+ if (!reset_n) begin
+ select <= 0;
+ packet_in_progress <= 0;
+ end else begin
+ if (!selected_valid && !packet_in_progress) begin
+ select <= decision;
+ end else begin
+ packet_in_progress <= 1;
+ end
+ if (selected_endofpacket && selected_valid && selected_ready) begin
+ select <= decision;
+ packet_in_progress <= 0;
+ end
+ end
+ end
+
+ // ---------------------------------------------------------------------
+ //| Mux
+ // ---------------------------------------------------------------------
+ always @* begin
+ case(select)
+ 0 : begin
+ selected_payload = in0_payload;
+ selected_valid = in0_valid;
+ selected_endofpacket = in0_endofpacket;
+ end
+ 1 : begin
+ selected_payload = in1_payload;
+ selected_valid = in1_valid;
+ selected_endofpacket = in1_endofpacket;
+ end
+ default : begin
+ selected_payload = in0_payload;
+ selected_valid = in0_valid;
+ selected_endofpacket = in0_endofpacket;
+ end
+ endcase
+
+ end
+
+ // ---------------------------------------------------------------------
+ //| Back Pressure
+ // ---------------------------------------------------------------------
+ always @* begin
+ in0_ready <= ~in0_valid ;
+ in1_ready <= ~in1_valid ;
+ case(select)
+ 0 : in0_ready <= selected_ready;
+ 1 : in1_ready <= selected_ready;
+ default : in0_ready <= selected_ready;
+ endcase
+ end
+
+ // ---------------------------------------------------------------------
+ //| output Pipeline
+ // ---------------------------------------------------------------------
+ ip_stratixiv_mac_10g_tx_st_mux_flow_control_user_frame_1stage_pipeline #( .PAYLOAD_WIDTH( 71 + 1 ) ) outpipe
+ ( .clk (clk ),
+ .reset_n (reset_n ),
+ .in_ready ( selected_ready ),
+ .in_valid ( selected_valid ),
+ .in_payload ({select,selected_payload}),
+ .out_ready(out_ready ),
+ .out_valid(out_valid_wire),
+ .out_payload({out_select,out_payload}) );
+
+ // ---------------------------------------------------------------------
+ //| Output Mapping
+ // ---------------------------------------------------------------------
+ always @* begin
+ out_valid = out_valid_wire;
+ out_channel = out_select;
+ {out_data,out_empty,out_endofpacket,out_error,out_startofpacket} = out_payload;
+ end
+
+
+endmodule
+
+// --------------------------------------------------------------------------------
+// | single buffered pipeline stage
+// --------------------------------------------------------------------------------
+module ip_stratixiv_mac_10g_tx_st_mux_flow_control_user_frame_1stage_pipeline
+#( parameter PAYLOAD_WIDTH = 8 )
+ ( input clk,
+ input reset_n,
+ output reg in_ready,
+ input in_valid,
+ input [PAYLOAD_WIDTH-1:0] in_payload,
+ input out_ready,
+ output reg out_valid,
+ output reg [PAYLOAD_WIDTH-1:0] out_payload
+ );
+
+ reg in_ready1;
+
+ always @* begin
+
+ in_ready = out_ready || ~out_valid;
+
+// in_ready = in_ready1;
+// if (!out_ready)
+// in_ready = 0;
+ end
+
+ always @ (negedge reset_n, posedge clk) begin
+ if (!reset_n) begin
+ in_ready1 <= 0;
+ out_valid <= 0;
+ out_payload <= 0;
+ end else begin
+ in_ready1 <= out_ready || !out_valid;
+
+ if (in_valid) begin
+ out_valid <= 1;
+ end else if (out_ready) begin
+ out_valid <= 0;
+ end
+
+ if(in_valid && in_ready) begin
+ out_payload <= in_payload;
+ end
+ end
+ end
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_tx_st_pause_ctrl_error_adapter.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_tx_st_pause_ctrl_error_adapter.v
new file mode 100644
index 0000000000000000000000000000000000000000..e59ebefc8cbd4a352dfb3c21aa3ab126bbc4c2c6
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_tx_st_pause_ctrl_error_adapter.v
@@ -0,0 +1,53 @@
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Error Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+module ip_stratixiv_mac_10g_tx_st_pause_ctrl_error_adapter (
+
+ // Interface: clk
+ input clk,
+ // Interface: reset
+ input reset_n,
+ // Interface: in
+ output reg in_ready,
+ input in_valid,
+ input [63: 0] in_data,
+ input [ 0: 0] in_error,
+ input in_startofpacket,
+ input in_endofpacket,
+ input [ 2: 0] in_empty,
+ // Interface: out
+ input out_ready,
+ output reg out_valid,
+ output reg [63: 0] out_data,
+ output reg [ 1: 0] out_error,
+ output reg out_startofpacket,
+ output reg out_endofpacket,
+ output reg [ 2: 0] out_empty
+);
+
+
+
+ // ---------------------------------------------------------------------
+ //| Pass-through Mapping
+ // ---------------------------------------------------------------------
+ always @* begin
+ in_ready = out_ready;
+ out_valid = in_valid;
+ out_data = in_data;
+ out_startofpacket = in_startofpacket;
+ out_endofpacket = in_endofpacket;
+ out_empty = in_empty;
+
+ end
+
+ // ---------------------------------------------------------------------
+ //| Error Mapping
+ // ---------------------------------------------------------------------
+ always @* begin
+ out_error = 0;
+
+ out_error = in_error;
+ end
+endmodule
\ No newline at end of file
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_tx_st_timing_adapter_frame_decoder.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_tx_st_timing_adapter_frame_decoder.v
new file mode 100644
index 0000000000000000000000000000000000000000..8679c00c1fcd068d609796db6bbea8cb0bf59028
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_tx_st_timing_adapter_frame_decoder.v
@@ -0,0 +1,64 @@
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Timing Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+module ip_stratixiv_mac_10g_tx_st_timing_adapter_frame_decoder (
+
+ // Interface: clk
+ input clk,
+ // Interface: reset
+ input reset_n,
+ // Interface: in
+ output reg in_ready,
+ input in_valid,
+ input [63: 0] in_data,
+ input [ 2: 0] in_error,
+ input in_startofpacket,
+ input in_endofpacket,
+ input [ 2: 0] in_empty,
+ // Interface: out
+ output reg out_valid,
+ output reg [63: 0] out_data,
+ output reg [ 2: 0] out_error,
+ output reg out_startofpacket,
+ output reg out_endofpacket,
+ output reg [ 2: 0] out_empty
+);
+
+
+
+
+ // ---------------------------------------------------------------------
+ //| Signal Declarations
+ // ---------------------------------------------------------------------
+
+ reg [71: 0] in_payload;
+ reg [71: 0] out_payload;
+ reg [ 0: 0] ready;
+ reg out_ready = 1;
+
+
+ // ---------------------------------------------------------------------
+ //| Payload Mapping
+ // ---------------------------------------------------------------------
+ always @* begin
+ in_payload = {in_data,in_error,in_startofpacket,in_endofpacket,in_empty};
+ {out_data,out_error,out_startofpacket,out_endofpacket,out_empty} = out_payload;
+ end
+
+ // ---------------------------------------------------------------------
+ //| Ready & valid signals.
+ // ---------------------------------------------------------------------
+ always @* begin
+ ready[0] = out_ready;
+ out_valid = in_valid;
+ out_payload = in_payload;
+ in_ready = ready[0];
+ end
+
+
+
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_in.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_in.v
new file mode 100644
index 0000000000000000000000000000000000000000..7445e9ed76d4e59de8a3c0d804bb837fe2887767
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_in.v
@@ -0,0 +1,63 @@
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Timing Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+module ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_in (
+
+ // Interface: clk
+ input clk,
+ // Interface: reset
+ input reset_n,
+ // Interface: in
+ input in_valid,
+ input [39: 0] in_data,
+ input [ 6: 0] in_error,
+ // Interface: out
+ output reg out_valid,
+ output reg [39: 0] out_data,
+ output reg [ 6: 0] out_error,
+ input out_ready
+);
+
+
+
+
+ // ---------------------------------------------------------------------
+ //| Signal Declarations
+ // ---------------------------------------------------------------------
+
+ reg [46: 0] in_payload;
+ reg [46: 0] out_payload;
+ reg [ 0: 0] ready;
+ reg in_ready;
+ // synthesis translate_off
+ always @(negedge in_ready) begin
+ $display("%m: The downstream component is backpressuring by deasserting ready, but the upstream component can't be backpressured.");
+ end
+ // synthesis translate_on
+
+
+ // ---------------------------------------------------------------------
+ //| Payload Mapping
+ // ---------------------------------------------------------------------
+ always @* begin
+ in_payload = {in_data,in_error};
+ {out_data,out_error} = out_payload;
+ end
+
+ // ---------------------------------------------------------------------
+ //| Ready & valid signals.
+ // ---------------------------------------------------------------------
+ always @* begin
+ ready[0] = out_ready;
+ out_valid = in_valid;
+ out_payload = in_payload;
+ in_ready = ready[0];
+ end
+
+
+
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_output.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_output.v
new file mode 100644
index 0000000000000000000000000000000000000000..8a1726654b83b02ee270d90e11d21e820c4c2a62
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_output.v
@@ -0,0 +1,58 @@
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Timing Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+module ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_output (
+
+ // Interface: clk
+ input clk,
+ // Interface: reset
+ input reset_n,
+ // Interface: in
+ output reg in_ready,
+ input in_valid,
+ input [39: 0] in_data,
+ input [ 6: 0] in_error,
+ // Interface: out
+ output reg out_valid,
+ output reg [39: 0] out_data,
+ output reg [ 6: 0] out_error
+);
+
+
+
+
+ // ---------------------------------------------------------------------
+ //| Signal Declarations
+ // ---------------------------------------------------------------------
+
+ reg [46: 0] in_payload;
+ reg [46: 0] out_payload;
+ reg [ 0: 0] ready;
+ reg out_ready = 1;
+
+
+ // ---------------------------------------------------------------------
+ //| Payload Mapping
+ // ---------------------------------------------------------------------
+ always @* begin
+ in_payload = {in_data,in_error};
+ {out_data,out_error} = out_payload;
+ end
+
+ // ---------------------------------------------------------------------
+ //| Ready & valid signals.
+ // ---------------------------------------------------------------------
+ always @* begin
+ ready[0] = out_ready;
+ out_valid = in_valid;
+ out_payload = in_payload;
+ in_ready = ready[0];
+ end
+
+
+
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_export.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_export.v
new file mode 100644
index 0000000000000000000000000000000000000000..582ed5f02493be7e3c8fa7f6c0957be9e2ae0119
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_export.v
@@ -0,0 +1,61 @@
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Timing Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+module ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_export (
+
+ // Interface: clk
+ input clk,
+ // Interface: reset
+ input reset_n,
+ // Interface: in
+ output reg in_ready,
+ input in_valid,
+ input [ 1: 0] in_data,
+ // Interface: out
+ output reg [ 1: 0] out_data
+);
+
+
+
+
+ // ---------------------------------------------------------------------
+ //| Signal Declarations
+ // ---------------------------------------------------------------------
+
+ reg [ 1: 0] in_payload;
+ reg [ 1: 0] out_payload;
+ reg [ 0: 0] ready;
+ reg out_ready = 1;
+ reg out_valid;
+ // synthesis translate_off
+ always @(negedge out_valid) begin
+ $display("%m: The downstream component expects valid data, but the upstream component cannot provide it.");
+ end
+ // synthesis translate_on
+
+
+ // ---------------------------------------------------------------------
+ //| Payload Mapping
+ // ---------------------------------------------------------------------
+ always @* begin
+ in_payload = {in_data};
+ {out_data} = out_payload;
+ end
+
+ // ---------------------------------------------------------------------
+ //| Ready & valid signals.
+ // ---------------------------------------------------------------------
+ always @* begin
+ ready[0] = out_ready;
+ out_valid = in_valid;
+ out_payload = in_payload;
+ in_ready = ready[0];
+ end
+
+
+
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_rx.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_rx.v
new file mode 100644
index 0000000000000000000000000000000000000000..f1a3c3915ca65dab61e866acb699e1e35d540724
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g/ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_rx.v
@@ -0,0 +1,70 @@
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Timing Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+module ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_rx (
+
+ // Interface: clk
+ input clk,
+ // Interface: reset
+ input reset_n,
+ // Interface: in
+ input [ 1: 0] in_data,
+ // Interface: out
+ output reg [ 1: 0] out_data,
+ input out_ready,
+ output reg out_valid
+);
+
+
+
+
+ // ---------------------------------------------------------------------
+ //| Signal Declarations
+ // ---------------------------------------------------------------------
+
+ reg [ 1: 0] in_payload;
+ reg [ 1: 0] out_payload;
+ reg [ 0: 0] ready;
+ reg in_ready;
+ // synthesis translate_off
+ always @(negedge in_ready) begin
+ $display("%m: The downstream component is backpressuring by deasserting ready, but the upstream component can't be backpressured.");
+ end
+ // synthesis translate_on
+ reg in_valid;
+ reg [ 0: 0] valid_vector;
+
+
+ // ---------------------------------------------------------------------
+ //| Payload Mapping
+ // ---------------------------------------------------------------------
+ always @* begin
+ in_payload = {in_data};
+ {out_data} = out_payload;
+ end
+
+ // ---------------------------------------------------------------------
+ //| Ready & valid signals.
+ // ---------------------------------------------------------------------
+ always @* begin
+ ready[0] = out_ready;
+ out_valid = in_valid;
+ out_payload = in_payload;
+ in_ready = ready[0];
+ end
+
+
+
+ // ---------------------------------------------------------------------
+ //| Input Valid Generation
+ // ---------------------------------------------------------------------
+ always @* begin
+ valid_vector[0] = in_ready;
+ in_valid = valid_vector[0];
+ end
+
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_dc_fifo/altera_avalon_dc_fifo_0001.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_dc_fifo/altera_avalon_dc_fifo_0001.vho
new file mode 100644
index 0000000000000000000000000000000000000000..15f1731782a79cc3857db60c057cd3284b26b0f4
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_dc_fifo/altera_avalon_dc_fifo_0001.vho
@@ -0,0 +1,416 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+ LIBRARY altera_mf;
+ USE altera_mf.altera_mf_components.all;
+
+ LIBRARY sgate;
+ USE sgate.sgate_pack.all;
+
+--synthesis_resources = altera_std_synchronizer 10 altsyncram 1 lut 25 mux21 10 oper_add 2
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_avalon_dc_fifo_0001 IS
+ PORT
+ (
+ in_clk : IN STD_LOGIC;
+ in_data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+ in_ready : OUT STD_LOGIC;
+ in_reset_n : IN STD_LOGIC;
+ in_valid : IN STD_LOGIC;
+ out_clk : IN STD_LOGIC;
+ out_data : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+ out_ready : IN STD_LOGIC;
+ out_reset_n : IN STD_LOGIC;
+ out_valid : OUT STD_LOGIC
+ );
+ END altera_avalon_dc_fifo_0001;
+
+ ARCHITECTURE RTL OF altera_avalon_dc_fifo_0001 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_0_u_444_dout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_1_u_443_dout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_2_u_442_dout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_3_u_441_dout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_4_u_440_dout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_0_u_466_dout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_1_u_465_dout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_2_u_464_dout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_3_u_463_dout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_4_u_462_dout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altsyncram_mem_409_address_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altsyncram_mem_409_address_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altsyncram_mem_409_data_a : STD_LOGIC_VECTOR (1 DOWNTO 0);
+ SIGNAL wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altsyncram_mem_409_q_b : STD_LOGIC_VECTOR (1 DOWNTO 0);
+ SIGNAL altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_payload_0_61q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_payload_1_116q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_valid_115q : STD_LOGIC := '0';
+ SIGNAL wire_ni_w83w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_0_60q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_1_44q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_2_43q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_3_42q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_4_41q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_gray_0_114q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_gray_1_94q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_gray_2_93q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_gray_3_92q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_gray_4_91q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_empty_65q : STD_LOGIC := '0';
+ SIGNAL wire_nlO_w28w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_full_70q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_0_40q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_1_39q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_2_38q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_3_37q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_4_36q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_gray_0_90q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_gray_1_74q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_gray_2_73q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_gray_3_72q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_gray_4_71q : STD_LOGIC := '0';
+ SIGNAL wire_nO_w1w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_mem_rd_ptr_0_58m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_mem_rd_ptr_1_57m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_mem_rd_ptr_2_56m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_mem_rd_ptr_3_55m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_in_wr_ptr_0_51m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_in_wr_ptr_1_50m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_in_wr_ptr_2_49m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_in_wr_ptr_3_48m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_in_wr_ptr_4_47m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_out_rd_ptr_4_54m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add0_46_a : STD_LOGIC_VECTOR (4 DOWNTO 0);
+ SIGNAL wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add0_46_b : STD_LOGIC_VECTOR (4 DOWNTO 0);
+ SIGNAL wire_gnd : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add0_46_o : STD_LOGIC_VECTOR (4 DOWNTO 0);
+ SIGNAL wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add1_53_a : STD_LOGIC_VECTOR (4 DOWNTO 0);
+ SIGNAL wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add1_53_b : STD_LOGIC_VECTOR (4 DOWNTO 0);
+ SIGNAL wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add1_53_o : STD_LOGIC_VECTOR (4 DOWNTO 0);
+ SIGNAL s_wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_empty_320_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_internal_out_ready_109_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_in_wr_ptr_45_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_out_rd_ptr_52_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ BEGIN
+
+ wire_gnd <= '0';
+ in_ready <= wire_nO_w1w(0);
+ out_data <= ( altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_payload_1_116q & altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_payload_0_61q);
+ out_valid <= altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_valid_115q;
+ s_wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_empty_320_dataout <= (((((NOT (wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_mem_rd_ptr_0_58m_dataout XOR ((((wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_4_u_462_dout XOR wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_0_u_466_dout) XOR wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_3_u_463_dout) XOR wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_2_u_464_dout) XOR wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_1_u_465_dout))) AND (NOT (wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_mem_rd_ptr_1_57m_dataout XOR (((wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_4_u_462_dout XOR wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_1_u_465_dout) XOR wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_3_u_463_dout) XOR wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_2_u_464_dout)))) AND (NOT (wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_mem_rd_ptr_2_56m_dataout
+ XOR ((wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_4_u_462_dout XOR wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_2_u_464_dout) XOR wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_3_u_463_dout)))) AND (NOT (wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_mem_rd_ptr_3_55m_dataout XOR (wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_4_u_462_dout XOR wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_3_u_463_dout)))) AND (NOT (wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_out_rd_ptr_4_54m_dataout XOR wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_4_u_462_dout)));
+ s_wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_internal_out_ready_109_dataout <= (out_ready OR wire_ni_w83w(0));
+ s_wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_in_wr_ptr_45_dataout <= (in_valid AND wire_nO_w1w(0));
+ s_wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_out_rd_ptr_52_dataout <= (wire_nlO_w28w(0) AND s_wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_internal_out_ready_109_dataout);
+ s_wire_vcc <= '1';
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_0_u_444 : altera_std_synchronizer
+ GENERIC MAP (
+ depth => 2
+ )
+ PORT MAP (
+ clk => in_clk,
+ din => altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_gray_0_114q,
+ dout => wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_0_u_444_dout,
+ reset_n => in_reset_n
+ );
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_1_u_443 : altera_std_synchronizer
+ GENERIC MAP (
+ depth => 2
+ )
+ PORT MAP (
+ clk => in_clk,
+ din => altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_gray_1_94q,
+ dout => wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_1_u_443_dout,
+ reset_n => in_reset_n
+ );
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_2_u_442 : altera_std_synchronizer
+ GENERIC MAP (
+ depth => 2
+ )
+ PORT MAP (
+ clk => in_clk,
+ din => altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_gray_2_93q,
+ dout => wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_2_u_442_dout,
+ reset_n => in_reset_n
+ );
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_3_u_441 : altera_std_synchronizer
+ GENERIC MAP (
+ depth => 2
+ )
+ PORT MAP (
+ clk => in_clk,
+ din => altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_gray_3_92q,
+ dout => wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_3_u_441_dout,
+ reset_n => in_reset_n
+ );
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_4_u_440 : altera_std_synchronizer
+ GENERIC MAP (
+ depth => 2
+ )
+ PORT MAP (
+ clk => in_clk,
+ din => altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_gray_4_91q,
+ dout => wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_4_u_440_dout,
+ reset_n => in_reset_n
+ );
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_0_u_466 : altera_std_synchronizer
+ GENERIC MAP (
+ depth => 2
+ )
+ PORT MAP (
+ clk => out_clk,
+ din => altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_gray_0_90q,
+ dout => wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_0_u_466_dout,
+ reset_n => out_reset_n
+ );
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_1_u_465 : altera_std_synchronizer
+ GENERIC MAP (
+ depth => 2
+ )
+ PORT MAP (
+ clk => out_clk,
+ din => altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_gray_1_74q,
+ dout => wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_1_u_465_dout,
+ reset_n => out_reset_n
+ );
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_2_u_464 : altera_std_synchronizer
+ GENERIC MAP (
+ depth => 2
+ )
+ PORT MAP (
+ clk => out_clk,
+ din => altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_gray_2_73q,
+ dout => wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_2_u_464_dout,
+ reset_n => out_reset_n
+ );
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_3_u_463 : altera_std_synchronizer
+ GENERIC MAP (
+ depth => 2
+ )
+ PORT MAP (
+ clk => out_clk,
+ din => altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_gray_3_72q,
+ dout => wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_3_u_463_dout,
+ reset_n => out_reset_n
+ );
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_4_u_462 : altera_std_synchronizer
+ GENERIC MAP (
+ depth => 2
+ )
+ PORT MAP (
+ clk => out_clk,
+ din => altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_gray_4_71q,
+ dout => wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_4_u_462_dout,
+ reset_n => out_reset_n
+ );
+ wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altsyncram_mem_409_address_a <= ( altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_3_37q & altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_2_38q & altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_1_39q & altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_0_40q);
+ wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altsyncram_mem_409_address_b <= ( wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_mem_rd_ptr_3_55m_dataout & wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_mem_rd_ptr_2_56m_dataout & wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_mem_rd_ptr_1_57m_dataout & wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_mem_rd_ptr_0_58m_dataout);
+ wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altsyncram_mem_409_data_a <= ( in_data(1 DOWNTO 0));
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altsyncram_mem_409 : altsyncram
+ GENERIC MAP (
+ ADDRESS_ACLR_A => "NONE",
+ ADDRESS_ACLR_B => "NONE",
+ ADDRESS_REG_B => "CLOCK1",
+ BYTE_SIZE => 8,
+ BYTEENA_ACLR_A => "NONE",
+ BYTEENA_ACLR_B => "NONE",
+ BYTEENA_REG_B => "CLOCK1",
+ CLOCK_ENABLE_CORE_A => "USE_INPUT_CLKEN",
+ CLOCK_ENABLE_CORE_B => "USE_INPUT_CLKEN",
+ CLOCK_ENABLE_INPUT_A => "NORMAL",
+ CLOCK_ENABLE_INPUT_B => "NORMAL",
+ CLOCK_ENABLE_OUTPUT_A => "NORMAL",
+ CLOCK_ENABLE_OUTPUT_B => "NORMAL",
+ ENABLE_ECC => "FALSE",
+ INDATA_ACLR_A => "NONE",
+ INDATA_ACLR_B => "NONE",
+ INDATA_REG_B => "CLOCK1",
+ INIT_FILE_LAYOUT => "PORT_A",
+ INTENDED_DEVICE_FAMILY => "Stratix IV",
+ NUMWORDS_A => 16,
+ NUMWORDS_B => 16,
+ OPERATION_MODE => "DUAL_PORT",
+ OUTDATA_ACLR_A => "NONE",
+ OUTDATA_ACLR_B => "NONE",
+ OUTDATA_REG_A => "UNREGISTERED",
+ OUTDATA_REG_B => "UNREGISTERED",
+ RAM_BLOCK_TYPE => "AUTO",
+ RDCONTROL_ACLR_B => "NONE",
+ RDCONTROL_REG_B => "CLOCK1",
+ READ_DURING_WRITE_MODE_MIXED_PORTS => "DONT_CARE",
+ READ_DURING_WRITE_MODE_PORT_A => "NEW_DATA_NO_NBE_READ",
+ READ_DURING_WRITE_MODE_PORT_B => "NEW_DATA_NO_NBE_READ",
+ WIDTH_A => 2,
+ WIDTH_B => 2,
+ WIDTH_BYTEENA_A => 1,
+ WIDTH_BYTEENA_B => 1,
+ WIDTH_ECCSTATUS => 3,
+ WIDTHAD_A => 4,
+ WIDTHAD_B => 4,
+ WRCONTROL_ACLR_A => "NONE",
+ WRCONTROL_ACLR_B => "NONE",
+ WRCONTROL_WRADDRESS_REG_B => "CLOCK1",
+ lpm_hint => "WIDTH_BYTEENA=1"
+ )
+ PORT MAP (
+ address_a => wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altsyncram_mem_409_address_a,
+ address_b => wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altsyncram_mem_409_address_b,
+ clock0 => in_clk,
+ clock1 => out_clk,
+ data_a => wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altsyncram_mem_409_data_a,
+ q_b => wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altsyncram_mem_409_q_b,
+ wren_a => s_wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_in_wr_ptr_45_dataout
+ );
+ PROCESS (out_clk, out_reset_n)
+ BEGIN
+ IF (out_reset_n = '0') THEN
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_payload_0_61q <= '0';
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_payload_1_116q <= '0';
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_valid_115q <= '0';
+ ELSIF (out_clk = '1' AND out_clk'event) THEN
+ IF (s_wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_internal_out_ready_109_dataout = '1') THEN
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_payload_0_61q <= wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altsyncram_mem_409_q_b(0);
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_payload_1_116q <= wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altsyncram_mem_409_q_b(1);
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_valid_115q <= wire_nlO_w28w(0);
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_ni_w83w(0) <= NOT altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_valid_115q;
+ PROCESS (out_clk, out_reset_n)
+ BEGIN
+ IF (out_reset_n = '0') THEN
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_0_60q <= '0';
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_1_44q <= '0';
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_2_43q <= '0';
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_3_42q <= '0';
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_4_41q <= '0';
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_gray_0_114q <= '0';
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_gray_1_94q <= '0';
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_gray_2_93q <= '0';
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_gray_3_92q <= '0';
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_gray_4_91q <= '0';
+ ELSIF (out_clk = '1' AND out_clk'event) THEN
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_0_60q <= wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_mem_rd_ptr_0_58m_dataout;
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_1_44q <= wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_mem_rd_ptr_1_57m_dataout;
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_2_43q <= wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_mem_rd_ptr_2_56m_dataout;
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_3_42q <= wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_mem_rd_ptr_3_55m_dataout;
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_4_41q <= wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_out_rd_ptr_4_54m_dataout;
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_gray_0_114q <= (altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_1_44q XOR altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_0_60q);
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_gray_1_94q <= (altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_2_43q XOR altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_1_44q);
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_gray_2_93q <= (altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_3_42q XOR altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_2_43q);
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_gray_3_92q <= (altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_4_41q XOR altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_3_42q);
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_gray_4_91q <= altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_4_41q;
+ END IF;
+ END PROCESS;
+ PROCESS (out_clk, out_reset_n)
+ BEGIN
+ IF (out_reset_n = '0') THEN
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_empty_65q <= '1';
+ ELSIF (out_clk = '1' AND out_clk'event) THEN
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_empty_65q <= s_wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_empty_320_dataout;
+ END IF;
+ if (now = 0 ns) then
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_empty_65q <= '1' after 1 ps;
+ end if;
+ END PROCESS;
+ wire_nlO_w28w(0) <= NOT altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_empty_65q;
+ PROCESS (in_clk, in_reset_n)
+ BEGIN
+ IF (in_reset_n = '0') THEN
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_full_70q <= '0';
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_0_40q <= '0';
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_1_39q <= '0';
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_2_38q <= '0';
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_3_37q <= '0';
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_4_36q <= '0';
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_gray_0_90q <= '0';
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_gray_1_74q <= '0';
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_gray_2_73q <= '0';
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_gray_3_72q <= '0';
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_gray_4_71q <= '0';
+ ELSIF (in_clk = '1' AND in_clk'event) THEN
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_full_70q <= ((wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_in_wr_ptr_4_47m_dataout XOR wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_4_u_440_dout) AND ((((NOT (wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_in_wr_ptr_0_51m_dataout XOR ((((wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_4_u_440_dout XOR wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_0_u_444_dout) XOR wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_3_u_441_dout) XOR wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_2_u_442_dout) XOR wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_1_u_443_dout))) AND (NOT (wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_in_wr_ptr_1_50m_dataout XOR (((wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_4_u_440_dout XOR wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_1_u_443_dout) XOR wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_3_u_441_dout
+) XOR wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_2_u_442_dout)))) AND (NOT (wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_in_wr_ptr_2_49m_dataout XOR ((wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_4_u_440_dout XOR wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_2_u_442_dout) XOR wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_3_u_441_dout)))) AND (NOT (wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_in_wr_ptr_3_48m_dataout XOR (wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_4_u_440_dout XOR wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_3_u_441_dout)))));
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_0_40q <= wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_in_wr_ptr_0_51m_dataout;
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_1_39q <= wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_in_wr_ptr_1_50m_dataout;
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_2_38q <= wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_in_wr_ptr_2_49m_dataout;
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_3_37q <= wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_in_wr_ptr_3_48m_dataout;
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_4_36q <= wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_in_wr_ptr_4_47m_dataout;
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_gray_0_90q <= (altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_1_39q XOR altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_0_40q);
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_gray_1_74q <= (altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_2_38q XOR altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_1_39q);
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_gray_2_73q <= (altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_3_37q XOR altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_2_38q);
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_gray_3_72q <= (altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_4_36q XOR altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_3_37q);
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_gray_4_71q <= altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_4_36q;
+ END IF;
+ END PROCESS;
+ wire_nO_w1w(0) <= NOT altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_full_70q;
+ wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_mem_rd_ptr_0_58m_dataout <= wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add1_53_o(0) WHEN s_wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_out_rd_ptr_52_dataout = '1' ELSE altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_0_60q;
+ wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_mem_rd_ptr_1_57m_dataout <= wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add1_53_o(1) WHEN s_wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_out_rd_ptr_52_dataout = '1' ELSE altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_1_44q;
+ wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_mem_rd_ptr_2_56m_dataout <= wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add1_53_o(2) WHEN s_wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_out_rd_ptr_52_dataout = '1' ELSE altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_2_43q;
+ wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_mem_rd_ptr_3_55m_dataout <= wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add1_53_o(3) WHEN s_wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_out_rd_ptr_52_dataout = '1' ELSE altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_3_42q;
+ wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_in_wr_ptr_0_51m_dataout <= wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add0_46_o(0) WHEN s_wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_in_wr_ptr_45_dataout = '1' ELSE altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_0_40q;
+ wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_in_wr_ptr_1_50m_dataout <= wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add0_46_o(1) WHEN s_wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_in_wr_ptr_45_dataout = '1' ELSE altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_1_39q;
+ wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_in_wr_ptr_2_49m_dataout <= wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add0_46_o(2) WHEN s_wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_in_wr_ptr_45_dataout = '1' ELSE altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_2_38q;
+ wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_in_wr_ptr_3_48m_dataout <= wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add0_46_o(3) WHEN s_wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_in_wr_ptr_45_dataout = '1' ELSE altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_3_37q;
+ wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_in_wr_ptr_4_47m_dataout <= wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add0_46_o(4) WHEN s_wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_in_wr_ptr_45_dataout = '1' ELSE altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_4_36q;
+ wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_out_rd_ptr_4_54m_dataout <= wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add1_53_o(4) WHEN s_wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_next_out_rd_ptr_52_dataout = '1' ELSE altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_4_41q;
+ wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add0_46_a <= ( altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_4_36q & altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_3_37q & altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_2_38q & altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_1_39q & altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_in_wr_ptr_0_40q);
+ wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add0_46_b <= ( "0" & "0" & "0" & "0" & "1");
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add0_46 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 5,
+ width_b => 5,
+ width_o => 5
+ )
+ PORT MAP (
+ a => wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add0_46_a,
+ b => wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add0_46_b,
+ cin => wire_gnd,
+ o => wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add0_46_o
+ );
+ wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add1_53_a <= ( altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_4_41q & altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_3_42q & altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_2_43q & altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_1_44q & altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_out_rd_ptr_0_60q);
+ wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add1_53_b <= ( "0" & "0" & "0" & "0" & "1");
+ altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add1_53 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 5,
+ width_b => 5,
+ width_o => 5
+ )
+ PORT MAP (
+ a => wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add1_53_a,
+ b => wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add1_53_b,
+ cin => wire_gnd,
+ o => wire_altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add1_53_o
+ );
+
+ END RTL; --altera_avalon_dc_fifo_0001
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_dc_fifo/altera_avalon_dc_fifo_0002.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_dc_fifo/altera_avalon_dc_fifo_0002.vho
new file mode 100644
index 0000000000000000000000000000000000000000..56b1fa5bf1ade0dbb9db060d3a51b16d8e74ebe4
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_dc_fifo/altera_avalon_dc_fifo_0002.vho
@@ -0,0 +1,458 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+ LIBRARY altera_mf;
+ USE altera_mf.altera_mf_components.all;
+
+ LIBRARY sgate;
+ USE sgate.sgate_pack.all;
+
+--synthesis_resources = altera_std_synchronizer 10 altsyncram 1 lut 39 mux21 10 oper_add 2
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_avalon_dc_fifo_0002 IS
+ PORT
+ (
+ in_clk : IN STD_LOGIC;
+ in_data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+ in_ready : OUT STD_LOGIC;
+ in_reset_n : IN STD_LOGIC;
+ in_valid : IN STD_LOGIC;
+ out_clk : IN STD_LOGIC;
+ out_data : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
+ out_ready : IN STD_LOGIC;
+ out_reset_n : IN STD_LOGIC;
+ out_valid : OUT STD_LOGIC
+ );
+ END altera_avalon_dc_fifo_0002;
+
+ ARCHITECTURE RTL OF altera_avalon_dc_fifo_0002 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_0_u_668_dout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_1_u_667_dout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_2_u_666_dout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_3_u_665_dout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_4_u_664_dout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_0_u_690_dout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_1_u_689_dout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_2_u_688_dout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_3_u_687_dout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_4_u_686_dout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altsyncram_mem_605_address_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altsyncram_mem_605_address_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altsyncram_mem_605_data_a : STD_LOGIC_VECTOR (15 DOWNTO 0);
+ SIGNAL wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altsyncram_mem_605_q_b : STD_LOGIC_VECTOR (15 DOWNTO 0);
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_0_133q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_10_210q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_11_209q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_12_208q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_13_207q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_14_206q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_15_205q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_1_219q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_2_218q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_3_217q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_4_216q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_5_215q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_6_214q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_7_213q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_8_212q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_9_211q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_valid_204q : STD_LOGIC := '0';
+ SIGNAL wire_ni_w97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_0_131q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_1_115q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_2_114q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_3_113q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_4_112q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_gray_0_202q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_gray_1_168q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_gray_2_167q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_gray_3_166q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_gray_4_165q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_empty_137q : STD_LOGIC := '0';
+ SIGNAL wire_nlO_w42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_full_142q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_0_110q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_1_109q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_2_108q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_3_107q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_4_106q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_gray_0_163q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_gray_1_147q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_gray_2_146q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_gray_3_145q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_gray_4_144q : STD_LOGIC := '0';
+ SIGNAL wire_nO_w1w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_mem_rd_ptr_0_129m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_mem_rd_ptr_1_128m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_mem_rd_ptr_2_127m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_mem_rd_ptr_3_126m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_in_wr_ptr_0_122m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_in_wr_ptr_1_121m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_in_wr_ptr_2_120m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_in_wr_ptr_3_119m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_in_wr_ptr_4_118m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_out_rd_ptr_4_125m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add0_117_a : STD_LOGIC_VECTOR (4 DOWNTO 0);
+ SIGNAL wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add0_117_b : STD_LOGIC_VECTOR (4 DOWNTO 0);
+ SIGNAL wire_gnd : STD_LOGIC;
+ SIGNAL wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add0_117_o : STD_LOGIC_VECTOR (4 DOWNTO 0);
+ SIGNAL wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add1_124_a : STD_LOGIC_VECTOR (4 DOWNTO 0);
+ SIGNAL wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add1_124_b : STD_LOGIC_VECTOR (4 DOWNTO 0);
+ SIGNAL wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add1_124_o : STD_LOGIC_VECTOR (4 DOWNTO 0);
+ SIGNAL s_wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_empty_460_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_internal_out_ready_183_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_in_wr_ptr_116_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_out_rd_ptr_123_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ BEGIN
+
+ wire_gnd <= '0';
+ in_ready <= wire_nO_w1w(0);
+ out_data <= ( altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_15_205q & altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_14_206q & altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_13_207q & altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_12_208q & altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_11_209q & altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_10_210q & altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_9_211q & altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_8_212q & altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_7_213q & altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_6_214q & altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_5_215q & altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_4_216q & altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_3_217q & altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_2_218q & altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_1_219q & altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_0_133q);
+ out_valid <= altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_valid_204q;
+ s_wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_empty_460_dataout <= (((((NOT (wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_mem_rd_ptr_0_129m_dataout XOR ((((wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_4_u_686_dout XOR wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_0_u_690_dout) XOR wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_3_u_687_dout) XOR wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_2_u_688_dout) XOR wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_1_u_689_dout))) AND (NOT (wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_mem_rd_ptr_1_128m_dataout XOR (((wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_4_u_686_dout XOR wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_1_u_689_dout) XOR wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_3_u_687_dout) XOR wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_2_u_688_dout)))) AND (NOT (wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_mem_rd_ptr_2_127m_dataout XOR ((wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_4_u_686_dout
+ XOR wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_2_u_688_dout) XOR wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_3_u_687_dout)))) AND (NOT (wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_mem_rd_ptr_3_126m_dataout XOR (wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_4_u_686_dout XOR wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_3_u_687_dout)))) AND (NOT (wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_out_rd_ptr_4_125m_dataout XOR wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_4_u_686_dout)));
+ s_wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_internal_out_ready_183_dataout <= (out_ready OR wire_ni_w97w(0));
+ s_wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_in_wr_ptr_116_dataout <= (in_valid AND wire_nO_w1w(0));
+ s_wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_out_rd_ptr_123_dataout <= (wire_nlO_w42w(0) AND s_wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_internal_out_ready_183_dataout);
+ s_wire_vcc <= '1';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_0_u_668 : altera_std_synchronizer
+ GENERIC MAP (
+ depth => 2
+ )
+ PORT MAP (
+ clk => in_clk,
+ din => altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_gray_0_202q,
+ dout => wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_0_u_668_dout,
+ reset_n => in_reset_n
+ );
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_1_u_667 : altera_std_synchronizer
+ GENERIC MAP (
+ depth => 2
+ )
+ PORT MAP (
+ clk => in_clk,
+ din => altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_gray_1_168q,
+ dout => wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_1_u_667_dout,
+ reset_n => in_reset_n
+ );
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_2_u_666 : altera_std_synchronizer
+ GENERIC MAP (
+ depth => 2
+ )
+ PORT MAP (
+ clk => in_clk,
+ din => altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_gray_2_167q,
+ dout => wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_2_u_666_dout,
+ reset_n => in_reset_n
+ );
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_3_u_665 : altera_std_synchronizer
+ GENERIC MAP (
+ depth => 2
+ )
+ PORT MAP (
+ clk => in_clk,
+ din => altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_gray_3_166q,
+ dout => wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_3_u_665_dout,
+ reset_n => in_reset_n
+ );
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_4_u_664 : altera_std_synchronizer
+ GENERIC MAP (
+ depth => 2
+ )
+ PORT MAP (
+ clk => in_clk,
+ din => altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_gray_4_165q,
+ dout => wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_4_u_664_dout,
+ reset_n => in_reset_n
+ );
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_0_u_690 : altera_std_synchronizer
+ GENERIC MAP (
+ depth => 2
+ )
+ PORT MAP (
+ clk => out_clk,
+ din => altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_gray_0_163q,
+ dout => wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_0_u_690_dout,
+ reset_n => out_reset_n
+ );
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_1_u_689 : altera_std_synchronizer
+ GENERIC MAP (
+ depth => 2
+ )
+ PORT MAP (
+ clk => out_clk,
+ din => altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_gray_1_147q,
+ dout => wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_1_u_689_dout,
+ reset_n => out_reset_n
+ );
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_2_u_688 : altera_std_synchronizer
+ GENERIC MAP (
+ depth => 2
+ )
+ PORT MAP (
+ clk => out_clk,
+ din => altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_gray_2_146q,
+ dout => wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_2_u_688_dout,
+ reset_n => out_reset_n
+ );
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_3_u_687 : altera_std_synchronizer
+ GENERIC MAP (
+ depth => 2
+ )
+ PORT MAP (
+ clk => out_clk,
+ din => altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_gray_3_145q,
+ dout => wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_3_u_687_dout,
+ reset_n => out_reset_n
+ );
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_4_u_686 : altera_std_synchronizer
+ GENERIC MAP (
+ depth => 2
+ )
+ PORT MAP (
+ clk => out_clk,
+ din => altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_gray_4_144q,
+ dout => wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_write_crosser_altera_std_synchronizer_sync_4_u_686_dout,
+ reset_n => out_reset_n
+ );
+ wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altsyncram_mem_605_address_a <= ( altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_3_107q & altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_2_108q & altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_1_109q & altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_0_110q);
+ wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altsyncram_mem_605_address_b <= ( wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_mem_rd_ptr_3_126m_dataout & wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_mem_rd_ptr_2_127m_dataout & wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_mem_rd_ptr_1_128m_dataout & wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_mem_rd_ptr_0_129m_dataout);
+ wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altsyncram_mem_605_data_a <= ( in_data(15 DOWNTO 0));
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altsyncram_mem_605 : altsyncram
+ GENERIC MAP (
+ ADDRESS_ACLR_A => "NONE",
+ ADDRESS_ACLR_B => "NONE",
+ ADDRESS_REG_B => "CLOCK1",
+ BYTE_SIZE => 8,
+ BYTEENA_ACLR_A => "NONE",
+ BYTEENA_ACLR_B => "NONE",
+ BYTEENA_REG_B => "CLOCK1",
+ CLOCK_ENABLE_CORE_A => "USE_INPUT_CLKEN",
+ CLOCK_ENABLE_CORE_B => "USE_INPUT_CLKEN",
+ CLOCK_ENABLE_INPUT_A => "NORMAL",
+ CLOCK_ENABLE_INPUT_B => "NORMAL",
+ CLOCK_ENABLE_OUTPUT_A => "NORMAL",
+ CLOCK_ENABLE_OUTPUT_B => "NORMAL",
+ ENABLE_ECC => "FALSE",
+ INDATA_ACLR_A => "NONE",
+ INDATA_ACLR_B => "NONE",
+ INDATA_REG_B => "CLOCK1",
+ INIT_FILE_LAYOUT => "PORT_A",
+ INTENDED_DEVICE_FAMILY => "Stratix IV",
+ NUMWORDS_A => 16,
+ NUMWORDS_B => 16,
+ OPERATION_MODE => "DUAL_PORT",
+ OUTDATA_ACLR_A => "NONE",
+ OUTDATA_ACLR_B => "NONE",
+ OUTDATA_REG_A => "UNREGISTERED",
+ OUTDATA_REG_B => "UNREGISTERED",
+ RAM_BLOCK_TYPE => "AUTO",
+ RDCONTROL_ACLR_B => "NONE",
+ RDCONTROL_REG_B => "CLOCK1",
+ READ_DURING_WRITE_MODE_MIXED_PORTS => "DONT_CARE",
+ READ_DURING_WRITE_MODE_PORT_A => "NEW_DATA_NO_NBE_READ",
+ READ_DURING_WRITE_MODE_PORT_B => "NEW_DATA_NO_NBE_READ",
+ WIDTH_A => 16,
+ WIDTH_B => 16,
+ WIDTH_BYTEENA_A => 1,
+ WIDTH_BYTEENA_B => 1,
+ WIDTH_ECCSTATUS => 3,
+ WIDTHAD_A => 4,
+ WIDTHAD_B => 4,
+ WRCONTROL_ACLR_A => "NONE",
+ WRCONTROL_ACLR_B => "NONE",
+ WRCONTROL_WRADDRESS_REG_B => "CLOCK1",
+ lpm_hint => "WIDTH_BYTEENA=1"
+ )
+ PORT MAP (
+ address_a => wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altsyncram_mem_605_address_a,
+ address_b => wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altsyncram_mem_605_address_b,
+ clock0 => in_clk,
+ clock1 => out_clk,
+ data_a => wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altsyncram_mem_605_data_a,
+ q_b => wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altsyncram_mem_605_q_b,
+ wren_a => s_wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_in_wr_ptr_116_dataout
+ );
+ PROCESS (out_clk, out_reset_n)
+ BEGIN
+ IF (out_reset_n = '0') THEN
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_0_133q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_10_210q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_11_209q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_12_208q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_13_207q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_14_206q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_15_205q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_1_219q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_2_218q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_3_217q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_4_216q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_5_215q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_6_214q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_7_213q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_8_212q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_9_211q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_valid_204q <= '0';
+ ELSIF (out_clk = '1' AND out_clk'event) THEN
+ IF (s_wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_internal_out_ready_183_dataout = '1') THEN
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_0_133q <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altsyncram_mem_605_q_b(0);
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_10_210q <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altsyncram_mem_605_q_b(10);
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_11_209q <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altsyncram_mem_605_q_b(11);
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_12_208q <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altsyncram_mem_605_q_b(12);
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_13_207q <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altsyncram_mem_605_q_b(13);
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_14_206q <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altsyncram_mem_605_q_b(14);
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_15_205q <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altsyncram_mem_605_q_b(15);
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_1_219q <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altsyncram_mem_605_q_b(1);
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_2_218q <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altsyncram_mem_605_q_b(2);
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_3_217q <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altsyncram_mem_605_q_b(3);
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_4_216q <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altsyncram_mem_605_q_b(4);
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_5_215q <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altsyncram_mem_605_q_b(5);
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_6_214q <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altsyncram_mem_605_q_b(6);
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_7_213q <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altsyncram_mem_605_q_b(7);
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_8_212q <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altsyncram_mem_605_q_b(8);
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_payload_9_211q <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altsyncram_mem_605_q_b(9);
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_valid_204q <= wire_nlO_w42w(0);
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_ni_w97w(0) <= NOT altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_valid_204q;
+ PROCESS (out_clk, out_reset_n)
+ BEGIN
+ IF (out_reset_n = '0') THEN
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_0_131q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_1_115q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_2_114q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_3_113q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_4_112q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_gray_0_202q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_gray_1_168q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_gray_2_167q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_gray_3_166q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_gray_4_165q <= '0';
+ ELSIF (out_clk = '1' AND out_clk'event) THEN
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_0_131q <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_mem_rd_ptr_0_129m_dataout;
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_1_115q <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_mem_rd_ptr_1_128m_dataout;
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_2_114q <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_mem_rd_ptr_2_127m_dataout;
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_3_113q <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_mem_rd_ptr_3_126m_dataout;
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_4_112q <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_out_rd_ptr_4_125m_dataout;
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_gray_0_202q <= (altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_1_115q XOR altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_0_131q);
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_gray_1_168q <= (altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_2_114q XOR altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_1_115q);
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_gray_2_167q <= (altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_3_113q XOR altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_2_114q);
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_gray_3_166q <= (altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_4_112q XOR altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_3_113q);
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_gray_4_165q <= altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_4_112q;
+ END IF;
+ END PROCESS;
+ PROCESS (out_clk, out_reset_n)
+ BEGIN
+ IF (out_reset_n = '0') THEN
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_empty_137q <= '1';
+ ELSIF (out_clk = '1' AND out_clk'event) THEN
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_empty_137q <= s_wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_empty_460_dataout;
+ END IF;
+ if (now = 0 ns) then
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_empty_137q <= '1' after 1 ps;
+ end if;
+ END PROCESS;
+ wire_nlO_w42w(0) <= NOT altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_empty_137q;
+ PROCESS (in_clk, in_reset_n)
+ BEGIN
+ IF (in_reset_n = '0') THEN
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_full_142q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_0_110q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_1_109q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_2_108q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_3_107q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_4_106q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_gray_0_163q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_gray_1_147q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_gray_2_146q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_gray_3_145q <= '0';
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_gray_4_144q <= '0';
+ ELSIF (in_clk = '1' AND in_clk'event) THEN
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_full_142q <= ((wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_in_wr_ptr_4_118m_dataout XOR wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_4_u_664_dout) AND ((((NOT (wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_in_wr_ptr_0_122m_dataout XOR ((((wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_4_u_664_dout XOR wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_0_u_668_dout) XOR wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_3_u_665_dout) XOR wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_2_u_666_dout) XOR wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_1_u_667_dout))) AND (NOT (wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_in_wr_ptr_1_121m_dataout XOR (((wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_4_u_664_dout XOR wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_1_u_667_dout) XOR wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_3_u_665_dout) XOR wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_2_u_666_dout
+)))) AND (NOT (wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_in_wr_ptr_2_120m_dataout XOR ((wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_4_u_664_dout XOR wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_2_u_666_dout) XOR wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_3_u_665_dout)))) AND (NOT (wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_in_wr_ptr_3_119m_dataout XOR (wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_4_u_664_dout XOR wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_altera_dcfifo_synchronizer_bundle_read_crosser_altera_std_synchronizer_sync_3_u_665_dout)))));
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_0_110q <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_in_wr_ptr_0_122m_dataout;
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_1_109q <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_in_wr_ptr_1_121m_dataout;
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_2_108q <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_in_wr_ptr_2_120m_dataout;
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_3_107q <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_in_wr_ptr_3_119m_dataout;
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_4_106q <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_in_wr_ptr_4_118m_dataout;
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_gray_0_163q <= (altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_1_109q XOR altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_0_110q);
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_gray_1_147q <= (altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_2_108q XOR altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_1_109q);
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_gray_2_146q <= (altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_3_107q XOR altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_2_108q);
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_gray_3_145q <= (altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_4_106q XOR altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_3_107q);
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_gray_4_144q <= altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_4_106q;
+ END IF;
+ END PROCESS;
+ wire_nO_w1w(0) <= NOT altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_full_142q;
+ wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_mem_rd_ptr_0_129m_dataout <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add1_124_o(0) WHEN s_wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_out_rd_ptr_123_dataout = '1' ELSE altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_0_131q;
+ wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_mem_rd_ptr_1_128m_dataout <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add1_124_o(1) WHEN s_wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_out_rd_ptr_123_dataout = '1' ELSE altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_1_115q;
+ wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_mem_rd_ptr_2_127m_dataout <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add1_124_o(2) WHEN s_wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_out_rd_ptr_123_dataout = '1' ELSE altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_2_114q;
+ wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_mem_rd_ptr_3_126m_dataout <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add1_124_o(3) WHEN s_wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_out_rd_ptr_123_dataout = '1' ELSE altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_3_113q;
+ wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_in_wr_ptr_0_122m_dataout <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add0_117_o(0) WHEN s_wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_in_wr_ptr_116_dataout = '1' ELSE altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_0_110q;
+ wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_in_wr_ptr_1_121m_dataout <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add0_117_o(1) WHEN s_wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_in_wr_ptr_116_dataout = '1' ELSE altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_1_109q;
+ wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_in_wr_ptr_2_120m_dataout <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add0_117_o(2) WHEN s_wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_in_wr_ptr_116_dataout = '1' ELSE altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_2_108q;
+ wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_in_wr_ptr_3_119m_dataout <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add0_117_o(3) WHEN s_wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_in_wr_ptr_116_dataout = '1' ELSE altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_3_107q;
+ wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_in_wr_ptr_4_118m_dataout <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add0_117_o(4) WHEN s_wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_in_wr_ptr_116_dataout = '1' ELSE altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_4_106q;
+ wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_out_rd_ptr_4_125m_dataout <= wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add1_124_o(4) WHEN s_wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_next_out_rd_ptr_123_dataout = '1' ELSE altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_4_112q;
+ wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add0_117_a <= ( altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_4_106q & altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_3_107q & altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_2_108q & altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_1_109q & altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_in_wr_ptr_0_110q);
+ wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add0_117_b <= ( "0" & "0" & "0" & "0" & "1");
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add0_117 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 5,
+ width_b => 5,
+ width_o => 5
+ )
+ PORT MAP (
+ a => wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add0_117_a,
+ b => wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add0_117_b,
+ cin => wire_gnd,
+ o => wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add0_117_o
+ );
+ wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add1_124_a <= ( altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_4_112q & altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_3_113q & altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_2_114q & altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_1_115q & altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_out_rd_ptr_0_131q);
+ wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add1_124_b <= ( "0" & "0" & "0" & "0" & "1");
+ altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add1_124 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 5,
+ width_b => 5,
+ width_o => 5
+ )
+ PORT MAP (
+ a => wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add1_124_a,
+ b => wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add1_124_b,
+ cin => wire_gnd,
+ o => wire_altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add1_124_o
+ );
+
+ END RTL; --altera_avalon_dc_fifo_0002
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_mm_bridge/altera_avalon_mm_bridge_0001.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_mm_bridge/altera_avalon_mm_bridge_0001.vho
new file mode 100644
index 0000000000000000000000000000000000000000..56ac3bfea13ee56a732b41980fe5c7085b9f852f
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_mm_bridge/altera_avalon_mm_bridge_0001.vho
@@ -0,0 +1,77 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_avalon_mm_bridge_0001 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ m0_address : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
+ m0_burstcount : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
+ m0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+ m0_debugaccess : OUT STD_LOGIC;
+ m0_read : OUT STD_LOGIC;
+ m0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ m0_readdatavalid : IN STD_LOGIC;
+ m0_waitrequest : IN STD_LOGIC;
+ m0_write : OUT STD_LOGIC;
+ m0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ reset : IN STD_LOGIC;
+ s0_address : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
+ s0_burstcount : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
+ s0_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+ s0_debugaccess : IN STD_LOGIC;
+ s0_read : IN STD_LOGIC;
+ s0_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ s0_readdatavalid : OUT STD_LOGIC;
+ s0_waitrequest : OUT STD_LOGIC;
+ s0_write : IN STD_LOGIC;
+ s0_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
+ );
+ END altera_avalon_mm_bridge_0001;
+
+ ARCHITECTURE RTL OF altera_avalon_mm_bridge_0001 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ BEGIN
+
+ m0_address <= ( s0_address(13 DOWNTO 0));
+ m0_burstcount(0) <= ( s0_burstcount(0));
+ m0_byteenable <= ( s0_byteenable(3 DOWNTO 0));
+ m0_debugaccess <= s0_debugaccess;
+ m0_read <= s0_read;
+ m0_write <= s0_write;
+ m0_writedata <= ( s0_writedata(31 DOWNTO 0));
+ s0_readdata <= ( m0_readdata(31 DOWNTO 0));
+ s0_readdatavalid <= m0_readdatavalid;
+ s0_waitrequest <= m0_waitrequest;
+
+ END RTL; --altera_avalon_mm_bridge_0001
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0001.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0001.vho
new file mode 100644
index 0000000000000000000000000000000000000000..5754ba9d9d9c78b4a5b9a2a7f5d003a23c377277
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0001.vho
@@ -0,0 +1,664 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources = lut 140 mux21 74
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_avalon_sc_fifo_0001 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ in_data : IN STD_LOGIC_VECTOR (66 DOWNTO 0);
+ in_endofpacket : IN STD_LOGIC;
+ in_ready : OUT STD_LOGIC;
+ in_startofpacket : IN STD_LOGIC;
+ in_valid : IN STD_LOGIC;
+ out_data : OUT STD_LOGIC_VECTOR (66 DOWNTO 0);
+ out_endofpacket : OUT STD_LOGIC;
+ out_ready : IN STD_LOGIC;
+ out_startofpacket : OUT STD_LOGIC;
+ out_valid : OUT STD_LOGIC;
+ reset : IN STD_LOGIC
+ );
+ END altera_avalon_sc_fifo_0001;
+
+ ARCHITECTURE RTL OF altera_avalon_sc_fifo_0001 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_0_431q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_10_414q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_11_413q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_12_412q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_13_411q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_14_410q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_15_409q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_16_408q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_17_407q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_18_406q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_19_405q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_1_423q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_20_404q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_21_403q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_22_402q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_23_401q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_24_400q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_25_399q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_26_398q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_27_397q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_28_396q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_29_395q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_2_422q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_30_394q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_31_393q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_32_392q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_33_391q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_34_390q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_35_389q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_36_388q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_37_387q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_38_386q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_39_385q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_3_421q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_40_384q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_41_383q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_42_382q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_43_381q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_44_380q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_45_379q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_46_378q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_47_377q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_48_376q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_49_375q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_4_420q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_50_374q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_51_373q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_52_372q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_53_371q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_54_370q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_55_369q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_56_368q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_57_367q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_58_366q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_59_365q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_5_419q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_60_364q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_61_363q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_62_362q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_63_361q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_64_360q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_65_359q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_66_358q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_67_357q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_68_356q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_6_418q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_7_417q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_8_416q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_9_415q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_434q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_1_471q : STD_LOGIC := '0';
+ SIGNAL wire_nl_w70w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w1w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_0_355q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_10_345q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_11_344q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_12_343q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_13_342q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_14_341q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_15_340q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_16_339q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_17_338q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_18_337q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_19_336q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_1_354q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_20_335q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_21_334q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_22_333q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_23_332q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_24_331q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_25_330q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_26_329q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_27_328q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_28_327q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_29_326q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_2_353q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_30_325q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_31_324q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_32_323q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_33_322q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_34_321q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_35_320q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_36_319q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_37_318q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_38_317q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_39_316q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_3_352q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_40_315q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_41_314q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_42_313q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_43_312q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_44_311q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_45_310q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_46_309q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_47_308q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_48_307q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_49_306q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_4_351q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_50_305q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_51_304q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_52_303q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_53_302q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_54_301q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_55_300q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_56_299q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_57_298q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_58_297q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_59_296q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_5_350q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_60_295q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_61_294q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_62_293q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_63_292q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_64_291q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_65_290q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_66_289q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_67_288q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_68_287q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_6_349q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_7_348q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_8_347q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_9_346q : STD_LOGIC := '0';
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_149m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_150m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_151m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_152m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_153m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_154m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_155m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_156m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_157m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_158m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_159m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_160m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_161m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_162m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_163m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_164m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_165m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_166m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_167m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_174m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_175m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_176m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_177m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_184m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_185m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_186m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_187m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_188m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_189m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_190m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_191m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_192m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_193m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_194m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_195m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_196m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_197m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_198m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_199m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_200m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_201m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_202m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_203m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_204m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_205m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_206m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_207m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_208m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_209m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_210m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_211m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_212m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_213m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_214m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_215m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_216m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_217m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_723m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_1_724m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_428m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_429m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_432m_dataout : STD_LOGIC;
+ SIGNAL wire_w_lg_reset139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_always0_148_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_always2_427_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_read_424_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_write_426_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ BEGIN
+
+ wire_w_lg_reset139w(0) <= NOT reset;
+ in_ready <= wire_nl_w1w(0);
+ out_data <= ( altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_66_289q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_65_290q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_64_291q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_63_292q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_62_293q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_61_294q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_60_295q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_59_296q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_58_297q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_57_298q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_56_299q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_55_300q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_54_301q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_53_302q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_52_303q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_51_304q
+ & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_50_305q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_49_306q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_48_307q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_47_308q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_46_309q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_45_310q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_44_311q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_43_312q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_42_313q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_41_314q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_40_315q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_39_316q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_38_317q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_37_318q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_36_319q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_35_320q
+ & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_34_321q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_33_322q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_32_323q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_31_324q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_30_325q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_29_326q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_28_327q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_27_328q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_26_329q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_25_330q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_24_331q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_23_332q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_22_333q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_21_334q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_20_335q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_19_336q
+ & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_18_337q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_17_338q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_16_339q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_15_340q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_14_341q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_13_342q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_12_343q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_11_344q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_10_345q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_9_346q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_8_347q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_7_348q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_6_349q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_5_350q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_4_351q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_3_352q
+ & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_2_353q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_1_354q & altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_0_355q);
+ out_endofpacket <= altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_67_288q;
+ out_startofpacket <= altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_68_287q;
+ out_valid <= altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_434q;
+ s_wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_always0_148_dataout <= (s_wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_read_424_dataout OR wire_nl_w70w(0));
+ s_wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_always2_427_dataout <= (s_wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_read_424_dataout XOR s_wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_write_426_dataout);
+ s_wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_read_424_dataout <= (altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_434q AND (out_ready OR wire_nl_w70w(0)));
+ s_wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_write_426_dataout <= (in_valid AND wire_nl_w1w(0));
+ s_wire_vcc <= '1';
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_0_431q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_10_414q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_11_413q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_12_412q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_13_411q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_14_410q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_15_409q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_16_408q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_17_407q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_18_406q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_19_405q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_1_423q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_20_404q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_21_403q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_22_402q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_23_401q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_24_400q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_25_399q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_26_398q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_27_397q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_28_396q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_29_395q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_2_422q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_30_394q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_31_393q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_32_392q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_33_391q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_34_390q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_35_389q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_36_388q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_37_387q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_38_386q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_39_385q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_3_421q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_40_384q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_41_383q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_42_382q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_43_381q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_44_380q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_45_379q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_46_378q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_47_377q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_48_376q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_49_375q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_4_420q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_50_374q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_51_373q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_52_372q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_53_371q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_54_370q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_55_369q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_56_368q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_57_367q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_58_366q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_59_365q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_5_419q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_60_364q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_61_363q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_62_362q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_63_361q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_64_360q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_65_359q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_66_358q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_67_357q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_68_356q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_6_418q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_7_417q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_8_416q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_9_415q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_434q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_1_471q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_0_431q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_217m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_10_414q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_207m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_11_413q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_206m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_12_412q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_205m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_13_411q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_204m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_14_410q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_203m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_15_409q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_202m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_16_408q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_201m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_17_407q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_200m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_18_406q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_199m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_19_405q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_198m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_1_423q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_216m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_20_404q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_197m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_21_403q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_196m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_22_402q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_195m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_23_401q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_194m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_24_400q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_193m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_25_399q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_192m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_26_398q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_191m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_27_397q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_190m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_28_396q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_189m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_29_395q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_188m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_2_422q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_215m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_30_394q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_187m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_31_393q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_186m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_32_392q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_185m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_33_391q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_184m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_34_390q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_35_389q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_36_388q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_37_387q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_38_386q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_39_385q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_3_421q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_214m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_40_384q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_177m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_41_383q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_176m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_42_382q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_175m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_43_381q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_174m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_44_380q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_45_379q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_46_378q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_47_377q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_48_376q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_49_375q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_4_420q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_213m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_50_374q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_167m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_51_373q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_166m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_52_372q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_165m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_53_371q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_164m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_54_370q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_163m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_55_369q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_162m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_56_368q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_161m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_57_367q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_160m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_58_366q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_159m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_59_365q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_158m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_5_419q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_212m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_60_364q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_157m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_61_363q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_156m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_62_362q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_155m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_63_361q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_154m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_64_360q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_153m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_65_359q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_152m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_66_358q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_151m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_67_357q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_150m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_68_356q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_149m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_6_418q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_211m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_7_417q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_210m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_8_416q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_209m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_9_415q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_208m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_434q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_723m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_1_471q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_1_724m_dataout;
+ END IF;
+ END PROCESS;
+ wire_nl_w70w(0) <= NOT altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_434q;
+ wire_nl_w1w(0) <= NOT altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_1_471q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_0_355q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_10_345q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_11_344q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_12_343q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_13_342q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_14_341q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_15_340q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_16_339q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_17_338q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_18_337q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_19_336q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_1_354q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_20_335q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_21_334q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_22_333q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_23_332q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_24_331q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_25_330q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_26_329q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_27_328q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_28_327q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_29_326q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_2_353q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_30_325q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_31_324q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_32_323q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_33_322q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_34_321q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_35_320q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_36_319q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_37_318q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_38_317q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_39_316q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_3_352q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_40_315q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_41_314q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_42_313q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_43_312q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_44_311q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_45_310q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_46_309q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_47_308q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_48_307q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_49_306q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_4_351q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_50_305q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_51_304q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_52_303q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_53_302q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_54_301q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_55_300q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_56_299q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_57_298q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_58_297q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_59_296q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_5_350q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_60_295q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_61_294q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_62_293q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_63_292q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_64_291q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_65_290q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_66_289q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_67_288q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_68_287q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_6_349q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_7_348q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_8_347q <= '0';
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_9_346q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_always0_148_dataout = '1') THEN
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_0_355q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_217m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_10_345q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_207m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_11_344q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_206m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_12_343q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_205m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_13_342q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_204m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_14_341q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_203m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_15_340q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_202m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_16_339q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_201m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_17_338q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_200m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_18_337q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_199m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_19_336q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_198m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_1_354q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_216m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_20_335q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_197m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_21_334q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_196m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_22_333q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_195m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_23_332q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_194m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_24_331q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_193m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_25_330q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_192m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_26_329q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_191m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_27_328q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_190m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_28_327q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_189m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_29_326q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_188m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_2_353q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_215m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_30_325q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_187m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_31_324q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_186m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_32_323q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_185m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_33_322q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_184m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_34_321q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_35_320q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_36_319q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_37_318q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_38_317q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_39_316q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_3_352q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_214m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_40_315q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_177m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_41_314q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_176m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_42_313q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_175m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_43_312q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_174m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_44_311q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_45_310q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_46_309q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_47_308q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_48_307q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_49_306q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_4_351q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_213m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_50_305q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_167m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_51_304q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_166m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_52_303q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_165m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_53_302q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_164m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_54_301q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_163m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_55_300q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_162m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_56_299q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_161m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_57_298q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_160m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_58_297q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_159m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_59_296q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_158m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_5_350q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_212m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_60_295q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_157m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_61_294q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_156m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_62_293q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_155m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_63_292q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_154m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_64_291q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_153m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_65_290q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_152m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_66_289q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_151m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_67_288q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_150m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_68_287q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_149m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_6_349q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_211m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_7_348q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_210m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_8_347q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_209m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_9_346q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_208m_dataout;
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_149m_dataout <= in_startofpacket WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_68_356q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_150m_dataout <= in_endofpacket WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_67_357q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_151m_dataout <= in_data(66) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_66_358q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_152m_dataout <= in_data(65) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_65_359q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_153m_dataout <= in_data(64) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_64_360q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_154m_dataout <= in_data(63) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_63_361q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_155m_dataout <= in_data(62) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_62_362q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_156m_dataout <= in_data(61) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_61_363q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_157m_dataout <= in_data(60) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_60_364q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_158m_dataout <= in_data(59) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_59_365q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_159m_dataout <= in_data(58) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_58_366q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_160m_dataout <= in_data(57) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_57_367q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_161m_dataout <= in_data(56) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_56_368q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_162m_dataout <= in_data(55) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_55_369q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_163m_dataout <= in_data(54) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_54_370q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_164m_dataout <= in_data(53) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_53_371q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_165m_dataout <= in_data(52) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_52_372q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_166m_dataout <= in_data(51) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_51_373q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_167m_dataout <= in_data(50) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_50_374q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout <= in_data(49) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_49_375q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout <= in_data(48) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_48_376q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout <= in_data(47) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_47_377q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout <= in_data(46) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_46_378q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout <= in_data(45) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_45_379q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout <= in_data(44) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_44_380q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_174m_dataout <= in_data(43) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_43_381q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_175m_dataout <= in_data(42) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_42_382q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_176m_dataout <= in_data(41) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_41_383q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_177m_dataout <= in_data(40) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_40_384q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout <= in_data(39) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_39_385q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout <= in_data(38) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_38_386q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout <= in_data(37) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_37_387q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout <= in_data(36) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_36_388q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout <= in_data(35) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_35_389q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout <= in_data(34) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_34_390q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_184m_dataout <= in_data(33) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_33_391q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_185m_dataout <= in_data(32) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_32_392q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_186m_dataout <= in_data(31) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_31_393q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_187m_dataout <= in_data(30) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_30_394q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_188m_dataout <= in_data(29) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_29_395q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_189m_dataout <= in_data(28) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_28_396q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_190m_dataout <= in_data(27) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_27_397q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_191m_dataout <= in_data(26) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_26_398q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_192m_dataout <= in_data(25) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_25_399q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_193m_dataout <= in_data(24) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_24_400q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_194m_dataout <= in_data(23) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_23_401q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_195m_dataout <= in_data(22) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_22_402q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_196m_dataout <= in_data(21) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_21_403q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_197m_dataout <= in_data(20) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_20_404q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_198m_dataout <= in_data(19) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_19_405q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_199m_dataout <= in_data(18) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_18_406q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_200m_dataout <= in_data(17) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_17_407q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_201m_dataout <= in_data(16) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_16_408q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_202m_dataout <= in_data(15) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_15_409q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_203m_dataout <= in_data(14) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_14_410q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_204m_dataout <= in_data(13) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_13_411q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_205m_dataout <= in_data(12) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_12_412q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_206m_dataout <= in_data(11) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_11_413q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_207m_dataout <= in_data(10) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_10_414q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_208m_dataout <= in_data(9) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_9_415q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_209m_dataout <= in_data(8) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_8_416q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_210m_dataout <= in_data(7) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_7_417q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_211m_dataout <= in_data(6) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_6_418q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_212m_dataout <= in_data(5) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_5_419q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_213m_dataout <= in_data(4) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_4_420q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_214m_dataout <= in_data(3) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_3_421q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_215m_dataout <= in_data(2) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_2_422q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_216m_dataout <= in_data(1) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_1_423q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_217m_dataout <= in_data(0) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_0_431q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_723m_dataout <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_429m_dataout WHEN s_wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_always2_427_dataout = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_434q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_1_724m_dataout <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_432m_dataout WHEN s_wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_always2_427_dataout = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_1_471q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_428m_dataout <= altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_1_471q WHEN s_wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_read_424_dataout = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_434q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_429m_dataout <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_428m_dataout OR s_wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_write_426_dataout;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_432m_dataout <= altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_434q AND s_wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_write_426_dataout;
+
+ END RTL; --altera_avalon_sc_fifo_0001
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0002.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0002.vho
new file mode 100644
index 0000000000000000000000000000000000000000..2eb559c8133d33aeb5efd306240ccadc9b1f4edc
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0002.vho
@@ -0,0 +1,432 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources = lut 66 mux21 69
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_avalon_sc_fifo_0002 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ in_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ in_ready : OUT STD_LOGIC;
+ in_valid : IN STD_LOGIC;
+ out_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ out_ready : IN STD_LOGIC;
+ out_valid : OUT STD_LOGIC;
+ reset : IN STD_LOGIC
+ );
+ END altera_avalon_sc_fifo_0002;
+
+ ARCHITECTURE RTL OF altera_avalon_sc_fifo_0002 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_0_208q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_10_191q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_11_190q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_12_189q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_13_188q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_14_187q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_15_186q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_16_185q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_17_184q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_18_183q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_19_182q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_1_200q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_20_181q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_21_180q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_22_179q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_23_178q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_24_177q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_25_176q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_26_175q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_27_174q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_28_173q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_29_172q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_2_199q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_30_171q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_31_170q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_3_198q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_4_197q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_5_196q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_6_195q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_7_194q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_8_193q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_9_192q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_used_0_211q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_used_1_285q : STD_LOGIC := '0';
+ SIGNAL wire_nl_w36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w1w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_0_169q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_10_159q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_11_158q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_12_157q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_13_156q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_14_155q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_15_154q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_16_153q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_17_152q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_18_151q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_19_150q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_1_168q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_20_149q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_21_148q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_22_147q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_23_146q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_24_145q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_25_144q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_26_143q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_27_142q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_28_141q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_29_140q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_2_167q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_30_139q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_31_138q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_3_166q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_4_165q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_5_164q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_6_163q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_7_162q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_8_161q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_9_160q : STD_LOGIC := '0';
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_100m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_101m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_102m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_103m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_104m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_105m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_74m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_75m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_76m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_77m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_78m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_79m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_80m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_81m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_82m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_83m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_84m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_85m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_86m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_87m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_88m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_89m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_90m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_91m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_92m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_93m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_94m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_95m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_96m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_97m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_98m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_99m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_used_0_467m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_used_1_468m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_used_205m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_used_206m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_used_209m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_0_247m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_10_237m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_11_236m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_12_235m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_13_234m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_14_233m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_15_232m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_16_231m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_17_230m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_18_229m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_19_228m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_1_246m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_20_227m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_21_226m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_22_225m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_23_224m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_24_223m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_25_222m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_26_221m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_27_220m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_28_219m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_29_218m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_2_245m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_30_217m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_31_216m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_3_244m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_4_243m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_5_242m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_6_241m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_7_240m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_8_239m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_9_238m_dataout : STD_LOGIC;
+ SIGNAL wire_w_lg_in_valid75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_reset70w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w35w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always0_73_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always2_204_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_empty_213_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_read_201_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_write_203_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ BEGIN
+
+ wire_w_lg_in_valid75w(0) <= NOT in_valid;
+ wire_w_lg_reset70w(0) <= NOT reset;
+ wire_w35w(0) <= NOT s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_empty_213_dataout;
+ in_ready <= wire_nl_w1w(0);
+ out_data <= ( wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_31_216m_dataout & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_30_217m_dataout & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_29_218m_dataout & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_28_219m_dataout & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_27_220m_dataout & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_26_221m_dataout & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_25_222m_dataout & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_24_223m_dataout & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_23_224m_dataout & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_22_225m_dataout & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_21_226m_dataout & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_20_227m_dataout & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_19_228m_dataout & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_18_229m_dataout
+ & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_17_230m_dataout & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_16_231m_dataout & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_15_232m_dataout & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_14_233m_dataout & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_13_234m_dataout & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_12_235m_dataout & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_11_236m_dataout & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_10_237m_dataout & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_9_238m_dataout & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_8_239m_dataout & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_7_240m_dataout & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_6_241m_dataout & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_5_242m_dataout & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_4_243m_dataout
+ & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_3_244m_dataout & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_2_245m_dataout & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_1_246m_dataout & wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_0_247m_dataout);
+ out_valid <= wire_w35w(0);
+ s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always0_73_dataout <= (s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_read_201_dataout OR wire_nl_w36w(0));
+ s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always2_204_dataout <= (s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_read_201_dataout XOR s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_write_203_dataout);
+ s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout <= (in_valid AND wire_nl_w36w(0));
+ s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_empty_213_dataout <= (wire_w_lg_in_valid75w(0) AND wire_nl_w36w(0));
+ s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_read_201_dataout <= (wire_w35w(0) AND (out_ready OR s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_empty_213_dataout));
+ s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_write_203_dataout <= (in_valid AND wire_nl_w1w(0));
+ s_wire_vcc <= '1';
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_0_208q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_10_191q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_11_190q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_12_189q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_13_188q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_14_187q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_15_186q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_16_185q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_17_184q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_18_183q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_19_182q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_1_200q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_20_181q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_21_180q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_22_179q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_23_178q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_24_177q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_25_176q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_26_175q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_27_174q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_28_173q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_29_172q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_2_199q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_30_171q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_31_170q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_3_198q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_4_197q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_5_196q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_6_195q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_7_194q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_8_193q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_9_192q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_used_0_211q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_used_1_285q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_0_208q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_105m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_10_191q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_95m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_11_190q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_94m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_12_189q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_93m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_13_188q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_92m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_14_187q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_91m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_15_186q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_90m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_16_185q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_89m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_17_184q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_88m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_18_183q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_87m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_19_182q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_86m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_1_200q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_104m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_20_181q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_85m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_21_180q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_84m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_22_179q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_83m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_23_178q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_82m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_24_177q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_81m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_25_176q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_80m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_26_175q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_79m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_27_174q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_78m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_28_173q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_77m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_29_172q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_76m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_2_199q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_103m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_30_171q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_75m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_31_170q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_74m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_3_198q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_102m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_4_197q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_101m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_5_196q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_100m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_6_195q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_99m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_7_194q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_98m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_8_193q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_97m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_9_192q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_96m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_used_0_211q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_used_0_467m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_used_1_285q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_used_1_468m_dataout;
+ END IF;
+ END PROCESS;
+ wire_nl_w36w(0) <= NOT altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_used_0_211q;
+ wire_nl_w1w(0) <= NOT altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_used_1_285q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_0_169q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_10_159q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_11_158q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_12_157q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_13_156q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_14_155q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_15_154q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_16_153q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_17_152q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_18_151q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_19_150q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_1_168q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_20_149q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_21_148q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_22_147q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_23_146q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_24_145q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_25_144q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_26_143q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_27_142q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_28_141q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_29_140q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_2_167q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_30_139q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_31_138q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_3_166q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_4_165q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_5_164q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_6_163q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_7_162q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_8_161q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_9_160q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always0_73_dataout = '1') THEN
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_0_169q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_105m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_10_159q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_95m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_11_158q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_94m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_12_157q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_93m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_13_156q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_92m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_14_155q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_91m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_15_154q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_90m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_16_153q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_89m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_17_152q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_88m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_18_151q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_87m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_19_150q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_86m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_1_168q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_104m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_20_149q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_85m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_21_148q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_84m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_22_147q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_83m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_23_146q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_82m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_24_145q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_81m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_25_144q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_80m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_26_143q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_79m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_27_142q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_78m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_28_141q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_77m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_29_140q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_76m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_2_167q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_103m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_30_139q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_75m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_31_138q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_74m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_3_166q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_102m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_4_165q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_101m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_5_164q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_100m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_6_163q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_99m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_7_162q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_98m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_8_161q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_97m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_9_160q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_96m_dataout;
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_100m_dataout <= in_data(5) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_5_196q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_101m_dataout <= in_data(4) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_4_197q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_102m_dataout <= in_data(3) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_3_198q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_103m_dataout <= in_data(2) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_2_199q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_104m_dataout <= in_data(1) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_1_200q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_105m_dataout <= in_data(0) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_0_208q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_74m_dataout <= in_data(31) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_31_170q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_75m_dataout <= in_data(30) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_30_171q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_76m_dataout <= in_data(29) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_29_172q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_77m_dataout <= in_data(28) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_28_173q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_78m_dataout <= in_data(27) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_27_174q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_79m_dataout <= in_data(26) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_26_175q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_80m_dataout <= in_data(25) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_25_176q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_81m_dataout <= in_data(24) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_24_177q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_82m_dataout <= in_data(23) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_23_178q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_83m_dataout <= in_data(22) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_22_179q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_84m_dataout <= in_data(21) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_21_180q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_85m_dataout <= in_data(20) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_20_181q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_86m_dataout <= in_data(19) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_19_182q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_87m_dataout <= in_data(18) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_18_183q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_88m_dataout <= in_data(17) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_17_184q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_89m_dataout <= in_data(16) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_16_185q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_90m_dataout <= in_data(15) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_15_186q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_91m_dataout <= in_data(14) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_14_187q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_92m_dataout <= in_data(13) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_13_188q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_93m_dataout <= in_data(12) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_12_189q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_94m_dataout <= in_data(11) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_11_190q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_95m_dataout <= in_data(10) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_10_191q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_96m_dataout <= in_data(9) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_9_192q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_97m_dataout <= in_data(8) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_8_193q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_98m_dataout <= in_data(7) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_7_194q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_99m_dataout <= in_data(6) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_6_195q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_used_0_467m_dataout <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_used_206m_dataout WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always2_204_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_used_0_211q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_used_1_468m_dataout <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_used_209m_dataout WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always2_204_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_used_1_285q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_used_205m_dataout <= altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_used_1_285q WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_read_201_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_used_0_211q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_used_206m_dataout <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_used_205m_dataout OR s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_write_203_dataout;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_used_209m_dataout <= altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_used_0_211q AND s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_write_203_dataout;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_0_247m_dataout <= in_data(0) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_0_169q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_10_237m_dataout <= in_data(10) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_10_159q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_11_236m_dataout <= in_data(11) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_11_158q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_12_235m_dataout <= in_data(12) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_12_157q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_13_234m_dataout <= in_data(13) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_13_156q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_14_233m_dataout <= in_data(14) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_14_155q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_15_232m_dataout <= in_data(15) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_15_154q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_16_231m_dataout <= in_data(16) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_16_153q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_17_230m_dataout <= in_data(17) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_17_152q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_18_229m_dataout <= in_data(18) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_18_151q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_19_228m_dataout <= in_data(19) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_19_150q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_1_246m_dataout <= in_data(1) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_1_168q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_20_227m_dataout <= in_data(20) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_20_149q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_21_226m_dataout <= in_data(21) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_21_148q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_22_225m_dataout <= in_data(22) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_22_147q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_23_224m_dataout <= in_data(23) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_23_146q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_24_223m_dataout <= in_data(24) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_24_145q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_25_222m_dataout <= in_data(25) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_25_144q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_26_221m_dataout <= in_data(26) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_26_143q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_27_220m_dataout <= in_data(27) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_27_142q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_28_219m_dataout <= in_data(28) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_28_141q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_29_218m_dataout <= in_data(29) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_29_140q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_2_245m_dataout <= in_data(2) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_2_167q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_30_217m_dataout <= in_data(30) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_30_139q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_31_216m_dataout <= in_data(31) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_31_138q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_3_244m_dataout <= in_data(3) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_3_166q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_4_243m_dataout <= in_data(4) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_4_165q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_5_242m_dataout <= in_data(5) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_5_164q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_6_241m_dataout <= in_data(6) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_6_163q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_7_240m_dataout <= in_data(7) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_7_162q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_8_239m_dataout <= in_data(8) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_8_161q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data_9_238m_dataout <= in_data(9) WHEN s_wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_always4_215_dataout = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_0_9_160q;
+
+ END RTL; --altera_avalon_sc_fifo_0002
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0003.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0003.vho
new file mode 100644
index 0000000000000000000000000000000000000000..57e0b1e004ebc10843b144d157b2e78c34686c37
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0003.vho
@@ -0,0 +1,1076 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources = lut 219 mux21 151
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_avalon_sc_fifo_0003 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ in_data : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
+ in_endofpacket : IN STD_LOGIC;
+ in_ready : OUT STD_LOGIC;
+ in_startofpacket : IN STD_LOGIC;
+ in_valid : IN STD_LOGIC;
+ out_data : OUT STD_LOGIC_VECTOR (69 DOWNTO 0);
+ out_endofpacket : OUT STD_LOGIC;
+ out_ready : IN STD_LOGIC;
+ out_startofpacket : OUT STD_LOGIC;
+ out_valid : OUT STD_LOGIC;
+ reset : IN STD_LOGIC
+ );
+ END altera_avalon_sc_fifo_0003;
+
+ ARCHITECTURE RTL OF altera_avalon_sc_fifo_0003 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_0_667q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_10_650q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_11_649q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_12_648q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_13_647q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_14_646q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_15_645q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_16_644q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_17_643q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_18_642q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_19_641q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_1_659q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_20_640q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_21_639q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_22_638q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_23_637q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_24_636q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_25_635q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_26_634q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_27_633q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_28_632q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_29_631q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_2_658q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_30_630q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_31_629q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_32_628q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_33_627q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_34_626q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_35_625q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_36_624q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_37_623q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_38_622q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_39_621q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_3_657q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_40_620q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_41_619q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_42_618q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_43_617q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_44_616q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_45_615q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_46_614q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_47_613q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_48_612q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_49_611q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_4_656q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_50_610q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_51_609q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_52_608q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_53_607q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_54_606q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_55_605q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_56_604q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_57_603q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_58_602q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_59_601q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_5_655q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_60_600q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_61_599q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_62_598q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_63_597q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_64_596q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_65_595q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_66_594q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_67_593q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_68_592q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_69_591q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_6_654q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_70_590q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_71_589q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_7_653q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_8_652q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_9_651q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_670q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_2_674q : STD_LOGIC := '0';
+ SIGNAL wire_ni_w73w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_ni_w1w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_0_588q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_10_578q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_11_577q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_12_576q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_13_575q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_14_574q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_15_573q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_16_572q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_17_571q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_18_570q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_19_569q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_1_587q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_20_568q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_21_567q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_22_566q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_23_565q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_24_564q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_25_563q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_26_562q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_27_561q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_28_560q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_29_559q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_2_586q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_30_558q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_31_557q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_32_556q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_33_555q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_34_554q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_35_553q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_36_552q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_37_551q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_38_550q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_39_549q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_3_585q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_40_548q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_41_547q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_42_546q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_43_545q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_44_544q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_45_543q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_46_542q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_47_541q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_48_540q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_49_539q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_4_584q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_50_538q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_51_537q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_52_536q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_53_535q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_54_534q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_55_533q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_56_532q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_57_531q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_58_530q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_59_529q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_5_583q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_60_528q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_61_527q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_62_526q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_63_525q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_64_524q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_65_523q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_66_522q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_67_521q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_68_520q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_69_519q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_6_582q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_70_518q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_71_517q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_7_581q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_8_580q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_9_579q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_1_711q : STD_LOGIC := '0';
+ SIGNAL wire_nlO_w75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_0_516q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_10_361q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_11_360q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_12_359q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_13_358q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_14_357q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_15_356q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_16_355q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_17_354q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_18_353q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_19_352q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_1_370q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_20_351q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_21_350q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_22_349q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_23_348q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_24_347q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_25_346q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_26_345q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_27_344q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_28_343q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_29_342q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_2_369q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_30_341q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_31_340q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_32_339q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_33_338q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_34_337q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_35_336q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_36_335q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_37_334q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_38_333q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_39_332q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_3_368q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_40_331q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_41_330q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_42_329q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_43_328q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_44_327q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_45_326q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_46_325q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_47_324q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_48_323q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_49_322q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_4_367q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_50_321q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_51_320q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_52_319q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_53_318q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_54_317q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_55_316q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_56_315q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_57_314q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_58_313q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_59_312q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_5_366q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_60_311q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_61_310q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_62_309q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_63_308q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_64_307q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_65_306q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_66_305q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_67_304q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_68_303q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_69_302q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_6_365q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_70_301q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_71_300q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_7_364q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_8_363q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_9_362q : STD_LOGIC := '0';
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_156m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_157m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_158m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_159m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_160m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_161m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_162m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_163m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_164m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_165m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_166m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_167m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_174m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_175m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_176m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_177m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_184m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_185m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_186m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_187m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_188m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_189m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_190m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_191m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_192m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_193m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_194m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_195m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_196m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_197m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_198m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_199m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_200m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_201m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_202m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_203m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_204m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_205m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_206m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_207m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_208m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_209m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_210m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_211m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_212m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_213m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_214m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_215m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_216m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_217m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_218m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_219m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_220m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_221m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_222m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_223m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_224m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_225m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_226m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_227m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_372m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_373m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_374m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_375m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_376m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_377m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_378m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_379m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_380m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_381m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_382m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_383m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_384m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_385m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_386m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_387m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_388m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_389m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_390m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_391m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_392m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_393m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_394m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_395m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_396m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_397m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_398m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_399m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_400m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_401m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_402m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_403m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_404m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_405m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_406m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_407m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_408m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_409m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_410m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_411m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_412m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_413m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_414m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_415m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_416m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_417m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_418m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_419m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_420m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_421m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_422m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_423m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_424m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_425m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_426m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_427m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_428m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_429m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_430m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_431m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_432m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_433m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_434m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_435m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_436m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_437m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_438m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_439m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_440m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_441m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_442m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_443m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_969m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_2_970m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_664m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_665m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_668m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_671m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_672m_dataout : STD_LOGIC;
+ SIGNAL wire_w_lg_reset146w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_always0_154_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_always1_371_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_always3_663_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_read_660_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_write_662_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ BEGIN
+
+ wire_w_lg_reset146w(0) <= NOT reset;
+ in_ready <= wire_ni_w1w(0);
+ out_data <= ( altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_69_302q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_68_303q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_67_304q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_66_305q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_65_306q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_64_307q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_63_308q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_62_309q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_61_310q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_60_311q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_59_312q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_58_313q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_57_314q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_56_315q
+ & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_55_316q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_54_317q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_53_318q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_52_319q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_51_320q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_50_321q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_49_322q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_48_323q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_47_324q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_46_325q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_45_326q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_44_327q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_43_328q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_42_329q
+ & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_41_330q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_40_331q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_39_332q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_38_333q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_37_334q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_36_335q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_35_336q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_34_337q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_33_338q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_32_339q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_31_340q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_30_341q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_29_342q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_28_343q
+ & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_27_344q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_26_345q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_25_346q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_24_347q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_23_348q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_22_349q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_21_350q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_20_351q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_19_352q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_18_353q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_17_354q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_16_355q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_15_356q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_14_357q
+ & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_13_358q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_12_359q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_11_360q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_10_361q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_9_362q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_8_363q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_7_364q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_6_365q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_5_366q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_4_367q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_3_368q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_2_369q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_1_370q & altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_0_516q
+);
+ out_endofpacket <= altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_70_301q;
+ out_startofpacket <= altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_71_300q;
+ out_valid <= altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_670q;
+ s_wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_always0_154_dataout <= (s_wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_read_660_dataout OR wire_ni_w73w(0));
+ s_wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_always1_371_dataout <= (s_wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_read_660_dataout OR wire_nlO_w75w(0));
+ s_wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_always3_663_dataout <= (s_wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_read_660_dataout XOR s_wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_write_662_dataout);
+ s_wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_read_660_dataout <= (altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_670q AND (out_ready OR wire_ni_w73w(0)));
+ s_wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_write_662_dataout <= (in_valid AND wire_ni_w1w(0));
+ s_wire_vcc <= '1';
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_0_667q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_10_650q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_11_649q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_12_648q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_13_647q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_14_646q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_15_645q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_16_644q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_17_643q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_18_642q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_19_641q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_1_659q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_20_640q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_21_639q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_22_638q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_23_637q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_24_636q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_25_635q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_26_634q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_27_633q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_28_632q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_29_631q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_2_658q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_30_630q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_31_629q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_32_628q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_33_627q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_34_626q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_35_625q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_36_624q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_37_623q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_38_622q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_39_621q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_3_657q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_40_620q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_41_619q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_42_618q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_43_617q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_44_616q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_45_615q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_46_614q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_47_613q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_48_612q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_49_611q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_4_656q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_50_610q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_51_609q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_52_608q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_53_607q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_54_606q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_55_605q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_56_604q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_57_603q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_58_602q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_59_601q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_5_655q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_60_600q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_61_599q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_62_598q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_63_597q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_64_596q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_65_595q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_66_594q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_67_593q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_68_592q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_69_591q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_6_654q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_70_590q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_71_589q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_7_653q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_8_652q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_9_651q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_670q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_2_674q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_0_667q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_443m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_10_650q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_433m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_11_649q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_432m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_12_648q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_431m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_13_647q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_430m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_14_646q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_429m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_15_645q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_428m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_16_644q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_427m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_17_643q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_426m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_18_642q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_425m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_19_641q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_424m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_1_659q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_442m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_20_640q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_423m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_21_639q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_422m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_22_638q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_421m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_23_637q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_420m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_24_636q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_419m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_25_635q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_418m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_26_634q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_417m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_27_633q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_416m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_28_632q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_415m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_29_631q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_414m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_2_658q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_441m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_30_630q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_413m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_31_629q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_412m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_32_628q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_411m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_33_627q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_410m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_34_626q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_409m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_35_625q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_408m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_36_624q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_407m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_37_623q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_406m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_38_622q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_405m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_39_621q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_404m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_3_657q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_440m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_40_620q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_403m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_41_619q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_402m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_42_618q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_401m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_43_617q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_400m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_44_616q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_399m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_45_615q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_398m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_46_614q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_397m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_47_613q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_396m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_48_612q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_395m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_49_611q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_394m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_4_656q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_439m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_50_610q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_393m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_51_609q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_392m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_52_608q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_391m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_53_607q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_390m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_54_606q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_389m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_55_605q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_388m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_56_604q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_387m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_57_603q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_386m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_58_602q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_385m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_59_601q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_384m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_5_655q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_438m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_60_600q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_383m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_61_599q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_382m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_62_598q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_381m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_63_597q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_380m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_64_596q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_379m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_65_595q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_378m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_66_594q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_377m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_67_593q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_376m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_68_592q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_375m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_69_591q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_374m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_6_654q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_437m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_70_590q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_373m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_71_589q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_372m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_7_653q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_436m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_8_652q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_435m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_9_651q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_434m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_670q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_969m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_2_674q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_2_970m_dataout;
+ END IF;
+ END PROCESS;
+ wire_ni_w73w(0) <= NOT altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_670q;
+ wire_ni_w1w(0) <= NOT altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_2_674q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_0_588q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_10_578q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_11_577q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_12_576q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_13_575q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_14_574q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_15_573q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_16_572q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_17_571q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_18_570q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_19_569q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_1_587q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_20_568q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_21_567q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_22_566q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_23_565q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_24_564q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_25_563q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_26_562q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_27_561q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_28_560q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_29_559q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_2_586q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_30_558q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_31_557q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_32_556q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_33_555q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_34_554q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_35_553q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_36_552q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_37_551q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_38_550q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_39_549q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_3_585q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_40_548q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_41_547q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_42_546q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_43_545q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_44_544q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_45_543q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_46_542q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_47_541q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_48_540q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_49_539q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_4_584q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_50_538q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_51_537q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_52_536q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_53_535q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_54_534q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_55_533q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_56_532q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_57_531q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_58_530q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_59_529q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_5_583q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_60_528q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_61_527q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_62_526q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_63_525q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_64_524q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_65_523q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_66_522q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_67_521q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_68_520q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_69_519q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_6_582q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_70_518q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_71_517q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_7_581q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_8_580q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_9_579q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_always1_371_dataout = '1') THEN
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_0_588q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_443m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_10_578q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_433m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_11_577q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_432m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_12_576q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_431m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_13_575q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_430m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_14_574q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_429m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_15_573q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_428m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_16_572q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_427m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_17_571q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_426m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_18_570q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_425m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_19_569q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_424m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_1_587q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_442m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_20_568q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_423m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_21_567q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_422m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_22_566q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_421m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_23_565q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_420m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_24_564q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_419m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_25_563q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_418m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_26_562q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_417m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_27_561q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_416m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_28_560q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_415m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_29_559q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_414m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_2_586q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_441m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_30_558q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_413m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_31_557q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_412m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_32_556q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_411m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_33_555q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_410m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_34_554q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_409m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_35_553q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_408m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_36_552q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_407m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_37_551q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_406m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_38_550q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_405m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_39_549q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_404m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_3_585q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_440m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_40_548q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_403m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_41_547q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_402m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_42_546q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_401m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_43_545q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_400m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_44_544q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_399m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_45_543q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_398m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_46_542q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_397m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_47_541q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_396m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_48_540q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_395m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_49_539q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_394m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_4_584q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_439m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_50_538q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_393m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_51_537q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_392m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_52_536q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_391m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_53_535q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_390m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_54_534q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_389m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_55_533q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_388m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_56_532q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_387m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_57_531q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_386m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_58_530q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_385m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_59_529q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_384m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_5_583q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_438m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_60_528q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_383m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_61_527q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_382m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_62_526q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_381m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_63_525q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_380m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_64_524q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_379m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_65_523q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_378m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_66_522q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_377m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_67_521q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_376m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_68_520q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_375m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_69_519q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_374m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_6_582q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_437m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_70_518q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_373m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_71_517q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_372m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_7_581q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_436m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_8_580q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_435m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_9_579q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_434m_dataout;
+ END IF;
+ END IF;
+ END PROCESS;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_1_711q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_always3_663_dataout = '1') THEN
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_1_711q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_672m_dataout;
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_nlO_w75w(0) <= NOT altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_1_711q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_0_516q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_10_361q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_11_360q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_12_359q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_13_358q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_14_357q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_15_356q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_16_355q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_17_354q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_18_353q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_19_352q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_1_370q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_20_351q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_21_350q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_22_349q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_23_348q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_24_347q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_25_346q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_26_345q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_27_344q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_28_343q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_29_342q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_2_369q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_30_341q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_31_340q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_32_339q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_33_338q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_34_337q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_35_336q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_36_335q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_37_334q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_38_333q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_39_332q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_3_368q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_40_331q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_41_330q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_42_329q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_43_328q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_44_327q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_45_326q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_46_325q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_47_324q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_48_323q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_49_322q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_4_367q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_50_321q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_51_320q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_52_319q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_53_318q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_54_317q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_55_316q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_56_315q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_57_314q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_58_313q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_59_312q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_5_366q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_60_311q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_61_310q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_62_309q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_63_308q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_64_307q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_65_306q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_66_305q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_67_304q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_68_303q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_69_302q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_6_365q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_70_301q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_71_300q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_7_364q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_8_363q <= '0';
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_9_362q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_always0_154_dataout = '1') THEN
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_0_516q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_227m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_10_361q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_217m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_11_360q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_216m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_12_359q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_215m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_13_358q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_214m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_14_357q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_213m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_15_356q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_212m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_16_355q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_211m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_17_354q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_210m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_18_353q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_209m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_19_352q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_208m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_1_370q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_226m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_20_351q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_207m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_21_350q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_206m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_22_349q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_205m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_23_348q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_204m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_24_347q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_203m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_25_346q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_202m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_26_345q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_201m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_27_344q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_200m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_28_343q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_199m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_29_342q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_198m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_2_369q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_225m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_30_341q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_197m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_31_340q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_196m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_32_339q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_195m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_33_338q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_194m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_34_337q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_193m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_35_336q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_192m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_36_335q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_191m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_37_334q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_190m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_38_333q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_189m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_39_332q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_188m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_3_368q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_224m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_40_331q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_187m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_41_330q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_186m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_42_329q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_185m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_43_328q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_184m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_44_327q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_45_326q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_46_325q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_47_324q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_48_323q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_49_322q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_4_367q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_223m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_50_321q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_177m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_51_320q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_176m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_52_319q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_175m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_53_318q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_174m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_54_317q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_55_316q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_56_315q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_57_314q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_58_313q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_59_312q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_5_366q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_222m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_60_311q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_167m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_61_310q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_166m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_62_309q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_165m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_63_308q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_164m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_64_307q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_163m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_65_306q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_162m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_66_305q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_161m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_67_304q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_160m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_68_303q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_159m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_69_302q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_158m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_6_365q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_221m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_70_301q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_157m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_71_300q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_156m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_7_364q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_220m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_8_363q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_219m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_9_362q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_218m_dataout;
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_156m_dataout <= in_startofpacket WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_71_517q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_157m_dataout <= in_endofpacket WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_70_518q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_158m_dataout <= in_data(69) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_69_519q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_159m_dataout <= in_data(68) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_68_520q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_160m_dataout <= in_data(67) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_67_521q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_161m_dataout <= in_data(66) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_66_522q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_162m_dataout <= in_data(65) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_65_523q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_163m_dataout <= in_data(64) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_64_524q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_164m_dataout <= in_data(63) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_63_525q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_165m_dataout <= in_data(62) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_62_526q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_166m_dataout <= in_data(61) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_61_527q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_167m_dataout <= in_data(60) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_60_528q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout <= in_data(59) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_59_529q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout <= in_data(58) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_58_530q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout <= in_data(57) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_57_531q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout <= in_data(56) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_56_532q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout <= in_data(55) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_55_533q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout <= in_data(54) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_54_534q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_174m_dataout <= in_data(53) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_53_535q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_175m_dataout <= in_data(52) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_52_536q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_176m_dataout <= in_data(51) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_51_537q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_177m_dataout <= in_data(50) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_50_538q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout <= in_data(49) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_49_539q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout <= in_data(48) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_48_540q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout <= in_data(47) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_47_541q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout <= in_data(46) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_46_542q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout <= in_data(45) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_45_543q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout <= in_data(44) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_44_544q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_184m_dataout <= in_data(43) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_43_545q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_185m_dataout <= in_data(42) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_42_546q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_186m_dataout <= in_data(41) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_41_547q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_187m_dataout <= in_data(40) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_40_548q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_188m_dataout <= in_data(39) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_39_549q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_189m_dataout <= in_data(38) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_38_550q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_190m_dataout <= in_data(37) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_37_551q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_191m_dataout <= in_data(36) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_36_552q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_192m_dataout <= in_data(35) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_35_553q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_193m_dataout <= in_data(34) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_34_554q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_194m_dataout <= in_data(33) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_33_555q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_195m_dataout <= in_data(32) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_32_556q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_196m_dataout <= in_data(31) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_31_557q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_197m_dataout <= in_data(30) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_30_558q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_198m_dataout <= in_data(29) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_29_559q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_199m_dataout <= in_data(28) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_28_560q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_200m_dataout <= in_data(27) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_27_561q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_201m_dataout <= in_data(26) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_26_562q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_202m_dataout <= in_data(25) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_25_563q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_203m_dataout <= in_data(24) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_24_564q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_204m_dataout <= in_data(23) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_23_565q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_205m_dataout <= in_data(22) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_22_566q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_206m_dataout <= in_data(21) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_21_567q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_207m_dataout <= in_data(20) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_20_568q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_208m_dataout <= in_data(19) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_19_569q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_209m_dataout <= in_data(18) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_18_570q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_210m_dataout <= in_data(17) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_17_571q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_211m_dataout <= in_data(16) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_16_572q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_212m_dataout <= in_data(15) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_15_573q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_213m_dataout <= in_data(14) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_14_574q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_214m_dataout <= in_data(13) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_13_575q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_215m_dataout <= in_data(12) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_12_576q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_216m_dataout <= in_data(11) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_11_577q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_217m_dataout <= in_data(10) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_10_578q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_218m_dataout <= in_data(9) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_9_579q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_219m_dataout <= in_data(8) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_8_580q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_220m_dataout <= in_data(7) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_7_581q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_221m_dataout <= in_data(6) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_6_582q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_222m_dataout <= in_data(5) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_5_583q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_223m_dataout <= in_data(4) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_4_584q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_224m_dataout <= in_data(3) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_3_585q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_225m_dataout <= in_data(2) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_2_586q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_226m_dataout <= in_data(1) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_1_587q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_227m_dataout <= in_data(0) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_0_588q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_372m_dataout <= in_startofpacket WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_71_589q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_373m_dataout <= in_endofpacket WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_70_590q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_374m_dataout <= in_data(69) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_69_591q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_375m_dataout <= in_data(68) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_68_592q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_376m_dataout <= in_data(67) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_67_593q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_377m_dataout <= in_data(66) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_66_594q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_378m_dataout <= in_data(65) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_65_595q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_379m_dataout <= in_data(64) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_64_596q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_380m_dataout <= in_data(63) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_63_597q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_381m_dataout <= in_data(62) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_62_598q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_382m_dataout <= in_data(61) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_61_599q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_383m_dataout <= in_data(60) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_60_600q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_384m_dataout <= in_data(59) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_59_601q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_385m_dataout <= in_data(58) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_58_602q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_386m_dataout <= in_data(57) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_57_603q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_387m_dataout <= in_data(56) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_56_604q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_388m_dataout <= in_data(55) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_55_605q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_389m_dataout <= in_data(54) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_54_606q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_390m_dataout <= in_data(53) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_53_607q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_391m_dataout <= in_data(52) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_52_608q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_392m_dataout <= in_data(51) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_51_609q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_393m_dataout <= in_data(50) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_50_610q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_394m_dataout <= in_data(49) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_49_611q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_395m_dataout <= in_data(48) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_48_612q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_396m_dataout <= in_data(47) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_47_613q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_397m_dataout <= in_data(46) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_46_614q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_398m_dataout <= in_data(45) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_45_615q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_399m_dataout <= in_data(44) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_44_616q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_400m_dataout <= in_data(43) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_43_617q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_401m_dataout <= in_data(42) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_42_618q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_402m_dataout <= in_data(41) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_41_619q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_403m_dataout <= in_data(40) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_40_620q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_404m_dataout <= in_data(39) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_39_621q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_405m_dataout <= in_data(38) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_38_622q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_406m_dataout <= in_data(37) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_37_623q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_407m_dataout <= in_data(36) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_36_624q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_408m_dataout <= in_data(35) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_35_625q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_409m_dataout <= in_data(34) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_34_626q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_410m_dataout <= in_data(33) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_33_627q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_411m_dataout <= in_data(32) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_32_628q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_412m_dataout <= in_data(31) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_31_629q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_413m_dataout <= in_data(30) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_30_630q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_414m_dataout <= in_data(29) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_29_631q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_415m_dataout <= in_data(28) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_28_632q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_416m_dataout <= in_data(27) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_27_633q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_417m_dataout <= in_data(26) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_26_634q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_418m_dataout <= in_data(25) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_25_635q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_419m_dataout <= in_data(24) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_24_636q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_420m_dataout <= in_data(23) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_23_637q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_421m_dataout <= in_data(22) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_22_638q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_422m_dataout <= in_data(21) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_21_639q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_423m_dataout <= in_data(20) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_20_640q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_424m_dataout <= in_data(19) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_19_641q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_425m_dataout <= in_data(18) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_18_642q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_426m_dataout <= in_data(17) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_17_643q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_427m_dataout <= in_data(16) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_16_644q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_428m_dataout <= in_data(15) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_15_645q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_429m_dataout <= in_data(14) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_14_646q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_430m_dataout <= in_data(13) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_13_647q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_431m_dataout <= in_data(12) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_12_648q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_432m_dataout <= in_data(11) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_11_649q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_433m_dataout <= in_data(10) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_10_650q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_434m_dataout <= in_data(9) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_9_651q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_435m_dataout <= in_data(8) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_8_652q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_436m_dataout <= in_data(7) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_7_653q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_437m_dataout <= in_data(6) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_6_654q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_438m_dataout <= in_data(5) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_5_655q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_439m_dataout <= in_data(4) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_4_656q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_440m_dataout <= in_data(3) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_3_657q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_441m_dataout <= in_data(2) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_2_658q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_442m_dataout <= in_data(1) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_1_659q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_443m_dataout <= in_data(0) WHEN wire_ni_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_2_0_667q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_969m_dataout <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_665m_dataout WHEN s_wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_always3_663_dataout = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_670q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_2_970m_dataout <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_668m_dataout WHEN s_wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_always3_663_dataout = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_2_674q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_664m_dataout <= altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_1_711q WHEN s_wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_read_660_dataout = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_670q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_665m_dataout <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_664m_dataout OR s_wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_write_662_dataout;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_668m_dataout <= altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_1_711q AND s_wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_write_662_dataout;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_671m_dataout <= altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_2_674q WHEN s_wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_read_660_dataout = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_1_711q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_672m_dataout <= altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_670q WHEN s_wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_write_662_dataout = '1' ELSE wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_671m_dataout;
+
+ END RTL; --altera_avalon_sc_fifo_0003
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0004.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0004.vho
new file mode 100644
index 0000000000000000000000000000000000000000..989baf850fd0b53ee9f3efb8a2ea2264cb61d766
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0004.vho
@@ -0,0 +1,688 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources = lut 146 mux21 77
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_avalon_sc_fifo_0004 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ in_data : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
+ in_endofpacket : IN STD_LOGIC;
+ in_ready : OUT STD_LOGIC;
+ in_startofpacket : IN STD_LOGIC;
+ in_valid : IN STD_LOGIC;
+ out_data : OUT STD_LOGIC_VECTOR (69 DOWNTO 0);
+ out_endofpacket : OUT STD_LOGIC;
+ out_ready : IN STD_LOGIC;
+ out_startofpacket : OUT STD_LOGIC;
+ out_valid : OUT STD_LOGIC;
+ reset : IN STD_LOGIC
+ );
+ END altera_avalon_sc_fifo_0004;
+
+ ARCHITECTURE RTL OF altera_avalon_sc_fifo_0004 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_0_449q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_10_432q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_11_431q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_12_430q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_13_429q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_14_428q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_15_427q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_16_426q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_17_425q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_18_424q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_19_423q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_1_441q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_20_422q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_21_421q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_22_420q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_23_419q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_24_418q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_25_417q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_26_416q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_27_415q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_28_414q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_29_413q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_2_440q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_30_412q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_31_411q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_32_410q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_33_409q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_34_408q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_35_407q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_36_406q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_37_405q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_38_404q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_39_403q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_3_439q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_40_402q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_41_401q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_42_400q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_43_399q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_44_398q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_45_397q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_46_396q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_47_395q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_48_394q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_49_393q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_4_438q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_50_392q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_51_391q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_52_390q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_53_389q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_54_388q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_55_387q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_56_386q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_57_385q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_58_384q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_59_383q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_5_437q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_60_382q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_61_381q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_62_380q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_63_379q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_64_378q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_65_377q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_66_376q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_67_375q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_68_374q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_69_373q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_6_436q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_70_372q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_71_371q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_7_435q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_8_434q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_9_433q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_452q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_1_489q : STD_LOGIC := '0';
+ SIGNAL wire_nl_w73w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w1w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_0_370q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_10_360q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_11_359q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_12_358q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_13_357q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_14_356q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_15_355q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_16_354q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_17_353q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_18_352q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_19_351q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_1_369q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_20_350q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_21_349q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_22_348q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_23_347q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_24_346q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_25_345q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_26_344q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_27_343q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_28_342q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_29_341q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_2_368q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_30_340q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_31_339q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_32_338q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_33_337q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_34_336q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_35_335q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_36_334q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_37_333q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_38_332q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_39_331q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_3_367q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_40_330q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_41_329q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_42_328q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_43_327q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_44_326q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_45_325q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_46_324q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_47_323q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_48_322q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_49_321q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_4_366q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_50_320q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_51_319q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_52_318q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_53_317q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_54_316q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_55_315q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_56_314q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_57_313q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_58_312q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_59_311q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_5_365q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_60_310q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_61_309q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_62_308q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_63_307q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_64_306q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_65_305q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_66_304q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_67_303q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_68_302q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_69_301q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_6_364q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_70_300q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_71_299q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_7_363q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_8_362q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_9_361q : STD_LOGIC := '0';
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_155m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_156m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_157m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_158m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_159m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_160m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_161m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_162m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_163m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_164m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_165m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_166m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_167m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_174m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_175m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_176m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_177m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_184m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_185m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_186m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_187m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_188m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_189m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_190m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_191m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_192m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_193m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_194m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_195m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_196m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_197m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_198m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_199m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_200m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_201m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_202m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_203m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_204m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_205m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_206m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_207m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_208m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_209m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_210m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_211m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_212m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_213m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_214m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_215m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_216m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_217m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_218m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_219m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_220m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_221m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_222m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_223m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_224m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_225m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_226m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_747m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_1_748m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_446m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_447m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_450m_dataout : STD_LOGIC;
+ SIGNAL wire_w_lg_reset145w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_always0_154_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_always2_445_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_read_442_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_write_444_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ BEGIN
+
+ wire_w_lg_reset145w(0) <= NOT reset;
+ in_ready <= wire_nl_w1w(0);
+ out_data <= ( altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_69_301q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_68_302q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_67_303q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_66_304q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_65_305q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_64_306q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_63_307q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_62_308q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_61_309q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_60_310q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_59_311q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_58_312q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_57_313q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_56_314q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_55_315q
+ & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_54_316q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_53_317q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_52_318q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_51_319q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_50_320q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_49_321q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_48_322q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_47_323q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_46_324q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_45_325q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_44_326q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_43_327q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_42_328q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_41_329q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_40_330q
+ & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_39_331q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_38_332q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_37_333q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_36_334q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_35_335q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_34_336q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_33_337q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_32_338q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_31_339q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_30_340q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_29_341q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_28_342q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_27_343q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_26_344q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_25_345q
+ & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_24_346q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_23_347q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_22_348q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_21_349q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_20_350q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_19_351q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_18_352q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_17_353q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_16_354q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_15_355q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_14_356q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_13_357q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_12_358q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_11_359q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_10_360q
+ & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_9_361q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_8_362q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_7_363q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_6_364q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_5_365q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_4_366q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_3_367q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_2_368q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_1_369q & altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_0_370q);
+ out_endofpacket <= altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_70_300q;
+ out_startofpacket <= altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_71_299q;
+ out_valid <= altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_452q;
+ s_wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_always0_154_dataout <= (s_wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_read_442_dataout OR wire_nl_w73w(0));
+ s_wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_always2_445_dataout <= (s_wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_read_442_dataout XOR s_wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_write_444_dataout);
+ s_wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_read_442_dataout <= (altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_452q AND (out_ready OR wire_nl_w73w(0)));
+ s_wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_write_444_dataout <= (in_valid AND wire_nl_w1w(0));
+ s_wire_vcc <= '1';
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_0_449q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_10_432q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_11_431q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_12_430q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_13_429q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_14_428q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_15_427q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_16_426q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_17_425q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_18_424q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_19_423q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_1_441q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_20_422q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_21_421q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_22_420q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_23_419q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_24_418q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_25_417q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_26_416q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_27_415q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_28_414q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_29_413q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_2_440q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_30_412q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_31_411q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_32_410q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_33_409q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_34_408q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_35_407q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_36_406q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_37_405q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_38_404q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_39_403q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_3_439q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_40_402q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_41_401q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_42_400q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_43_399q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_44_398q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_45_397q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_46_396q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_47_395q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_48_394q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_49_393q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_4_438q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_50_392q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_51_391q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_52_390q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_53_389q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_54_388q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_55_387q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_56_386q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_57_385q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_58_384q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_59_383q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_5_437q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_60_382q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_61_381q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_62_380q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_63_379q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_64_378q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_65_377q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_66_376q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_67_375q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_68_374q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_69_373q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_6_436q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_70_372q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_71_371q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_7_435q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_8_434q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_9_433q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_452q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_1_489q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_0_449q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_226m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_10_432q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_216m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_11_431q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_215m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_12_430q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_214m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_13_429q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_213m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_14_428q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_212m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_15_427q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_211m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_16_426q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_210m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_17_425q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_209m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_18_424q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_208m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_19_423q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_207m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_1_441q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_225m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_20_422q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_206m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_21_421q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_205m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_22_420q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_204m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_23_419q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_203m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_24_418q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_202m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_25_417q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_201m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_26_416q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_200m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_27_415q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_199m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_28_414q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_198m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_29_413q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_197m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_2_440q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_224m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_30_412q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_196m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_31_411q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_195m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_32_410q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_194m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_33_409q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_193m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_34_408q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_192m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_35_407q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_191m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_36_406q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_190m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_37_405q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_189m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_38_404q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_188m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_39_403q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_187m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_3_439q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_223m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_40_402q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_186m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_41_401q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_185m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_42_400q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_184m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_43_399q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_44_398q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_45_397q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_46_396q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_47_395q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_48_394q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_49_393q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_177m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_4_438q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_222m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_50_392q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_176m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_51_391q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_175m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_52_390q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_174m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_53_389q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_54_388q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_55_387q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_56_386q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_57_385q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_58_384q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_59_383q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_167m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_5_437q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_221m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_60_382q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_166m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_61_381q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_165m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_62_380q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_164m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_63_379q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_163m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_64_378q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_162m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_65_377q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_161m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_66_376q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_160m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_67_375q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_159m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_68_374q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_158m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_69_373q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_157m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_6_436q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_220m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_70_372q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_156m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_71_371q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_155m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_7_435q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_219m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_8_434q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_218m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_9_433q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_217m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_452q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_747m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_1_489q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_1_748m_dataout;
+ END IF;
+ END PROCESS;
+ wire_nl_w73w(0) <= NOT altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_452q;
+ wire_nl_w1w(0) <= NOT altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_1_489q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_0_370q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_10_360q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_11_359q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_12_358q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_13_357q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_14_356q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_15_355q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_16_354q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_17_353q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_18_352q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_19_351q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_1_369q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_20_350q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_21_349q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_22_348q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_23_347q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_24_346q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_25_345q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_26_344q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_27_343q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_28_342q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_29_341q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_2_368q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_30_340q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_31_339q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_32_338q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_33_337q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_34_336q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_35_335q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_36_334q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_37_333q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_38_332q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_39_331q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_3_367q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_40_330q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_41_329q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_42_328q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_43_327q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_44_326q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_45_325q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_46_324q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_47_323q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_48_322q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_49_321q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_4_366q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_50_320q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_51_319q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_52_318q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_53_317q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_54_316q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_55_315q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_56_314q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_57_313q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_58_312q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_59_311q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_5_365q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_60_310q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_61_309q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_62_308q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_63_307q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_64_306q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_65_305q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_66_304q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_67_303q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_68_302q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_69_301q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_6_364q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_70_300q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_71_299q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_7_363q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_8_362q <= '0';
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_9_361q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_always0_154_dataout = '1') THEN
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_0_370q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_226m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_10_360q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_216m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_11_359q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_215m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_12_358q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_214m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_13_357q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_213m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_14_356q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_212m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_15_355q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_211m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_16_354q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_210m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_17_353q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_209m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_18_352q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_208m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_19_351q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_207m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_1_369q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_225m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_20_350q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_206m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_21_349q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_205m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_22_348q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_204m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_23_347q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_203m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_24_346q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_202m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_25_345q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_201m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_26_344q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_200m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_27_343q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_199m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_28_342q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_198m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_29_341q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_197m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_2_368q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_224m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_30_340q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_196m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_31_339q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_195m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_32_338q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_194m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_33_337q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_193m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_34_336q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_192m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_35_335q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_191m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_36_334q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_190m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_37_333q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_189m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_38_332q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_188m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_39_331q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_187m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_3_367q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_223m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_40_330q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_186m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_41_329q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_185m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_42_328q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_184m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_43_327q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_44_326q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_45_325q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_46_324q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_47_323q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_48_322q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_49_321q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_177m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_4_366q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_222m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_50_320q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_176m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_51_319q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_175m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_52_318q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_174m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_53_317q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_54_316q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_55_315q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_56_314q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_57_313q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_58_312q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_59_311q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_167m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_5_365q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_221m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_60_310q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_166m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_61_309q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_165m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_62_308q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_164m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_63_307q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_163m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_64_306q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_162m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_65_305q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_161m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_66_304q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_160m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_67_303q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_159m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_68_302q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_158m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_69_301q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_157m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_6_364q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_220m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_70_300q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_156m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_71_299q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_155m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_7_363q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_219m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_8_362q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_218m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_9_361q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_217m_dataout;
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_155m_dataout <= in_startofpacket WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_71_371q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_156m_dataout <= in_endofpacket WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_70_372q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_157m_dataout <= in_data(69) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_69_373q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_158m_dataout <= in_data(68) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_68_374q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_159m_dataout <= in_data(67) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_67_375q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_160m_dataout <= in_data(66) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_66_376q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_161m_dataout <= in_data(65) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_65_377q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_162m_dataout <= in_data(64) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_64_378q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_163m_dataout <= in_data(63) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_63_379q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_164m_dataout <= in_data(62) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_62_380q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_165m_dataout <= in_data(61) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_61_381q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_166m_dataout <= in_data(60) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_60_382q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_167m_dataout <= in_data(59) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_59_383q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout <= in_data(58) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_58_384q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout <= in_data(57) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_57_385q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout <= in_data(56) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_56_386q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout <= in_data(55) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_55_387q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout <= in_data(54) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_54_388q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout <= in_data(53) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_53_389q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_174m_dataout <= in_data(52) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_52_390q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_175m_dataout <= in_data(51) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_51_391q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_176m_dataout <= in_data(50) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_50_392q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_177m_dataout <= in_data(49) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_49_393q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout <= in_data(48) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_48_394q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout <= in_data(47) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_47_395q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout <= in_data(46) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_46_396q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout <= in_data(45) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_45_397q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout <= in_data(44) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_44_398q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout <= in_data(43) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_43_399q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_184m_dataout <= in_data(42) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_42_400q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_185m_dataout <= in_data(41) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_41_401q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_186m_dataout <= in_data(40) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_40_402q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_187m_dataout <= in_data(39) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_39_403q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_188m_dataout <= in_data(38) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_38_404q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_189m_dataout <= in_data(37) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_37_405q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_190m_dataout <= in_data(36) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_36_406q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_191m_dataout <= in_data(35) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_35_407q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_192m_dataout <= in_data(34) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_34_408q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_193m_dataout <= in_data(33) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_33_409q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_194m_dataout <= in_data(32) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_32_410q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_195m_dataout <= in_data(31) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_31_411q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_196m_dataout <= in_data(30) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_30_412q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_197m_dataout <= in_data(29) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_29_413q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_198m_dataout <= in_data(28) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_28_414q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_199m_dataout <= in_data(27) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_27_415q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_200m_dataout <= in_data(26) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_26_416q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_201m_dataout <= in_data(25) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_25_417q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_202m_dataout <= in_data(24) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_24_418q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_203m_dataout <= in_data(23) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_23_419q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_204m_dataout <= in_data(22) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_22_420q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_205m_dataout <= in_data(21) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_21_421q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_206m_dataout <= in_data(20) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_20_422q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_207m_dataout <= in_data(19) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_19_423q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_208m_dataout <= in_data(18) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_18_424q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_209m_dataout <= in_data(17) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_17_425q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_210m_dataout <= in_data(16) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_16_426q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_211m_dataout <= in_data(15) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_15_427q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_212m_dataout <= in_data(14) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_14_428q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_213m_dataout <= in_data(13) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_13_429q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_214m_dataout <= in_data(12) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_12_430q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_215m_dataout <= in_data(11) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_11_431q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_216m_dataout <= in_data(10) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_10_432q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_217m_dataout <= in_data(9) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_9_433q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_218m_dataout <= in_data(8) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_8_434q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_219m_dataout <= in_data(7) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_7_435q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_220m_dataout <= in_data(6) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_6_436q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_221m_dataout <= in_data(5) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_5_437q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_222m_dataout <= in_data(4) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_4_438q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_223m_dataout <= in_data(3) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_3_439q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_224m_dataout <= in_data(2) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_2_440q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_225m_dataout <= in_data(1) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_1_441q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_226m_dataout <= in_data(0) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_0_449q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_747m_dataout <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_447m_dataout WHEN s_wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_always2_445_dataout = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_452q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_1_748m_dataout <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_450m_dataout WHEN s_wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_always2_445_dataout = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_1_489q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_446m_dataout <= altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_1_489q WHEN s_wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_read_442_dataout = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_452q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_447m_dataout <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_446m_dataout OR s_wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_write_444_dataout;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_450m_dataout <= altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_used_0_452q AND s_wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_write_444_dataout;
+
+ END RTL; --altera_avalon_sc_fifo_0004
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_st_delay/altera_avalon_st_delay_0001.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_st_delay/altera_avalon_st_delay_0001.vho
new file mode 100644
index 0000000000000000000000000000000000000000..3a476e14dd36695404e1033eb9f45bf851a01d5b
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_st_delay/altera_avalon_st_delay_0001.vho
@@ -0,0 +1,261 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources = lut 96 mux21 2
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_avalon_st_delay_0001 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ in0_data : IN STD_LOGIC_VECTOR (39 DOWNTO 0);
+ in0_error : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+ in0_valid : IN STD_LOGIC;
+ out0_data : OUT STD_LOGIC_VECTOR (39 DOWNTO 0);
+ out0_error : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
+ out0_valid : OUT STD_LOGIC;
+ reset_n : IN STD_LOGIC
+ );
+ END altera_avalon_st_delay_0001;
+
+ ARCHITECTURE RTL OF altera_avalon_st_delay_0001 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_0_379q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_10_389q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_11_390q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_12_391q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_13_392q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_14_393q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_15_394q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_16_395q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_17_396q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_18_397q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_19_398q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_1_380q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_20_399q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_21_400q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_22_401q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_23_402q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_24_403q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_25_404q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_26_405q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_27_406q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_28_407q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_29_408q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_2_381q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_30_409q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_31_410q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_32_411q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_33_412q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_34_413q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_35_414q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_36_415q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_37_416q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_38_417q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_39_418q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_3_382q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_4_383q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_5_384q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_6_385q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_7_386q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_8_387q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_9_388q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_error_0_371q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_error_1_372q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_error_2_373q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_error_3_374q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_error_4_375q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_error_5_376q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_error_6_377q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_valid_367q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_0_538q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_10_548q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_11_549q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_12_550q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_13_551q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_14_552q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_15_553q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_16_554q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_17_555q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_18_556q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_19_557q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_1_539q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_20_558q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_21_559q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_22_560q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_23_561q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_24_562q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_25_563q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_26_564q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_27_565q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_28_566q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_29_567q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_2_540q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_30_568q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_31_569q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_32_570q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_33_571q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_34_572q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_35_573q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_36_574q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_37_575q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_38_576q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_39_577q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_3_541q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_4_542q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_5_543q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_6_544q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_7_545q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_8_546q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_9_547q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_error_0_530q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_error_1_531q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_error_2_532q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_error_3_533q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_error_4_534q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_error_5_535q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_error_6_536q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_valid_526q : STD_LOGIC := '0';
+ SIGNAL wire_altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_valid_366m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_valid_525m_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ BEGIN
+
+ out0_data <= ( altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_39_577q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_38_576q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_37_575q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_36_574q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_35_573q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_34_572q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_33_571q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_32_570q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_31_569q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_30_568q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_29_567q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_28_566q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_27_565q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_26_564q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_25_563q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_24_562q
+ & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_23_561q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_22_560q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_21_559q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_20_558q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_19_557q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_18_556q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_17_555q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_16_554q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_15_553q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_14_552q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_13_551q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_12_550q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_11_549q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_10_548q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_9_547q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_8_546q
+ & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_7_545q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_6_544q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_5_543q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_4_542q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_3_541q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_2_540q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_1_539q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_0_538q);
+ out0_error <= ( altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_error_6_536q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_error_5_535q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_error_4_534q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_error_3_533q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_error_2_532q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_error_1_531q & altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_error_0_530q);
+ out0_valid <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_valid_526q;
+ s_wire_vcc <= '1';
+ PROCESS (clk)
+ BEGIN
+ IF (clk = '1' AND clk'event) THEN
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_0_379q <= in0_data(0);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_10_389q <= in0_data(10);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_11_390q <= in0_data(11);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_12_391q <= in0_data(12);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_13_392q <= in0_data(13);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_14_393q <= in0_data(14);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_15_394q <= in0_data(15);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_16_395q <= in0_data(16);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_17_396q <= in0_data(17);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_18_397q <= in0_data(18);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_19_398q <= in0_data(19);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_1_380q <= in0_data(1);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_20_399q <= in0_data(20);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_21_400q <= in0_data(21);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_22_401q <= in0_data(22);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_23_402q <= in0_data(23);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_24_403q <= in0_data(24);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_25_404q <= in0_data(25);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_26_405q <= in0_data(26);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_27_406q <= in0_data(27);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_28_407q <= in0_data(28);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_29_408q <= in0_data(29);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_2_381q <= in0_data(2);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_30_409q <= in0_data(30);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_31_410q <= in0_data(31);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_32_411q <= in0_data(32);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_33_412q <= in0_data(33);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_34_413q <= in0_data(34);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_35_414q <= in0_data(35);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_36_415q <= in0_data(36);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_37_416q <= in0_data(37);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_38_417q <= in0_data(38);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_39_418q <= in0_data(39);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_3_382q <= in0_data(3);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_4_383q <= in0_data(4);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_5_384q <= in0_data(5);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_6_385q <= in0_data(6);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_7_386q <= in0_data(7);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_8_387q <= in0_data(8);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_9_388q <= in0_data(9);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_error_0_371q <= in0_error(0);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_error_1_372q <= in0_error(1);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_error_2_373q <= in0_error(2);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_error_3_374q <= in0_error(3);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_error_4_375q <= in0_error(4);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_error_5_376q <= in0_error(5);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_error_6_377q <= in0_error(6);
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_valid_367q <= wire_altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_valid_366m_dataout;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_0_538q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_0_379q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_10_548q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_10_389q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_11_549q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_11_390q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_12_550q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_12_391q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_13_551q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_13_392q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_14_552q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_14_393q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_15_553q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_15_394q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_16_554q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_16_395q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_17_555q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_17_396q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_18_556q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_18_397q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_19_557q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_19_398q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_1_539q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_1_380q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_20_558q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_20_399q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_21_559q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_21_400q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_22_560q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_22_401q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_23_561q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_23_402q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_24_562q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_24_403q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_25_563q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_25_404q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_26_564q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_26_405q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_27_565q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_27_406q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_28_566q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_28_407q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_29_567q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_29_408q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_2_540q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_2_381q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_30_568q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_30_409q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_31_569q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_31_410q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_32_570q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_32_411q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_33_571q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_33_412q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_34_572q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_34_413q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_35_573q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_35_414q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_36_574q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_36_415q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_37_575q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_37_416q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_38_576q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_38_417q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_39_577q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_39_418q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_3_541q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_3_382q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_4_542q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_4_383q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_5_543q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_5_384q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_6_544q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_6_385q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_7_545q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_7_386q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_8_546q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_8_387q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_data_9_547q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_data_9_388q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_error_0_530q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_error_0_371q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_error_1_531q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_error_1_372q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_error_2_532q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_error_2_373q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_error_3_533q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_error_3_374q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_error_4_534q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_error_4_375q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_error_5_535q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_error_5_376q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_error_6_536q <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_error_6_377q;
+ altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_valid_526q <= wire_altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_valid_525m_dataout;
+ END IF;
+ END PROCESS;
+ wire_altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_valid_366m_dataout <= in0_valid AND reset_n;
+ wire_altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_1_u_out_valid_525m_dataout <= altera_avalon_st_delay_0001_altera_avalon_st_delay_rx_st_status_output_delay_altera_st_delay_reg_delay_port_0_u_out_valid_367q AND reset_n;
+
+ END RTL; --altera_avalon_st_delay_0001
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_st_delay/altera_avalon_st_delay_0002.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_st_delay/altera_avalon_st_delay_0002.vho
new file mode 100644
index 0000000000000000000000000000000000000000..ea63c59a4b5b9c1a33379f927a405f97d922ab94
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_st_delay/altera_avalon_st_delay_0002.vho
@@ -0,0 +1,163 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources = lut 48 mux21 1
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_avalon_st_delay_0002 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ in0_data : IN STD_LOGIC_VECTOR (39 DOWNTO 0);
+ in0_error : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+ in0_valid : IN STD_LOGIC;
+ out0_data : OUT STD_LOGIC_VECTOR (39 DOWNTO 0);
+ out0_error : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
+ out0_valid : OUT STD_LOGIC;
+ reset_n : IN STD_LOGIC
+ );
+ END altera_avalon_st_delay_0002;
+
+ ARCHITECTURE RTL OF altera_avalon_st_delay_0002 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_0_326q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_10_336q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_11_337q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_12_338q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_13_339q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_14_340q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_15_341q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_16_342q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_17_343q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_18_344q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_19_345q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_1_327q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_20_346q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_21_347q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_22_348q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_23_349q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_24_350q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_25_351q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_26_352q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_27_353q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_28_354q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_29_355q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_2_328q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_30_356q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_31_357q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_32_358q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_33_359q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_34_360q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_35_361q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_36_362q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_37_363q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_38_364q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_39_365q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_3_329q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_4_330q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_5_331q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_6_332q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_7_333q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_8_334q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_9_335q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_error_0_318q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_error_1_319q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_error_2_320q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_error_3_321q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_error_4_322q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_error_5_323q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_error_6_324q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_valid_314q : STD_LOGIC := '0';
+ SIGNAL wire_altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_valid_313m_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ BEGIN
+
+ out0_data <= ( altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_39_365q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_38_364q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_37_363q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_36_362q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_35_361q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_34_360q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_33_359q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_32_358q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_31_357q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_30_356q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_29_355q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_28_354q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_27_353q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_26_352q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_25_351q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_24_350q
+ & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_23_349q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_22_348q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_21_347q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_20_346q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_19_345q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_18_344q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_17_343q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_16_342q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_15_341q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_14_340q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_13_339q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_12_338q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_11_337q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_10_336q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_9_335q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_8_334q
+ & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_7_333q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_6_332q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_5_331q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_4_330q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_3_329q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_2_328q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_1_327q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_0_326q);
+ out0_error <= ( altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_error_6_324q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_error_5_323q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_error_4_322q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_error_3_321q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_error_2_320q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_error_1_319q & altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_error_0_318q);
+ out0_valid <= altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_valid_314q;
+ s_wire_vcc <= '1';
+ PROCESS (clk)
+ BEGIN
+ IF (clk = '1' AND clk'event) THEN
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_0_326q <= in0_data(0);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_10_336q <= in0_data(10);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_11_337q <= in0_data(11);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_12_338q <= in0_data(12);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_13_339q <= in0_data(13);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_14_340q <= in0_data(14);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_15_341q <= in0_data(15);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_16_342q <= in0_data(16);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_17_343q <= in0_data(17);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_18_344q <= in0_data(18);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_19_345q <= in0_data(19);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_1_327q <= in0_data(1);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_20_346q <= in0_data(20);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_21_347q <= in0_data(21);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_22_348q <= in0_data(22);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_23_349q <= in0_data(23);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_24_350q <= in0_data(24);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_25_351q <= in0_data(25);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_26_352q <= in0_data(26);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_27_353q <= in0_data(27);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_28_354q <= in0_data(28);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_29_355q <= in0_data(29);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_2_328q <= in0_data(2);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_30_356q <= in0_data(30);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_31_357q <= in0_data(31);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_32_358q <= in0_data(32);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_33_359q <= in0_data(33);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_34_360q <= in0_data(34);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_35_361q <= in0_data(35);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_36_362q <= in0_data(36);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_37_363q <= in0_data(37);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_38_364q <= in0_data(38);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_39_365q <= in0_data(39);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_3_329q <= in0_data(3);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_4_330q <= in0_data(4);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_5_331q <= in0_data(5);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_6_332q <= in0_data(6);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_7_333q <= in0_data(7);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_8_334q <= in0_data(8);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_data_9_335q <= in0_data(9);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_error_0_318q <= in0_error(0);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_error_1_319q <= in0_error(1);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_error_2_320q <= in0_error(2);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_error_3_321q <= in0_error(3);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_error_4_322q <= in0_error(4);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_error_5_323q <= in0_error(5);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_error_6_324q <= in0_error(6);
+ altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_valid_314q <= wire_altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_valid_313m_dataout;
+ END IF;
+ END PROCESS;
+ wire_altera_avalon_st_delay_0002_altera_avalon_st_delay_rx_st_status_statistics_delay_altera_st_delay_reg_delay_port_0_u_out_valid_313m_dataout <= in0_valid AND reset_n;
+
+ END RTL; --altera_avalon_st_delay_0002
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser_0001.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser_0001.vho
new file mode 100644
index 0000000000000000000000000000000000000000..845e680e63893fb432bb88f19e49079bfd10a0d4
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser_0001.vho
@@ -0,0 +1,567 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+ LIBRARY altera_mf;
+ USE altera_mf.altera_mf_components.all;
+
+--synthesis_resources = altera_std_synchronizer 2 lut 142 mux21 2
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_avalon_st_handshake_clock_crosser_0001 IS
+ PORT
+ (
+ in_channel : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+ in_clk : IN STD_LOGIC;
+ in_data : IN STD_LOGIC_VECTOR (65 DOWNTO 0);
+ in_endofpacket : IN STD_LOGIC;
+ in_ready : OUT STD_LOGIC;
+ in_reset : IN STD_LOGIC;
+ in_startofpacket : IN STD_LOGIC;
+ in_valid : IN STD_LOGIC;
+ out_channel : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+ out_clk : IN STD_LOGIC;
+ out_data : OUT STD_LOGIC_VECTOR (65 DOWNTO 0);
+ out_endofpacket : OUT STD_LOGIC;
+ out_ready : IN STD_LOGIC;
+ out_reset : IN STD_LOGIC;
+ out_startofpacket : OUT STD_LOGIC;
+ out_valid : OUT STD_LOGIC
+ );
+ END altera_avalon_st_handshake_clock_crosser_0001;
+
+ ARCHITECTURE RTL OF altera_avalon_st_handshake_clock_crosser_0001 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL wire_altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_altera_std_synchronizer_in_to_out_synchronizer_985_dout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_altera_std_synchronizer_in_to_out_synchronizer_985_reset_n : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_altera_std_synchronizer_out_to_in_synchronizer_984_dout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_altera_std_synchronizer_out_to_in_synchronizer_984_reset_n : STD_LOGIC;
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_0_816q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_10_802q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_11_801q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_12_800q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_13_799q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_14_798q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_15_797q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_16_796q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_17_795q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_18_794q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_19_793q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_1_811q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_20_792q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_21_791q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_22_790q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_23_789q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_24_788q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_25_787q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_26_786q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_27_785q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_28_784q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_29_783q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_2_810q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_30_782q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_31_781q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_32_780q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_33_779q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_34_778q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_35_777q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_36_776q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_37_775q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_38_774q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_39_773q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_3_809q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_40_772q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_41_771q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_42_770q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_43_769q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_44_768q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_45_767q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_46_766q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_47_765q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_48_764q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_49_763q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_4_808q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_50_762q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_51_761q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_52_760q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_53_759q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_54_758q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_55_757q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_56_756q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_57_755q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_58_754q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_59_753q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_5_807q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_60_752q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_61_751q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_62_750q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_63_749q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_64_748q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_65_747q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_66_746q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_67_745q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_68_744q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_69_743q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_6_806q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_7_805q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_8_804q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_9_803q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_toggle_flopped_742q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_toggle_671q : STD_LOGIC := '0';
+ SIGNAL wire_nl_w75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_0_668q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_10_658q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_11_657q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_12_656q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_13_655q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_14_654q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_15_653q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_16_652q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_17_651q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_18_650q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_19_649q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_1_667q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_20_648q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_21_647q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_22_646q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_23_645q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_24_644q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_25_643q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_26_642q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_27_641q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_28_640q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_29_639q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_2_666q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_30_638q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_31_637q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_32_636q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_33_635q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_34_634q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_35_633q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_36_632q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_37_631q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_38_630q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_39_629q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_3_665q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_40_628q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_41_627q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_42_626q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_43_625q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_44_624q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_45_623q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_46_622q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_47_621q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_48_620q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_49_619q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_4_664q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_50_618q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_51_617q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_52_616q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_53_615q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_54_614q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_55_613q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_56_612q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_57_611q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_58_610q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_59_609q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_5_663q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_60_608q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_61_607q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_62_606q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_63_605q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_64_604q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_65_603q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_66_602q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_67_601q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_68_600q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_69_599q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_6_662q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_7_661q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_8_660q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_9_659q : STD_LOGIC := '0';
+ SIGNAL wire_altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_toggle_458m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_toggle_flopped_669m_dataout : STD_LOGIC;
+ SIGNAL wire_w_lg_in_reset77w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_out_reset146w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_ready_452_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_valid_455_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_take_in_data_454_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ BEGIN
+
+ wire_w_lg_in_reset77w(0) <= NOT in_reset;
+ wire_w_lg_out_reset146w(0) <= NOT out_reset;
+ wire_w1w(0) <= NOT s_wire_altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_ready_452_dataout;
+ in_ready <= wire_w1w(0);
+ out_channel <= ( altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_69_743q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_68_744q);
+ out_data <= ( altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_65_747q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_64_748q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_63_749q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_62_750q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_61_751q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_60_752q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_59_753q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_58_754q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_57_755q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_56_756q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_55_757q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_54_758q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_53_759q
+ & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_52_760q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_51_761q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_50_762q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_49_763q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_48_764q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_47_765q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_46_766q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_45_767q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_44_768q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_43_769q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_42_770q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_41_771q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_40_772q
+ & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_39_773q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_38_774q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_37_775q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_36_776q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_35_777q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_34_778q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_33_779q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_32_780q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_31_781q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_30_782q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_29_783q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_28_784q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_27_785q
+ & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_26_786q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_25_787q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_24_788q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_23_789q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_22_790q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_21_791q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_20_792q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_19_793q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_18_794q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_17_795q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_16_796q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_15_797q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_14_798q
+ & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_13_799q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_12_800q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_11_801q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_10_802q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_9_803q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_8_804q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_7_805q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_6_806q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_5_807q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_4_808q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_3_809q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_2_810q & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_1_811q
+ & altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_0_816q);
+ out_endofpacket <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_66_746q;
+ out_startofpacket <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_67_745q;
+ out_valid <= s_wire_altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_valid_455_dataout;
+ s_wire_altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_ready_452_dataout <= (altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_toggle_671q XOR wire_altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_altera_std_synchronizer_out_to_in_synchronizer_984_dout);
+ s_wire_altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_valid_455_dataout <= (altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_toggle_flopped_742q XOR wire_altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_altera_std_synchronizer_in_to_out_synchronizer_985_dout);
+ s_wire_altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_take_in_data_454_dataout <= (in_valid AND wire_w1w(0));
+ s_wire_vcc <= '1';
+ wire_altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_altera_std_synchronizer_in_to_out_synchronizer_985_reset_n <= wire_w_lg_out_reset146w(0);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_altera_std_synchronizer_in_to_out_synchronizer_985 : altera_std_synchronizer
+ GENERIC MAP (
+ depth => 2
+ )
+ PORT MAP (
+ clk => out_clk,
+ din => altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_toggle_671q,
+ dout => wire_altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_altera_std_synchronizer_in_to_out_synchronizer_985_dout,
+ reset_n => wire_altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_altera_std_synchronizer_in_to_out_synchronizer_985_reset_n
+ );
+ wire_altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_altera_std_synchronizer_out_to_in_synchronizer_984_reset_n <= wire_w_lg_in_reset77w(0);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_altera_std_synchronizer_out_to_in_synchronizer_984 : altera_std_synchronizer
+ GENERIC MAP (
+ depth => 2
+ )
+ PORT MAP (
+ clk => in_clk,
+ din => altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_toggle_flopped_742q,
+ dout => wire_altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_altera_std_synchronizer_out_to_in_synchronizer_984_dout,
+ reset_n => wire_altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_altera_std_synchronizer_out_to_in_synchronizer_984_reset_n
+ );
+ PROCESS (out_clk, out_reset)
+ BEGIN
+ IF (out_reset = '1') THEN
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_0_816q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_10_802q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_11_801q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_12_800q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_13_799q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_14_798q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_15_797q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_16_796q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_17_795q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_18_794q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_19_793q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_1_811q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_20_792q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_21_791q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_22_790q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_23_789q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_24_788q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_25_787q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_26_786q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_27_785q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_28_784q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_29_783q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_2_810q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_30_782q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_31_781q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_32_780q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_33_779q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_34_778q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_35_777q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_36_776q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_37_775q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_38_774q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_39_773q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_3_809q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_40_772q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_41_771q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_42_770q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_43_769q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_44_768q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_45_767q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_46_766q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_47_765q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_48_764q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_49_763q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_4_808q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_50_762q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_51_761q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_52_760q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_53_759q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_54_758q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_55_757q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_56_756q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_57_755q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_58_754q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_59_753q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_5_807q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_60_752q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_61_751q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_62_750q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_63_749q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_64_748q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_65_747q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_66_746q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_67_745q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_68_744q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_69_743q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_6_806q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_7_805q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_8_804q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_9_803q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_toggle_flopped_742q <= '0';
+ ELSIF (out_clk = '1' AND out_clk'event) THEN
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_0_816q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_0_668q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_10_802q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_10_658q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_11_801q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_11_657q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_12_800q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_12_656q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_13_799q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_13_655q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_14_798q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_14_654q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_15_797q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_15_653q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_16_796q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_16_652q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_17_795q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_17_651q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_18_794q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_18_650q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_19_793q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_19_649q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_1_811q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_1_667q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_20_792q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_20_648q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_21_791q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_21_647q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_22_790q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_22_646q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_23_789q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_23_645q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_24_788q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_24_644q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_25_787q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_25_643q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_26_786q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_26_642q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_27_785q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_27_641q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_28_784q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_28_640q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_29_783q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_29_639q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_2_810q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_2_666q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_30_782q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_30_638q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_31_781q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_31_637q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_32_780q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_32_636q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_33_779q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_33_635q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_34_778q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_34_634q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_35_777q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_35_633q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_36_776q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_36_632q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_37_775q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_37_631q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_38_774q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_38_630q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_39_773q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_39_629q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_3_809q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_3_665q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_40_772q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_40_628q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_41_771q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_41_627q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_42_770q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_42_626q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_43_769q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_43_625q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_44_768q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_44_624q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_45_767q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_45_623q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_46_766q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_46_622q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_47_765q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_47_621q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_48_764q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_48_620q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_49_763q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_49_619q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_4_808q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_4_664q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_50_762q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_50_618q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_51_761q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_51_617q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_52_760q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_52_616q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_53_759q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_53_615q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_54_758q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_54_614q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_55_757q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_55_613q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_56_756q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_56_612q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_57_755q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_57_611q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_58_754q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_58_610q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_59_753q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_59_609q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_5_807q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_5_663q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_60_752q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_60_608q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_61_751q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_61_607q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_62_750q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_62_606q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_63_749q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_63_605q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_64_748q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_64_604q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_65_747q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_65_603q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_66_746q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_66_602q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_67_745q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_67_601q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_68_744q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_68_600q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_69_743q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_69_599q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_6_806q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_6_662q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_7_805q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_7_661q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_8_804q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_8_660q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_buffer_9_803q <= altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_9_659q;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_toggle_flopped_742q <= wire_altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_toggle_flopped_669m_dataout;
+ END IF;
+ END PROCESS;
+ PROCESS (in_clk, in_reset)
+ BEGIN
+ IF (in_reset = '1') THEN
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_toggle_671q <= '0';
+ ELSIF (in_clk = '1' AND in_clk'event) THEN
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_toggle_671q <= wire_altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_toggle_458m_dataout;
+ END IF;
+ END PROCESS;
+ wire_nl_w75w(0) <= NOT altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_toggle_671q;
+ PROCESS (in_clk, in_reset)
+ BEGIN
+ IF (in_reset = '1') THEN
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_0_668q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_10_658q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_11_657q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_12_656q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_13_655q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_14_654q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_15_653q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_16_652q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_17_651q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_18_650q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_19_649q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_1_667q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_20_648q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_21_647q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_22_646q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_23_645q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_24_644q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_25_643q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_26_642q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_27_641q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_28_640q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_29_639q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_2_666q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_30_638q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_31_637q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_32_636q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_33_635q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_34_634q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_35_633q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_36_632q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_37_631q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_38_630q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_39_629q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_3_665q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_40_628q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_41_627q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_42_626q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_43_625q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_44_624q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_45_623q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_46_622q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_47_621q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_48_620q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_49_619q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_4_664q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_50_618q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_51_617q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_52_616q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_53_615q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_54_614q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_55_613q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_56_612q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_57_611q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_58_610q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_59_609q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_5_663q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_60_608q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_61_607q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_62_606q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_63_605q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_64_604q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_65_603q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_66_602q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_67_601q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_68_600q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_69_599q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_6_662q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_7_661q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_8_660q <= '0';
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_9_659q <= '0';
+ ELSIF (in_clk = '1' AND in_clk'event) THEN
+ IF (s_wire_altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_take_in_data_454_dataout = '1') THEN
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_0_668q <= in_data(0);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_10_658q <= in_data(10);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_11_657q <= in_data(11);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_12_656q <= in_data(12);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_13_655q <= in_data(13);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_14_654q <= in_data(14);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_15_653q <= in_data(15);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_16_652q <= in_data(16);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_17_651q <= in_data(17);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_18_650q <= in_data(18);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_19_649q <= in_data(19);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_1_667q <= in_data(1);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_20_648q <= in_data(20);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_21_647q <= in_data(21);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_22_646q <= in_data(22);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_23_645q <= in_data(23);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_24_644q <= in_data(24);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_25_643q <= in_data(25);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_26_642q <= in_data(26);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_27_641q <= in_data(27);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_28_640q <= in_data(28);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_29_639q <= in_data(29);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_2_666q <= in_data(2);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_30_638q <= in_data(30);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_31_637q <= in_data(31);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_32_636q <= in_data(32);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_33_635q <= in_data(33);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_34_634q <= in_data(34);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_35_633q <= in_data(35);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_36_632q <= in_data(36);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_37_631q <= in_data(37);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_38_630q <= in_data(38);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_39_629q <= in_data(39);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_3_665q <= in_data(3);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_40_628q <= in_data(40);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_41_627q <= in_data(41);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_42_626q <= in_data(42);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_43_625q <= in_data(43);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_44_624q <= in_data(44);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_45_623q <= in_data(45);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_46_622q <= in_data(46);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_47_621q <= in_data(47);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_48_620q <= in_data(48);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_49_619q <= in_data(49);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_4_664q <= in_data(4);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_50_618q <= in_data(50);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_51_617q <= in_data(51);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_52_616q <= in_data(52);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_53_615q <= in_data(53);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_54_614q <= in_data(54);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_55_613q <= in_data(55);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_56_612q <= in_data(56);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_57_611q <= in_data(57);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_58_610q <= in_data(58);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_59_609q <= in_data(59);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_5_663q <= in_data(5);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_60_608q <= in_data(60);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_61_607q <= in_data(61);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_62_606q <= in_data(62);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_63_605q <= in_data(63);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_64_604q <= in_data(64);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_65_603q <= in_data(65);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_66_602q <= in_endofpacket;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_67_601q <= in_startofpacket;
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_68_600q <= in_channel(0);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_69_599q <= in_channel(1);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_6_662q <= in_data(6);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_7_661q <= in_data(7);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_8_660q <= in_data(8);
+ altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_buffer_9_659q <= in_data(9);
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_toggle_458m_dataout <= wire_nl_w75w(0) WHEN s_wire_altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_take_in_data_454_dataout = '1' ELSE altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_in_data_toggle_671q;
+ wire_altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_toggle_flopped_669m_dataout <= wire_altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_altera_std_synchronizer_in_to_out_synchronizer_985_dout WHEN (out_ready AND s_wire_altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_valid_455_dataout) = '1' ELSE altera_avalon_st_handshake_clock_crosser_0001_altera_avalon_st_handshake_clock_crosser_crosser_altera_avalon_st_clock_crosser_clock_xer_out_data_toggle_flopped_742q;
+
+ END RTL; --altera_avalon_st_handshake_clock_crosser_0001
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_stage_0001.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_stage_0001.vho
new file mode 100644
index 0000000000000000000000000000000000000000..8d86ea4878f1ce8283772ef42dde0104a666b06e
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_stage_0001.vho
@@ -0,0 +1,708 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources = lut 146 mux21 80
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_avalon_st_pipeline_stage_0001 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ in_data : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+ in_empty : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+ in_endofpacket : IN STD_LOGIC;
+ in_error : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+ in_ready : OUT STD_LOGIC;
+ in_startofpacket : IN STD_LOGIC;
+ in_valid : IN STD_LOGIC;
+ out_data : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
+ out_empty : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ out_endofpacket : OUT STD_LOGIC;
+ out_error : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ out_ready : IN STD_LOGIC;
+ out_startofpacket : OUT STD_LOGIC;
+ out_valid : OUT STD_LOGIC;
+ reset : IN STD_LOGIC
+ );
+ END altera_avalon_st_pipeline_stage_0001;
+
+ ARCHITECTURE RTL OF altera_avalon_st_pipeline_stage_0001 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full1_981q : STD_LOGIC := '0';
+ SIGNAL wire_ni_w1w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_ni_w76w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_0_978q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_10_951q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_11_950q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_12_949q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_13_948q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_14_947q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_15_946q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_16_945q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_17_944q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_18_943q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_19_942q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_1_960q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_20_941q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_21_940q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_22_939q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_23_938q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_24_937q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_25_936q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_26_935q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_27_934q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_28_933q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_29_932q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_2_959q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_30_931q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_31_930q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_32_929q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_33_928q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_34_927q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_35_926q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_36_925q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_37_924q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_38_923q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_39_922q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_3_958q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_40_921q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_41_920q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_42_919q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_43_918q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_44_917q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_45_916q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_46_915q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_47_914q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_48_913q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_49_912q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_4_957q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_50_911q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_51_910q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_52_909q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_53_908q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_54_907q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_55_906q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_56_905q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_57_904q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_58_903q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_59_902q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_5_956q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_60_901q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_61_900q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_62_899q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_63_898q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_64_897q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_65_896q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_66_895q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_67_894q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_68_893q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_69_892q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_6_955q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_70_891q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_71_890q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_7_954q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_8_953q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_9_952q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_0_889q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_10_879q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_11_878q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_12_877q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_13_876q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_14_875q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_15_874q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_16_873q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_17_872q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_18_871q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_19_870q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_1_888q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_20_869q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_21_868q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_22_867q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_23_866q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_24_865q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_25_864q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_26_863q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_27_862q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_28_861q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_29_860q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_2_887q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_30_859q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_31_858q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_32_857q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_33_856q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_34_855q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_35_854q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_36_853q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_37_852q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_38_851q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_39_850q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_3_886q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_40_849q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_41_848q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_42_847q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_43_846q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_44_845q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_45_844q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_46_843q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_47_842q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_48_841q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_49_840q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_4_885q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_50_839q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_51_838q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_52_837q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_53_836q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_54_835q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_55_834q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_56_833q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_57_832q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_58_831q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_59_830q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_5_884q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_60_829q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_61_828q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_62_827q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_63_826q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_64_825q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_65_824q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_66_823q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_67_822q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_68_821q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_69_820q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_6_883q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_70_819q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_71_818q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_7_882q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_8_881q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_9_880q : STD_LOGIC := '0';
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_531m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_532m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_533m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_534m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_535m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_536m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_537m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_538m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_539m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_540m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_541m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_542m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_543m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_544m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_545m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_546m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_547m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_548m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_549m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_550m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_551m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_552m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_553m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_554m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_555m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_556m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_557m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_558m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_559m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_560m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_561m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_562m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_563m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_564m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_565m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_566m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_567m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_568m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_569m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_570m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_571m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_572m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_573m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_574m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_575m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_576m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_577m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_578m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_579m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_580m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_581m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_582m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_583m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_584m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_585m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_586m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_587m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_588m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_589m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_590m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_591m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_592m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_593m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_594m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_595m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_596m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_597m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_598m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_599m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_600m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_601m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_602m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_968m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_972m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_975m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_976m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full1_963m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full1_964m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full1_971m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full1_973m_dataout : STD_LOGIC;
+ SIGNAL wire_w_lg_in_valid153w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_out_ready151w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_reset148w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_always0_530_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_always1_965_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ BEGIN
+
+ wire_w_lg_in_valid153w(0) <= NOT in_valid;
+ wire_w_lg_out_ready151w(0) <= NOT out_ready;
+ wire_w_lg_reset148w(0) <= NOT reset;
+ in_ready <= wire_ni_w1w(0);
+ out_data <= ( altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_63_898q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_62_899q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_61_900q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_60_901q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_59_902q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_58_903q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_57_904q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_56_905q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_55_906q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_54_907q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_53_908q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_52_909q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_51_910q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_50_911q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_49_912q
+ & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_48_913q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_47_914q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_46_915q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_45_916q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_44_917q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_43_918q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_42_919q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_41_920q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_40_921q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_39_922q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_38_923q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_37_924q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_36_925q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_35_926q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_34_927q
+ & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_33_928q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_32_929q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_31_930q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_30_931q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_29_932q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_28_933q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_27_934q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_26_935q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_25_936q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_24_937q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_23_938q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_22_939q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_21_940q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_20_941q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_19_942q
+ & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_18_943q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_17_944q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_16_945q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_15_946q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_14_947q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_13_948q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_12_949q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_11_950q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_10_951q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_9_952q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_8_953q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_7_954q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_6_955q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_5_956q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_4_957q
+ & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_3_958q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_2_959q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_1_960q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_0_978q);
+ out_empty <= ( altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_68_893q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_67_894q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_66_895q);
+ out_endofpacket <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_64_897q;
+ out_error <= ( altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_71_890q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_70_891q & altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_69_892q);
+ out_startofpacket <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_65_896q;
+ out_valid <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full1_981q;
+ s_wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_always0_530_dataout <= ((out_ready AND altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full1_981q) OR wire_ni_w76w(0));
+ s_wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_always1_965_dataout <= (wire_ni_w1w(0) AND altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full1_981q);
+ s_wire_vcc <= '1';
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full1_981q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_976m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full1_981q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full1_973m_dataout;
+ END IF;
+ END PROCESS;
+ wire_ni_w1w(0) <= NOT altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q;
+ wire_ni_w76w(0) <= NOT altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full1_981q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_0_978q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_10_951q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_11_950q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_12_949q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_13_948q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_14_947q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_15_946q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_16_945q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_17_944q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_18_943q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_19_942q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_1_960q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_20_941q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_21_940q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_22_939q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_23_938q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_24_937q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_25_936q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_26_935q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_27_934q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_28_933q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_29_932q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_2_959q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_30_931q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_31_930q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_32_929q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_33_928q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_34_927q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_35_926q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_36_925q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_37_924q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_38_923q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_39_922q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_3_958q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_40_921q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_41_920q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_42_919q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_43_918q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_44_917q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_45_916q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_46_915q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_47_914q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_48_913q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_49_912q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_4_957q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_50_911q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_51_910q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_52_909q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_53_908q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_54_907q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_55_906q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_56_905q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_57_904q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_58_903q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_59_902q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_5_956q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_60_901q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_61_900q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_62_899q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_63_898q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_64_897q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_65_896q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_66_895q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_67_894q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_68_893q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_69_892q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_6_955q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_70_891q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_71_890q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_7_954q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_8_953q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_9_952q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_always0_530_dataout = '1') THEN
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_0_978q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_602m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_10_951q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_592m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_11_950q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_591m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_12_949q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_590m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_13_948q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_589m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_14_947q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_588m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_15_946q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_587m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_16_945q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_586m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_17_944q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_585m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_18_943q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_584m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_19_942q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_583m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_1_960q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_601m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_20_941q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_582m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_21_940q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_581m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_22_939q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_580m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_23_938q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_579m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_24_937q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_578m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_25_936q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_577m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_26_935q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_576m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_27_934q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_575m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_28_933q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_574m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_29_932q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_573m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_2_959q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_600m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_30_931q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_572m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_31_930q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_571m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_32_929q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_570m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_33_928q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_569m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_34_927q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_568m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_35_926q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_567m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_36_925q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_566m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_37_924q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_565m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_38_923q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_564m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_39_922q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_563m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_3_958q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_599m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_40_921q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_562m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_41_920q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_561m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_42_919q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_560m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_43_918q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_559m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_44_917q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_558m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_45_916q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_557m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_46_915q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_556m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_47_914q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_555m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_48_913q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_554m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_49_912q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_553m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_4_957q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_598m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_50_911q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_552m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_51_910q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_551m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_52_909q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_550m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_53_908q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_549m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_54_907q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_548m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_55_906q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_547m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_56_905q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_546m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_57_904q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_545m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_58_903q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_544m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_59_902q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_543m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_5_956q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_597m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_60_901q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_542m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_61_900q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_541m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_62_899q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_540m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_63_898q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_539m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_64_897q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_538m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_65_896q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_537m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_66_895q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_536m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_67_894q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_535m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_68_893q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_534m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_69_892q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_533m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_6_955q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_596m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_70_891q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_532m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_71_890q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_531m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_7_954q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_595m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_8_953q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_594m_dataout;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_9_952q <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_593m_dataout;
+ END IF;
+ END IF;
+ END PROCESS;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_0_889q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_10_879q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_11_878q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_12_877q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_13_876q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_14_875q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_15_874q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_16_873q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_17_872q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_18_871q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_19_870q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_1_888q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_20_869q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_21_868q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_22_867q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_23_866q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_24_865q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_25_864q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_26_863q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_27_862q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_28_861q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_29_860q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_2_887q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_30_859q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_31_858q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_32_857q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_33_856q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_34_855q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_35_854q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_36_853q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_37_852q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_38_851q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_39_850q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_3_886q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_40_849q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_41_848q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_42_847q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_43_846q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_44_845q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_45_844q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_46_843q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_47_842q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_48_841q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_49_840q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_4_885q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_50_839q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_51_838q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_52_837q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_53_836q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_54_835q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_55_834q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_56_833q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_57_832q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_58_831q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_59_830q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_5_884q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_60_829q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_61_828q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_62_827q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_63_826q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_64_825q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_65_824q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_66_823q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_67_822q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_68_821q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_69_820q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_6_883q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_70_819q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_71_818q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_7_882q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_8_881q <= '0';
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_9_880q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '0') THEN
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_0_889q <= in_data(0);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_10_879q <= in_data(10);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_11_878q <= in_data(11);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_12_877q <= in_data(12);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_13_876q <= in_data(13);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_14_875q <= in_data(14);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_15_874q <= in_data(15);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_16_873q <= in_data(16);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_17_872q <= in_data(17);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_18_871q <= in_data(18);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_19_870q <= in_data(19);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_1_888q <= in_data(1);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_20_869q <= in_data(20);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_21_868q <= in_data(21);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_22_867q <= in_data(22);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_23_866q <= in_data(23);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_24_865q <= in_data(24);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_25_864q <= in_data(25);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_26_863q <= in_data(26);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_27_862q <= in_data(27);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_28_861q <= in_data(28);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_29_860q <= in_data(29);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_2_887q <= in_data(2);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_30_859q <= in_data(30);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_31_858q <= in_data(31);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_32_857q <= in_data(32);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_33_856q <= in_data(33);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_34_855q <= in_data(34);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_35_854q <= in_data(35);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_36_853q <= in_data(36);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_37_852q <= in_data(37);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_38_851q <= in_data(38);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_39_850q <= in_data(39);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_3_886q <= in_data(3);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_40_849q <= in_data(40);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_41_848q <= in_data(41);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_42_847q <= in_data(42);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_43_846q <= in_data(43);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_44_845q <= in_data(44);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_45_844q <= in_data(45);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_46_843q <= in_data(46);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_47_842q <= in_data(47);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_48_841q <= in_data(48);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_49_840q <= in_data(49);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_4_885q <= in_data(4);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_50_839q <= in_data(50);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_51_838q <= in_data(51);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_52_837q <= in_data(52);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_53_836q <= in_data(53);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_54_835q <= in_data(54);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_55_834q <= in_data(55);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_56_833q <= in_data(56);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_57_832q <= in_data(57);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_58_831q <= in_data(58);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_59_830q <= in_data(59);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_5_884q <= in_data(5);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_60_829q <= in_data(60);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_61_828q <= in_data(61);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_62_827q <= in_data(62);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_63_826q <= in_data(63);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_64_825q <= in_endofpacket;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_65_824q <= in_startofpacket;
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_66_823q <= in_empty(0);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_67_822q <= in_empty(1);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_68_821q <= in_empty(2);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_69_820q <= in_error(0);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_6_883q <= in_data(6);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_70_819q <= in_error(1);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_71_818q <= in_error(2);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_7_882q <= in_data(7);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_8_881q <= in_data(8);
+ altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_9_880q <= in_data(9);
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_531m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_71_818q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_error(2);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_532m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_70_819q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_error(1);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_533m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_69_820q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_error(0);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_534m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_68_821q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_empty(2);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_535m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_67_822q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_empty(1);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_536m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_66_823q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_empty(0);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_537m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_65_824q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_startofpacket;
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_538m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_64_825q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_endofpacket;
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_539m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_63_826q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(63);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_540m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_62_827q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(62);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_541m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_61_828q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(61);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_542m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_60_829q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(60);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_543m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_59_830q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(59);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_544m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_58_831q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(58);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_545m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_57_832q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(57);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_546m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_56_833q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(56);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_547m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_55_834q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(55);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_548m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_54_835q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(54);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_549m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_53_836q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(53);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_550m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_52_837q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(52);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_551m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_51_838q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(51);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_552m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_50_839q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(50);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_553m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_49_840q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(49);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_554m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_48_841q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(48);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_555m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_47_842q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(47);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_556m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_46_843q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(46);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_557m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_45_844q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(45);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_558m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_44_845q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(44);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_559m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_43_846q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(43);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_560m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_42_847q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(42);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_561m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_41_848q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(41);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_562m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_40_849q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(40);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_563m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_39_850q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(39);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_564m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_38_851q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(38);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_565m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_37_852q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(37);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_566m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_36_853q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(36);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_567m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_35_854q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(35);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_568m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_34_855q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(34);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_569m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_33_856q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(33);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_570m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_32_857q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(32);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_571m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_31_858q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(31);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_572m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_30_859q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(30);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_573m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_29_860q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(29);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_574m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_28_861q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(28);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_575m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_27_862q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(27);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_576m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_26_863q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(26);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_577m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_25_864q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(25);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_578m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_24_865q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(24);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_579m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_23_866q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(23);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_580m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_22_867q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(22);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_581m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_21_868q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(21);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_582m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_20_869q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(20);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_583m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_19_870q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(19);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_584m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_18_871q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(18);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_585m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_17_872q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(17);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_586m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_16_873q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(16);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_587m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_15_874q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(15);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_588m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_14_875q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(14);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_589m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_13_876q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(13);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_590m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_12_877q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(12);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_591m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_11_878q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(11);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_592m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_10_879q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(10);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_593m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_9_880q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(9);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_594m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_8_881q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(8);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_595m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_7_882q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(7);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_596m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_6_883q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(6);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_597m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_5_884q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(5);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_598m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_4_885q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(4);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_599m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_3_886q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(3);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_600m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_2_887q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(2);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_601m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_1_888q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(1);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data1_602m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_data0_0_889q WHEN altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q = '1' ELSE in_data(0);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_968m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q OR (in_valid AND wire_w_lg_out_ready151w(0));
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_972m_dataout <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_968m_dataout WHEN s_wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_always1_965_dataout = '1' ELSE altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q;
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_975m_dataout <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_972m_dataout AND NOT(out_ready);
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_976m_dataout <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_975m_dataout WHEN (altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_980q AND altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full1_981q) = '1' ELSE wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full0_972m_dataout;
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full1_963m_dataout <= altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full1_981q OR in_valid;
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full1_964m_dataout <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full1_963m_dataout WHEN (wire_ni_w1w(0) AND wire_ni_w76w(0)) = '1' ELSE altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full1_981q;
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full1_971m_dataout <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full1_964m_dataout AND NOT((wire_w_lg_in_valid153w(0) AND out_ready));
+ wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full1_973m_dataout <= wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full1_971m_dataout WHEN s_wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_always1_965_dataout = '1' ELSE wire_altera_avalon_st_pipeline_stage_0001_altera_avalon_st_pipeline_stage_tx_st_pipeline_stage_rs_altera_avalon_st_pipeline_base_core_full1_964m_dataout;
+
+ END RTL; --altera_avalon_st_pipeline_stage_0001
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_st_splitter/altera_avalon_st_splitter_0001.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_st_splitter/altera_avalon_st_splitter_0001.vho
new file mode 100644
index 0000000000000000000000000000000000000000..9b2eb28b54534dde368ed71e99508219cf90a197
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_st_splitter/altera_avalon_st_splitter_0001.vho
@@ -0,0 +1,80 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_avalon_st_splitter_0001 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ in0_data : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+ in0_empty : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+ in0_endofpacket : IN STD_LOGIC;
+ in0_error : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+ in0_ready : OUT STD_LOGIC;
+ in0_startofpacket : IN STD_LOGIC;
+ in0_valid : IN STD_LOGIC;
+ out0_data : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
+ out0_empty : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ out0_endofpacket : OUT STD_LOGIC;
+ out0_error : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ out0_ready : IN STD_LOGIC;
+ out0_startofpacket : OUT STD_LOGIC;
+ out0_valid : OUT STD_LOGIC;
+ out1_data : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
+ out1_empty : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ out1_endofpacket : OUT STD_LOGIC;
+ out1_error : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ out1_ready : IN STD_LOGIC;
+ out1_startofpacket : OUT STD_LOGIC;
+ out1_valid : OUT STD_LOGIC
+ );
+ END altera_avalon_st_splitter_0001;
+
+ ARCHITECTURE RTL OF altera_avalon_st_splitter_0001 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ BEGIN
+
+ in0_ready <= (out0_ready AND out1_ready);
+ out0_data <= ( in0_data(63 DOWNTO 0));
+ out0_empty <= ( in0_empty(2 DOWNTO 0));
+ out0_endofpacket <= in0_endofpacket;
+ out0_error <= ( in0_error(2 DOWNTO 0));
+ out0_startofpacket <= in0_startofpacket;
+ out0_valid <= (in0_valid AND out1_ready);
+ out1_data <= ( in0_data(63 DOWNTO 0));
+ out1_empty <= ( in0_empty(2 DOWNTO 0));
+ out1_endofpacket <= in0_endofpacket;
+ out1_error <= ( in0_error(2 DOWNTO 0));
+ out1_startofpacket <= in0_startofpacket;
+ out1_valid <= (in0_valid AND out0_ready);
+
+ END RTL; --altera_avalon_st_splitter_0001
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_st_splitter/altera_avalon_st_splitter_0002.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_st_splitter/altera_avalon_st_splitter_0002.vho
new file mode 100644
index 0000000000000000000000000000000000000000..3b2be9beb951dc165e0f0513db630d85c4cdf6ca
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_st_splitter/altera_avalon_st_splitter_0002.vho
@@ -0,0 +1,65 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_avalon_st_splitter_0002 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ in0_data : IN STD_LOGIC_VECTOR (39 DOWNTO 0);
+ in0_error : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+ in0_ready : OUT STD_LOGIC;
+ in0_valid : IN STD_LOGIC;
+ out0_data : OUT STD_LOGIC_VECTOR (39 DOWNTO 0);
+ out0_error : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
+ out0_ready : IN STD_LOGIC;
+ out0_valid : OUT STD_LOGIC;
+ out1_data : OUT STD_LOGIC_VECTOR (39 DOWNTO 0);
+ out1_error : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
+ out1_ready : IN STD_LOGIC;
+ out1_valid : OUT STD_LOGIC
+ );
+ END altera_avalon_st_splitter_0002;
+
+ ARCHITECTURE RTL OF altera_avalon_st_splitter_0002 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ BEGIN
+
+ in0_ready <= (out0_ready AND out1_ready);
+ out0_data <= ( in0_data(39 DOWNTO 0));
+ out0_error <= ( in0_error(6 DOWNTO 0));
+ out0_valid <= (in0_valid AND out1_ready);
+ out1_data <= ( in0_data(39 DOWNTO 0));
+ out1_error <= ( in0_error(6 DOWNTO 0));
+ out1_valid <= (in0_valid AND out0_ready);
+
+ END RTL; --altera_avalon_st_splitter_0002
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_st_splitter/altera_avalon_st_splitter_0003.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_st_splitter/altera_avalon_st_splitter_0003.vho
new file mode 100644
index 0000000000000000000000000000000000000000..e48d3c14adbf8896fcce9196c879f50019f6437d
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_st_splitter/altera_avalon_st_splitter_0003.vho
@@ -0,0 +1,60 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_avalon_st_splitter_0003 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ in0_data : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
+ in0_ready : OUT STD_LOGIC;
+ in0_valid : IN STD_LOGIC;
+ out0_data : OUT STD_LOGIC_VECTOR (71 DOWNTO 0);
+ out0_ready : IN STD_LOGIC;
+ out0_valid : OUT STD_LOGIC;
+ out1_data : OUT STD_LOGIC_VECTOR (71 DOWNTO 0);
+ out1_ready : IN STD_LOGIC;
+ out1_valid : OUT STD_LOGIC
+ );
+ END altera_avalon_st_splitter_0003;
+
+ ARCHITECTURE RTL OF altera_avalon_st_splitter_0003 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ BEGIN
+
+ in0_ready <= (out0_ready AND out1_ready);
+ out0_data <= ( in0_data(71 DOWNTO 0));
+ out0_valid <= (in0_valid AND out1_ready);
+ out1_data <= ( in0_data(71 DOWNTO 0));
+ out1_valid <= (in0_valid AND out0_ready);
+
+ END RTL; --altera_avalon_st_splitter_0003
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_st_splitter/altera_avalon_st_splitter_0004.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_st_splitter/altera_avalon_st_splitter_0004.vho
new file mode 100644
index 0000000000000000000000000000000000000000..ef0835f48ab41873c1028c90ddd63e20a8043001
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_st_splitter/altera_avalon_st_splitter_0004.vho
@@ -0,0 +1,80 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_avalon_st_splitter_0004 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ in0_data : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+ in0_empty : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+ in0_endofpacket : IN STD_LOGIC;
+ in0_error : IN STD_LOGIC;
+ in0_ready : OUT STD_LOGIC;
+ in0_startofpacket : IN STD_LOGIC;
+ in0_valid : IN STD_LOGIC;
+ out0_data : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
+ out0_empty : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ out0_endofpacket : OUT STD_LOGIC;
+ out0_error : OUT STD_LOGIC;
+ out0_ready : IN STD_LOGIC;
+ out0_startofpacket : OUT STD_LOGIC;
+ out0_valid : OUT STD_LOGIC;
+ out1_data : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
+ out1_empty : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ out1_endofpacket : OUT STD_LOGIC;
+ out1_error : OUT STD_LOGIC;
+ out1_ready : IN STD_LOGIC;
+ out1_startofpacket : OUT STD_LOGIC;
+ out1_valid : OUT STD_LOGIC
+ );
+ END altera_avalon_st_splitter_0004;
+
+ ARCHITECTURE RTL OF altera_avalon_st_splitter_0004 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ BEGIN
+
+ in0_ready <= (out0_ready AND out1_ready);
+ out0_data <= ( in0_data(63 DOWNTO 0));
+ out0_empty <= ( in0_empty(2 DOWNTO 0));
+ out0_endofpacket <= in0_endofpacket;
+ out0_error <= in0_error;
+ out0_startofpacket <= in0_startofpacket;
+ out0_valid <= (in0_valid AND out1_ready);
+ out1_data <= ( in0_data(63 DOWNTO 0));
+ out1_empty <= ( in0_empty(2 DOWNTO 0));
+ out1_endofpacket <= in0_endofpacket;
+ out1_error <= in0_error;
+ out1_startofpacket <= in0_startofpacket;
+ out1_valid <= (in0_valid AND out0_ready);
+
+ END RTL; --altera_avalon_st_splitter_0004
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_st_splitter/altera_avalon_st_splitter_0005.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_st_splitter/altera_avalon_st_splitter_0005.vho
new file mode 100644
index 0000000000000000000000000000000000000000..4218fd8f858a6f1855f66452ca5f4a65f74e369c
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_st_splitter/altera_avalon_st_splitter_0005.vho
@@ -0,0 +1,60 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_avalon_st_splitter_0005 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ in0_data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+ in0_ready : OUT STD_LOGIC;
+ in0_valid : IN STD_LOGIC;
+ out0_data : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+ out0_ready : IN STD_LOGIC;
+ out0_valid : OUT STD_LOGIC;
+ out1_data : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+ out1_ready : IN STD_LOGIC;
+ out1_valid : OUT STD_LOGIC
+ );
+ END altera_avalon_st_splitter_0005;
+
+ ARCHITECTURE RTL OF altera_avalon_st_splitter_0005 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ BEGIN
+
+ in0_ready <= (out0_ready AND out1_ready);
+ out0_data <= ( in0_data(1 DOWNTO 0));
+ out0_valid <= in0_valid;
+ out1_data <= ( in0_data(1 DOWNTO 0));
+ out1_valid <= in0_valid;
+
+ END RTL; --altera_avalon_st_splitter_0005
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_10gmem_statistics_collector/mentor/altera_eth_10gmem_statistics_collector.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_10gmem_statistics_collector/mentor/altera_eth_10gmem_statistics_collector.v
new file mode 100644
index 0000000000000000000000000000000000000000..5c7400f13fcff9176e84dc10b098e96111dc44cb
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_10gmem_statistics_collector/mentor/altera_eth_10gmem_statistics_collector.v
@@ -0,0 +1,743 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_address_inserter/mentor/altera_eth_address_inserter.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_address_inserter/mentor/altera_eth_address_inserter.v
new file mode 100644
index 0000000000000000000000000000000000000000..8fe52cc5da1afaa911adce516e39e625e951983d
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_address_inserter/mentor/altera_eth_address_inserter.v
@@ -0,0 +1,572 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 25696)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_crc/mentor/altera_eth_crc.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_crc/mentor/altera_eth_crc.v
new file mode 100644
index 0000000000000000000000000000000000000000..f45669611bf8346e4c49ab359f685bf9d58bdb8f
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_crc/mentor/altera_eth_crc.v
@@ -0,0 +1,715 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 32576)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_crc/mentor/crc32.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_crc/mentor/crc32.v
new file mode 100644
index 0000000000000000000000000000000000000000..496edc27f904fd9932b3e9242a8c005403ee8b25
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_crc/mentor/crc32.v
@@ -0,0 +1,566 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 25408)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_crc/mentor/gf_mult32_kc.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_crc/mentor/gf_mult32_kc.v
new file mode 100644
index 0000000000000000000000000000000000000000..ff9f755910b8a3c9f2b69497b1ff4f33c200d615
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_crc/mentor/gf_mult32_kc.v
@@ -0,0 +1,685 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 31152)
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+/0PvSQyST2oNzSAc2zzsOP0Ev7Vzi9BkLeI8phlR5hxiTYCWb2w+s22HMszejXuI
+YhS/w7/9ugKtRfImek4HoezhGMGwR8P3YB1/8twhtIkvVpyA67B+EG/6sV82SoFe
+7nni3Nz+PwpBJixNgTw/fjOsGGiAyZziip5HPaLlobHevmHKfssHDNfrpGisvejn
+7+UqA8B7chPIud7/aQXkc4ihjffSchxenAEamsSuEGOyg7zdnt0j/pUHQdUsCQWC
+Ucvajhlo+oUd+2el+7vyegs4OjwOfWgsqtyv+ZNUlKtJTIN6gXa4gtquhxurSGzH
+pUm3GrgaGeQyuDpkFKa8oj4tJ5cKPOVyI1D0HyN9V4TdSHlNnKD1LNV+bJpKW2GO
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+l1kJ4fsYqC6XpsSIKMnr71LnEU4z+MH9MZ/3+DcC+xbUbRV4+/tJVKR1Q/uUKFhr
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_crc_pad_rem/altera_avalon_st_pipeline_base.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_crc_pad_rem/altera_avalon_st_pipeline_base.v
new file mode 100644
index 0000000000000000000000000000000000000000..d4edf573860c7fdc4727abf8d58db933c23d0664
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_crc_pad_rem/altera_avalon_st_pipeline_base.v
@@ -0,0 +1,136 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1ns / 1ns
+
+module altera_avalon_st_pipeline_base (
+ clk,
+ reset,
+ in_ready,
+ in_valid,
+ in_data,
+ out_ready,
+ out_valid,
+ out_data
+ );
+
+ parameter SYMBOLS_PER_BEAT = 1;
+ parameter BITS_PER_SYMBOL = 8;
+ parameter PIPELINE_READY = 1;
+ localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
+
+ input clk;
+ input reset;
+
+ output in_ready;
+ input in_valid;
+ input [DATA_WIDTH-1:0] in_data;
+
+ input out_ready;
+ output out_valid;
+ output [DATA_WIDTH-1:0] out_data;
+
+ reg full0;
+ reg full1;
+ reg [DATA_WIDTH-1:0] data0;
+ reg [DATA_WIDTH-1:0] data1;
+
+ assign out_valid = full1;
+ assign out_data = data1;
+
+ generate if (PIPELINE_READY == 1)
+ begin : REGISTERED_READY_PLINE
+
+ assign in_ready = !full0;
+
+ always @(posedge clk, posedge reset) begin
+ if (reset) begin
+ data0 <= 1'b0;
+ data1 <= 1'b0;
+ end else begin
+ // ----------------------------
+ // always load the second slot if we can
+ // ----------------------------
+ if (~full0)
+ data0 <= in_data;
+ // ----------------------------
+ // first slot is loaded either from the second,
+ // or with new data
+ // ----------------------------
+ if (~full1 || (out_ready && out_valid)) begin
+ if (full0)
+ data1 <= data0;
+ else
+ data1 <= in_data;
+ end
+ end
+ end
+
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ full0 <= 1'b0;
+ full1 <= 1'b0;
+ end else begin
+ // no data in pipeline
+ if (~full0 & ~full1) begin
+ if (in_valid) begin
+ full1 <= 1'b1;
+ end
+ end // ~f1 & ~f0
+
+ // one datum in pipeline
+ if (full1 & ~full0) begin
+ if (in_valid & ~out_ready) begin
+ full0 <= 1'b1;
+ end
+ // back to empty
+ if (~in_valid & out_ready) begin
+ full1 <= 1'b0;
+ end
+ end // f1 & ~f0
+
+ // two data in pipeline
+ if (full1 & full0) begin
+ // go back to one datum state
+ if (out_ready) begin
+ full0 <= 1'b0;
+ end
+ end // end go back to one datum stage
+ end
+ end
+
+ end
+ else
+ begin : UNREGISTERED_READY_PLINE
+
+ // in_ready will be a pass through of the out_ready signal as it is not registered
+ assign in_ready = (~full1) | out_ready;
+
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ data1 <= 'b0;
+ full1 <= 1'b0;
+ end
+ else begin
+ if (in_ready) begin
+ data1 <= in_data;
+ full1 <= in_valid;
+ end
+ end
+ end
+
+ end
+ endgenerate
+
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_crc_pad_rem/altera_avalon_st_pipeline_stage.sv b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_crc_pad_rem/altera_avalon_st_pipeline_stage.sv
new file mode 100644
index 0000000000000000000000000000000000000000..1d22052c0796462cdc1bcf6069c3fb4f53ba0045
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_crc_pad_rem/altera_avalon_st_pipeline_stage.sv
@@ -0,0 +1,160 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1ns / 1ns
+
+module altera_avalon_st_pipeline_stage #(
+ parameter
+ SYMBOLS_PER_BEAT = 1,
+ BITS_PER_SYMBOL = 8,
+ USE_PACKETS = 0,
+ USE_EMPTY = 0,
+ PIPELINE_READY = 1,
+
+ // Optional ST signal widths. Value "0" means no such port.
+ CHANNEL_WIDTH = 0,
+ ERROR_WIDTH = 0,
+
+ // Derived parameters
+ DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
+ PACKET_WIDTH = 0,
+ EMPTY_WIDTH = 0
+ )
+ (
+ input clk,
+ input reset,
+
+ output in_ready,
+ input in_valid,
+ input [DATA_WIDTH - 1 : 0] in_data,
+ input [(CHANNEL_WIDTH ? (CHANNEL_WIDTH - 1) : 0) : 0] in_channel,
+ input [(ERROR_WIDTH ? (ERROR_WIDTH - 1) : 0) : 0] in_error,
+ input in_startofpacket,
+ input in_endofpacket,
+ input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
+
+ input out_ready,
+ output out_valid,
+ output [DATA_WIDTH - 1 : 0] out_data,
+ output [(CHANNEL_WIDTH ? (CHANNEL_WIDTH - 1) : 0) : 0] out_channel,
+ output [(ERROR_WIDTH ? (ERROR_WIDTH - 1) : 0) : 0] out_error,
+ output out_startofpacket,
+ output out_endofpacket,
+ output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
+);
+ localparam
+ PAYLOAD_WIDTH =
+ DATA_WIDTH +
+ PACKET_WIDTH +
+ CHANNEL_WIDTH +
+ EMPTY_WIDTH +
+ ERROR_WIDTH;
+
+ wire [PAYLOAD_WIDTH - 1: 0] in_payload;
+ wire [PAYLOAD_WIDTH - 1: 0] out_payload;
+
+ // Assign in_data and other optional in_* interface signals to in_payload.
+ assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
+ generate
+ // optional packet inputs
+ if (PACKET_WIDTH) begin
+ assign in_payload[
+ DATA_WIDTH + PACKET_WIDTH - 1 :
+ DATA_WIDTH
+ ] = {in_startofpacket, in_endofpacket};
+ end
+ // optional channel input
+ if (CHANNEL_WIDTH) begin
+ assign in_payload[
+ DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH - 1 :
+ DATA_WIDTH + PACKET_WIDTH
+ ] = in_channel;
+ end
+ // optional empty input
+ if (EMPTY_WIDTH) begin
+ assign in_payload[
+ DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH - 1 :
+ DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH
+ ] = in_empty;
+ end
+ // optional error input
+ if (ERROR_WIDTH) begin
+ assign in_payload[
+ DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ERROR_WIDTH - 1 :
+ DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH
+ ] = in_error;
+ end
+ endgenerate
+
+ altera_avalon_st_pipeline_base #(
+ .SYMBOLS_PER_BEAT (PAYLOAD_WIDTH),
+ .BITS_PER_SYMBOL (1),
+ .PIPELINE_READY (PIPELINE_READY)
+ ) core (
+ .clk (clk),
+ .reset (reset),
+ .in_ready (in_ready),
+ .in_valid (in_valid),
+ .in_data (in_payload),
+ .out_ready (out_ready),
+ .out_valid (out_valid),
+ .out_data (out_payload)
+ );
+
+ // Assign out_data and other optional out_* interface signals from out_payload.
+ assign out_data = out_payload[DATA_WIDTH - 1 : 0];
+ generate
+ // optional packet outputs
+ if (PACKET_WIDTH) begin
+ assign {out_startofpacket, out_endofpacket} =
+ out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
+ end else begin
+ // Avoid a "has no driver" warning.
+ assign {out_startofpacket, out_endofpacket} = '0;
+ end
+
+ // optional channel output
+ if (CHANNEL_WIDTH) begin
+ assign out_channel = out_payload[
+ DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH - 1 :
+ DATA_WIDTH + PACKET_WIDTH
+ ];
+ end else begin
+ // Avoid a "has no driver" warning.
+ assign out_channel = '0;
+ end
+ // optional empty output
+ if (EMPTY_WIDTH) begin
+ assign out_empty = out_payload[
+ DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH - 1 :
+ DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH
+ ];
+ end else begin
+ // Avoid a "has no driver" warning.
+ assign out_empty = '0;
+ end
+ // optional error output
+ if (ERROR_WIDTH) begin
+ assign out_error = out_payload[
+ DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ERROR_WIDTH - 1 :
+ DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH
+ ];
+ end else begin
+ // Avoid a "has no driver" warning.
+ assign out_error = '0;
+ end
+ endgenerate
+
+endmodule
+
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_crc_pad_rem/mentor/altera_eth_crc_pad_rem.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_crc_pad_rem/mentor/altera_eth_crc_pad_rem.v
new file mode 100644
index 0000000000000000000000000000000000000000..fdbad951d45576cd20a161f323135f60f6dc8b1b
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_crc_pad_rem/mentor/altera_eth_crc_pad_rem.v
@@ -0,0 +1,291 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_crc_pad_rem/mentor/altera_eth_crc_rem.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_crc_pad_rem/mentor/altera_eth_crc_rem.v
new file mode 100644
index 0000000000000000000000000000000000000000..e1b349d73262ebf85a0c8aa46549a99f48420a84
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_crc_pad_rem/mentor/altera_eth_crc_rem.v
@@ -0,0 +1,252 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 10352)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_crc_pad_rem/mentor/altera_packet_stripper.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_crc_pad_rem/mentor/altera_packet_stripper.v
new file mode 100644
index 0000000000000000000000000000000000000000..db090dd72154b13abeead90b6a3e8302240582c8
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_crc_pad_rem/mentor/altera_packet_stripper.v
@@ -0,0 +1,289 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 12128)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_frame_decoder/altera_avalon_st_pipeline_base.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_frame_decoder/altera_avalon_st_pipeline_base.v
new file mode 100644
index 0000000000000000000000000000000000000000..d4edf573860c7fdc4727abf8d58db933c23d0664
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_frame_decoder/altera_avalon_st_pipeline_base.v
@@ -0,0 +1,136 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1ns / 1ns
+
+module altera_avalon_st_pipeline_base (
+ clk,
+ reset,
+ in_ready,
+ in_valid,
+ in_data,
+ out_ready,
+ out_valid,
+ out_data
+ );
+
+ parameter SYMBOLS_PER_BEAT = 1;
+ parameter BITS_PER_SYMBOL = 8;
+ parameter PIPELINE_READY = 1;
+ localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
+
+ input clk;
+ input reset;
+
+ output in_ready;
+ input in_valid;
+ input [DATA_WIDTH-1:0] in_data;
+
+ input out_ready;
+ output out_valid;
+ output [DATA_WIDTH-1:0] out_data;
+
+ reg full0;
+ reg full1;
+ reg [DATA_WIDTH-1:0] data0;
+ reg [DATA_WIDTH-1:0] data1;
+
+ assign out_valid = full1;
+ assign out_data = data1;
+
+ generate if (PIPELINE_READY == 1)
+ begin : REGISTERED_READY_PLINE
+
+ assign in_ready = !full0;
+
+ always @(posedge clk, posedge reset) begin
+ if (reset) begin
+ data0 <= 1'b0;
+ data1 <= 1'b0;
+ end else begin
+ // ----------------------------
+ // always load the second slot if we can
+ // ----------------------------
+ if (~full0)
+ data0 <= in_data;
+ // ----------------------------
+ // first slot is loaded either from the second,
+ // or with new data
+ // ----------------------------
+ if (~full1 || (out_ready && out_valid)) begin
+ if (full0)
+ data1 <= data0;
+ else
+ data1 <= in_data;
+ end
+ end
+ end
+
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ full0 <= 1'b0;
+ full1 <= 1'b0;
+ end else begin
+ // no data in pipeline
+ if (~full0 & ~full1) begin
+ if (in_valid) begin
+ full1 <= 1'b1;
+ end
+ end // ~f1 & ~f0
+
+ // one datum in pipeline
+ if (full1 & ~full0) begin
+ if (in_valid & ~out_ready) begin
+ full0 <= 1'b1;
+ end
+ // back to empty
+ if (~in_valid & out_ready) begin
+ full1 <= 1'b0;
+ end
+ end // f1 & ~f0
+
+ // two data in pipeline
+ if (full1 & full0) begin
+ // go back to one datum state
+ if (out_ready) begin
+ full0 <= 1'b0;
+ end
+ end // end go back to one datum stage
+ end
+ end
+
+ end
+ else
+ begin : UNREGISTERED_READY_PLINE
+
+ // in_ready will be a pass through of the out_ready signal as it is not registered
+ assign in_ready = (~full1) | out_ready;
+
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ data1 <= 'b0;
+ full1 <= 1'b0;
+ end
+ else begin
+ if (in_ready) begin
+ data1 <= in_data;
+ full1 <= in_valid;
+ end
+ end
+ end
+
+ end
+ endgenerate
+
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_frame_decoder/altera_avalon_st_pipeline_stage.sv b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_frame_decoder/altera_avalon_st_pipeline_stage.sv
new file mode 100644
index 0000000000000000000000000000000000000000..1d22052c0796462cdc1bcf6069c3fb4f53ba0045
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_frame_decoder/altera_avalon_st_pipeline_stage.sv
@@ -0,0 +1,160 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1ns / 1ns
+
+module altera_avalon_st_pipeline_stage #(
+ parameter
+ SYMBOLS_PER_BEAT = 1,
+ BITS_PER_SYMBOL = 8,
+ USE_PACKETS = 0,
+ USE_EMPTY = 0,
+ PIPELINE_READY = 1,
+
+ // Optional ST signal widths. Value "0" means no such port.
+ CHANNEL_WIDTH = 0,
+ ERROR_WIDTH = 0,
+
+ // Derived parameters
+ DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
+ PACKET_WIDTH = 0,
+ EMPTY_WIDTH = 0
+ )
+ (
+ input clk,
+ input reset,
+
+ output in_ready,
+ input in_valid,
+ input [DATA_WIDTH - 1 : 0] in_data,
+ input [(CHANNEL_WIDTH ? (CHANNEL_WIDTH - 1) : 0) : 0] in_channel,
+ input [(ERROR_WIDTH ? (ERROR_WIDTH - 1) : 0) : 0] in_error,
+ input in_startofpacket,
+ input in_endofpacket,
+ input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
+
+ input out_ready,
+ output out_valid,
+ output [DATA_WIDTH - 1 : 0] out_data,
+ output [(CHANNEL_WIDTH ? (CHANNEL_WIDTH - 1) : 0) : 0] out_channel,
+ output [(ERROR_WIDTH ? (ERROR_WIDTH - 1) : 0) : 0] out_error,
+ output out_startofpacket,
+ output out_endofpacket,
+ output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
+);
+ localparam
+ PAYLOAD_WIDTH =
+ DATA_WIDTH +
+ PACKET_WIDTH +
+ CHANNEL_WIDTH +
+ EMPTY_WIDTH +
+ ERROR_WIDTH;
+
+ wire [PAYLOAD_WIDTH - 1: 0] in_payload;
+ wire [PAYLOAD_WIDTH - 1: 0] out_payload;
+
+ // Assign in_data and other optional in_* interface signals to in_payload.
+ assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
+ generate
+ // optional packet inputs
+ if (PACKET_WIDTH) begin
+ assign in_payload[
+ DATA_WIDTH + PACKET_WIDTH - 1 :
+ DATA_WIDTH
+ ] = {in_startofpacket, in_endofpacket};
+ end
+ // optional channel input
+ if (CHANNEL_WIDTH) begin
+ assign in_payload[
+ DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH - 1 :
+ DATA_WIDTH + PACKET_WIDTH
+ ] = in_channel;
+ end
+ // optional empty input
+ if (EMPTY_WIDTH) begin
+ assign in_payload[
+ DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH - 1 :
+ DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH
+ ] = in_empty;
+ end
+ // optional error input
+ if (ERROR_WIDTH) begin
+ assign in_payload[
+ DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ERROR_WIDTH - 1 :
+ DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH
+ ] = in_error;
+ end
+ endgenerate
+
+ altera_avalon_st_pipeline_base #(
+ .SYMBOLS_PER_BEAT (PAYLOAD_WIDTH),
+ .BITS_PER_SYMBOL (1),
+ .PIPELINE_READY (PIPELINE_READY)
+ ) core (
+ .clk (clk),
+ .reset (reset),
+ .in_ready (in_ready),
+ .in_valid (in_valid),
+ .in_data (in_payload),
+ .out_ready (out_ready),
+ .out_valid (out_valid),
+ .out_data (out_payload)
+ );
+
+ // Assign out_data and other optional out_* interface signals from out_payload.
+ assign out_data = out_payload[DATA_WIDTH - 1 : 0];
+ generate
+ // optional packet outputs
+ if (PACKET_WIDTH) begin
+ assign {out_startofpacket, out_endofpacket} =
+ out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
+ end else begin
+ // Avoid a "has no driver" warning.
+ assign {out_startofpacket, out_endofpacket} = '0;
+ end
+
+ // optional channel output
+ if (CHANNEL_WIDTH) begin
+ assign out_channel = out_payload[
+ DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH - 1 :
+ DATA_WIDTH + PACKET_WIDTH
+ ];
+ end else begin
+ // Avoid a "has no driver" warning.
+ assign out_channel = '0;
+ end
+ // optional empty output
+ if (EMPTY_WIDTH) begin
+ assign out_empty = out_payload[
+ DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH - 1 :
+ DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH
+ ];
+ end else begin
+ // Avoid a "has no driver" warning.
+ assign out_empty = '0;
+ end
+ // optional error output
+ if (ERROR_WIDTH) begin
+ assign out_error = out_payload[
+ DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ERROR_WIDTH - 1 :
+ DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH
+ ];
+ end else begin
+ // Avoid a "has no driver" warning.
+ assign out_error = '0;
+ end
+ endgenerate
+
+endmodule
+
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_frame_decoder/mentor/altera_eth_frame_decoder.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_frame_decoder/mentor/altera_eth_frame_decoder.v
new file mode 100644
index 0000000000000000000000000000000000000000..6b392aa59a16caa99c1cbb0f7840449ea9c4b37b
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_frame_decoder/mentor/altera_eth_frame_decoder.v
@@ -0,0 +1,1315 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+hdI+Imxq93azgQLrM1Yc430vX1jDmqb0J9NybZpzJnM=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 61392)
+Kw1eghGlQiOUErIUqBmqzKoZGRoBZ3JGi6MpHlFG6PTOTMDRExyBBhjgV5xor7P4
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_frame_status_merger/mentor/altera_eth_frame_status_merger.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_frame_status_merger/mentor/altera_eth_frame_status_merger.v
new file mode 100644
index 0000000000000000000000000000000000000000..39ec820b0377591bb5b05aefed5582bcc1c230e8
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_frame_status_merger/mentor/altera_eth_frame_status_merger.v
@@ -0,0 +1,232 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 9376)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_lane_decoder/mentor/altera_eth_lane_decoder.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_lane_decoder/mentor/altera_eth_lane_decoder.v
new file mode 100644
index 0000000000000000000000000000000000000000..e6aa4ba19e6615488a69b232d73c7d61ae69dc3d
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_lane_decoder/mentor/altera_eth_lane_decoder.v
@@ -0,0 +1,721 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 32848)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_link_fault_detection/mentor/altera_eth_link_fault_detection.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_link_fault_detection/mentor/altera_eth_link_fault_detection.v
new file mode 100644
index 0000000000000000000000000000000000000000..b719585f572f47fce4ad1a6ec2267f2c508cca61
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_link_fault_detection/mentor/altera_eth_link_fault_detection.v
@@ -0,0 +1,1139 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 52912)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_link_fault_generation/mentor/altera_eth_link_fault_generation.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_link_fault_generation/mentor/altera_eth_link_fault_generation.v
new file mode 100644
index 0000000000000000000000000000000000000000..69c400f3194c7aa23e7227e8ac6265c030b4a668
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_link_fault_generation/mentor/altera_eth_link_fault_generation.v
@@ -0,0 +1,417 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+CRIvwwB4rU0mZ9Me22CCBX5dYg+e1+9LhgT3Ss2uSQQ=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 18272)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_packet_formatter/mentor/altera_eth_packet_formatter.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_packet_formatter/mentor/altera_eth_packet_formatter.v
new file mode 100644
index 0000000000000000000000000000000000000000..dbf8e95e36f8f923db8bc147e2e60d12a8726f71
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_packet_formatter/mentor/altera_eth_packet_formatter.v
@@ -0,0 +1,519 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 23168)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_packet_overflow_control/mentor/altera_eth_packet_overflow_control.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_packet_overflow_control/mentor/altera_eth_packet_overflow_control.v
new file mode 100644
index 0000000000000000000000000000000000000000..d1154e887bf97bba65657738e8c3b067878383e5
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_packet_overflow_control/mentor/altera_eth_packet_overflow_control.v
@@ -0,0 +1,320 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 13600)
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+iNwnuXA7VkCw+QDz/b9yvQ==
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_packet_underflow_control/mentor/altera_eth_packet_underflow_control.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_packet_underflow_control/mentor/altera_eth_packet_underflow_control.v
new file mode 100644
index 0000000000000000000000000000000000000000..a659ae16938cbf29edbaba014a6893446184c0c0
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_packet_underflow_control/mentor/altera_eth_packet_underflow_control.v
@@ -0,0 +1,177 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+xiMn9XPii7Std+YkTMX6dKKHJJYK5tBjGQuhv24C+gw=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 6736)
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+ihQYIy5fh7gHJaqhd/bG7g==
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_pad_inserter/mentor/altera_eth_pad_inserter.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_pad_inserter/mentor/altera_eth_pad_inserter.v
new file mode 100644
index 0000000000000000000000000000000000000000..46f677d7cface33f213b25e2430463e4d58f69bb
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_pad_inserter/mentor/altera_eth_pad_inserter.v
@@ -0,0 +1,451 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 19888)
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+viH7c1pvnnzNA81Zx/ZNnw==
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_pause_beat_conversion/mentor/altera_eth_pause_beat_conversion.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_pause_beat_conversion/mentor/altera_eth_pause_beat_conversion.v
new file mode 100644
index 0000000000000000000000000000000000000000..9e764c6d14adf13acf1c9ea33f1bff196b8a0f41
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_pause_beat_conversion/mentor/altera_eth_pause_beat_conversion.v
@@ -0,0 +1,105 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 3312)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_pause_ctrl_gen/mentor/altera_eth_pause_controller.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_pause_ctrl_gen/mentor/altera_eth_pause_controller.v
new file mode 100644
index 0000000000000000000000000000000000000000..b26f6af93c56267b936fa61f67ec202dcecc081c
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_pause_ctrl_gen/mentor/altera_eth_pause_controller.v
@@ -0,0 +1,288 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 12080)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_pause_ctrl_gen/mentor/altera_eth_pause_ctrl_gen.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_pause_ctrl_gen/mentor/altera_eth_pause_ctrl_gen.v
new file mode 100644
index 0000000000000000000000000000000000000000..eae73421be5ac10bcac25aa9dd06c22ec5be59da
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_pause_ctrl_gen/mentor/altera_eth_pause_ctrl_gen.v
@@ -0,0 +1,169 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 6368)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_pause_ctrl_gen/mentor/altera_eth_pause_gen.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_pause_ctrl_gen/mentor/altera_eth_pause_gen.v
new file mode 100644
index 0000000000000000000000000000000000000000..94b0bc86d8d048f3d8bb268f6fff64485d2351c9
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_pause_ctrl_gen/mentor/altera_eth_pause_gen.v
@@ -0,0 +1,222 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 8912)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_pkt_backpressure_control/mentor/altera_eth_pkt_backpressure_control.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_pkt_backpressure_control/mentor/altera_eth_pkt_backpressure_control.v
new file mode 100644
index 0000000000000000000000000000000000000000..da2dc35cba973bc2e89af06bac974fd8dce152fa
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_pkt_backpressure_control/mentor/altera_eth_pkt_backpressure_control.v
@@ -0,0 +1,328 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 13984)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_xgmii_termination/mentor/altera_eth_xgmii_termination.v b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_xgmii_termination/mentor/altera_eth_xgmii_termination.v
new file mode 100644
index 0000000000000000000000000000000000000000..0949141c00066760ec1f192a58fa06ad5ca20aae
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_eth_xgmii_termination/mentor/altera_eth_xgmii_termination.v
@@ -0,0 +1,436 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 19168)
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+BOsCOrjA/g2SguOU/HJquk2mmvltzzOtklJ0V95/vboPw9oddPdAlQ7QzzVsYSPy
+T8s+F6+qmI5Utj0Pl/3nz2roU+WO/5GbfUgyJ6PNvgeiO1WcW6TdRQ2aaDkdDPCO
+gnEbcrxFj3lpc/RiCOQnYE0iqEpc9yNUjJhTYvuD3TdEyilxuDAouGV41LTqdQKN
+XBjgV83/rW1XL2BSjQl8DTSleaHBhX1q6K+FdPCCMPv8eeMHfAXd6O2pf4+5sD8F
+NdlgqiH1QoWOQG2GJN5jZeNAP2A1crgi2FpZ8x+NKpKZfAypu1qCKFXqlKy2ee3C
+RHu1tMyEs7Vpf/sLOQTJAn/23+8VV2aC6bMORog8hmsNEHGOQBj7EbIHGFqbkpGy
+utiQMPUbEEJ9Ry2xKxLx0TC5SI3UBfXaBlQWDTETbGyOLP4P6Pv4lKX4B8LcPROE
+QNYkM7scdn3cyFl71GVrXfrZUcdDkiRhPP81zcGPvLhDSD9AH/2dg/ro9UJSdbth
+kMrYU2U2MdMBkFKjobpxLDeS2Ru9HTZIFAsfRymw7KQ/igmvBEnKWSuXMXdU9MdQ
+EqPfudx/w0qXsfeZK59RhDlm5ocRU6y7bh+Z7lQAhl9DL/UQBnHicwY137817UW5
+3x9r/HootSyGu5lhg/+EbdT5FkvQ4Zsl6Yiwgyp7OFdCkTqh5ctuwVG6NWk/zhut
+odWksE3TTZk6GAa3lfdcf2NUA5M7Q6hnTbxHpiy9N0jBr9FbaTliSe0vTh5OuVA7
+q7ASdlGIqZczXX+j31C5yD9uq7cuZYRdW7pm2DgRpHbXzBB0Goj59pqWOzh3W1q4
+9gtvRe85DBQL0qR/Guzb9LxNU6Kf4vLUr0mQMrOevLy4wsR2IDvPjD6XMRNfDjaq
+GM/F3+0mJPO4pTpPwApmL+hz0tBMQlY1DkNssKGQVLAjYD3JRju0TSRbs/vqOPiv
+Pw1ccnwFvVpObunMtgWy3ULwK94QnCIPZyrReJyI8HFUtfOJjfDPB6/7ZEg0YxEn
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+Tdz9IX2s5HyhK9f0OoxsJWsHrdzZqmHZPZvea56XG4gti+1ex15VNqdAsHg+t91A
+begzdKBLaDxwfcjKlAIW2Q==
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_demultiplexer/altera_merlin_demultiplexer_0001.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_demultiplexer/altera_merlin_demultiplexer_0001.vho
new file mode 100644
index 0000000000000000000000000000000000000000..9067638c02703f37d5c4c719d9b58cd4a64ef12c
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_demultiplexer/altera_merlin_demultiplexer_0001.vho
@@ -0,0 +1,84 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_demultiplexer_0001 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ reset : IN STD_LOGIC;
+ sink_channel : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+ sink_data : IN STD_LOGIC_VECTOR (65 DOWNTO 0);
+ sink_endofpacket : IN STD_LOGIC;
+ sink_ready : OUT STD_LOGIC;
+ sink_startofpacket : IN STD_LOGIC;
+ sink_valid : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+ src0_channel : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+ src0_data : OUT STD_LOGIC_VECTOR (65 DOWNTO 0);
+ src0_endofpacket : OUT STD_LOGIC;
+ src0_ready : IN STD_LOGIC;
+ src0_startofpacket : OUT STD_LOGIC;
+ src0_valid : OUT STD_LOGIC;
+ src1_channel : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+ src1_data : OUT STD_LOGIC_VECTOR (65 DOWNTO 0);
+ src1_endofpacket : OUT STD_LOGIC;
+ src1_ready : IN STD_LOGIC;
+ src1_startofpacket : OUT STD_LOGIC;
+ src1_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_demultiplexer_0001;
+
+ ARCHITECTURE RTL OF altera_merlin_demultiplexer_0001 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL wire_w_lg_w_sink_channel_range1w2w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_sink_channel_range3w4w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink_channel_range1w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink_channel_range3w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+ wire_w_lg_w_sink_channel_range1w2w(0) <= wire_w_sink_channel_range1w(0) AND src0_ready;
+ wire_w_lg_w_sink_channel_range3w4w(0) <= wire_w_sink_channel_range3w(0) AND src1_ready;
+ sink_ready <= (wire_w_lg_w_sink_channel_range1w2w(0) OR wire_w_lg_w_sink_channel_range3w4w(0));
+ src0_channel <= ( "0" & "0");
+ src0_data <= ( sink_data(65 DOWNTO 0));
+ src0_endofpacket <= sink_endofpacket;
+ src0_startofpacket <= sink_startofpacket;
+ src0_valid <= (sink_valid(0) AND sink_channel(0));
+ src1_channel <= ( "0" & "0");
+ src1_data <= ( sink_data(65 DOWNTO 0));
+ src1_endofpacket <= sink_endofpacket;
+ src1_startofpacket <= sink_startofpacket;
+ src1_valid <= (sink_valid(1) AND sink_channel(1));
+ wire_w_sink_channel_range1w(0) <= sink_channel(0);
+ wire_w_sink_channel_range3w(0) <= sink_channel(1);
+
+ END RTL; --altera_merlin_demultiplexer_0001
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_demultiplexer/altera_merlin_demultiplexer_0002.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_demultiplexer/altera_merlin_demultiplexer_0002.vho
new file mode 100644
index 0000000000000000000000000000000000000000..a648c911a6bb606cc40ae6df4c6d4b600255e037
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_demultiplexer/altera_merlin_demultiplexer_0002.vho
@@ -0,0 +1,65 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_demultiplexer_0002 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ reset : IN STD_LOGIC;
+ sink_channel : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+ sink_data : IN STD_LOGIC_VECTOR (65 DOWNTO 0);
+ sink_endofpacket : IN STD_LOGIC;
+ sink_ready : OUT STD_LOGIC;
+ sink_startofpacket : IN STD_LOGIC;
+ sink_valid : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
+ src0_channel : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+ src0_data : OUT STD_LOGIC_VECTOR (65 DOWNTO 0);
+ src0_endofpacket : OUT STD_LOGIC;
+ src0_ready : IN STD_LOGIC;
+ src0_startofpacket : OUT STD_LOGIC;
+ src0_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_demultiplexer_0002;
+
+ ARCHITECTURE RTL OF altera_merlin_demultiplexer_0002 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ BEGIN
+
+ sink_ready <= (sink_channel(0) AND src0_ready);
+ src0_channel <= ( "0" & sink_channel(1));
+ src0_data <= ( sink_data(65 DOWNTO 0));
+ src0_endofpacket <= sink_endofpacket;
+ src0_startofpacket <= sink_startofpacket;
+ src0_valid <= (sink_valid(0) AND sink_channel(0));
+
+ END RTL; --altera_merlin_demultiplexer_0002
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_demultiplexer/altera_merlin_demultiplexer_0003.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_demultiplexer/altera_merlin_demultiplexer_0003.vho
new file mode 100644
index 0000000000000000000000000000000000000000..7577af487983a50b81851c62c2124bd4184ede97
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_demultiplexer/altera_merlin_demultiplexer_0003.vho
@@ -0,0 +1,176 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_demultiplexer_0003 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ reset : IN STD_LOGIC;
+ sink_channel : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ sink_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ sink_endofpacket : IN STD_LOGIC;
+ sink_ready : OUT STD_LOGIC;
+ sink_startofpacket : IN STD_LOGIC;
+ sink_valid : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ src0_channel : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ src0_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ src0_endofpacket : OUT STD_LOGIC;
+ src0_ready : IN STD_LOGIC;
+ src0_startofpacket : OUT STD_LOGIC;
+ src0_valid : OUT STD_LOGIC;
+ src1_channel : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ src1_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ src1_endofpacket : OUT STD_LOGIC;
+ src1_ready : IN STD_LOGIC;
+ src1_startofpacket : OUT STD_LOGIC;
+ src1_valid : OUT STD_LOGIC;
+ src2_channel : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ src2_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ src2_endofpacket : OUT STD_LOGIC;
+ src2_ready : IN STD_LOGIC;
+ src2_startofpacket : OUT STD_LOGIC;
+ src2_valid : OUT STD_LOGIC;
+ src3_channel : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ src3_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ src3_endofpacket : OUT STD_LOGIC;
+ src3_ready : IN STD_LOGIC;
+ src3_startofpacket : OUT STD_LOGIC;
+ src3_valid : OUT STD_LOGIC;
+ src4_channel : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ src4_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ src4_endofpacket : OUT STD_LOGIC;
+ src4_ready : IN STD_LOGIC;
+ src4_startofpacket : OUT STD_LOGIC;
+ src4_valid : OUT STD_LOGIC;
+ src5_channel : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ src5_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ src5_endofpacket : OUT STD_LOGIC;
+ src5_ready : IN STD_LOGIC;
+ src5_startofpacket : OUT STD_LOGIC;
+ src5_valid : OUT STD_LOGIC;
+ src6_channel : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ src6_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ src6_endofpacket : OUT STD_LOGIC;
+ src6_ready : IN STD_LOGIC;
+ src6_startofpacket : OUT STD_LOGIC;
+ src6_valid : OUT STD_LOGIC;
+ src7_channel : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ src7_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ src7_endofpacket : OUT STD_LOGIC;
+ src7_ready : IN STD_LOGIC;
+ src7_startofpacket : OUT STD_LOGIC;
+ src7_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_demultiplexer_0003;
+
+ ARCHITECTURE RTL OF altera_merlin_demultiplexer_0003 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL wire_w_lg_w_sink_channel_range1w2w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_sink_channel_range3w4w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_sink_channel_range6w7w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_sink_channel_range9w10w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_sink_channel_range12w13w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_sink_channel_range15w16w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_sink_channel_range18w19w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_sink_channel_range21w22w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_merlin_demultiplexer_0003_wideor0_17_dataout : STD_LOGIC;
+ SIGNAL wire_w_sink_channel_range1w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink_channel_range3w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink_channel_range6w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink_channel_range9w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink_channel_range12w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink_channel_range15w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink_channel_range18w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink_channel_range21w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+ wire_w_lg_w_sink_channel_range1w2w(0) <= wire_w_sink_channel_range1w(0) AND src0_ready;
+ wire_w_lg_w_sink_channel_range3w4w(0) <= wire_w_sink_channel_range3w(0) AND src1_ready;
+ wire_w_lg_w_sink_channel_range6w7w(0) <= wire_w_sink_channel_range6w(0) AND src2_ready;
+ wire_w_lg_w_sink_channel_range9w10w(0) <= wire_w_sink_channel_range9w(0) AND src3_ready;
+ wire_w_lg_w_sink_channel_range12w13w(0) <= wire_w_sink_channel_range12w(0) AND src4_ready;
+ wire_w_lg_w_sink_channel_range15w16w(0) <= wire_w_sink_channel_range15w(0) AND src5_ready;
+ wire_w_lg_w_sink_channel_range18w19w(0) <= wire_w_sink_channel_range18w(0) AND src6_ready;
+ wire_w_lg_w_sink_channel_range21w22w(0) <= wire_w_sink_channel_range21w(0) AND src7_ready;
+ s_wire_altera_merlin_demultiplexer_0003_wideor0_17_dataout <= (((((((wire_w_lg_w_sink_channel_range1w2w(0) OR wire_w_lg_w_sink_channel_range3w4w(0)) OR wire_w_lg_w_sink_channel_range6w7w(0)) OR wire_w_lg_w_sink_channel_range9w10w(0)) OR wire_w_lg_w_sink_channel_range12w13w(0)) OR wire_w_lg_w_sink_channel_range15w16w(0)) OR wire_w_lg_w_sink_channel_range18w19w(0)) OR wire_w_lg_w_sink_channel_range21w22w(0));
+ sink_ready <= s_wire_altera_merlin_demultiplexer_0003_wideor0_17_dataout;
+ src0_channel <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ src0_data <= ( sink_data(68 DOWNTO 0));
+ src0_endofpacket <= sink_endofpacket;
+ src0_startofpacket <= sink_startofpacket;
+ src0_valid <= (sink_valid(0) AND sink_channel(0));
+ src1_channel <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ src1_data <= ( sink_data(68 DOWNTO 0));
+ src1_endofpacket <= sink_endofpacket;
+ src1_startofpacket <= sink_startofpacket;
+ src1_valid <= (sink_valid(1) AND sink_channel(1));
+ src2_channel <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ src2_data <= ( sink_data(68 DOWNTO 0));
+ src2_endofpacket <= sink_endofpacket;
+ src2_startofpacket <= sink_startofpacket;
+ src2_valid <= (sink_valid(2) AND sink_channel(2));
+ src3_channel <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ src3_data <= ( sink_data(68 DOWNTO 0));
+ src3_endofpacket <= sink_endofpacket;
+ src3_startofpacket <= sink_startofpacket;
+ src3_valid <= (sink_valid(3) AND sink_channel(3));
+ src4_channel <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ src4_data <= ( sink_data(68 DOWNTO 0));
+ src4_endofpacket <= sink_endofpacket;
+ src4_startofpacket <= sink_startofpacket;
+ src4_valid <= (sink_valid(4) AND sink_channel(4));
+ src5_channel <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ src5_data <= ( sink_data(68 DOWNTO 0));
+ src5_endofpacket <= sink_endofpacket;
+ src5_startofpacket <= sink_startofpacket;
+ src5_valid <= (sink_valid(5) AND sink_channel(5));
+ src6_channel <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ src6_data <= ( sink_data(68 DOWNTO 0));
+ src6_endofpacket <= sink_endofpacket;
+ src6_startofpacket <= sink_startofpacket;
+ src6_valid <= (sink_valid(6) AND sink_channel(6));
+ src7_channel <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ src7_data <= ( sink_data(68 DOWNTO 0));
+ src7_endofpacket <= sink_endofpacket;
+ src7_startofpacket <= sink_startofpacket;
+ src7_valid <= (sink_valid(7) AND sink_channel(7));
+ wire_w_sink_channel_range1w(0) <= sink_channel(0);
+ wire_w_sink_channel_range3w(0) <= sink_channel(1);
+ wire_w_sink_channel_range6w(0) <= sink_channel(2);
+ wire_w_sink_channel_range9w(0) <= sink_channel(3);
+ wire_w_sink_channel_range12w(0) <= sink_channel(4);
+ wire_w_sink_channel_range15w(0) <= sink_channel(5);
+ wire_w_sink_channel_range18w(0) <= sink_channel(6);
+ wire_w_sink_channel_range21w(0) <= sink_channel(7);
+
+ END RTL; --altera_merlin_demultiplexer_0003
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_demultiplexer/altera_merlin_demultiplexer_0004.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_demultiplexer/altera_merlin_demultiplexer_0004.vho
new file mode 100644
index 0000000000000000000000000000000000000000..40f244e12fa07e9d14a52ca878e54eefe2f89406
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_demultiplexer/altera_merlin_demultiplexer_0004.vho
@@ -0,0 +1,65 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_demultiplexer_0004 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ reset : IN STD_LOGIC;
+ sink_channel : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ sink_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ sink_endofpacket : IN STD_LOGIC;
+ sink_ready : OUT STD_LOGIC;
+ sink_startofpacket : IN STD_LOGIC;
+ sink_valid : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
+ src0_channel : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ src0_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ src0_endofpacket : OUT STD_LOGIC;
+ src0_ready : IN STD_LOGIC;
+ src0_startofpacket : OUT STD_LOGIC;
+ src0_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_demultiplexer_0004;
+
+ ARCHITECTURE RTL OF altera_merlin_demultiplexer_0004 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ BEGIN
+
+ sink_ready <= (sink_channel(0) AND src0_ready);
+ src0_channel <= ( "0" & sink_channel(7 DOWNTO 1));
+ src0_data <= ( sink_data(68 DOWNTO 0));
+ src0_endofpacket <= sink_endofpacket;
+ src0_startofpacket <= sink_startofpacket;
+ src0_valid <= (sink_valid(0) AND sink_channel(0));
+
+ END RTL; --altera_merlin_demultiplexer_0004
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_demultiplexer/altera_merlin_demultiplexer_0005.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_demultiplexer/altera_merlin_demultiplexer_0005.vho
new file mode 100644
index 0000000000000000000000000000000000000000..9017aad7e83b68d630f4954dcd3fcde541f73b58
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_demultiplexer/altera_merlin_demultiplexer_0005.vho
@@ -0,0 +1,161 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_demultiplexer_0005 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ reset : IN STD_LOGIC;
+ sink_channel : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+ sink_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ sink_endofpacket : IN STD_LOGIC;
+ sink_ready : OUT STD_LOGIC;
+ sink_startofpacket : IN STD_LOGIC;
+ sink_valid : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+ src0_channel : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
+ src0_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ src0_endofpacket : OUT STD_LOGIC;
+ src0_ready : IN STD_LOGIC;
+ src0_startofpacket : OUT STD_LOGIC;
+ src0_valid : OUT STD_LOGIC;
+ src1_channel : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
+ src1_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ src1_endofpacket : OUT STD_LOGIC;
+ src1_ready : IN STD_LOGIC;
+ src1_startofpacket : OUT STD_LOGIC;
+ src1_valid : OUT STD_LOGIC;
+ src2_channel : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
+ src2_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ src2_endofpacket : OUT STD_LOGIC;
+ src2_ready : IN STD_LOGIC;
+ src2_startofpacket : OUT STD_LOGIC;
+ src2_valid : OUT STD_LOGIC;
+ src3_channel : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
+ src3_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ src3_endofpacket : OUT STD_LOGIC;
+ src3_ready : IN STD_LOGIC;
+ src3_startofpacket : OUT STD_LOGIC;
+ src3_valid : OUT STD_LOGIC;
+ src4_channel : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
+ src4_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ src4_endofpacket : OUT STD_LOGIC;
+ src4_ready : IN STD_LOGIC;
+ src4_startofpacket : OUT STD_LOGIC;
+ src4_valid : OUT STD_LOGIC;
+ src5_channel : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
+ src5_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ src5_endofpacket : OUT STD_LOGIC;
+ src5_ready : IN STD_LOGIC;
+ src5_startofpacket : OUT STD_LOGIC;
+ src5_valid : OUT STD_LOGIC;
+ src6_channel : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
+ src6_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ src6_endofpacket : OUT STD_LOGIC;
+ src6_ready : IN STD_LOGIC;
+ src6_startofpacket : OUT STD_LOGIC;
+ src6_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_demultiplexer_0005;
+
+ ARCHITECTURE RTL OF altera_merlin_demultiplexer_0005 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL wire_w_lg_w_sink_channel_range1w2w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_sink_channel_range3w4w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_sink_channel_range6w7w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_sink_channel_range9w10w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_sink_channel_range12w13w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_sink_channel_range15w16w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_sink_channel_range18w19w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_merlin_demultiplexer_0005_wideor0_15_dataout : STD_LOGIC;
+ SIGNAL wire_w_sink_channel_range1w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink_channel_range3w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink_channel_range6w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink_channel_range9w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink_channel_range12w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink_channel_range15w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink_channel_range18w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+ wire_w_lg_w_sink_channel_range1w2w(0) <= wire_w_sink_channel_range1w(0) AND src0_ready;
+ wire_w_lg_w_sink_channel_range3w4w(0) <= wire_w_sink_channel_range3w(0) AND src1_ready;
+ wire_w_lg_w_sink_channel_range6w7w(0) <= wire_w_sink_channel_range6w(0) AND src2_ready;
+ wire_w_lg_w_sink_channel_range9w10w(0) <= wire_w_sink_channel_range9w(0) AND src3_ready;
+ wire_w_lg_w_sink_channel_range12w13w(0) <= wire_w_sink_channel_range12w(0) AND src4_ready;
+ wire_w_lg_w_sink_channel_range15w16w(0) <= wire_w_sink_channel_range15w(0) AND src5_ready;
+ wire_w_lg_w_sink_channel_range18w19w(0) <= wire_w_sink_channel_range18w(0) AND src6_ready;
+ s_wire_altera_merlin_demultiplexer_0005_wideor0_15_dataout <= ((((((wire_w_lg_w_sink_channel_range1w2w(0) OR wire_w_lg_w_sink_channel_range3w4w(0)) OR wire_w_lg_w_sink_channel_range6w7w(0)) OR wire_w_lg_w_sink_channel_range9w10w(0)) OR wire_w_lg_w_sink_channel_range12w13w(0)) OR wire_w_lg_w_sink_channel_range15w16w(0)) OR wire_w_lg_w_sink_channel_range18w19w(0));
+ sink_ready <= s_wire_altera_merlin_demultiplexer_0005_wideor0_15_dataout;
+ src0_channel <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ src0_data <= ( sink_data(68 DOWNTO 0));
+ src0_endofpacket <= sink_endofpacket;
+ src0_startofpacket <= sink_startofpacket;
+ src0_valid <= (sink_valid(0) AND sink_channel(0));
+ src1_channel <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ src1_data <= ( sink_data(68 DOWNTO 0));
+ src1_endofpacket <= sink_endofpacket;
+ src1_startofpacket <= sink_startofpacket;
+ src1_valid <= (sink_valid(1) AND sink_channel(1));
+ src2_channel <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ src2_data <= ( sink_data(68 DOWNTO 0));
+ src2_endofpacket <= sink_endofpacket;
+ src2_startofpacket <= sink_startofpacket;
+ src2_valid <= (sink_valid(2) AND sink_channel(2));
+ src3_channel <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ src3_data <= ( sink_data(68 DOWNTO 0));
+ src3_endofpacket <= sink_endofpacket;
+ src3_startofpacket <= sink_startofpacket;
+ src3_valid <= (sink_valid(3) AND sink_channel(3));
+ src4_channel <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ src4_data <= ( sink_data(68 DOWNTO 0));
+ src4_endofpacket <= sink_endofpacket;
+ src4_startofpacket <= sink_startofpacket;
+ src4_valid <= (sink_valid(4) AND sink_channel(4));
+ src5_channel <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ src5_data <= ( sink_data(68 DOWNTO 0));
+ src5_endofpacket <= sink_endofpacket;
+ src5_startofpacket <= sink_startofpacket;
+ src5_valid <= (sink_valid(5) AND sink_channel(5));
+ src6_channel <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ src6_data <= ( sink_data(68 DOWNTO 0));
+ src6_endofpacket <= sink_endofpacket;
+ src6_startofpacket <= sink_startofpacket;
+ src6_valid <= (sink_valid(6) AND sink_channel(6));
+ wire_w_sink_channel_range1w(0) <= sink_channel(0);
+ wire_w_sink_channel_range3w(0) <= sink_channel(1);
+ wire_w_sink_channel_range6w(0) <= sink_channel(2);
+ wire_w_sink_channel_range9w(0) <= sink_channel(3);
+ wire_w_sink_channel_range12w(0) <= sink_channel(4);
+ wire_w_sink_channel_range15w(0) <= sink_channel(5);
+ wire_w_sink_channel_range18w(0) <= sink_channel(6);
+
+ END RTL; --altera_merlin_demultiplexer_0005
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_demultiplexer/altera_merlin_demultiplexer_0006.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_demultiplexer/altera_merlin_demultiplexer_0006.vho
new file mode 100644
index 0000000000000000000000000000000000000000..2110ebf2403d3f0e487e41cfdc5f5ebb56a5b545
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_demultiplexer/altera_merlin_demultiplexer_0006.vho
@@ -0,0 +1,65 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_demultiplexer_0006 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ reset : IN STD_LOGIC;
+ sink_channel : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+ sink_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ sink_endofpacket : IN STD_LOGIC;
+ sink_ready : OUT STD_LOGIC;
+ sink_startofpacket : IN STD_LOGIC;
+ sink_valid : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
+ src0_channel : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
+ src0_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ src0_endofpacket : OUT STD_LOGIC;
+ src0_ready : IN STD_LOGIC;
+ src0_startofpacket : OUT STD_LOGIC;
+ src0_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_demultiplexer_0006;
+
+ ARCHITECTURE RTL OF altera_merlin_demultiplexer_0006 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ BEGIN
+
+ sink_ready <= (sink_channel(0) AND src0_ready);
+ src0_channel <= ( "0" & sink_channel(6 DOWNTO 1));
+ src0_data <= ( sink_data(68 DOWNTO 0));
+ src0_endofpacket <= sink_endofpacket;
+ src0_startofpacket <= sink_startofpacket;
+ src0_valid <= (sink_valid(0) AND sink_channel(0));
+
+ END RTL; --altera_merlin_demultiplexer_0006
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_master_agent/altera_merlin_master_agent_0001.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_master_agent/altera_merlin_master_agent_0001.vho
new file mode 100644
index 0000000000000000000000000000000000000000..cac339f7b1e9bdcecc46f44cc5da388512561524
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_master_agent/altera_merlin_master_agent_0001.vho
@@ -0,0 +1,79 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_master_agent_0001 IS
+ PORT
+ (
+ av_address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
+ av_burstcount : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+ av_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+ av_debugaccess : IN STD_LOGIC;
+ av_lock : IN STD_LOGIC;
+ av_read : IN STD_LOGIC;
+ av_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ av_readdatavalid : OUT STD_LOGIC;
+ av_waitrequest : OUT STD_LOGIC;
+ av_write : IN STD_LOGIC;
+ av_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ clk : IN STD_LOGIC;
+ cp_data : OUT STD_LOGIC_VECTOR (65 DOWNTO 0);
+ cp_endofpacket : OUT STD_LOGIC;
+ cp_ready : IN STD_LOGIC;
+ cp_startofpacket : OUT STD_LOGIC;
+ cp_valid : OUT STD_LOGIC;
+ reset : IN STD_LOGIC;
+ rp_channel : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+ rp_data : IN STD_LOGIC_VECTOR (65 DOWNTO 0);
+ rp_endofpacket : IN STD_LOGIC;
+ rp_ready : OUT STD_LOGIC;
+ rp_startofpacket : IN STD_LOGIC;
+ rp_valid : IN STD_LOGIC
+ );
+ END altera_merlin_master_agent_0001;
+
+ ARCHITECTURE RTL OF altera_merlin_master_agent_0001 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL wire_w_lg_cp_ready97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+ wire_w_lg_cp_ready97w(0) <= NOT cp_ready;
+ av_readdata <= ( rp_data(31 DOWNTO 0));
+ av_readdatavalid <= rp_valid;
+ av_waitrequest <= wire_w_lg_cp_ready97w(0);
+ cp_data <= ( av_debugaccess & "0" & "0" & "0" & "1" & "1" & "1" & av_burstcount(2 DOWNTO 0) & av_lock & av_read & av_write & av_write & "0" & av_address(14 DOWNTO 2) & "0" & "0" & av_byteenable(3 DOWNTO 0) & av_writedata(31 DOWNTO 0));
+ cp_endofpacket <= '1';
+ cp_startofpacket <= '1';
+ cp_valid <= (av_write OR av_read);
+ rp_ready <= '1';
+
+ END RTL; --altera_merlin_master_agent_0001
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_master_agent/altera_merlin_master_agent_0002.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_master_agent/altera_merlin_master_agent_0002.vho
new file mode 100644
index 0000000000000000000000000000000000000000..31e3898a89f4d445ddde2ff27083b7e4a2fa7640
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_master_agent/altera_merlin_master_agent_0002.vho
@@ -0,0 +1,79 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_master_agent_0002 IS
+ PORT
+ (
+ av_address : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
+ av_burstcount : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+ av_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+ av_debugaccess : IN STD_LOGIC;
+ av_lock : IN STD_LOGIC;
+ av_read : IN STD_LOGIC;
+ av_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ av_readdatavalid : OUT STD_LOGIC;
+ av_waitrequest : OUT STD_LOGIC;
+ av_write : IN STD_LOGIC;
+ av_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ clk : IN STD_LOGIC;
+ cp_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ cp_endofpacket : OUT STD_LOGIC;
+ cp_ready : IN STD_LOGIC;
+ cp_startofpacket : OUT STD_LOGIC;
+ cp_valid : OUT STD_LOGIC;
+ reset : IN STD_LOGIC;
+ rp_channel : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ rp_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ rp_endofpacket : IN STD_LOGIC;
+ rp_ready : OUT STD_LOGIC;
+ rp_startofpacket : IN STD_LOGIC;
+ rp_valid : IN STD_LOGIC
+ );
+ END altera_merlin_master_agent_0002;
+
+ ARCHITECTURE RTL OF altera_merlin_master_agent_0002 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL wire_w_lg_cp_ready97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+ wire_w_lg_cp_ready97w(0) <= NOT cp_ready;
+ av_readdata <= ( rp_data(31 DOWNTO 0));
+ av_readdatavalid <= rp_valid;
+ av_waitrequest <= wire_w_lg_cp_ready97w(0);
+ cp_data <= ( av_debugaccess & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "1" & "1" & av_burstcount(2 DOWNTO 0) & av_lock & av_read & av_write & av_write & "0" & av_address(13 DOWNTO 2) & "0" & "0" & av_byteenable(3 DOWNTO 0) & av_writedata(31 DOWNTO 0));
+ cp_endofpacket <= '1';
+ cp_startofpacket <= '1';
+ cp_valid <= (av_write OR av_read);
+ rp_ready <= '1';
+
+ END RTL; --altera_merlin_master_agent_0002
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_master_agent/altera_merlin_master_agent_0003.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_master_agent/altera_merlin_master_agent_0003.vho
new file mode 100644
index 0000000000000000000000000000000000000000..ca139f728c06561e9e0f269a1cfbc3395872c495
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_master_agent/altera_merlin_master_agent_0003.vho
@@ -0,0 +1,79 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_master_agent_0003 IS
+ PORT
+ (
+ av_address : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
+ av_burstcount : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+ av_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+ av_debugaccess : IN STD_LOGIC;
+ av_lock : IN STD_LOGIC;
+ av_read : IN STD_LOGIC;
+ av_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ av_readdatavalid : OUT STD_LOGIC;
+ av_waitrequest : OUT STD_LOGIC;
+ av_write : IN STD_LOGIC;
+ av_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ clk : IN STD_LOGIC;
+ cp_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ cp_endofpacket : OUT STD_LOGIC;
+ cp_ready : IN STD_LOGIC;
+ cp_startofpacket : OUT STD_LOGIC;
+ cp_valid : OUT STD_LOGIC;
+ reset : IN STD_LOGIC;
+ rp_channel : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+ rp_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ rp_endofpacket : IN STD_LOGIC;
+ rp_ready : OUT STD_LOGIC;
+ rp_startofpacket : IN STD_LOGIC;
+ rp_valid : IN STD_LOGIC
+ );
+ END altera_merlin_master_agent_0003;
+
+ ARCHITECTURE RTL OF altera_merlin_master_agent_0003 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL wire_w_lg_cp_ready97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+ wire_w_lg_cp_ready97w(0) <= NOT cp_ready;
+ av_readdata <= ( rp_data(31 DOWNTO 0));
+ av_readdatavalid <= rp_valid;
+ av_waitrequest <= wire_w_lg_cp_ready97w(0);
+ cp_data <= ( av_debugaccess & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "1" & "1" & av_burstcount(2 DOWNTO 0) & av_lock & av_read & av_write & av_write & "0" & av_address(13 DOWNTO 2) & "0" & "0" & av_byteenable(3 DOWNTO 0) & av_writedata(31 DOWNTO 0));
+ cp_endofpacket <= '1';
+ cp_startofpacket <= '1';
+ cp_valid <= (av_write OR av_read);
+ rp_ready <= '1';
+
+ END RTL; --altera_merlin_master_agent_0003
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_master_translator/altera_merlin_master_translator_0001.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_master_translator/altera_merlin_master_translator_0001.vho
new file mode 100644
index 0000000000000000000000000000000000000000..91c65f7c5c3d80984b5f45333e77392639281389
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_master_translator/altera_merlin_master_translator_0001.vho
@@ -0,0 +1,101 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources = lut 1 mux21 4
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_master_translator_0001 IS
+ PORT
+ (
+ av_address : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+ av_read : IN STD_LOGIC;
+ av_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ av_waitrequest : OUT STD_LOGIC;
+ av_write : IN STD_LOGIC;
+ av_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ clk : IN STD_LOGIC;
+ reset : IN STD_LOGIC;
+ uav_address : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
+ uav_burstcount : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ uav_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+ uav_debugaccess : OUT STD_LOGIC;
+ uav_lock : OUT STD_LOGIC;
+ uav_read : OUT STD_LOGIC;
+ uav_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ uav_readdatavalid : IN STD_LOGIC;
+ uav_waitrequest : IN STD_LOGIC;
+ uav_write : OUT STD_LOGIC;
+ uav_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+ );
+ END altera_merlin_master_translator_0001;
+
+ ARCHITECTURE RTL OF altera_merlin_master_translator_0001 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_186q : STD_LOGIC := '0';
+ SIGNAL wire_nO_w51w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_av_waitrequest_183m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_177m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_180m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_181m_dataout : STD_LOGIC;
+ SIGNAL wire_w_lg_reset258w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_uav_readdatavalid257w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_uav_waitrequest255w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ BEGIN
+
+ wire_w_lg_reset258w(0) <= NOT reset;
+ wire_w_lg_uav_readdatavalid257w(0) <= NOT uav_readdatavalid;
+ wire_w_lg_uav_waitrequest255w(0) <= NOT uav_waitrequest;
+ av_readdata <= ( uav_readdata(31 DOWNTO 0));
+ av_waitrequest <= wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_av_waitrequest_183m_dataout;
+ s_wire_vcc <= '1';
+ uav_address <= ( av_address(12 DOWNTO 0) & "0" & "0");
+ uav_burstcount <= ( "1" & "0" & "0");
+ uav_byteenable <= ( "1" & "1" & "1" & "1");
+ uav_debugaccess <= '0';
+ uav_lock <= '0';
+ uav_read <= (av_read AND wire_nO_w51w(0));
+ uav_write <= av_write;
+ uav_writedata <= ( av_writedata(31 DOWNTO 0));
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_186q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_186q <= wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_181m_dataout;
+ END IF;
+ END PROCESS;
+ wire_nO_w51w(0) <= NOT altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_186q;
+ wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_av_waitrequest_183m_dataout <= wire_w_lg_uav_readdatavalid257w(0) WHEN av_read = '1' ELSE uav_waitrequest;
+ wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_177m_dataout <= altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_186q AND NOT((uav_readdatavalid AND altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_186q));
+ wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_180m_dataout <= (wire_w_lg_uav_waitrequest255w(0) AND av_read) AND wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_av_waitrequest_183m_dataout;
+ wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_181m_dataout <= wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_177m_dataout WHEN altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_186q = '1' ELSE wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_180m_dataout;
+
+ END RTL; --altera_merlin_master_translator_0001
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_master_translator/altera_merlin_master_translator_0002.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_master_translator/altera_merlin_master_translator_0002.vho
new file mode 100644
index 0000000000000000000000000000000000000000..e48147ca75bb47adc1087be41f392087feb9c1e4
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_master_translator/altera_merlin_master_translator_0002.vho
@@ -0,0 +1,80 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_master_translator_0002 IS
+ PORT
+ (
+ av_address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
+ av_burstcount : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+ av_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+ av_debugaccess : IN STD_LOGIC;
+ av_lock : IN STD_LOGIC;
+ av_read : IN STD_LOGIC;
+ av_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ av_readdatavalid : OUT STD_LOGIC;
+ av_waitrequest : OUT STD_LOGIC;
+ av_write : IN STD_LOGIC;
+ av_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ clk : IN STD_LOGIC;
+ reset : IN STD_LOGIC;
+ uav_address : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
+ uav_burstcount : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ uav_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+ uav_debugaccess : OUT STD_LOGIC;
+ uav_lock : OUT STD_LOGIC;
+ uav_read : OUT STD_LOGIC;
+ uav_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ uav_readdatavalid : IN STD_LOGIC;
+ uav_waitrequest : IN STD_LOGIC;
+ uav_write : OUT STD_LOGIC;
+ uav_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+ );
+ END altera_merlin_master_translator_0002;
+
+ ARCHITECTURE RTL OF altera_merlin_master_translator_0002 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ BEGIN
+
+ av_readdata <= ( uav_readdata(31 DOWNTO 0));
+ av_readdatavalid <= uav_readdatavalid;
+ av_waitrequest <= uav_waitrequest;
+ uav_address <= ( av_address(14 DOWNTO 0));
+ uav_burstcount <= ( av_burstcount(2 DOWNTO 0));
+ uav_byteenable <= ( av_byteenable(3 DOWNTO 0));
+ uav_debugaccess <= av_debugaccess;
+ uav_lock <= av_lock;
+ uav_read <= av_read;
+ uav_write <= av_write;
+ uav_writedata <= ( av_writedata(31 DOWNTO 0));
+
+ END RTL; --altera_merlin_master_translator_0002
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_master_translator/altera_merlin_master_translator_0003.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_master_translator/altera_merlin_master_translator_0003.vho
new file mode 100644
index 0000000000000000000000000000000000000000..591af96257796bd5dc743eb5bb5f3cbca430dd59
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_master_translator/altera_merlin_master_translator_0003.vho
@@ -0,0 +1,79 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_master_translator_0003 IS
+ PORT
+ (
+ av_address : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
+ av_burstcount : IN STD_LOGIC;
+ av_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+ av_debugaccess : IN STD_LOGIC;
+ av_read : IN STD_LOGIC;
+ av_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ av_readdatavalid : OUT STD_LOGIC;
+ av_waitrequest : OUT STD_LOGIC;
+ av_write : IN STD_LOGIC;
+ av_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ clk : IN STD_LOGIC;
+ reset : IN STD_LOGIC;
+ uav_address : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
+ uav_burstcount : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ uav_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+ uav_debugaccess : OUT STD_LOGIC;
+ uav_lock : OUT STD_LOGIC;
+ uav_read : OUT STD_LOGIC;
+ uav_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ uav_readdatavalid : IN STD_LOGIC;
+ uav_waitrequest : IN STD_LOGIC;
+ uav_write : OUT STD_LOGIC;
+ uav_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+ );
+ END altera_merlin_master_translator_0003;
+
+ ARCHITECTURE RTL OF altera_merlin_master_translator_0003 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ BEGIN
+
+ av_readdata <= ( uav_readdata(31 DOWNTO 0));
+ av_readdatavalid <= uav_readdatavalid;
+ av_waitrequest <= uav_waitrequest;
+ uav_address <= ( av_address(13 DOWNTO 0));
+ uav_burstcount <= ( av_burstcount & "0" & "0");
+ uav_byteenable <= ( av_byteenable(3 DOWNTO 0));
+ uav_debugaccess <= av_debugaccess;
+ uav_lock <= '0';
+ uav_read <= av_read;
+ uav_write <= av_write;
+ uav_writedata <= ( av_writedata(31 DOWNTO 0));
+
+ END RTL; --altera_merlin_master_translator_0003
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_multiplexer/altera_merlin_multiplexer_0001.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_multiplexer/altera_merlin_multiplexer_0001.vho
new file mode 100644
index 0000000000000000000000000000000000000000..9dc7f8a76e5d0674e4b4a913cd43142a1259422c
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_multiplexer/altera_merlin_multiplexer_0001.vho
@@ -0,0 +1,753 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_multiplexer_0001 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ reset : IN STD_LOGIC;
+ sink0_channel : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+ sink0_data : IN STD_LOGIC_VECTOR (65 DOWNTO 0);
+ sink0_endofpacket : IN STD_LOGIC;
+ sink0_ready : OUT STD_LOGIC;
+ sink0_startofpacket : IN STD_LOGIC;
+ sink0_valid : IN STD_LOGIC;
+ sink1_channel : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+ sink1_data : IN STD_LOGIC_VECTOR (65 DOWNTO 0);
+ sink1_endofpacket : IN STD_LOGIC;
+ sink1_ready : OUT STD_LOGIC;
+ sink1_startofpacket : IN STD_LOGIC;
+ sink1_valid : IN STD_LOGIC;
+ src_channel : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+ src_data : OUT STD_LOGIC_VECTOR (65 DOWNTO 0);
+ src_endofpacket : OUT STD_LOGIC;
+ src_ready : IN STD_LOGIC;
+ src_startofpacket : OUT STD_LOGIC;
+ src_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_multiplexer_0001;
+
+ ARCHITECTURE RTL OF altera_merlin_multiplexer_0001 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL wire_w_lg_sink0_valid402w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid409w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid5w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid66w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid72w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid78w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid84w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid90w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid96w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid114w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid120w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid12w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid126w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid132w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid138w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid144w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid150w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid156w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid162w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid168w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid174w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid180w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid18w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid186w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid192w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid198w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid204w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid216w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid222w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid228w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid234w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid240w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid24w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid246w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid252w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid258w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid264w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid270w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid276w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid282w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid288w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid294w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid300w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid30w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid306w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid312w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid318w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid324w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid330w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid336w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid342w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid348w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid354w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid360w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid366w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid372w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid378w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid384w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid390w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid396w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid48w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid54w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid404w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid411w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid7w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid68w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid74w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid80w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid86w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid92w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid98w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid104w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid116w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid122w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid14w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid128w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid134w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid140w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid146w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid152w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid158w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid164w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid170w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid176w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid182w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid20w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid188w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid194w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid200w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid206w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid212w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid218w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid224w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid230w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid236w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid242w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid26w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid248w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid254w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid260w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid266w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid272w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid278w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid284w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid290w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid296w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid302w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid32w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid308w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid314w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid320w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid326w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid332w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid338w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid344w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid350w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid356w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid362w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid38w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid368w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid374w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid380w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid386w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid392w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid398w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid44w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid50w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid56w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid402w405w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid409w412w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid5w8w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid66w69w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid72w75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid78w81w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid84w87w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid90w93w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid96w99w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid102w105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid108w111w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid114w117w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid120w123w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid12w15w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid126w129w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid132w135w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid138w141w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid144w147w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid150w153w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid156w159w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid162w165w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid168w171w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid174w177w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid180w183w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid18w21w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid186w189w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid192w195w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid198w201w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid204w207w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid210w213w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid216w219w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid222w225w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid228w231w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid234w237w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid240w243w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid24w27w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid246w249w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid252w255w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid258w261w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid264w267w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid270w273w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid276w279w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid282w285w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid288w291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid294w297w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid300w303w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid30w33w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid306w309w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid312w315w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid318w321w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid324w327w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid330w333w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid336w339w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid342w345w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid348w351w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid354w357w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid360w363w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid36w39w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid366w369w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid372w375w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid378w381w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid384w387w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid390w393w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid396w399w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid42w45w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid48w51w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid54w57w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid60w63w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_channel_range401w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_channel_range408w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range4w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range65w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range71w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range77w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range83w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range89w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range95w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range11w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range125w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range137w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range143w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range149w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range155w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range161w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range167w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range173w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range17w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range185w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range191w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range197w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range203w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range215w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range221w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range227w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range233w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range239w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range23w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range245w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range251w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range257w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range263w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range269w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range275w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range281w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range287w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range293w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range299w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range29w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range305w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range311w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range317w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range323w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range329w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range335w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range341w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range347w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range353w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range359w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range35w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range365w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range371w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range377w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range383w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range389w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range395w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range47w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range53w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range59w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_channel_range403w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_channel_range410w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range6w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range67w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range73w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range79w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range85w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range91w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range115w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range121w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range13w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range127w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range133w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range145w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range151w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range157w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range163w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range169w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range175w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range181w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range19w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range193w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range199w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range205w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range217w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range223w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range229w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range235w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range241w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range25w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range247w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range253w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range259w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range265w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range271w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range277w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range283w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range289w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range295w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range301w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range31w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range307w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range313w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range319w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range325w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range331w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range337w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range343w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range349w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range355w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range361w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range367w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range373w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range379w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range385w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range391w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range397w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range43w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range49w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range55w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+ wire_w_lg_sink0_valid402w(0) <= sink0_valid AND wire_w_sink0_channel_range401w(0);
+ wire_w_lg_sink0_valid409w(0) <= sink0_valid AND wire_w_sink0_channel_range408w(0);
+ wire_w_lg_sink0_valid5w(0) <= sink0_valid AND wire_w_sink0_data_range4w(0);
+ wire_w_lg_sink0_valid66w(0) <= sink0_valid AND wire_w_sink0_data_range65w(0);
+ wire_w_lg_sink0_valid72w(0) <= sink0_valid AND wire_w_sink0_data_range71w(0);
+ wire_w_lg_sink0_valid78w(0) <= sink0_valid AND wire_w_sink0_data_range77w(0);
+ wire_w_lg_sink0_valid84w(0) <= sink0_valid AND wire_w_sink0_data_range83w(0);
+ wire_w_lg_sink0_valid90w(0) <= sink0_valid AND wire_w_sink0_data_range89w(0);
+ wire_w_lg_sink0_valid96w(0) <= sink0_valid AND wire_w_sink0_data_range95w(0);
+ wire_w_lg_sink0_valid102w(0) <= sink0_valid AND wire_w_sink0_data_range101w(0);
+ wire_w_lg_sink0_valid108w(0) <= sink0_valid AND wire_w_sink0_data_range107w(0);
+ wire_w_lg_sink0_valid114w(0) <= sink0_valid AND wire_w_sink0_data_range113w(0);
+ wire_w_lg_sink0_valid120w(0) <= sink0_valid AND wire_w_sink0_data_range119w(0);
+ wire_w_lg_sink0_valid12w(0) <= sink0_valid AND wire_w_sink0_data_range11w(0);
+ wire_w_lg_sink0_valid126w(0) <= sink0_valid AND wire_w_sink0_data_range125w(0);
+ wire_w_lg_sink0_valid132w(0) <= sink0_valid AND wire_w_sink0_data_range131w(0);
+ wire_w_lg_sink0_valid138w(0) <= sink0_valid AND wire_w_sink0_data_range137w(0);
+ wire_w_lg_sink0_valid144w(0) <= sink0_valid AND wire_w_sink0_data_range143w(0);
+ wire_w_lg_sink0_valid150w(0) <= sink0_valid AND wire_w_sink0_data_range149w(0);
+ wire_w_lg_sink0_valid156w(0) <= sink0_valid AND wire_w_sink0_data_range155w(0);
+ wire_w_lg_sink0_valid162w(0) <= sink0_valid AND wire_w_sink0_data_range161w(0);
+ wire_w_lg_sink0_valid168w(0) <= sink0_valid AND wire_w_sink0_data_range167w(0);
+ wire_w_lg_sink0_valid174w(0) <= sink0_valid AND wire_w_sink0_data_range173w(0);
+ wire_w_lg_sink0_valid180w(0) <= sink0_valid AND wire_w_sink0_data_range179w(0);
+ wire_w_lg_sink0_valid18w(0) <= sink0_valid AND wire_w_sink0_data_range17w(0);
+ wire_w_lg_sink0_valid186w(0) <= sink0_valid AND wire_w_sink0_data_range185w(0);
+ wire_w_lg_sink0_valid192w(0) <= sink0_valid AND wire_w_sink0_data_range191w(0);
+ wire_w_lg_sink0_valid198w(0) <= sink0_valid AND wire_w_sink0_data_range197w(0);
+ wire_w_lg_sink0_valid204w(0) <= sink0_valid AND wire_w_sink0_data_range203w(0);
+ wire_w_lg_sink0_valid210w(0) <= sink0_valid AND wire_w_sink0_data_range209w(0);
+ wire_w_lg_sink0_valid216w(0) <= sink0_valid AND wire_w_sink0_data_range215w(0);
+ wire_w_lg_sink0_valid222w(0) <= sink0_valid AND wire_w_sink0_data_range221w(0);
+ wire_w_lg_sink0_valid228w(0) <= sink0_valid AND wire_w_sink0_data_range227w(0);
+ wire_w_lg_sink0_valid234w(0) <= sink0_valid AND wire_w_sink0_data_range233w(0);
+ wire_w_lg_sink0_valid240w(0) <= sink0_valid AND wire_w_sink0_data_range239w(0);
+ wire_w_lg_sink0_valid24w(0) <= sink0_valid AND wire_w_sink0_data_range23w(0);
+ wire_w_lg_sink0_valid246w(0) <= sink0_valid AND wire_w_sink0_data_range245w(0);
+ wire_w_lg_sink0_valid252w(0) <= sink0_valid AND wire_w_sink0_data_range251w(0);
+ wire_w_lg_sink0_valid258w(0) <= sink0_valid AND wire_w_sink0_data_range257w(0);
+ wire_w_lg_sink0_valid264w(0) <= sink0_valid AND wire_w_sink0_data_range263w(0);
+ wire_w_lg_sink0_valid270w(0) <= sink0_valid AND wire_w_sink0_data_range269w(0);
+ wire_w_lg_sink0_valid276w(0) <= sink0_valid AND wire_w_sink0_data_range275w(0);
+ wire_w_lg_sink0_valid282w(0) <= sink0_valid AND wire_w_sink0_data_range281w(0);
+ wire_w_lg_sink0_valid288w(0) <= sink0_valid AND wire_w_sink0_data_range287w(0);
+ wire_w_lg_sink0_valid294w(0) <= sink0_valid AND wire_w_sink0_data_range293w(0);
+ wire_w_lg_sink0_valid300w(0) <= sink0_valid AND wire_w_sink0_data_range299w(0);
+ wire_w_lg_sink0_valid30w(0) <= sink0_valid AND wire_w_sink0_data_range29w(0);
+ wire_w_lg_sink0_valid306w(0) <= sink0_valid AND wire_w_sink0_data_range305w(0);
+ wire_w_lg_sink0_valid312w(0) <= sink0_valid AND wire_w_sink0_data_range311w(0);
+ wire_w_lg_sink0_valid318w(0) <= sink0_valid AND wire_w_sink0_data_range317w(0);
+ wire_w_lg_sink0_valid324w(0) <= sink0_valid AND wire_w_sink0_data_range323w(0);
+ wire_w_lg_sink0_valid330w(0) <= sink0_valid AND wire_w_sink0_data_range329w(0);
+ wire_w_lg_sink0_valid336w(0) <= sink0_valid AND wire_w_sink0_data_range335w(0);
+ wire_w_lg_sink0_valid342w(0) <= sink0_valid AND wire_w_sink0_data_range341w(0);
+ wire_w_lg_sink0_valid348w(0) <= sink0_valid AND wire_w_sink0_data_range347w(0);
+ wire_w_lg_sink0_valid354w(0) <= sink0_valid AND wire_w_sink0_data_range353w(0);
+ wire_w_lg_sink0_valid360w(0) <= sink0_valid AND wire_w_sink0_data_range359w(0);
+ wire_w_lg_sink0_valid36w(0) <= sink0_valid AND wire_w_sink0_data_range35w(0);
+ wire_w_lg_sink0_valid366w(0) <= sink0_valid AND wire_w_sink0_data_range365w(0);
+ wire_w_lg_sink0_valid372w(0) <= sink0_valid AND wire_w_sink0_data_range371w(0);
+ wire_w_lg_sink0_valid378w(0) <= sink0_valid AND wire_w_sink0_data_range377w(0);
+ wire_w_lg_sink0_valid384w(0) <= sink0_valid AND wire_w_sink0_data_range383w(0);
+ wire_w_lg_sink0_valid390w(0) <= sink0_valid AND wire_w_sink0_data_range389w(0);
+ wire_w_lg_sink0_valid396w(0) <= sink0_valid AND wire_w_sink0_data_range395w(0);
+ wire_w_lg_sink0_valid42w(0) <= sink0_valid AND wire_w_sink0_data_range41w(0);
+ wire_w_lg_sink0_valid48w(0) <= sink0_valid AND wire_w_sink0_data_range47w(0);
+ wire_w_lg_sink0_valid54w(0) <= sink0_valid AND wire_w_sink0_data_range53w(0);
+ wire_w_lg_sink0_valid60w(0) <= sink0_valid AND wire_w_sink0_data_range59w(0);
+ wire_w_lg_sink1_valid404w(0) <= sink1_valid AND wire_w_sink1_channel_range403w(0);
+ wire_w_lg_sink1_valid411w(0) <= sink1_valid AND wire_w_sink1_channel_range410w(0);
+ wire_w_lg_sink1_valid7w(0) <= sink1_valid AND wire_w_sink1_data_range6w(0);
+ wire_w_lg_sink1_valid68w(0) <= sink1_valid AND wire_w_sink1_data_range67w(0);
+ wire_w_lg_sink1_valid74w(0) <= sink1_valid AND wire_w_sink1_data_range73w(0);
+ wire_w_lg_sink1_valid80w(0) <= sink1_valid AND wire_w_sink1_data_range79w(0);
+ wire_w_lg_sink1_valid86w(0) <= sink1_valid AND wire_w_sink1_data_range85w(0);
+ wire_w_lg_sink1_valid92w(0) <= sink1_valid AND wire_w_sink1_data_range91w(0);
+ wire_w_lg_sink1_valid98w(0) <= sink1_valid AND wire_w_sink1_data_range97w(0);
+ wire_w_lg_sink1_valid104w(0) <= sink1_valid AND wire_w_sink1_data_range103w(0);
+ wire_w_lg_sink1_valid110w(0) <= sink1_valid AND wire_w_sink1_data_range109w(0);
+ wire_w_lg_sink1_valid116w(0) <= sink1_valid AND wire_w_sink1_data_range115w(0);
+ wire_w_lg_sink1_valid122w(0) <= sink1_valid AND wire_w_sink1_data_range121w(0);
+ wire_w_lg_sink1_valid14w(0) <= sink1_valid AND wire_w_sink1_data_range13w(0);
+ wire_w_lg_sink1_valid128w(0) <= sink1_valid AND wire_w_sink1_data_range127w(0);
+ wire_w_lg_sink1_valid134w(0) <= sink1_valid AND wire_w_sink1_data_range133w(0);
+ wire_w_lg_sink1_valid140w(0) <= sink1_valid AND wire_w_sink1_data_range139w(0);
+ wire_w_lg_sink1_valid146w(0) <= sink1_valid AND wire_w_sink1_data_range145w(0);
+ wire_w_lg_sink1_valid152w(0) <= sink1_valid AND wire_w_sink1_data_range151w(0);
+ wire_w_lg_sink1_valid158w(0) <= sink1_valid AND wire_w_sink1_data_range157w(0);
+ wire_w_lg_sink1_valid164w(0) <= sink1_valid AND wire_w_sink1_data_range163w(0);
+ wire_w_lg_sink1_valid170w(0) <= sink1_valid AND wire_w_sink1_data_range169w(0);
+ wire_w_lg_sink1_valid176w(0) <= sink1_valid AND wire_w_sink1_data_range175w(0);
+ wire_w_lg_sink1_valid182w(0) <= sink1_valid AND wire_w_sink1_data_range181w(0);
+ wire_w_lg_sink1_valid20w(0) <= sink1_valid AND wire_w_sink1_data_range19w(0);
+ wire_w_lg_sink1_valid188w(0) <= sink1_valid AND wire_w_sink1_data_range187w(0);
+ wire_w_lg_sink1_valid194w(0) <= sink1_valid AND wire_w_sink1_data_range193w(0);
+ wire_w_lg_sink1_valid200w(0) <= sink1_valid AND wire_w_sink1_data_range199w(0);
+ wire_w_lg_sink1_valid206w(0) <= sink1_valid AND wire_w_sink1_data_range205w(0);
+ wire_w_lg_sink1_valid212w(0) <= sink1_valid AND wire_w_sink1_data_range211w(0);
+ wire_w_lg_sink1_valid218w(0) <= sink1_valid AND wire_w_sink1_data_range217w(0);
+ wire_w_lg_sink1_valid224w(0) <= sink1_valid AND wire_w_sink1_data_range223w(0);
+ wire_w_lg_sink1_valid230w(0) <= sink1_valid AND wire_w_sink1_data_range229w(0);
+ wire_w_lg_sink1_valid236w(0) <= sink1_valid AND wire_w_sink1_data_range235w(0);
+ wire_w_lg_sink1_valid242w(0) <= sink1_valid AND wire_w_sink1_data_range241w(0);
+ wire_w_lg_sink1_valid26w(0) <= sink1_valid AND wire_w_sink1_data_range25w(0);
+ wire_w_lg_sink1_valid248w(0) <= sink1_valid AND wire_w_sink1_data_range247w(0);
+ wire_w_lg_sink1_valid254w(0) <= sink1_valid AND wire_w_sink1_data_range253w(0);
+ wire_w_lg_sink1_valid260w(0) <= sink1_valid AND wire_w_sink1_data_range259w(0);
+ wire_w_lg_sink1_valid266w(0) <= sink1_valid AND wire_w_sink1_data_range265w(0);
+ wire_w_lg_sink1_valid272w(0) <= sink1_valid AND wire_w_sink1_data_range271w(0);
+ wire_w_lg_sink1_valid278w(0) <= sink1_valid AND wire_w_sink1_data_range277w(0);
+ wire_w_lg_sink1_valid284w(0) <= sink1_valid AND wire_w_sink1_data_range283w(0);
+ wire_w_lg_sink1_valid290w(0) <= sink1_valid AND wire_w_sink1_data_range289w(0);
+ wire_w_lg_sink1_valid296w(0) <= sink1_valid AND wire_w_sink1_data_range295w(0);
+ wire_w_lg_sink1_valid302w(0) <= sink1_valid AND wire_w_sink1_data_range301w(0);
+ wire_w_lg_sink1_valid32w(0) <= sink1_valid AND wire_w_sink1_data_range31w(0);
+ wire_w_lg_sink1_valid308w(0) <= sink1_valid AND wire_w_sink1_data_range307w(0);
+ wire_w_lg_sink1_valid314w(0) <= sink1_valid AND wire_w_sink1_data_range313w(0);
+ wire_w_lg_sink1_valid320w(0) <= sink1_valid AND wire_w_sink1_data_range319w(0);
+ wire_w_lg_sink1_valid326w(0) <= sink1_valid AND wire_w_sink1_data_range325w(0);
+ wire_w_lg_sink1_valid332w(0) <= sink1_valid AND wire_w_sink1_data_range331w(0);
+ wire_w_lg_sink1_valid338w(0) <= sink1_valid AND wire_w_sink1_data_range337w(0);
+ wire_w_lg_sink1_valid344w(0) <= sink1_valid AND wire_w_sink1_data_range343w(0);
+ wire_w_lg_sink1_valid350w(0) <= sink1_valid AND wire_w_sink1_data_range349w(0);
+ wire_w_lg_sink1_valid356w(0) <= sink1_valid AND wire_w_sink1_data_range355w(0);
+ wire_w_lg_sink1_valid362w(0) <= sink1_valid AND wire_w_sink1_data_range361w(0);
+ wire_w_lg_sink1_valid38w(0) <= sink1_valid AND wire_w_sink1_data_range37w(0);
+ wire_w_lg_sink1_valid368w(0) <= sink1_valid AND wire_w_sink1_data_range367w(0);
+ wire_w_lg_sink1_valid374w(0) <= sink1_valid AND wire_w_sink1_data_range373w(0);
+ wire_w_lg_sink1_valid380w(0) <= sink1_valid AND wire_w_sink1_data_range379w(0);
+ wire_w_lg_sink1_valid386w(0) <= sink1_valid AND wire_w_sink1_data_range385w(0);
+ wire_w_lg_sink1_valid392w(0) <= sink1_valid AND wire_w_sink1_data_range391w(0);
+ wire_w_lg_sink1_valid398w(0) <= sink1_valid AND wire_w_sink1_data_range397w(0);
+ wire_w_lg_sink1_valid44w(0) <= sink1_valid AND wire_w_sink1_data_range43w(0);
+ wire_w_lg_sink1_valid50w(0) <= sink1_valid AND wire_w_sink1_data_range49w(0);
+ wire_w_lg_sink1_valid56w(0) <= sink1_valid AND wire_w_sink1_data_range55w(0);
+ wire_w_lg_sink1_valid62w(0) <= sink1_valid AND wire_w_sink1_data_range61w(0);
+ wire_w_lg_w_lg_sink0_valid402w405w(0) <= wire_w_lg_sink0_valid402w(0) OR wire_w_lg_sink1_valid404w(0);
+ wire_w_lg_w_lg_sink0_valid409w412w(0) <= wire_w_lg_sink0_valid409w(0) OR wire_w_lg_sink1_valid411w(0);
+ wire_w_lg_w_lg_sink0_valid5w8w(0) <= wire_w_lg_sink0_valid5w(0) OR wire_w_lg_sink1_valid7w(0);
+ wire_w_lg_w_lg_sink0_valid66w69w(0) <= wire_w_lg_sink0_valid66w(0) OR wire_w_lg_sink1_valid68w(0);
+ wire_w_lg_w_lg_sink0_valid72w75w(0) <= wire_w_lg_sink0_valid72w(0) OR wire_w_lg_sink1_valid74w(0);
+ wire_w_lg_w_lg_sink0_valid78w81w(0) <= wire_w_lg_sink0_valid78w(0) OR wire_w_lg_sink1_valid80w(0);
+ wire_w_lg_w_lg_sink0_valid84w87w(0) <= wire_w_lg_sink0_valid84w(0) OR wire_w_lg_sink1_valid86w(0);
+ wire_w_lg_w_lg_sink0_valid90w93w(0) <= wire_w_lg_sink0_valid90w(0) OR wire_w_lg_sink1_valid92w(0);
+ wire_w_lg_w_lg_sink0_valid96w99w(0) <= wire_w_lg_sink0_valid96w(0) OR wire_w_lg_sink1_valid98w(0);
+ wire_w_lg_w_lg_sink0_valid102w105w(0) <= wire_w_lg_sink0_valid102w(0) OR wire_w_lg_sink1_valid104w(0);
+ wire_w_lg_w_lg_sink0_valid108w111w(0) <= wire_w_lg_sink0_valid108w(0) OR wire_w_lg_sink1_valid110w(0);
+ wire_w_lg_w_lg_sink0_valid114w117w(0) <= wire_w_lg_sink0_valid114w(0) OR wire_w_lg_sink1_valid116w(0);
+ wire_w_lg_w_lg_sink0_valid120w123w(0) <= wire_w_lg_sink0_valid120w(0) OR wire_w_lg_sink1_valid122w(0);
+ wire_w_lg_w_lg_sink0_valid12w15w(0) <= wire_w_lg_sink0_valid12w(0) OR wire_w_lg_sink1_valid14w(0);
+ wire_w_lg_w_lg_sink0_valid126w129w(0) <= wire_w_lg_sink0_valid126w(0) OR wire_w_lg_sink1_valid128w(0);
+ wire_w_lg_w_lg_sink0_valid132w135w(0) <= wire_w_lg_sink0_valid132w(0) OR wire_w_lg_sink1_valid134w(0);
+ wire_w_lg_w_lg_sink0_valid138w141w(0) <= wire_w_lg_sink0_valid138w(0) OR wire_w_lg_sink1_valid140w(0);
+ wire_w_lg_w_lg_sink0_valid144w147w(0) <= wire_w_lg_sink0_valid144w(0) OR wire_w_lg_sink1_valid146w(0);
+ wire_w_lg_w_lg_sink0_valid150w153w(0) <= wire_w_lg_sink0_valid150w(0) OR wire_w_lg_sink1_valid152w(0);
+ wire_w_lg_w_lg_sink0_valid156w159w(0) <= wire_w_lg_sink0_valid156w(0) OR wire_w_lg_sink1_valid158w(0);
+ wire_w_lg_w_lg_sink0_valid162w165w(0) <= wire_w_lg_sink0_valid162w(0) OR wire_w_lg_sink1_valid164w(0);
+ wire_w_lg_w_lg_sink0_valid168w171w(0) <= wire_w_lg_sink0_valid168w(0) OR wire_w_lg_sink1_valid170w(0);
+ wire_w_lg_w_lg_sink0_valid174w177w(0) <= wire_w_lg_sink0_valid174w(0) OR wire_w_lg_sink1_valid176w(0);
+ wire_w_lg_w_lg_sink0_valid180w183w(0) <= wire_w_lg_sink0_valid180w(0) OR wire_w_lg_sink1_valid182w(0);
+ wire_w_lg_w_lg_sink0_valid18w21w(0) <= wire_w_lg_sink0_valid18w(0) OR wire_w_lg_sink1_valid20w(0);
+ wire_w_lg_w_lg_sink0_valid186w189w(0) <= wire_w_lg_sink0_valid186w(0) OR wire_w_lg_sink1_valid188w(0);
+ wire_w_lg_w_lg_sink0_valid192w195w(0) <= wire_w_lg_sink0_valid192w(0) OR wire_w_lg_sink1_valid194w(0);
+ wire_w_lg_w_lg_sink0_valid198w201w(0) <= wire_w_lg_sink0_valid198w(0) OR wire_w_lg_sink1_valid200w(0);
+ wire_w_lg_w_lg_sink0_valid204w207w(0) <= wire_w_lg_sink0_valid204w(0) OR wire_w_lg_sink1_valid206w(0);
+ wire_w_lg_w_lg_sink0_valid210w213w(0) <= wire_w_lg_sink0_valid210w(0) OR wire_w_lg_sink1_valid212w(0);
+ wire_w_lg_w_lg_sink0_valid216w219w(0) <= wire_w_lg_sink0_valid216w(0) OR wire_w_lg_sink1_valid218w(0);
+ wire_w_lg_w_lg_sink0_valid222w225w(0) <= wire_w_lg_sink0_valid222w(0) OR wire_w_lg_sink1_valid224w(0);
+ wire_w_lg_w_lg_sink0_valid228w231w(0) <= wire_w_lg_sink0_valid228w(0) OR wire_w_lg_sink1_valid230w(0);
+ wire_w_lg_w_lg_sink0_valid234w237w(0) <= wire_w_lg_sink0_valid234w(0) OR wire_w_lg_sink1_valid236w(0);
+ wire_w_lg_w_lg_sink0_valid240w243w(0) <= wire_w_lg_sink0_valid240w(0) OR wire_w_lg_sink1_valid242w(0);
+ wire_w_lg_w_lg_sink0_valid24w27w(0) <= wire_w_lg_sink0_valid24w(0) OR wire_w_lg_sink1_valid26w(0);
+ wire_w_lg_w_lg_sink0_valid246w249w(0) <= wire_w_lg_sink0_valid246w(0) OR wire_w_lg_sink1_valid248w(0);
+ wire_w_lg_w_lg_sink0_valid252w255w(0) <= wire_w_lg_sink0_valid252w(0) OR wire_w_lg_sink1_valid254w(0);
+ wire_w_lg_w_lg_sink0_valid258w261w(0) <= wire_w_lg_sink0_valid258w(0) OR wire_w_lg_sink1_valid260w(0);
+ wire_w_lg_w_lg_sink0_valid264w267w(0) <= wire_w_lg_sink0_valid264w(0) OR wire_w_lg_sink1_valid266w(0);
+ wire_w_lg_w_lg_sink0_valid270w273w(0) <= wire_w_lg_sink0_valid270w(0) OR wire_w_lg_sink1_valid272w(0);
+ wire_w_lg_w_lg_sink0_valid276w279w(0) <= wire_w_lg_sink0_valid276w(0) OR wire_w_lg_sink1_valid278w(0);
+ wire_w_lg_w_lg_sink0_valid282w285w(0) <= wire_w_lg_sink0_valid282w(0) OR wire_w_lg_sink1_valid284w(0);
+ wire_w_lg_w_lg_sink0_valid288w291w(0) <= wire_w_lg_sink0_valid288w(0) OR wire_w_lg_sink1_valid290w(0);
+ wire_w_lg_w_lg_sink0_valid294w297w(0) <= wire_w_lg_sink0_valid294w(0) OR wire_w_lg_sink1_valid296w(0);
+ wire_w_lg_w_lg_sink0_valid300w303w(0) <= wire_w_lg_sink0_valid300w(0) OR wire_w_lg_sink1_valid302w(0);
+ wire_w_lg_w_lg_sink0_valid30w33w(0) <= wire_w_lg_sink0_valid30w(0) OR wire_w_lg_sink1_valid32w(0);
+ wire_w_lg_w_lg_sink0_valid306w309w(0) <= wire_w_lg_sink0_valid306w(0) OR wire_w_lg_sink1_valid308w(0);
+ wire_w_lg_w_lg_sink0_valid312w315w(0) <= wire_w_lg_sink0_valid312w(0) OR wire_w_lg_sink1_valid314w(0);
+ wire_w_lg_w_lg_sink0_valid318w321w(0) <= wire_w_lg_sink0_valid318w(0) OR wire_w_lg_sink1_valid320w(0);
+ wire_w_lg_w_lg_sink0_valid324w327w(0) <= wire_w_lg_sink0_valid324w(0) OR wire_w_lg_sink1_valid326w(0);
+ wire_w_lg_w_lg_sink0_valid330w333w(0) <= wire_w_lg_sink0_valid330w(0) OR wire_w_lg_sink1_valid332w(0);
+ wire_w_lg_w_lg_sink0_valid336w339w(0) <= wire_w_lg_sink0_valid336w(0) OR wire_w_lg_sink1_valid338w(0);
+ wire_w_lg_w_lg_sink0_valid342w345w(0) <= wire_w_lg_sink0_valid342w(0) OR wire_w_lg_sink1_valid344w(0);
+ wire_w_lg_w_lg_sink0_valid348w351w(0) <= wire_w_lg_sink0_valid348w(0) OR wire_w_lg_sink1_valid350w(0);
+ wire_w_lg_w_lg_sink0_valid354w357w(0) <= wire_w_lg_sink0_valid354w(0) OR wire_w_lg_sink1_valid356w(0);
+ wire_w_lg_w_lg_sink0_valid360w363w(0) <= wire_w_lg_sink0_valid360w(0) OR wire_w_lg_sink1_valid362w(0);
+ wire_w_lg_w_lg_sink0_valid36w39w(0) <= wire_w_lg_sink0_valid36w(0) OR wire_w_lg_sink1_valid38w(0);
+ wire_w_lg_w_lg_sink0_valid366w369w(0) <= wire_w_lg_sink0_valid366w(0) OR wire_w_lg_sink1_valid368w(0);
+ wire_w_lg_w_lg_sink0_valid372w375w(0) <= wire_w_lg_sink0_valid372w(0) OR wire_w_lg_sink1_valid374w(0);
+ wire_w_lg_w_lg_sink0_valid378w381w(0) <= wire_w_lg_sink0_valid378w(0) OR wire_w_lg_sink1_valid380w(0);
+ wire_w_lg_w_lg_sink0_valid384w387w(0) <= wire_w_lg_sink0_valid384w(0) OR wire_w_lg_sink1_valid386w(0);
+ wire_w_lg_w_lg_sink0_valid390w393w(0) <= wire_w_lg_sink0_valid390w(0) OR wire_w_lg_sink1_valid392w(0);
+ wire_w_lg_w_lg_sink0_valid396w399w(0) <= wire_w_lg_sink0_valid396w(0) OR wire_w_lg_sink1_valid398w(0);
+ wire_w_lg_w_lg_sink0_valid42w45w(0) <= wire_w_lg_sink0_valid42w(0) OR wire_w_lg_sink1_valid44w(0);
+ wire_w_lg_w_lg_sink0_valid48w51w(0) <= wire_w_lg_sink0_valid48w(0) OR wire_w_lg_sink1_valid50w(0);
+ wire_w_lg_w_lg_sink0_valid54w57w(0) <= wire_w_lg_sink0_valid54w(0) OR wire_w_lg_sink1_valid56w(0);
+ wire_w_lg_w_lg_sink0_valid60w63w(0) <= wire_w_lg_sink0_valid60w(0) OR wire_w_lg_sink1_valid62w(0);
+ sink0_ready <= (sink0_valid AND src_ready);
+ sink1_ready <= (sink1_valid AND src_ready);
+ src_channel <= ( wire_w_lg_w_lg_sink0_valid409w412w & wire_w_lg_w_lg_sink0_valid402w405w);
+ src_data <= ( wire_w_lg_w_lg_sink0_valid396w399w & wire_w_lg_w_lg_sink0_valid390w393w & wire_w_lg_w_lg_sink0_valid384w387w & wire_w_lg_w_lg_sink0_valid378w381w & wire_w_lg_w_lg_sink0_valid372w375w & wire_w_lg_w_lg_sink0_valid366w369w & wire_w_lg_w_lg_sink0_valid360w363w & wire_w_lg_w_lg_sink0_valid354w357w & wire_w_lg_w_lg_sink0_valid348w351w & wire_w_lg_w_lg_sink0_valid342w345w & wire_w_lg_w_lg_sink0_valid336w339w & wire_w_lg_w_lg_sink0_valid330w333w & wire_w_lg_w_lg_sink0_valid324w327w & wire_w_lg_w_lg_sink0_valid318w321w & wire_w_lg_w_lg_sink0_valid312w315w & wire_w_lg_w_lg_sink0_valid306w309w & wire_w_lg_w_lg_sink0_valid300w303w & wire_w_lg_w_lg_sink0_valid294w297w & wire_w_lg_w_lg_sink0_valid288w291w & wire_w_lg_w_lg_sink0_valid282w285w & wire_w_lg_w_lg_sink0_valid276w279w & wire_w_lg_w_lg_sink0_valid270w273w & wire_w_lg_w_lg_sink0_valid264w267w & wire_w_lg_w_lg_sink0_valid258w261w & wire_w_lg_w_lg_sink0_valid252w255w & wire_w_lg_w_lg_sink0_valid246w249w & wire_w_lg_w_lg_sink0_valid240w243w & wire_w_lg_w_lg_sink0_valid234w237w & wire_w_lg_w_lg_sink0_valid228w231w & wire_w_lg_w_lg_sink0_valid222w225w & wire_w_lg_w_lg_sink0_valid216w219w & wire_w_lg_w_lg_sink0_valid210w213w & wire_w_lg_w_lg_sink0_valid204w207w & wire_w_lg_w_lg_sink0_valid198w201w & wire_w_lg_w_lg_sink0_valid192w195w & wire_w_lg_w_lg_sink0_valid186w189w & wire_w_lg_w_lg_sink0_valid180w183w & wire_w_lg_w_lg_sink0_valid174w177w & wire_w_lg_w_lg_sink0_valid168w171w & wire_w_lg_w_lg_sink0_valid162w165w & wire_w_lg_w_lg_sink0_valid156w159w & wire_w_lg_w_lg_sink0_valid150w153w & wire_w_lg_w_lg_sink0_valid144w147w & wire_w_lg_w_lg_sink0_valid138w141w & wire_w_lg_w_lg_sink0_valid132w135w & wire_w_lg_w_lg_sink0_valid126w129w & wire_w_lg_w_lg_sink0_valid120w123w & wire_w_lg_w_lg_sink0_valid114w117w & wire_w_lg_w_lg_sink0_valid108w111w & wire_w_lg_w_lg_sink0_valid102w105w & wire_w_lg_w_lg_sink0_valid96w99w & wire_w_lg_w_lg_sink0_valid90w93w & wire_w_lg_w_lg_sink0_valid84w87w & wire_w_lg_w_lg_sink0_valid78w81w & wire_w_lg_w_lg_sink0_valid72w75w & wire_w_lg_w_lg_sink0_valid66w69w
+ & wire_w_lg_w_lg_sink0_valid60w63w & wire_w_lg_w_lg_sink0_valid54w57w & wire_w_lg_w_lg_sink0_valid48w51w & wire_w_lg_w_lg_sink0_valid42w45w & wire_w_lg_w_lg_sink0_valid36w39w & wire_w_lg_w_lg_sink0_valid30w33w & wire_w_lg_w_lg_sink0_valid24w27w & wire_w_lg_w_lg_sink0_valid18w21w & wire_w_lg_w_lg_sink0_valid12w15w & wire_w_lg_w_lg_sink0_valid5w8w);
+ src_endofpacket <= ((sink0_valid AND sink0_endofpacket) OR (sink1_valid AND sink1_endofpacket));
+ src_startofpacket <= ((sink0_valid AND sink0_startofpacket) OR (sink1_valid AND sink1_startofpacket));
+ src_valid <= (sink0_valid OR sink1_valid);
+ wire_w_sink0_channel_range401w(0) <= sink0_channel(0);
+ wire_w_sink0_channel_range408w(0) <= sink0_channel(1);
+ wire_w_sink0_data_range4w(0) <= sink0_data(0);
+ wire_w_sink0_data_range65w(0) <= sink0_data(10);
+ wire_w_sink0_data_range71w(0) <= sink0_data(11);
+ wire_w_sink0_data_range77w(0) <= sink0_data(12);
+ wire_w_sink0_data_range83w(0) <= sink0_data(13);
+ wire_w_sink0_data_range89w(0) <= sink0_data(14);
+ wire_w_sink0_data_range95w(0) <= sink0_data(15);
+ wire_w_sink0_data_range101w(0) <= sink0_data(16);
+ wire_w_sink0_data_range107w(0) <= sink0_data(17);
+ wire_w_sink0_data_range113w(0) <= sink0_data(18);
+ wire_w_sink0_data_range119w(0) <= sink0_data(19);
+ wire_w_sink0_data_range11w(0) <= sink0_data(1);
+ wire_w_sink0_data_range125w(0) <= sink0_data(20);
+ wire_w_sink0_data_range131w(0) <= sink0_data(21);
+ wire_w_sink0_data_range137w(0) <= sink0_data(22);
+ wire_w_sink0_data_range143w(0) <= sink0_data(23);
+ wire_w_sink0_data_range149w(0) <= sink0_data(24);
+ wire_w_sink0_data_range155w(0) <= sink0_data(25);
+ wire_w_sink0_data_range161w(0) <= sink0_data(26);
+ wire_w_sink0_data_range167w(0) <= sink0_data(27);
+ wire_w_sink0_data_range173w(0) <= sink0_data(28);
+ wire_w_sink0_data_range179w(0) <= sink0_data(29);
+ wire_w_sink0_data_range17w(0) <= sink0_data(2);
+ wire_w_sink0_data_range185w(0) <= sink0_data(30);
+ wire_w_sink0_data_range191w(0) <= sink0_data(31);
+ wire_w_sink0_data_range197w(0) <= sink0_data(32);
+ wire_w_sink0_data_range203w(0) <= sink0_data(33);
+ wire_w_sink0_data_range209w(0) <= sink0_data(34);
+ wire_w_sink0_data_range215w(0) <= sink0_data(35);
+ wire_w_sink0_data_range221w(0) <= sink0_data(36);
+ wire_w_sink0_data_range227w(0) <= sink0_data(37);
+ wire_w_sink0_data_range233w(0) <= sink0_data(38);
+ wire_w_sink0_data_range239w(0) <= sink0_data(39);
+ wire_w_sink0_data_range23w(0) <= sink0_data(3);
+ wire_w_sink0_data_range245w(0) <= sink0_data(40);
+ wire_w_sink0_data_range251w(0) <= sink0_data(41);
+ wire_w_sink0_data_range257w(0) <= sink0_data(42);
+ wire_w_sink0_data_range263w(0) <= sink0_data(43);
+ wire_w_sink0_data_range269w(0) <= sink0_data(44);
+ wire_w_sink0_data_range275w(0) <= sink0_data(45);
+ wire_w_sink0_data_range281w(0) <= sink0_data(46);
+ wire_w_sink0_data_range287w(0) <= sink0_data(47);
+ wire_w_sink0_data_range293w(0) <= sink0_data(48);
+ wire_w_sink0_data_range299w(0) <= sink0_data(49);
+ wire_w_sink0_data_range29w(0) <= sink0_data(4);
+ wire_w_sink0_data_range305w(0) <= sink0_data(50);
+ wire_w_sink0_data_range311w(0) <= sink0_data(51);
+ wire_w_sink0_data_range317w(0) <= sink0_data(52);
+ wire_w_sink0_data_range323w(0) <= sink0_data(53);
+ wire_w_sink0_data_range329w(0) <= sink0_data(54);
+ wire_w_sink0_data_range335w(0) <= sink0_data(55);
+ wire_w_sink0_data_range341w(0) <= sink0_data(56);
+ wire_w_sink0_data_range347w(0) <= sink0_data(57);
+ wire_w_sink0_data_range353w(0) <= sink0_data(58);
+ wire_w_sink0_data_range359w(0) <= sink0_data(59);
+ wire_w_sink0_data_range35w(0) <= sink0_data(5);
+ wire_w_sink0_data_range365w(0) <= sink0_data(60);
+ wire_w_sink0_data_range371w(0) <= sink0_data(61);
+ wire_w_sink0_data_range377w(0) <= sink0_data(62);
+ wire_w_sink0_data_range383w(0) <= sink0_data(63);
+ wire_w_sink0_data_range389w(0) <= sink0_data(64);
+ wire_w_sink0_data_range395w(0) <= sink0_data(65);
+ wire_w_sink0_data_range41w(0) <= sink0_data(6);
+ wire_w_sink0_data_range47w(0) <= sink0_data(7);
+ wire_w_sink0_data_range53w(0) <= sink0_data(8);
+ wire_w_sink0_data_range59w(0) <= sink0_data(9);
+ wire_w_sink1_channel_range403w(0) <= sink1_channel(0);
+ wire_w_sink1_channel_range410w(0) <= sink1_channel(1);
+ wire_w_sink1_data_range6w(0) <= sink1_data(0);
+ wire_w_sink1_data_range67w(0) <= sink1_data(10);
+ wire_w_sink1_data_range73w(0) <= sink1_data(11);
+ wire_w_sink1_data_range79w(0) <= sink1_data(12);
+ wire_w_sink1_data_range85w(0) <= sink1_data(13);
+ wire_w_sink1_data_range91w(0) <= sink1_data(14);
+ wire_w_sink1_data_range97w(0) <= sink1_data(15);
+ wire_w_sink1_data_range103w(0) <= sink1_data(16);
+ wire_w_sink1_data_range109w(0) <= sink1_data(17);
+ wire_w_sink1_data_range115w(0) <= sink1_data(18);
+ wire_w_sink1_data_range121w(0) <= sink1_data(19);
+ wire_w_sink1_data_range13w(0) <= sink1_data(1);
+ wire_w_sink1_data_range127w(0) <= sink1_data(20);
+ wire_w_sink1_data_range133w(0) <= sink1_data(21);
+ wire_w_sink1_data_range139w(0) <= sink1_data(22);
+ wire_w_sink1_data_range145w(0) <= sink1_data(23);
+ wire_w_sink1_data_range151w(0) <= sink1_data(24);
+ wire_w_sink1_data_range157w(0) <= sink1_data(25);
+ wire_w_sink1_data_range163w(0) <= sink1_data(26);
+ wire_w_sink1_data_range169w(0) <= sink1_data(27);
+ wire_w_sink1_data_range175w(0) <= sink1_data(28);
+ wire_w_sink1_data_range181w(0) <= sink1_data(29);
+ wire_w_sink1_data_range19w(0) <= sink1_data(2);
+ wire_w_sink1_data_range187w(0) <= sink1_data(30);
+ wire_w_sink1_data_range193w(0) <= sink1_data(31);
+ wire_w_sink1_data_range199w(0) <= sink1_data(32);
+ wire_w_sink1_data_range205w(0) <= sink1_data(33);
+ wire_w_sink1_data_range211w(0) <= sink1_data(34);
+ wire_w_sink1_data_range217w(0) <= sink1_data(35);
+ wire_w_sink1_data_range223w(0) <= sink1_data(36);
+ wire_w_sink1_data_range229w(0) <= sink1_data(37);
+ wire_w_sink1_data_range235w(0) <= sink1_data(38);
+ wire_w_sink1_data_range241w(0) <= sink1_data(39);
+ wire_w_sink1_data_range25w(0) <= sink1_data(3);
+ wire_w_sink1_data_range247w(0) <= sink1_data(40);
+ wire_w_sink1_data_range253w(0) <= sink1_data(41);
+ wire_w_sink1_data_range259w(0) <= sink1_data(42);
+ wire_w_sink1_data_range265w(0) <= sink1_data(43);
+ wire_w_sink1_data_range271w(0) <= sink1_data(44);
+ wire_w_sink1_data_range277w(0) <= sink1_data(45);
+ wire_w_sink1_data_range283w(0) <= sink1_data(46);
+ wire_w_sink1_data_range289w(0) <= sink1_data(47);
+ wire_w_sink1_data_range295w(0) <= sink1_data(48);
+ wire_w_sink1_data_range301w(0) <= sink1_data(49);
+ wire_w_sink1_data_range31w(0) <= sink1_data(4);
+ wire_w_sink1_data_range307w(0) <= sink1_data(50);
+ wire_w_sink1_data_range313w(0) <= sink1_data(51);
+ wire_w_sink1_data_range319w(0) <= sink1_data(52);
+ wire_w_sink1_data_range325w(0) <= sink1_data(53);
+ wire_w_sink1_data_range331w(0) <= sink1_data(54);
+ wire_w_sink1_data_range337w(0) <= sink1_data(55);
+ wire_w_sink1_data_range343w(0) <= sink1_data(56);
+ wire_w_sink1_data_range349w(0) <= sink1_data(57);
+ wire_w_sink1_data_range355w(0) <= sink1_data(58);
+ wire_w_sink1_data_range361w(0) <= sink1_data(59);
+ wire_w_sink1_data_range37w(0) <= sink1_data(5);
+ wire_w_sink1_data_range367w(0) <= sink1_data(60);
+ wire_w_sink1_data_range373w(0) <= sink1_data(61);
+ wire_w_sink1_data_range379w(0) <= sink1_data(62);
+ wire_w_sink1_data_range385w(0) <= sink1_data(63);
+ wire_w_sink1_data_range391w(0) <= sink1_data(64);
+ wire_w_sink1_data_range397w(0) <= sink1_data(65);
+ wire_w_sink1_data_range43w(0) <= sink1_data(6);
+ wire_w_sink1_data_range49w(0) <= sink1_data(7);
+ wire_w_sink1_data_range55w(0) <= sink1_data(8);
+ wire_w_sink1_data_range61w(0) <= sink1_data(9);
+
+ END RTL; --altera_merlin_multiplexer_0001
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_multiplexer/altera_merlin_multiplexer_0002.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_multiplexer/altera_merlin_multiplexer_0002.vho
new file mode 100644
index 0000000000000000000000000000000000000000..7002ac135463e778922ab17b8fdddac7ccd1c52e
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_multiplexer/altera_merlin_multiplexer_0002.vho
@@ -0,0 +1,3659 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_multiplexer_0002 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ reset : IN STD_LOGIC;
+ sink0_channel : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ sink0_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ sink0_endofpacket : IN STD_LOGIC;
+ sink0_ready : OUT STD_LOGIC;
+ sink0_startofpacket : IN STD_LOGIC;
+ sink0_valid : IN STD_LOGIC;
+ sink1_channel : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ sink1_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ sink1_endofpacket : IN STD_LOGIC;
+ sink1_ready : OUT STD_LOGIC;
+ sink1_startofpacket : IN STD_LOGIC;
+ sink1_valid : IN STD_LOGIC;
+ sink2_channel : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ sink2_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ sink2_endofpacket : IN STD_LOGIC;
+ sink2_ready : OUT STD_LOGIC;
+ sink2_startofpacket : IN STD_LOGIC;
+ sink2_valid : IN STD_LOGIC;
+ sink3_channel : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ sink3_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ sink3_endofpacket : IN STD_LOGIC;
+ sink3_ready : OUT STD_LOGIC;
+ sink3_startofpacket : IN STD_LOGIC;
+ sink3_valid : IN STD_LOGIC;
+ sink4_channel : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ sink4_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ sink4_endofpacket : IN STD_LOGIC;
+ sink4_ready : OUT STD_LOGIC;
+ sink4_startofpacket : IN STD_LOGIC;
+ sink4_valid : IN STD_LOGIC;
+ sink5_channel : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ sink5_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ sink5_endofpacket : IN STD_LOGIC;
+ sink5_ready : OUT STD_LOGIC;
+ sink5_startofpacket : IN STD_LOGIC;
+ sink5_valid : IN STD_LOGIC;
+ sink6_channel : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ sink6_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ sink6_endofpacket : IN STD_LOGIC;
+ sink6_ready : OUT STD_LOGIC;
+ sink6_startofpacket : IN STD_LOGIC;
+ sink6_valid : IN STD_LOGIC;
+ sink7_channel : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ sink7_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ sink7_endofpacket : IN STD_LOGIC;
+ sink7_ready : OUT STD_LOGIC;
+ sink7_startofpacket : IN STD_LOGIC;
+ sink7_valid : IN STD_LOGIC;
+ src_channel : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ src_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ src_endofpacket : OUT STD_LOGIC;
+ src_ready : IN STD_LOGIC;
+ src_startofpacket : OUT STD_LOGIC;
+ src_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_multiplexer_0002;
+
+ ARCHITECTURE RTL OF altera_merlin_multiplexer_0002 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL wire_w_lg_sink0_valid1674w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1699w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1723w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1747w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1771w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1795w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1819w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1843w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid17w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid258w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid282w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid306w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid330w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid354w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid378w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid402w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid426w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid450w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid474w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid498w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid522w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid546w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid570w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid594w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid618w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid642w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid666w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid690w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid714w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid66w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid738w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid762w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid786w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid810w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid834w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid858w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid882w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid906w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid930w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid954w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid90w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid978w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1002w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1026w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1050w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1074w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1098w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1122w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1146w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1170w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1194w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid114w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1218w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1242w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1266w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1290w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1314w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1338w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1362w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1386w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1410w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1434w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid138w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1458w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1482w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1506w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1530w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1554w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1578w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1602w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1626w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1650w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid162w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid186w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid234w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1676w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1701w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1725w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1749w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1773w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1797w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1821w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1845w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid19w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid260w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid284w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid308w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid332w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid356w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid380w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid404w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid428w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid452w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid476w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid44w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid500w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid524w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid548w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid572w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid596w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid620w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid644w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid668w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid692w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid716w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid68w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid740w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid764w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid788w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid812w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid836w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid860w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid884w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid908w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid932w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid956w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid92w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid980w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1004w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1028w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1052w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1076w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1124w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1148w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1172w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1196w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid116w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1220w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1244w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1268w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1292w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1316w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1340w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1364w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1388w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1412w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1436w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid140w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1460w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1484w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1508w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1532w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1556w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1580w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1604w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1628w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1652w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid164w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid188w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid212w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid236w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1679w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1704w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1728w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1752w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1776w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1800w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1824w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1848w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid22w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid263w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid287w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid311w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid335w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid359w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid383w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid407w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid431w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid455w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid479w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid47w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid503w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid527w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid551w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid575w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid599w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid623w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid647w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid671w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid695w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid719w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid71w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid743w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid767w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid791w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid815w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid839w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid863w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid887w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid911w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid935w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid959w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid95w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid983w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1007w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1031w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1055w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1079w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1127w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1151w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1175w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1199w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1223w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1247w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1271w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1295w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1319w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1343w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1367w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1391w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1415w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1439w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid143w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1463w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1487w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1511w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1535w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1559w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1583w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1607w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1631w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1655w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid167w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid191w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid215w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid239w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1682w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1707w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1731w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1755w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1779w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1803w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1827w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1851w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid25w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid266w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid290w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid314w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid338w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid362w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid386w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid410w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid434w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid458w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid482w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid50w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid506w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid530w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid554w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid578w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid602w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid626w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid650w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid674w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid698w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid722w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid74w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid746w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid770w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid794w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid818w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid842w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid866w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid890w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid914w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid938w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid962w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid98w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid986w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1010w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1034w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1058w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1082w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1106w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1130w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1154w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1178w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1202w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid122w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1226w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1250w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1274w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1298w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1322w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1346w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1370w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1394w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1418w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1442w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid146w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1466w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1490w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1514w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1538w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1562w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1586w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1610w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1634w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1658w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid170w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid194w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid218w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid242w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1685w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1710w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1734w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1758w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1782w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1806w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1830w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1854w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid28w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid269w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid293w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid317w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid341w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid365w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid389w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid413w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid437w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid461w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid485w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid53w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid509w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid533w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid557w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid581w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid605w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid629w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid653w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid677w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid701w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid725w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid77w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid749w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid773w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid797w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid821w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid845w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid869w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid893w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid917w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid941w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid965w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid989w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1013w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1037w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1061w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1085w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1133w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1157w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1181w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1205w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid125w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1229w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1253w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1277w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1301w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1325w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1349w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1373w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1397w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1421w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1445w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid149w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1469w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1493w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1517w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1541w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1565w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1589w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1637w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1661w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid173w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid197w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid221w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid245w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1688w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1713w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1737w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1761w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1785w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1809w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1833w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1857w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid31w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid272w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid296w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid320w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid344w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid368w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid392w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid416w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid440w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid464w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid488w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid56w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid512w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid536w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid560w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid584w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid608w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid632w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid656w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid704w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid728w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid80w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid752w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid776w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid800w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid824w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid848w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid872w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid896w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid920w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid944w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid968w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid104w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid992w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1016w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1040w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1064w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1088w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1112w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1136w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1160w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1184w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1208w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid128w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1232w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1256w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1280w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1304w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1328w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1352w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1376w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1400w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1424w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1448w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid152w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1472w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1496w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1520w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1544w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1568w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1592w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1616w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1640w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1664w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid176w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid200w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid224w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid248w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1691w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1716w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1740w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1764w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1788w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1812w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1836w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1860w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid34w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid275w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid299w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid323w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid347w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid371w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid395w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid419w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid443w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid467w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid491w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid59w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid515w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid539w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid563w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid587w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid611w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid635w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid659w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid683w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid707w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid731w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid83w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid755w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid779w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid803w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid827w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid851w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid875w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid899w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid923w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid947w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid971w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid995w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1019w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1043w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1067w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1091w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1115w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1163w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1235w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1259w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1283w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1307w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1331w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1355w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1379w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1403w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1427w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1451w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid155w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1475w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1499w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1523w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1547w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1571w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1595w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1619w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1643w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1667w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid203w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid227w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid251w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1694w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1719w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1743w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1767w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1791w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1815w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1839w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1863w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid278w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid302w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid326w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid350w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid374w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid398w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid422w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid446w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid470w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid494w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid518w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid542w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid566w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid590w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid614w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid638w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid662w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid686w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid710w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid734w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid86w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid758w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid782w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid806w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid830w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid854w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid878w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid902w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid926w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid950w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid974w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid998w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1022w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1046w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1070w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1094w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1118w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1142w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1166w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1190w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid134w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1238w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1262w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1286w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1310w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1334w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1358w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1382w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1406w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1430w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1454w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid158w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1478w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1502w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1526w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1550w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1574w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1598w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1622w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1646w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid1670w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid182w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid206w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid230w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink7_valid254w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1674w1677w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1699w1702w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1723w1726w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1747w1750w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1771w1774w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1795w1798w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1819w1822w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1843w1846w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid17w20w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid258w261w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid282w285w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid306w309w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid330w333w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid354w357w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid378w381w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid402w405w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid426w429w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid450w453w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid474w477w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid42w45w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid498w501w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid522w525w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid546w549w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid570w573w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid594w597w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid618w621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid642w645w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid666w669w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid690w693w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid714w717w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid66w69w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid738w741w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid762w765w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid786w789w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid810w813w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid834w837w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid858w861w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid882w885w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid906w909w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid930w933w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid954w957w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid90w93w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid978w981w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1002w1005w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1026w1029w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1050w1053w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1074w1077w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1098w1101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1122w1125w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1146w1149w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1170w1173w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1194w1197w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid114w117w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1218w1221w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1242w1245w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1266w1269w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1290w1293w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1314w1317w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1338w1341w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1362w1365w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1386w1389w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1410w1413w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1434w1437w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid138w141w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1458w1461w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1482w1485w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1506w1509w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1530w1533w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1554w1557w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1578w1581w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1602w1605w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1626w1629w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1650w1653w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid162w165w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid186w189w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid210w213w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid234w237w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1674w1677w1680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1699w1702w1705w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1723w1726w1729w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1747w1750w1753w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1771w1774w1777w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1795w1798w1801w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1819w1822w1825w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1843w1846w1849w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid17w20w23w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid258w261w264w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid282w285w288w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid306w309w312w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid330w333w336w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid354w357w360w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid378w381w384w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid402w405w408w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid426w429w432w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid450w453w456w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid474w477w480w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid42w45w48w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid498w501w504w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid522w525w528w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid546w549w552w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid570w573w576w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid594w597w600w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid618w621w624w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid642w645w648w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid666w669w672w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid690w693w696w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid714w717w720w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid66w69w72w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid738w741w744w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid762w765w768w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid786w789w792w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid810w813w816w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid834w837w840w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid858w861w864w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid882w885w888w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid906w909w912w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid930w933w936w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid954w957w960w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid90w93w96w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid978w981w984w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1002w1005w1008w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1026w1029w1032w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1050w1053w1056w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1074w1077w1080w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1098w1101w1104w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1122w1125w1128w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1146w1149w1152w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1170w1173w1176w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1194w1197w1200w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid114w117w120w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1218w1221w1224w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1242w1245w1248w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1266w1269w1272w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1290w1293w1296w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1314w1317w1320w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1338w1341w1344w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1362w1365w1368w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1386w1389w1392w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1410w1413w1416w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1434w1437w1440w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid138w141w144w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1458w1461w1464w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1482w1485w1488w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1506w1509w1512w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1530w1533w1536w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1554w1557w1560w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1578w1581w1584w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1602w1605w1608w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1626w1629w1632w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1650w1653w1656w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid162w165w168w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid186w189w192w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid210w213w216w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid234w237w240w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1683w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1708w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1732w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1756w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1780w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1804w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1828w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1852w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid17w20w23w26w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid258w261w264w267w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid282w285w288w291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid306w309w312w315w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid330w333w336w339w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid354w357w360w363w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid378w381w384w387w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid402w405w408w411w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid426w429w432w435w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid450w453w456w459w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid474w477w480w483w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid42w45w48w51w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid498w501w504w507w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid522w525w528w531w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid546w549w552w555w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid570w573w576w579w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid594w597w600w603w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid618w621w624w627w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid642w645w648w651w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid666w669w672w675w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid690w693w696w699w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid714w717w720w723w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid66w69w72w75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid738w741w744w747w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid762w765w768w771w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid786w789w792w795w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid810w813w816w819w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid834w837w840w843w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid858w861w864w867w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid882w885w888w891w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid906w909w912w915w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid930w933w936w939w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid954w957w960w963w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid90w93w96w99w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid978w981w984w987w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1011w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1035w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1059w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1083w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1155w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1203w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid114w117w120w123w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1227w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1251w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1275w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1299w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1323w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1347w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1371w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1395w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1419w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1443w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid138w141w144w147w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1467w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1491w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1515w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1539w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1563w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1587w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1611w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1635w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1659w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid162w165w168w171w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid186w189w192w195w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid210w213w216w219w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid234w237w240w243w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1683w1686w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1708w1711w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1732w1735w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1756w1759w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1780w1783w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1804w1807w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1828w1831w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1852w1855w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w29w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w270w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w294w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w318w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w342w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w366w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w390w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w414w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w438w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w462w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w486w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w54w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w510w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w534w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w558w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w582w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w606w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w630w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w654w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w678w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w702w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w726w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w78w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w750w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w774w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w798w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w822w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w846w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w870w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w894w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w918w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w942w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w966w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w990w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1011w1014w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1035w1038w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1059w1062w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1083w1086w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1107w1110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1131w1134w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1155w1158w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1179w1182w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1203w1206w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w126w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1227w1230w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1251w1254w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1275w1278w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1299w1302w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1323w1326w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1347w1350w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1371w1374w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1395w1398w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1419w1422w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1443w1446w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w150w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1467w1470w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1491w1494w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1515w1518w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1539w1542w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1563w1566w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1587w1590w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1611w1614w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1635w1638w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1659w1662w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w174w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w198w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w222w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w246w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1683w1686w1689w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1708w1711w1714w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1732w1735w1738w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1756w1759w1762w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1780w1783w1786w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1804w1807w1810w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1828w1831w1834w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1852w1855w1858w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w29w32w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w270w273w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w294w297w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w318w321w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w342w345w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w366w369w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w390w393w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w414w417w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w438w441w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w462w465w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w486w489w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w54w57w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w510w513w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w534w537w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w558w561w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w582w585w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w606w609w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w630w633w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w654w657w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w678w681w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w702w705w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w726w729w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w78w81w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w750w753w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w774w777w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w798w801w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w822w825w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w846w849w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w870w873w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w894w897w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w918w921w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w942w945w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w966w969w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w102w105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w990w993w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1011w1014w1017w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1035w1038w1041w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1059w1062w1065w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1083w1086w1089w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1107w1110w1113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1131w1134w1137w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1155w1158w1161w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1179w1182w1185w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1203w1206w1209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w126w129w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1227w1230w1233w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1251w1254w1257w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1275w1278w1281w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1299w1302w1305w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1323w1326w1329w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1347w1350w1353w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1371w1374w1377w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1395w1398w1401w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1419w1422w1425w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1443w1446w1449w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w150w153w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1467w1470w1473w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1491w1494w1497w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1515w1518w1521w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1539w1542w1545w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1563w1566w1569w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1587w1590w1593w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1611w1614w1617w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1635w1638w1641w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1659w1662w1665w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w174w177w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w198w201w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w222w225w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w246w249w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1683w1686w1689w1692w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1708w1711w1714w1717w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1732w1735w1738w1741w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1756w1759w1762w1765w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1780w1783w1786w1789w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1804w1807w1810w1813w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1828w1831w1834w1837w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1852w1855w1858w1861w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w29w32w35w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w270w273w276w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w294w297w300w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w318w321w324w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w342w345w348w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w366w369w372w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w390w393w396w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w414w417w420w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w438w441w444w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w462w465w468w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w486w489w492w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w54w57w60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w510w513w516w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w534w537w540w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w558w561w564w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w582w585w588w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w606w609w612w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w630w633w636w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w654w657w660w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w678w681w684w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w702w705w708w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w726w729w732w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w78w81w84w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w750w753w756w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w774w777w780w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w798w801w804w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w822w825w828w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w846w849w852w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w870w873w876w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w894w897w900w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w918w921w924w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w942w945w948w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w966w969w972w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w102w105w108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w990w993w996w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1011w1014w1017w1020w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1035w1038w1041w1044w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1059w1062w1065w1068w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1083w1086w1089w1092w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1107w1110w1113w1116w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1131w1134w1137w1140w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1155w1158w1161w1164w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1179w1182w1185w1188w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1203w1206w1209w1212w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w126w129w132w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1227w1230w1233w1236w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1251w1254w1257w1260w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1275w1278w1281w1284w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1299w1302w1305w1308w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1323w1326w1329w1332w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1347w1350w1353w1356w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1371w1374w1377w1380w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1395w1398w1401w1404w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1419w1422w1425w1428w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1443w1446w1449w1452w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w150w153w156w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1467w1470w1473w1476w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1491w1494w1497w1500w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1515w1518w1521w1524w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1539w1542w1545w1548w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1563w1566w1569w1572w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1587w1590w1593w1596w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1611w1614w1617w1620w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1635w1638w1641w1644w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1659w1662w1665w1668w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w174w177w180w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w198w201w204w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w222w225w228w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w246w249w252w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1683w1686w1689w1692w1695w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1708w1711w1714w1717w1720w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1732w1735w1738w1741w1744w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1756w1759w1762w1765w1768w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1780w1783w1786w1789w1792w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1804w1807w1810w1813w1816w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1828w1831w1834w1837w1840w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1852w1855w1858w1861w1864w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w29w32w35w38w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w270w273w276w279w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w294w297w300w303w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w318w321w324w327w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w342w345w348w351w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w366w369w372w375w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w390w393w396w399w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w414w417w420w423w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w438w441w444w447w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w462w465w468w471w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w486w489w492w495w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w54w57w60w63w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w510w513w516w519w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w534w537w540w543w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w558w561w564w567w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w582w585w588w591w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w606w609w612w615w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w630w633w636w639w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w654w657w660w663w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w678w681w684w687w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w702w705w708w711w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w726w729w732w735w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w78w81w84w87w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w750w753w756w759w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w774w777w780w783w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w798w801w804w807w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w822w825w828w831w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w846w849w852w855w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w870w873w876w879w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w894w897w900w903w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w918w921w924w927w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w942w945w948w951w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w966w969w972w975w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w102w105w108w111w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w990w993w996w999w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1011w1014w1017w1020w1023w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1035w1038w1041w1044w1047w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1059w1062w1065w1068w1071w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1083w1086w1089w1092w1095w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1107w1110w1113w1116w1119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1131w1134w1137w1140w1143w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1155w1158w1161w1164w1167w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1179w1182w1185w1188w1191w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1203w1206w1209w1212w1215w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w126w129w132w135w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1227w1230w1233w1236w1239w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1251w1254w1257w1260w1263w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1275w1278w1281w1284w1287w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1299w1302w1305w1308w1311w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1323w1326w1329w1332w1335w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1347w1350w1353w1356w1359w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1371w1374w1377w1380w1383w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1395w1398w1401w1404w1407w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1419w1422w1425w1428w1431w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1443w1446w1449w1452w1455w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w150w153w156w159w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1467w1470w1473w1476w1479w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1491w1494w1497w1500w1503w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1515w1518w1521w1524w1527w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1539w1542w1545w1548w1551w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1563w1566w1569w1572w1575w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1587w1590w1593w1596w1599w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1611w1614w1617w1620w1623w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1635w1638w1641w1644w1647w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1659w1662w1665w1668w1671w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w174w177w180w183w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w198w201w204w207w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w222w225w228w231w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w246w249w252w255w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_merlin_multiplexer_0002_wideor1_31_dataout : STD_LOGIC;
+ SIGNAL wire_w_sink0_channel_range1673w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_channel_range1698w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_channel_range1722w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_channel_range1746w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_channel_range1770w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_channel_range1794w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_channel_range1818w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_channel_range1842w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range16w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range257w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range281w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range305w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range329w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range353w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range377w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range401w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range425w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range449w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range473w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range497w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range521w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range545w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range569w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range593w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range617w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range641w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range665w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range689w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range713w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range65w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range737w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range761w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range785w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range809w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range833w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range857w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range881w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range905w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range929w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range953w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range89w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range977w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1001w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1025w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1049w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1073w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1097w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1121w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1145w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1169w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1193w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1217w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1241w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1265w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1289w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1313w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1337w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1361w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1385w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1409w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1433w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range137w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1457w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1481w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1505w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1529w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1553w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1577w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1601w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1625w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1649w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range161w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range185w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range233w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_channel_range1675w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_channel_range1700w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_channel_range1724w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_channel_range1748w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_channel_range1772w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_channel_range1796w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_channel_range1820w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_channel_range1844w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range18w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range259w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range283w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range307w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range331w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range355w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range379w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range403w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range427w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range451w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range475w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range43w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range499w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range523w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range547w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range571w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range595w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range619w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range643w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range667w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range691w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range715w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range67w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range739w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range763w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range787w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range811w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range835w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range859w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range883w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range907w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range931w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range955w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range91w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range979w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1003w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1027w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1051w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1075w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1099w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1123w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1147w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1171w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1195w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range115w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1219w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1243w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1267w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1315w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1339w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1363w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1387w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1411w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1435w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1459w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1483w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1507w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1531w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1555w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1579w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1603w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1627w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1651w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range163w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range235w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_channel_range1678w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_channel_range1703w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_channel_range1727w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_channel_range1751w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_channel_range1775w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_channel_range1799w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_channel_range1823w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_channel_range1847w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range21w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range262w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range286w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range310w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range334w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range358w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range382w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range406w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range430w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range454w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range478w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range46w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range502w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range526w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range550w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range574w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range598w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range622w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range646w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range670w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range694w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range718w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range70w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range742w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range766w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range790w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range814w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range838w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range862w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range886w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range910w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range934w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range958w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range94w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range982w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1006w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1030w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1054w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1078w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1126w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1150w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1174w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1198w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range118w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1222w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1246w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1270w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1294w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1318w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1342w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1366w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1390w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1414w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1438w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range142w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1462w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1486w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1510w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1534w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1558w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1582w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1606w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1630w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1654w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range166w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range190w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range238w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_channel_range1681w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_channel_range1706w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_channel_range1730w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_channel_range1754w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_channel_range1778w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_channel_range1802w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_channel_range1826w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_channel_range1850w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range24w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range265w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range289w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range313w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range337w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range361w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range385w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range409w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range433w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range457w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range481w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range49w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range505w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range529w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range553w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range577w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range601w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range625w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range649w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range673w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range697w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range721w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range73w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range745w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range769w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range793w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range817w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range841w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range865w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range889w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range913w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range937w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range961w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range985w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1009w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1033w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1057w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1081w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1129w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1153w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1177w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1201w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range121w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1225w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1249w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1273w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1297w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1321w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1345w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1369w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1393w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1417w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1441w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range145w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1465w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1489w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1513w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1537w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1561w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1585w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1609w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1633w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1657w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range169w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range193w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range217w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range241w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_channel_range1684w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_channel_range1709w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_channel_range1733w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_channel_range1757w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_channel_range1781w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_channel_range1805w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_channel_range1829w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_channel_range1853w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range27w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range268w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range292w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range316w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range340w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range364w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range388w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range412w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range436w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range460w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range484w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range52w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range508w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range532w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range556w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range580w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range604w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range628w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range652w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range676w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range700w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range724w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range76w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range748w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range772w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range796w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range820w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range844w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range868w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range892w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range916w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range940w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range964w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range988w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1012w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1036w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1060w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1084w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1132w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1156w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1180w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1204w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range124w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1228w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1252w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1276w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1300w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1324w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1348w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1372w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1396w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1420w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1444w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range148w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1468w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1492w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1516w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1540w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1564w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1588w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1612w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1636w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1660w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range172w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range196w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range220w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range244w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_channel_range1687w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_channel_range1712w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_channel_range1736w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_channel_range1760w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_channel_range1784w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_channel_range1808w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_channel_range1832w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_channel_range1856w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range30w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range271w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range295w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range319w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range343w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range367w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range391w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range415w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range439w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range463w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range487w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range55w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range511w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range535w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range559w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range583w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range607w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range631w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range655w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range679w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range703w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range727w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range79w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range751w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range775w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range799w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range823w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range847w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range871w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range895w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range919w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range943w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range967w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range991w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1015w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1039w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1063w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1087w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1111w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1135w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1159w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1183w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1207w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range127w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1231w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1255w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1279w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1303w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1327w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1351w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1375w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1399w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1423w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1447w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range151w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1471w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1495w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1519w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1543w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1567w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1591w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1615w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1639w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1663w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range175w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range199w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range223w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range247w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_channel_range1690w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_channel_range1715w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_channel_range1739w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_channel_range1763w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_channel_range1787w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_channel_range1811w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_channel_range1835w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_channel_range1859w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range33w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range274w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range298w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range322w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range346w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range370w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range394w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range418w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range442w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range466w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range490w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range58w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range514w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range538w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range562w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range586w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range610w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range634w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range658w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range682w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range706w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range730w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range82w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range754w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range778w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range802w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range826w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range850w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range874w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range898w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range922w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range946w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range970w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range106w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range994w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1018w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1042w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1066w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1090w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1114w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1138w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1162w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1186w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range130w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1234w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1258w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1282w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1306w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1330w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1354w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1378w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1402w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1426w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1450w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range154w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1474w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1498w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1522w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1546w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1570w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1594w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1618w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1642w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1666w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range178w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range202w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range226w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range250w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_channel_range1693w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_channel_range1718w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_channel_range1742w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_channel_range1766w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_channel_range1790w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_channel_range1814w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_channel_range1838w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_channel_range1862w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range277w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range301w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range325w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range349w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range373w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range397w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range421w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range445w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range469w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range493w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range517w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range541w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range565w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range589w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range637w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range661w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range685w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range709w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range733w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range85w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range757w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range781w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range805w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range829w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range853w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range877w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range901w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range925w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range949w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range973w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range997w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range1021w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range1045w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range1069w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range1093w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range1117w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range1141w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range1165w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range1189w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range1213w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range133w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range1237w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range1261w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range1285w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range1309w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range1333w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range1357w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range1381w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range1405w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range1429w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range1453w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range157w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range1477w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range1501w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range1525w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range1549w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range1573w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range1597w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range1621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range1645w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range1669w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range181w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range205w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range229w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink7_data_range253w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+ wire_w_lg_sink0_valid1674w(0) <= sink0_valid AND wire_w_sink0_channel_range1673w(0);
+ wire_w_lg_sink0_valid1699w(0) <= sink0_valid AND wire_w_sink0_channel_range1698w(0);
+ wire_w_lg_sink0_valid1723w(0) <= sink0_valid AND wire_w_sink0_channel_range1722w(0);
+ wire_w_lg_sink0_valid1747w(0) <= sink0_valid AND wire_w_sink0_channel_range1746w(0);
+ wire_w_lg_sink0_valid1771w(0) <= sink0_valid AND wire_w_sink0_channel_range1770w(0);
+ wire_w_lg_sink0_valid1795w(0) <= sink0_valid AND wire_w_sink0_channel_range1794w(0);
+ wire_w_lg_sink0_valid1819w(0) <= sink0_valid AND wire_w_sink0_channel_range1818w(0);
+ wire_w_lg_sink0_valid1843w(0) <= sink0_valid AND wire_w_sink0_channel_range1842w(0);
+ wire_w_lg_sink0_valid17w(0) <= sink0_valid AND wire_w_sink0_data_range16w(0);
+ wire_w_lg_sink0_valid258w(0) <= sink0_valid AND wire_w_sink0_data_range257w(0);
+ wire_w_lg_sink0_valid282w(0) <= sink0_valid AND wire_w_sink0_data_range281w(0);
+ wire_w_lg_sink0_valid306w(0) <= sink0_valid AND wire_w_sink0_data_range305w(0);
+ wire_w_lg_sink0_valid330w(0) <= sink0_valid AND wire_w_sink0_data_range329w(0);
+ wire_w_lg_sink0_valid354w(0) <= sink0_valid AND wire_w_sink0_data_range353w(0);
+ wire_w_lg_sink0_valid378w(0) <= sink0_valid AND wire_w_sink0_data_range377w(0);
+ wire_w_lg_sink0_valid402w(0) <= sink0_valid AND wire_w_sink0_data_range401w(0);
+ wire_w_lg_sink0_valid426w(0) <= sink0_valid AND wire_w_sink0_data_range425w(0);
+ wire_w_lg_sink0_valid450w(0) <= sink0_valid AND wire_w_sink0_data_range449w(0);
+ wire_w_lg_sink0_valid474w(0) <= sink0_valid AND wire_w_sink0_data_range473w(0);
+ wire_w_lg_sink0_valid42w(0) <= sink0_valid AND wire_w_sink0_data_range41w(0);
+ wire_w_lg_sink0_valid498w(0) <= sink0_valid AND wire_w_sink0_data_range497w(0);
+ wire_w_lg_sink0_valid522w(0) <= sink0_valid AND wire_w_sink0_data_range521w(0);
+ wire_w_lg_sink0_valid546w(0) <= sink0_valid AND wire_w_sink0_data_range545w(0);
+ wire_w_lg_sink0_valid570w(0) <= sink0_valid AND wire_w_sink0_data_range569w(0);
+ wire_w_lg_sink0_valid594w(0) <= sink0_valid AND wire_w_sink0_data_range593w(0);
+ wire_w_lg_sink0_valid618w(0) <= sink0_valid AND wire_w_sink0_data_range617w(0);
+ wire_w_lg_sink0_valid642w(0) <= sink0_valid AND wire_w_sink0_data_range641w(0);
+ wire_w_lg_sink0_valid666w(0) <= sink0_valid AND wire_w_sink0_data_range665w(0);
+ wire_w_lg_sink0_valid690w(0) <= sink0_valid AND wire_w_sink0_data_range689w(0);
+ wire_w_lg_sink0_valid714w(0) <= sink0_valid AND wire_w_sink0_data_range713w(0);
+ wire_w_lg_sink0_valid66w(0) <= sink0_valid AND wire_w_sink0_data_range65w(0);
+ wire_w_lg_sink0_valid738w(0) <= sink0_valid AND wire_w_sink0_data_range737w(0);
+ wire_w_lg_sink0_valid762w(0) <= sink0_valid AND wire_w_sink0_data_range761w(0);
+ wire_w_lg_sink0_valid786w(0) <= sink0_valid AND wire_w_sink0_data_range785w(0);
+ wire_w_lg_sink0_valid810w(0) <= sink0_valid AND wire_w_sink0_data_range809w(0);
+ wire_w_lg_sink0_valid834w(0) <= sink0_valid AND wire_w_sink0_data_range833w(0);
+ wire_w_lg_sink0_valid858w(0) <= sink0_valid AND wire_w_sink0_data_range857w(0);
+ wire_w_lg_sink0_valid882w(0) <= sink0_valid AND wire_w_sink0_data_range881w(0);
+ wire_w_lg_sink0_valid906w(0) <= sink0_valid AND wire_w_sink0_data_range905w(0);
+ wire_w_lg_sink0_valid930w(0) <= sink0_valid AND wire_w_sink0_data_range929w(0);
+ wire_w_lg_sink0_valid954w(0) <= sink0_valid AND wire_w_sink0_data_range953w(0);
+ wire_w_lg_sink0_valid90w(0) <= sink0_valid AND wire_w_sink0_data_range89w(0);
+ wire_w_lg_sink0_valid978w(0) <= sink0_valid AND wire_w_sink0_data_range977w(0);
+ wire_w_lg_sink0_valid1002w(0) <= sink0_valid AND wire_w_sink0_data_range1001w(0);
+ wire_w_lg_sink0_valid1026w(0) <= sink0_valid AND wire_w_sink0_data_range1025w(0);
+ wire_w_lg_sink0_valid1050w(0) <= sink0_valid AND wire_w_sink0_data_range1049w(0);
+ wire_w_lg_sink0_valid1074w(0) <= sink0_valid AND wire_w_sink0_data_range1073w(0);
+ wire_w_lg_sink0_valid1098w(0) <= sink0_valid AND wire_w_sink0_data_range1097w(0);
+ wire_w_lg_sink0_valid1122w(0) <= sink0_valid AND wire_w_sink0_data_range1121w(0);
+ wire_w_lg_sink0_valid1146w(0) <= sink0_valid AND wire_w_sink0_data_range1145w(0);
+ wire_w_lg_sink0_valid1170w(0) <= sink0_valid AND wire_w_sink0_data_range1169w(0);
+ wire_w_lg_sink0_valid1194w(0) <= sink0_valid AND wire_w_sink0_data_range1193w(0);
+ wire_w_lg_sink0_valid114w(0) <= sink0_valid AND wire_w_sink0_data_range113w(0);
+ wire_w_lg_sink0_valid1218w(0) <= sink0_valid AND wire_w_sink0_data_range1217w(0);
+ wire_w_lg_sink0_valid1242w(0) <= sink0_valid AND wire_w_sink0_data_range1241w(0);
+ wire_w_lg_sink0_valid1266w(0) <= sink0_valid AND wire_w_sink0_data_range1265w(0);
+ wire_w_lg_sink0_valid1290w(0) <= sink0_valid AND wire_w_sink0_data_range1289w(0);
+ wire_w_lg_sink0_valid1314w(0) <= sink0_valid AND wire_w_sink0_data_range1313w(0);
+ wire_w_lg_sink0_valid1338w(0) <= sink0_valid AND wire_w_sink0_data_range1337w(0);
+ wire_w_lg_sink0_valid1362w(0) <= sink0_valid AND wire_w_sink0_data_range1361w(0);
+ wire_w_lg_sink0_valid1386w(0) <= sink0_valid AND wire_w_sink0_data_range1385w(0);
+ wire_w_lg_sink0_valid1410w(0) <= sink0_valid AND wire_w_sink0_data_range1409w(0);
+ wire_w_lg_sink0_valid1434w(0) <= sink0_valid AND wire_w_sink0_data_range1433w(0);
+ wire_w_lg_sink0_valid138w(0) <= sink0_valid AND wire_w_sink0_data_range137w(0);
+ wire_w_lg_sink0_valid1458w(0) <= sink0_valid AND wire_w_sink0_data_range1457w(0);
+ wire_w_lg_sink0_valid1482w(0) <= sink0_valid AND wire_w_sink0_data_range1481w(0);
+ wire_w_lg_sink0_valid1506w(0) <= sink0_valid AND wire_w_sink0_data_range1505w(0);
+ wire_w_lg_sink0_valid1530w(0) <= sink0_valid AND wire_w_sink0_data_range1529w(0);
+ wire_w_lg_sink0_valid1554w(0) <= sink0_valid AND wire_w_sink0_data_range1553w(0);
+ wire_w_lg_sink0_valid1578w(0) <= sink0_valid AND wire_w_sink0_data_range1577w(0);
+ wire_w_lg_sink0_valid1602w(0) <= sink0_valid AND wire_w_sink0_data_range1601w(0);
+ wire_w_lg_sink0_valid1626w(0) <= sink0_valid AND wire_w_sink0_data_range1625w(0);
+ wire_w_lg_sink0_valid1650w(0) <= sink0_valid AND wire_w_sink0_data_range1649w(0);
+ wire_w_lg_sink0_valid162w(0) <= sink0_valid AND wire_w_sink0_data_range161w(0);
+ wire_w_lg_sink0_valid186w(0) <= sink0_valid AND wire_w_sink0_data_range185w(0);
+ wire_w_lg_sink0_valid210w(0) <= sink0_valid AND wire_w_sink0_data_range209w(0);
+ wire_w_lg_sink0_valid234w(0) <= sink0_valid AND wire_w_sink0_data_range233w(0);
+ wire_w_lg_sink1_valid1676w(0) <= sink1_valid AND wire_w_sink1_channel_range1675w(0);
+ wire_w_lg_sink1_valid1701w(0) <= sink1_valid AND wire_w_sink1_channel_range1700w(0);
+ wire_w_lg_sink1_valid1725w(0) <= sink1_valid AND wire_w_sink1_channel_range1724w(0);
+ wire_w_lg_sink1_valid1749w(0) <= sink1_valid AND wire_w_sink1_channel_range1748w(0);
+ wire_w_lg_sink1_valid1773w(0) <= sink1_valid AND wire_w_sink1_channel_range1772w(0);
+ wire_w_lg_sink1_valid1797w(0) <= sink1_valid AND wire_w_sink1_channel_range1796w(0);
+ wire_w_lg_sink1_valid1821w(0) <= sink1_valid AND wire_w_sink1_channel_range1820w(0);
+ wire_w_lg_sink1_valid1845w(0) <= sink1_valid AND wire_w_sink1_channel_range1844w(0);
+ wire_w_lg_sink1_valid19w(0) <= sink1_valid AND wire_w_sink1_data_range18w(0);
+ wire_w_lg_sink1_valid260w(0) <= sink1_valid AND wire_w_sink1_data_range259w(0);
+ wire_w_lg_sink1_valid284w(0) <= sink1_valid AND wire_w_sink1_data_range283w(0);
+ wire_w_lg_sink1_valid308w(0) <= sink1_valid AND wire_w_sink1_data_range307w(0);
+ wire_w_lg_sink1_valid332w(0) <= sink1_valid AND wire_w_sink1_data_range331w(0);
+ wire_w_lg_sink1_valid356w(0) <= sink1_valid AND wire_w_sink1_data_range355w(0);
+ wire_w_lg_sink1_valid380w(0) <= sink1_valid AND wire_w_sink1_data_range379w(0);
+ wire_w_lg_sink1_valid404w(0) <= sink1_valid AND wire_w_sink1_data_range403w(0);
+ wire_w_lg_sink1_valid428w(0) <= sink1_valid AND wire_w_sink1_data_range427w(0);
+ wire_w_lg_sink1_valid452w(0) <= sink1_valid AND wire_w_sink1_data_range451w(0);
+ wire_w_lg_sink1_valid476w(0) <= sink1_valid AND wire_w_sink1_data_range475w(0);
+ wire_w_lg_sink1_valid44w(0) <= sink1_valid AND wire_w_sink1_data_range43w(0);
+ wire_w_lg_sink1_valid500w(0) <= sink1_valid AND wire_w_sink1_data_range499w(0);
+ wire_w_lg_sink1_valid524w(0) <= sink1_valid AND wire_w_sink1_data_range523w(0);
+ wire_w_lg_sink1_valid548w(0) <= sink1_valid AND wire_w_sink1_data_range547w(0);
+ wire_w_lg_sink1_valid572w(0) <= sink1_valid AND wire_w_sink1_data_range571w(0);
+ wire_w_lg_sink1_valid596w(0) <= sink1_valid AND wire_w_sink1_data_range595w(0);
+ wire_w_lg_sink1_valid620w(0) <= sink1_valid AND wire_w_sink1_data_range619w(0);
+ wire_w_lg_sink1_valid644w(0) <= sink1_valid AND wire_w_sink1_data_range643w(0);
+ wire_w_lg_sink1_valid668w(0) <= sink1_valid AND wire_w_sink1_data_range667w(0);
+ wire_w_lg_sink1_valid692w(0) <= sink1_valid AND wire_w_sink1_data_range691w(0);
+ wire_w_lg_sink1_valid716w(0) <= sink1_valid AND wire_w_sink1_data_range715w(0);
+ wire_w_lg_sink1_valid68w(0) <= sink1_valid AND wire_w_sink1_data_range67w(0);
+ wire_w_lg_sink1_valid740w(0) <= sink1_valid AND wire_w_sink1_data_range739w(0);
+ wire_w_lg_sink1_valid764w(0) <= sink1_valid AND wire_w_sink1_data_range763w(0);
+ wire_w_lg_sink1_valid788w(0) <= sink1_valid AND wire_w_sink1_data_range787w(0);
+ wire_w_lg_sink1_valid812w(0) <= sink1_valid AND wire_w_sink1_data_range811w(0);
+ wire_w_lg_sink1_valid836w(0) <= sink1_valid AND wire_w_sink1_data_range835w(0);
+ wire_w_lg_sink1_valid860w(0) <= sink1_valid AND wire_w_sink1_data_range859w(0);
+ wire_w_lg_sink1_valid884w(0) <= sink1_valid AND wire_w_sink1_data_range883w(0);
+ wire_w_lg_sink1_valid908w(0) <= sink1_valid AND wire_w_sink1_data_range907w(0);
+ wire_w_lg_sink1_valid932w(0) <= sink1_valid AND wire_w_sink1_data_range931w(0);
+ wire_w_lg_sink1_valid956w(0) <= sink1_valid AND wire_w_sink1_data_range955w(0);
+ wire_w_lg_sink1_valid92w(0) <= sink1_valid AND wire_w_sink1_data_range91w(0);
+ wire_w_lg_sink1_valid980w(0) <= sink1_valid AND wire_w_sink1_data_range979w(0);
+ wire_w_lg_sink1_valid1004w(0) <= sink1_valid AND wire_w_sink1_data_range1003w(0);
+ wire_w_lg_sink1_valid1028w(0) <= sink1_valid AND wire_w_sink1_data_range1027w(0);
+ wire_w_lg_sink1_valid1052w(0) <= sink1_valid AND wire_w_sink1_data_range1051w(0);
+ wire_w_lg_sink1_valid1076w(0) <= sink1_valid AND wire_w_sink1_data_range1075w(0);
+ wire_w_lg_sink1_valid1100w(0) <= sink1_valid AND wire_w_sink1_data_range1099w(0);
+ wire_w_lg_sink1_valid1124w(0) <= sink1_valid AND wire_w_sink1_data_range1123w(0);
+ wire_w_lg_sink1_valid1148w(0) <= sink1_valid AND wire_w_sink1_data_range1147w(0);
+ wire_w_lg_sink1_valid1172w(0) <= sink1_valid AND wire_w_sink1_data_range1171w(0);
+ wire_w_lg_sink1_valid1196w(0) <= sink1_valid AND wire_w_sink1_data_range1195w(0);
+ wire_w_lg_sink1_valid116w(0) <= sink1_valid AND wire_w_sink1_data_range115w(0);
+ wire_w_lg_sink1_valid1220w(0) <= sink1_valid AND wire_w_sink1_data_range1219w(0);
+ wire_w_lg_sink1_valid1244w(0) <= sink1_valid AND wire_w_sink1_data_range1243w(0);
+ wire_w_lg_sink1_valid1268w(0) <= sink1_valid AND wire_w_sink1_data_range1267w(0);
+ wire_w_lg_sink1_valid1292w(0) <= sink1_valid AND wire_w_sink1_data_range1291w(0);
+ wire_w_lg_sink1_valid1316w(0) <= sink1_valid AND wire_w_sink1_data_range1315w(0);
+ wire_w_lg_sink1_valid1340w(0) <= sink1_valid AND wire_w_sink1_data_range1339w(0);
+ wire_w_lg_sink1_valid1364w(0) <= sink1_valid AND wire_w_sink1_data_range1363w(0);
+ wire_w_lg_sink1_valid1388w(0) <= sink1_valid AND wire_w_sink1_data_range1387w(0);
+ wire_w_lg_sink1_valid1412w(0) <= sink1_valid AND wire_w_sink1_data_range1411w(0);
+ wire_w_lg_sink1_valid1436w(0) <= sink1_valid AND wire_w_sink1_data_range1435w(0);
+ wire_w_lg_sink1_valid140w(0) <= sink1_valid AND wire_w_sink1_data_range139w(0);
+ wire_w_lg_sink1_valid1460w(0) <= sink1_valid AND wire_w_sink1_data_range1459w(0);
+ wire_w_lg_sink1_valid1484w(0) <= sink1_valid AND wire_w_sink1_data_range1483w(0);
+ wire_w_lg_sink1_valid1508w(0) <= sink1_valid AND wire_w_sink1_data_range1507w(0);
+ wire_w_lg_sink1_valid1532w(0) <= sink1_valid AND wire_w_sink1_data_range1531w(0);
+ wire_w_lg_sink1_valid1556w(0) <= sink1_valid AND wire_w_sink1_data_range1555w(0);
+ wire_w_lg_sink1_valid1580w(0) <= sink1_valid AND wire_w_sink1_data_range1579w(0);
+ wire_w_lg_sink1_valid1604w(0) <= sink1_valid AND wire_w_sink1_data_range1603w(0);
+ wire_w_lg_sink1_valid1628w(0) <= sink1_valid AND wire_w_sink1_data_range1627w(0);
+ wire_w_lg_sink1_valid1652w(0) <= sink1_valid AND wire_w_sink1_data_range1651w(0);
+ wire_w_lg_sink1_valid164w(0) <= sink1_valid AND wire_w_sink1_data_range163w(0);
+ wire_w_lg_sink1_valid188w(0) <= sink1_valid AND wire_w_sink1_data_range187w(0);
+ wire_w_lg_sink1_valid212w(0) <= sink1_valid AND wire_w_sink1_data_range211w(0);
+ wire_w_lg_sink1_valid236w(0) <= sink1_valid AND wire_w_sink1_data_range235w(0);
+ wire_w_lg_sink2_valid1679w(0) <= sink2_valid AND wire_w_sink2_channel_range1678w(0);
+ wire_w_lg_sink2_valid1704w(0) <= sink2_valid AND wire_w_sink2_channel_range1703w(0);
+ wire_w_lg_sink2_valid1728w(0) <= sink2_valid AND wire_w_sink2_channel_range1727w(0);
+ wire_w_lg_sink2_valid1752w(0) <= sink2_valid AND wire_w_sink2_channel_range1751w(0);
+ wire_w_lg_sink2_valid1776w(0) <= sink2_valid AND wire_w_sink2_channel_range1775w(0);
+ wire_w_lg_sink2_valid1800w(0) <= sink2_valid AND wire_w_sink2_channel_range1799w(0);
+ wire_w_lg_sink2_valid1824w(0) <= sink2_valid AND wire_w_sink2_channel_range1823w(0);
+ wire_w_lg_sink2_valid1848w(0) <= sink2_valid AND wire_w_sink2_channel_range1847w(0);
+ wire_w_lg_sink2_valid22w(0) <= sink2_valid AND wire_w_sink2_data_range21w(0);
+ wire_w_lg_sink2_valid263w(0) <= sink2_valid AND wire_w_sink2_data_range262w(0);
+ wire_w_lg_sink2_valid287w(0) <= sink2_valid AND wire_w_sink2_data_range286w(0);
+ wire_w_lg_sink2_valid311w(0) <= sink2_valid AND wire_w_sink2_data_range310w(0);
+ wire_w_lg_sink2_valid335w(0) <= sink2_valid AND wire_w_sink2_data_range334w(0);
+ wire_w_lg_sink2_valid359w(0) <= sink2_valid AND wire_w_sink2_data_range358w(0);
+ wire_w_lg_sink2_valid383w(0) <= sink2_valid AND wire_w_sink2_data_range382w(0);
+ wire_w_lg_sink2_valid407w(0) <= sink2_valid AND wire_w_sink2_data_range406w(0);
+ wire_w_lg_sink2_valid431w(0) <= sink2_valid AND wire_w_sink2_data_range430w(0);
+ wire_w_lg_sink2_valid455w(0) <= sink2_valid AND wire_w_sink2_data_range454w(0);
+ wire_w_lg_sink2_valid479w(0) <= sink2_valid AND wire_w_sink2_data_range478w(0);
+ wire_w_lg_sink2_valid47w(0) <= sink2_valid AND wire_w_sink2_data_range46w(0);
+ wire_w_lg_sink2_valid503w(0) <= sink2_valid AND wire_w_sink2_data_range502w(0);
+ wire_w_lg_sink2_valid527w(0) <= sink2_valid AND wire_w_sink2_data_range526w(0);
+ wire_w_lg_sink2_valid551w(0) <= sink2_valid AND wire_w_sink2_data_range550w(0);
+ wire_w_lg_sink2_valid575w(0) <= sink2_valid AND wire_w_sink2_data_range574w(0);
+ wire_w_lg_sink2_valid599w(0) <= sink2_valid AND wire_w_sink2_data_range598w(0);
+ wire_w_lg_sink2_valid623w(0) <= sink2_valid AND wire_w_sink2_data_range622w(0);
+ wire_w_lg_sink2_valid647w(0) <= sink2_valid AND wire_w_sink2_data_range646w(0);
+ wire_w_lg_sink2_valid671w(0) <= sink2_valid AND wire_w_sink2_data_range670w(0);
+ wire_w_lg_sink2_valid695w(0) <= sink2_valid AND wire_w_sink2_data_range694w(0);
+ wire_w_lg_sink2_valid719w(0) <= sink2_valid AND wire_w_sink2_data_range718w(0);
+ wire_w_lg_sink2_valid71w(0) <= sink2_valid AND wire_w_sink2_data_range70w(0);
+ wire_w_lg_sink2_valid743w(0) <= sink2_valid AND wire_w_sink2_data_range742w(0);
+ wire_w_lg_sink2_valid767w(0) <= sink2_valid AND wire_w_sink2_data_range766w(0);
+ wire_w_lg_sink2_valid791w(0) <= sink2_valid AND wire_w_sink2_data_range790w(0);
+ wire_w_lg_sink2_valid815w(0) <= sink2_valid AND wire_w_sink2_data_range814w(0);
+ wire_w_lg_sink2_valid839w(0) <= sink2_valid AND wire_w_sink2_data_range838w(0);
+ wire_w_lg_sink2_valid863w(0) <= sink2_valid AND wire_w_sink2_data_range862w(0);
+ wire_w_lg_sink2_valid887w(0) <= sink2_valid AND wire_w_sink2_data_range886w(0);
+ wire_w_lg_sink2_valid911w(0) <= sink2_valid AND wire_w_sink2_data_range910w(0);
+ wire_w_lg_sink2_valid935w(0) <= sink2_valid AND wire_w_sink2_data_range934w(0);
+ wire_w_lg_sink2_valid959w(0) <= sink2_valid AND wire_w_sink2_data_range958w(0);
+ wire_w_lg_sink2_valid95w(0) <= sink2_valid AND wire_w_sink2_data_range94w(0);
+ wire_w_lg_sink2_valid983w(0) <= sink2_valid AND wire_w_sink2_data_range982w(0);
+ wire_w_lg_sink2_valid1007w(0) <= sink2_valid AND wire_w_sink2_data_range1006w(0);
+ wire_w_lg_sink2_valid1031w(0) <= sink2_valid AND wire_w_sink2_data_range1030w(0);
+ wire_w_lg_sink2_valid1055w(0) <= sink2_valid AND wire_w_sink2_data_range1054w(0);
+ wire_w_lg_sink2_valid1079w(0) <= sink2_valid AND wire_w_sink2_data_range1078w(0);
+ wire_w_lg_sink2_valid1103w(0) <= sink2_valid AND wire_w_sink2_data_range1102w(0);
+ wire_w_lg_sink2_valid1127w(0) <= sink2_valid AND wire_w_sink2_data_range1126w(0);
+ wire_w_lg_sink2_valid1151w(0) <= sink2_valid AND wire_w_sink2_data_range1150w(0);
+ wire_w_lg_sink2_valid1175w(0) <= sink2_valid AND wire_w_sink2_data_range1174w(0);
+ wire_w_lg_sink2_valid1199w(0) <= sink2_valid AND wire_w_sink2_data_range1198w(0);
+ wire_w_lg_sink2_valid119w(0) <= sink2_valid AND wire_w_sink2_data_range118w(0);
+ wire_w_lg_sink2_valid1223w(0) <= sink2_valid AND wire_w_sink2_data_range1222w(0);
+ wire_w_lg_sink2_valid1247w(0) <= sink2_valid AND wire_w_sink2_data_range1246w(0);
+ wire_w_lg_sink2_valid1271w(0) <= sink2_valid AND wire_w_sink2_data_range1270w(0);
+ wire_w_lg_sink2_valid1295w(0) <= sink2_valid AND wire_w_sink2_data_range1294w(0);
+ wire_w_lg_sink2_valid1319w(0) <= sink2_valid AND wire_w_sink2_data_range1318w(0);
+ wire_w_lg_sink2_valid1343w(0) <= sink2_valid AND wire_w_sink2_data_range1342w(0);
+ wire_w_lg_sink2_valid1367w(0) <= sink2_valid AND wire_w_sink2_data_range1366w(0);
+ wire_w_lg_sink2_valid1391w(0) <= sink2_valid AND wire_w_sink2_data_range1390w(0);
+ wire_w_lg_sink2_valid1415w(0) <= sink2_valid AND wire_w_sink2_data_range1414w(0);
+ wire_w_lg_sink2_valid1439w(0) <= sink2_valid AND wire_w_sink2_data_range1438w(0);
+ wire_w_lg_sink2_valid143w(0) <= sink2_valid AND wire_w_sink2_data_range142w(0);
+ wire_w_lg_sink2_valid1463w(0) <= sink2_valid AND wire_w_sink2_data_range1462w(0);
+ wire_w_lg_sink2_valid1487w(0) <= sink2_valid AND wire_w_sink2_data_range1486w(0);
+ wire_w_lg_sink2_valid1511w(0) <= sink2_valid AND wire_w_sink2_data_range1510w(0);
+ wire_w_lg_sink2_valid1535w(0) <= sink2_valid AND wire_w_sink2_data_range1534w(0);
+ wire_w_lg_sink2_valid1559w(0) <= sink2_valid AND wire_w_sink2_data_range1558w(0);
+ wire_w_lg_sink2_valid1583w(0) <= sink2_valid AND wire_w_sink2_data_range1582w(0);
+ wire_w_lg_sink2_valid1607w(0) <= sink2_valid AND wire_w_sink2_data_range1606w(0);
+ wire_w_lg_sink2_valid1631w(0) <= sink2_valid AND wire_w_sink2_data_range1630w(0);
+ wire_w_lg_sink2_valid1655w(0) <= sink2_valid AND wire_w_sink2_data_range1654w(0);
+ wire_w_lg_sink2_valid167w(0) <= sink2_valid AND wire_w_sink2_data_range166w(0);
+ wire_w_lg_sink2_valid191w(0) <= sink2_valid AND wire_w_sink2_data_range190w(0);
+ wire_w_lg_sink2_valid215w(0) <= sink2_valid AND wire_w_sink2_data_range214w(0);
+ wire_w_lg_sink2_valid239w(0) <= sink2_valid AND wire_w_sink2_data_range238w(0);
+ wire_w_lg_sink3_valid1682w(0) <= sink3_valid AND wire_w_sink3_channel_range1681w(0);
+ wire_w_lg_sink3_valid1707w(0) <= sink3_valid AND wire_w_sink3_channel_range1706w(0);
+ wire_w_lg_sink3_valid1731w(0) <= sink3_valid AND wire_w_sink3_channel_range1730w(0);
+ wire_w_lg_sink3_valid1755w(0) <= sink3_valid AND wire_w_sink3_channel_range1754w(0);
+ wire_w_lg_sink3_valid1779w(0) <= sink3_valid AND wire_w_sink3_channel_range1778w(0);
+ wire_w_lg_sink3_valid1803w(0) <= sink3_valid AND wire_w_sink3_channel_range1802w(0);
+ wire_w_lg_sink3_valid1827w(0) <= sink3_valid AND wire_w_sink3_channel_range1826w(0);
+ wire_w_lg_sink3_valid1851w(0) <= sink3_valid AND wire_w_sink3_channel_range1850w(0);
+ wire_w_lg_sink3_valid25w(0) <= sink3_valid AND wire_w_sink3_data_range24w(0);
+ wire_w_lg_sink3_valid266w(0) <= sink3_valid AND wire_w_sink3_data_range265w(0);
+ wire_w_lg_sink3_valid290w(0) <= sink3_valid AND wire_w_sink3_data_range289w(0);
+ wire_w_lg_sink3_valid314w(0) <= sink3_valid AND wire_w_sink3_data_range313w(0);
+ wire_w_lg_sink3_valid338w(0) <= sink3_valid AND wire_w_sink3_data_range337w(0);
+ wire_w_lg_sink3_valid362w(0) <= sink3_valid AND wire_w_sink3_data_range361w(0);
+ wire_w_lg_sink3_valid386w(0) <= sink3_valid AND wire_w_sink3_data_range385w(0);
+ wire_w_lg_sink3_valid410w(0) <= sink3_valid AND wire_w_sink3_data_range409w(0);
+ wire_w_lg_sink3_valid434w(0) <= sink3_valid AND wire_w_sink3_data_range433w(0);
+ wire_w_lg_sink3_valid458w(0) <= sink3_valid AND wire_w_sink3_data_range457w(0);
+ wire_w_lg_sink3_valid482w(0) <= sink3_valid AND wire_w_sink3_data_range481w(0);
+ wire_w_lg_sink3_valid50w(0) <= sink3_valid AND wire_w_sink3_data_range49w(0);
+ wire_w_lg_sink3_valid506w(0) <= sink3_valid AND wire_w_sink3_data_range505w(0);
+ wire_w_lg_sink3_valid530w(0) <= sink3_valid AND wire_w_sink3_data_range529w(0);
+ wire_w_lg_sink3_valid554w(0) <= sink3_valid AND wire_w_sink3_data_range553w(0);
+ wire_w_lg_sink3_valid578w(0) <= sink3_valid AND wire_w_sink3_data_range577w(0);
+ wire_w_lg_sink3_valid602w(0) <= sink3_valid AND wire_w_sink3_data_range601w(0);
+ wire_w_lg_sink3_valid626w(0) <= sink3_valid AND wire_w_sink3_data_range625w(0);
+ wire_w_lg_sink3_valid650w(0) <= sink3_valid AND wire_w_sink3_data_range649w(0);
+ wire_w_lg_sink3_valid674w(0) <= sink3_valid AND wire_w_sink3_data_range673w(0);
+ wire_w_lg_sink3_valid698w(0) <= sink3_valid AND wire_w_sink3_data_range697w(0);
+ wire_w_lg_sink3_valid722w(0) <= sink3_valid AND wire_w_sink3_data_range721w(0);
+ wire_w_lg_sink3_valid74w(0) <= sink3_valid AND wire_w_sink3_data_range73w(0);
+ wire_w_lg_sink3_valid746w(0) <= sink3_valid AND wire_w_sink3_data_range745w(0);
+ wire_w_lg_sink3_valid770w(0) <= sink3_valid AND wire_w_sink3_data_range769w(0);
+ wire_w_lg_sink3_valid794w(0) <= sink3_valid AND wire_w_sink3_data_range793w(0);
+ wire_w_lg_sink3_valid818w(0) <= sink3_valid AND wire_w_sink3_data_range817w(0);
+ wire_w_lg_sink3_valid842w(0) <= sink3_valid AND wire_w_sink3_data_range841w(0);
+ wire_w_lg_sink3_valid866w(0) <= sink3_valid AND wire_w_sink3_data_range865w(0);
+ wire_w_lg_sink3_valid890w(0) <= sink3_valid AND wire_w_sink3_data_range889w(0);
+ wire_w_lg_sink3_valid914w(0) <= sink3_valid AND wire_w_sink3_data_range913w(0);
+ wire_w_lg_sink3_valid938w(0) <= sink3_valid AND wire_w_sink3_data_range937w(0);
+ wire_w_lg_sink3_valid962w(0) <= sink3_valid AND wire_w_sink3_data_range961w(0);
+ wire_w_lg_sink3_valid98w(0) <= sink3_valid AND wire_w_sink3_data_range97w(0);
+ wire_w_lg_sink3_valid986w(0) <= sink3_valid AND wire_w_sink3_data_range985w(0);
+ wire_w_lg_sink3_valid1010w(0) <= sink3_valid AND wire_w_sink3_data_range1009w(0);
+ wire_w_lg_sink3_valid1034w(0) <= sink3_valid AND wire_w_sink3_data_range1033w(0);
+ wire_w_lg_sink3_valid1058w(0) <= sink3_valid AND wire_w_sink3_data_range1057w(0);
+ wire_w_lg_sink3_valid1082w(0) <= sink3_valid AND wire_w_sink3_data_range1081w(0);
+ wire_w_lg_sink3_valid1106w(0) <= sink3_valid AND wire_w_sink3_data_range1105w(0);
+ wire_w_lg_sink3_valid1130w(0) <= sink3_valid AND wire_w_sink3_data_range1129w(0);
+ wire_w_lg_sink3_valid1154w(0) <= sink3_valid AND wire_w_sink3_data_range1153w(0);
+ wire_w_lg_sink3_valid1178w(0) <= sink3_valid AND wire_w_sink3_data_range1177w(0);
+ wire_w_lg_sink3_valid1202w(0) <= sink3_valid AND wire_w_sink3_data_range1201w(0);
+ wire_w_lg_sink3_valid122w(0) <= sink3_valid AND wire_w_sink3_data_range121w(0);
+ wire_w_lg_sink3_valid1226w(0) <= sink3_valid AND wire_w_sink3_data_range1225w(0);
+ wire_w_lg_sink3_valid1250w(0) <= sink3_valid AND wire_w_sink3_data_range1249w(0);
+ wire_w_lg_sink3_valid1274w(0) <= sink3_valid AND wire_w_sink3_data_range1273w(0);
+ wire_w_lg_sink3_valid1298w(0) <= sink3_valid AND wire_w_sink3_data_range1297w(0);
+ wire_w_lg_sink3_valid1322w(0) <= sink3_valid AND wire_w_sink3_data_range1321w(0);
+ wire_w_lg_sink3_valid1346w(0) <= sink3_valid AND wire_w_sink3_data_range1345w(0);
+ wire_w_lg_sink3_valid1370w(0) <= sink3_valid AND wire_w_sink3_data_range1369w(0);
+ wire_w_lg_sink3_valid1394w(0) <= sink3_valid AND wire_w_sink3_data_range1393w(0);
+ wire_w_lg_sink3_valid1418w(0) <= sink3_valid AND wire_w_sink3_data_range1417w(0);
+ wire_w_lg_sink3_valid1442w(0) <= sink3_valid AND wire_w_sink3_data_range1441w(0);
+ wire_w_lg_sink3_valid146w(0) <= sink3_valid AND wire_w_sink3_data_range145w(0);
+ wire_w_lg_sink3_valid1466w(0) <= sink3_valid AND wire_w_sink3_data_range1465w(0);
+ wire_w_lg_sink3_valid1490w(0) <= sink3_valid AND wire_w_sink3_data_range1489w(0);
+ wire_w_lg_sink3_valid1514w(0) <= sink3_valid AND wire_w_sink3_data_range1513w(0);
+ wire_w_lg_sink3_valid1538w(0) <= sink3_valid AND wire_w_sink3_data_range1537w(0);
+ wire_w_lg_sink3_valid1562w(0) <= sink3_valid AND wire_w_sink3_data_range1561w(0);
+ wire_w_lg_sink3_valid1586w(0) <= sink3_valid AND wire_w_sink3_data_range1585w(0);
+ wire_w_lg_sink3_valid1610w(0) <= sink3_valid AND wire_w_sink3_data_range1609w(0);
+ wire_w_lg_sink3_valid1634w(0) <= sink3_valid AND wire_w_sink3_data_range1633w(0);
+ wire_w_lg_sink3_valid1658w(0) <= sink3_valid AND wire_w_sink3_data_range1657w(0);
+ wire_w_lg_sink3_valid170w(0) <= sink3_valid AND wire_w_sink3_data_range169w(0);
+ wire_w_lg_sink3_valid194w(0) <= sink3_valid AND wire_w_sink3_data_range193w(0);
+ wire_w_lg_sink3_valid218w(0) <= sink3_valid AND wire_w_sink3_data_range217w(0);
+ wire_w_lg_sink3_valid242w(0) <= sink3_valid AND wire_w_sink3_data_range241w(0);
+ wire_w_lg_sink4_valid1685w(0) <= sink4_valid AND wire_w_sink4_channel_range1684w(0);
+ wire_w_lg_sink4_valid1710w(0) <= sink4_valid AND wire_w_sink4_channel_range1709w(0);
+ wire_w_lg_sink4_valid1734w(0) <= sink4_valid AND wire_w_sink4_channel_range1733w(0);
+ wire_w_lg_sink4_valid1758w(0) <= sink4_valid AND wire_w_sink4_channel_range1757w(0);
+ wire_w_lg_sink4_valid1782w(0) <= sink4_valid AND wire_w_sink4_channel_range1781w(0);
+ wire_w_lg_sink4_valid1806w(0) <= sink4_valid AND wire_w_sink4_channel_range1805w(0);
+ wire_w_lg_sink4_valid1830w(0) <= sink4_valid AND wire_w_sink4_channel_range1829w(0);
+ wire_w_lg_sink4_valid1854w(0) <= sink4_valid AND wire_w_sink4_channel_range1853w(0);
+ wire_w_lg_sink4_valid28w(0) <= sink4_valid AND wire_w_sink4_data_range27w(0);
+ wire_w_lg_sink4_valid269w(0) <= sink4_valid AND wire_w_sink4_data_range268w(0);
+ wire_w_lg_sink4_valid293w(0) <= sink4_valid AND wire_w_sink4_data_range292w(0);
+ wire_w_lg_sink4_valid317w(0) <= sink4_valid AND wire_w_sink4_data_range316w(0);
+ wire_w_lg_sink4_valid341w(0) <= sink4_valid AND wire_w_sink4_data_range340w(0);
+ wire_w_lg_sink4_valid365w(0) <= sink4_valid AND wire_w_sink4_data_range364w(0);
+ wire_w_lg_sink4_valid389w(0) <= sink4_valid AND wire_w_sink4_data_range388w(0);
+ wire_w_lg_sink4_valid413w(0) <= sink4_valid AND wire_w_sink4_data_range412w(0);
+ wire_w_lg_sink4_valid437w(0) <= sink4_valid AND wire_w_sink4_data_range436w(0);
+ wire_w_lg_sink4_valid461w(0) <= sink4_valid AND wire_w_sink4_data_range460w(0);
+ wire_w_lg_sink4_valid485w(0) <= sink4_valid AND wire_w_sink4_data_range484w(0);
+ wire_w_lg_sink4_valid53w(0) <= sink4_valid AND wire_w_sink4_data_range52w(0);
+ wire_w_lg_sink4_valid509w(0) <= sink4_valid AND wire_w_sink4_data_range508w(0);
+ wire_w_lg_sink4_valid533w(0) <= sink4_valid AND wire_w_sink4_data_range532w(0);
+ wire_w_lg_sink4_valid557w(0) <= sink4_valid AND wire_w_sink4_data_range556w(0);
+ wire_w_lg_sink4_valid581w(0) <= sink4_valid AND wire_w_sink4_data_range580w(0);
+ wire_w_lg_sink4_valid605w(0) <= sink4_valid AND wire_w_sink4_data_range604w(0);
+ wire_w_lg_sink4_valid629w(0) <= sink4_valid AND wire_w_sink4_data_range628w(0);
+ wire_w_lg_sink4_valid653w(0) <= sink4_valid AND wire_w_sink4_data_range652w(0);
+ wire_w_lg_sink4_valid677w(0) <= sink4_valid AND wire_w_sink4_data_range676w(0);
+ wire_w_lg_sink4_valid701w(0) <= sink4_valid AND wire_w_sink4_data_range700w(0);
+ wire_w_lg_sink4_valid725w(0) <= sink4_valid AND wire_w_sink4_data_range724w(0);
+ wire_w_lg_sink4_valid77w(0) <= sink4_valid AND wire_w_sink4_data_range76w(0);
+ wire_w_lg_sink4_valid749w(0) <= sink4_valid AND wire_w_sink4_data_range748w(0);
+ wire_w_lg_sink4_valid773w(0) <= sink4_valid AND wire_w_sink4_data_range772w(0);
+ wire_w_lg_sink4_valid797w(0) <= sink4_valid AND wire_w_sink4_data_range796w(0);
+ wire_w_lg_sink4_valid821w(0) <= sink4_valid AND wire_w_sink4_data_range820w(0);
+ wire_w_lg_sink4_valid845w(0) <= sink4_valid AND wire_w_sink4_data_range844w(0);
+ wire_w_lg_sink4_valid869w(0) <= sink4_valid AND wire_w_sink4_data_range868w(0);
+ wire_w_lg_sink4_valid893w(0) <= sink4_valid AND wire_w_sink4_data_range892w(0);
+ wire_w_lg_sink4_valid917w(0) <= sink4_valid AND wire_w_sink4_data_range916w(0);
+ wire_w_lg_sink4_valid941w(0) <= sink4_valid AND wire_w_sink4_data_range940w(0);
+ wire_w_lg_sink4_valid965w(0) <= sink4_valid AND wire_w_sink4_data_range964w(0);
+ wire_w_lg_sink4_valid101w(0) <= sink4_valid AND wire_w_sink4_data_range100w(0);
+ wire_w_lg_sink4_valid989w(0) <= sink4_valid AND wire_w_sink4_data_range988w(0);
+ wire_w_lg_sink4_valid1013w(0) <= sink4_valid AND wire_w_sink4_data_range1012w(0);
+ wire_w_lg_sink4_valid1037w(0) <= sink4_valid AND wire_w_sink4_data_range1036w(0);
+ wire_w_lg_sink4_valid1061w(0) <= sink4_valid AND wire_w_sink4_data_range1060w(0);
+ wire_w_lg_sink4_valid1085w(0) <= sink4_valid AND wire_w_sink4_data_range1084w(0);
+ wire_w_lg_sink4_valid1109w(0) <= sink4_valid AND wire_w_sink4_data_range1108w(0);
+ wire_w_lg_sink4_valid1133w(0) <= sink4_valid AND wire_w_sink4_data_range1132w(0);
+ wire_w_lg_sink4_valid1157w(0) <= sink4_valid AND wire_w_sink4_data_range1156w(0);
+ wire_w_lg_sink4_valid1181w(0) <= sink4_valid AND wire_w_sink4_data_range1180w(0);
+ wire_w_lg_sink4_valid1205w(0) <= sink4_valid AND wire_w_sink4_data_range1204w(0);
+ wire_w_lg_sink4_valid125w(0) <= sink4_valid AND wire_w_sink4_data_range124w(0);
+ wire_w_lg_sink4_valid1229w(0) <= sink4_valid AND wire_w_sink4_data_range1228w(0);
+ wire_w_lg_sink4_valid1253w(0) <= sink4_valid AND wire_w_sink4_data_range1252w(0);
+ wire_w_lg_sink4_valid1277w(0) <= sink4_valid AND wire_w_sink4_data_range1276w(0);
+ wire_w_lg_sink4_valid1301w(0) <= sink4_valid AND wire_w_sink4_data_range1300w(0);
+ wire_w_lg_sink4_valid1325w(0) <= sink4_valid AND wire_w_sink4_data_range1324w(0);
+ wire_w_lg_sink4_valid1349w(0) <= sink4_valid AND wire_w_sink4_data_range1348w(0);
+ wire_w_lg_sink4_valid1373w(0) <= sink4_valid AND wire_w_sink4_data_range1372w(0);
+ wire_w_lg_sink4_valid1397w(0) <= sink4_valid AND wire_w_sink4_data_range1396w(0);
+ wire_w_lg_sink4_valid1421w(0) <= sink4_valid AND wire_w_sink4_data_range1420w(0);
+ wire_w_lg_sink4_valid1445w(0) <= sink4_valid AND wire_w_sink4_data_range1444w(0);
+ wire_w_lg_sink4_valid149w(0) <= sink4_valid AND wire_w_sink4_data_range148w(0);
+ wire_w_lg_sink4_valid1469w(0) <= sink4_valid AND wire_w_sink4_data_range1468w(0);
+ wire_w_lg_sink4_valid1493w(0) <= sink4_valid AND wire_w_sink4_data_range1492w(0);
+ wire_w_lg_sink4_valid1517w(0) <= sink4_valid AND wire_w_sink4_data_range1516w(0);
+ wire_w_lg_sink4_valid1541w(0) <= sink4_valid AND wire_w_sink4_data_range1540w(0);
+ wire_w_lg_sink4_valid1565w(0) <= sink4_valid AND wire_w_sink4_data_range1564w(0);
+ wire_w_lg_sink4_valid1589w(0) <= sink4_valid AND wire_w_sink4_data_range1588w(0);
+ wire_w_lg_sink4_valid1613w(0) <= sink4_valid AND wire_w_sink4_data_range1612w(0);
+ wire_w_lg_sink4_valid1637w(0) <= sink4_valid AND wire_w_sink4_data_range1636w(0);
+ wire_w_lg_sink4_valid1661w(0) <= sink4_valid AND wire_w_sink4_data_range1660w(0);
+ wire_w_lg_sink4_valid173w(0) <= sink4_valid AND wire_w_sink4_data_range172w(0);
+ wire_w_lg_sink4_valid197w(0) <= sink4_valid AND wire_w_sink4_data_range196w(0);
+ wire_w_lg_sink4_valid221w(0) <= sink4_valid AND wire_w_sink4_data_range220w(0);
+ wire_w_lg_sink4_valid245w(0) <= sink4_valid AND wire_w_sink4_data_range244w(0);
+ wire_w_lg_sink5_valid1688w(0) <= sink5_valid AND wire_w_sink5_channel_range1687w(0);
+ wire_w_lg_sink5_valid1713w(0) <= sink5_valid AND wire_w_sink5_channel_range1712w(0);
+ wire_w_lg_sink5_valid1737w(0) <= sink5_valid AND wire_w_sink5_channel_range1736w(0);
+ wire_w_lg_sink5_valid1761w(0) <= sink5_valid AND wire_w_sink5_channel_range1760w(0);
+ wire_w_lg_sink5_valid1785w(0) <= sink5_valid AND wire_w_sink5_channel_range1784w(0);
+ wire_w_lg_sink5_valid1809w(0) <= sink5_valid AND wire_w_sink5_channel_range1808w(0);
+ wire_w_lg_sink5_valid1833w(0) <= sink5_valid AND wire_w_sink5_channel_range1832w(0);
+ wire_w_lg_sink5_valid1857w(0) <= sink5_valid AND wire_w_sink5_channel_range1856w(0);
+ wire_w_lg_sink5_valid31w(0) <= sink5_valid AND wire_w_sink5_data_range30w(0);
+ wire_w_lg_sink5_valid272w(0) <= sink5_valid AND wire_w_sink5_data_range271w(0);
+ wire_w_lg_sink5_valid296w(0) <= sink5_valid AND wire_w_sink5_data_range295w(0);
+ wire_w_lg_sink5_valid320w(0) <= sink5_valid AND wire_w_sink5_data_range319w(0);
+ wire_w_lg_sink5_valid344w(0) <= sink5_valid AND wire_w_sink5_data_range343w(0);
+ wire_w_lg_sink5_valid368w(0) <= sink5_valid AND wire_w_sink5_data_range367w(0);
+ wire_w_lg_sink5_valid392w(0) <= sink5_valid AND wire_w_sink5_data_range391w(0);
+ wire_w_lg_sink5_valid416w(0) <= sink5_valid AND wire_w_sink5_data_range415w(0);
+ wire_w_lg_sink5_valid440w(0) <= sink5_valid AND wire_w_sink5_data_range439w(0);
+ wire_w_lg_sink5_valid464w(0) <= sink5_valid AND wire_w_sink5_data_range463w(0);
+ wire_w_lg_sink5_valid488w(0) <= sink5_valid AND wire_w_sink5_data_range487w(0);
+ wire_w_lg_sink5_valid56w(0) <= sink5_valid AND wire_w_sink5_data_range55w(0);
+ wire_w_lg_sink5_valid512w(0) <= sink5_valid AND wire_w_sink5_data_range511w(0);
+ wire_w_lg_sink5_valid536w(0) <= sink5_valid AND wire_w_sink5_data_range535w(0);
+ wire_w_lg_sink5_valid560w(0) <= sink5_valid AND wire_w_sink5_data_range559w(0);
+ wire_w_lg_sink5_valid584w(0) <= sink5_valid AND wire_w_sink5_data_range583w(0);
+ wire_w_lg_sink5_valid608w(0) <= sink5_valid AND wire_w_sink5_data_range607w(0);
+ wire_w_lg_sink5_valid632w(0) <= sink5_valid AND wire_w_sink5_data_range631w(0);
+ wire_w_lg_sink5_valid656w(0) <= sink5_valid AND wire_w_sink5_data_range655w(0);
+ wire_w_lg_sink5_valid680w(0) <= sink5_valid AND wire_w_sink5_data_range679w(0);
+ wire_w_lg_sink5_valid704w(0) <= sink5_valid AND wire_w_sink5_data_range703w(0);
+ wire_w_lg_sink5_valid728w(0) <= sink5_valid AND wire_w_sink5_data_range727w(0);
+ wire_w_lg_sink5_valid80w(0) <= sink5_valid AND wire_w_sink5_data_range79w(0);
+ wire_w_lg_sink5_valid752w(0) <= sink5_valid AND wire_w_sink5_data_range751w(0);
+ wire_w_lg_sink5_valid776w(0) <= sink5_valid AND wire_w_sink5_data_range775w(0);
+ wire_w_lg_sink5_valid800w(0) <= sink5_valid AND wire_w_sink5_data_range799w(0);
+ wire_w_lg_sink5_valid824w(0) <= sink5_valid AND wire_w_sink5_data_range823w(0);
+ wire_w_lg_sink5_valid848w(0) <= sink5_valid AND wire_w_sink5_data_range847w(0);
+ wire_w_lg_sink5_valid872w(0) <= sink5_valid AND wire_w_sink5_data_range871w(0);
+ wire_w_lg_sink5_valid896w(0) <= sink5_valid AND wire_w_sink5_data_range895w(0);
+ wire_w_lg_sink5_valid920w(0) <= sink5_valid AND wire_w_sink5_data_range919w(0);
+ wire_w_lg_sink5_valid944w(0) <= sink5_valid AND wire_w_sink5_data_range943w(0);
+ wire_w_lg_sink5_valid968w(0) <= sink5_valid AND wire_w_sink5_data_range967w(0);
+ wire_w_lg_sink5_valid104w(0) <= sink5_valid AND wire_w_sink5_data_range103w(0);
+ wire_w_lg_sink5_valid992w(0) <= sink5_valid AND wire_w_sink5_data_range991w(0);
+ wire_w_lg_sink5_valid1016w(0) <= sink5_valid AND wire_w_sink5_data_range1015w(0);
+ wire_w_lg_sink5_valid1040w(0) <= sink5_valid AND wire_w_sink5_data_range1039w(0);
+ wire_w_lg_sink5_valid1064w(0) <= sink5_valid AND wire_w_sink5_data_range1063w(0);
+ wire_w_lg_sink5_valid1088w(0) <= sink5_valid AND wire_w_sink5_data_range1087w(0);
+ wire_w_lg_sink5_valid1112w(0) <= sink5_valid AND wire_w_sink5_data_range1111w(0);
+ wire_w_lg_sink5_valid1136w(0) <= sink5_valid AND wire_w_sink5_data_range1135w(0);
+ wire_w_lg_sink5_valid1160w(0) <= sink5_valid AND wire_w_sink5_data_range1159w(0);
+ wire_w_lg_sink5_valid1184w(0) <= sink5_valid AND wire_w_sink5_data_range1183w(0);
+ wire_w_lg_sink5_valid1208w(0) <= sink5_valid AND wire_w_sink5_data_range1207w(0);
+ wire_w_lg_sink5_valid128w(0) <= sink5_valid AND wire_w_sink5_data_range127w(0);
+ wire_w_lg_sink5_valid1232w(0) <= sink5_valid AND wire_w_sink5_data_range1231w(0);
+ wire_w_lg_sink5_valid1256w(0) <= sink5_valid AND wire_w_sink5_data_range1255w(0);
+ wire_w_lg_sink5_valid1280w(0) <= sink5_valid AND wire_w_sink5_data_range1279w(0);
+ wire_w_lg_sink5_valid1304w(0) <= sink5_valid AND wire_w_sink5_data_range1303w(0);
+ wire_w_lg_sink5_valid1328w(0) <= sink5_valid AND wire_w_sink5_data_range1327w(0);
+ wire_w_lg_sink5_valid1352w(0) <= sink5_valid AND wire_w_sink5_data_range1351w(0);
+ wire_w_lg_sink5_valid1376w(0) <= sink5_valid AND wire_w_sink5_data_range1375w(0);
+ wire_w_lg_sink5_valid1400w(0) <= sink5_valid AND wire_w_sink5_data_range1399w(0);
+ wire_w_lg_sink5_valid1424w(0) <= sink5_valid AND wire_w_sink5_data_range1423w(0);
+ wire_w_lg_sink5_valid1448w(0) <= sink5_valid AND wire_w_sink5_data_range1447w(0);
+ wire_w_lg_sink5_valid152w(0) <= sink5_valid AND wire_w_sink5_data_range151w(0);
+ wire_w_lg_sink5_valid1472w(0) <= sink5_valid AND wire_w_sink5_data_range1471w(0);
+ wire_w_lg_sink5_valid1496w(0) <= sink5_valid AND wire_w_sink5_data_range1495w(0);
+ wire_w_lg_sink5_valid1520w(0) <= sink5_valid AND wire_w_sink5_data_range1519w(0);
+ wire_w_lg_sink5_valid1544w(0) <= sink5_valid AND wire_w_sink5_data_range1543w(0);
+ wire_w_lg_sink5_valid1568w(0) <= sink5_valid AND wire_w_sink5_data_range1567w(0);
+ wire_w_lg_sink5_valid1592w(0) <= sink5_valid AND wire_w_sink5_data_range1591w(0);
+ wire_w_lg_sink5_valid1616w(0) <= sink5_valid AND wire_w_sink5_data_range1615w(0);
+ wire_w_lg_sink5_valid1640w(0) <= sink5_valid AND wire_w_sink5_data_range1639w(0);
+ wire_w_lg_sink5_valid1664w(0) <= sink5_valid AND wire_w_sink5_data_range1663w(0);
+ wire_w_lg_sink5_valid176w(0) <= sink5_valid AND wire_w_sink5_data_range175w(0);
+ wire_w_lg_sink5_valid200w(0) <= sink5_valid AND wire_w_sink5_data_range199w(0);
+ wire_w_lg_sink5_valid224w(0) <= sink5_valid AND wire_w_sink5_data_range223w(0);
+ wire_w_lg_sink5_valid248w(0) <= sink5_valid AND wire_w_sink5_data_range247w(0);
+ wire_w_lg_sink6_valid1691w(0) <= sink6_valid AND wire_w_sink6_channel_range1690w(0);
+ wire_w_lg_sink6_valid1716w(0) <= sink6_valid AND wire_w_sink6_channel_range1715w(0);
+ wire_w_lg_sink6_valid1740w(0) <= sink6_valid AND wire_w_sink6_channel_range1739w(0);
+ wire_w_lg_sink6_valid1764w(0) <= sink6_valid AND wire_w_sink6_channel_range1763w(0);
+ wire_w_lg_sink6_valid1788w(0) <= sink6_valid AND wire_w_sink6_channel_range1787w(0);
+ wire_w_lg_sink6_valid1812w(0) <= sink6_valid AND wire_w_sink6_channel_range1811w(0);
+ wire_w_lg_sink6_valid1836w(0) <= sink6_valid AND wire_w_sink6_channel_range1835w(0);
+ wire_w_lg_sink6_valid1860w(0) <= sink6_valid AND wire_w_sink6_channel_range1859w(0);
+ wire_w_lg_sink6_valid34w(0) <= sink6_valid AND wire_w_sink6_data_range33w(0);
+ wire_w_lg_sink6_valid275w(0) <= sink6_valid AND wire_w_sink6_data_range274w(0);
+ wire_w_lg_sink6_valid299w(0) <= sink6_valid AND wire_w_sink6_data_range298w(0);
+ wire_w_lg_sink6_valid323w(0) <= sink6_valid AND wire_w_sink6_data_range322w(0);
+ wire_w_lg_sink6_valid347w(0) <= sink6_valid AND wire_w_sink6_data_range346w(0);
+ wire_w_lg_sink6_valid371w(0) <= sink6_valid AND wire_w_sink6_data_range370w(0);
+ wire_w_lg_sink6_valid395w(0) <= sink6_valid AND wire_w_sink6_data_range394w(0);
+ wire_w_lg_sink6_valid419w(0) <= sink6_valid AND wire_w_sink6_data_range418w(0);
+ wire_w_lg_sink6_valid443w(0) <= sink6_valid AND wire_w_sink6_data_range442w(0);
+ wire_w_lg_sink6_valid467w(0) <= sink6_valid AND wire_w_sink6_data_range466w(0);
+ wire_w_lg_sink6_valid491w(0) <= sink6_valid AND wire_w_sink6_data_range490w(0);
+ wire_w_lg_sink6_valid59w(0) <= sink6_valid AND wire_w_sink6_data_range58w(0);
+ wire_w_lg_sink6_valid515w(0) <= sink6_valid AND wire_w_sink6_data_range514w(0);
+ wire_w_lg_sink6_valid539w(0) <= sink6_valid AND wire_w_sink6_data_range538w(0);
+ wire_w_lg_sink6_valid563w(0) <= sink6_valid AND wire_w_sink6_data_range562w(0);
+ wire_w_lg_sink6_valid587w(0) <= sink6_valid AND wire_w_sink6_data_range586w(0);
+ wire_w_lg_sink6_valid611w(0) <= sink6_valid AND wire_w_sink6_data_range610w(0);
+ wire_w_lg_sink6_valid635w(0) <= sink6_valid AND wire_w_sink6_data_range634w(0);
+ wire_w_lg_sink6_valid659w(0) <= sink6_valid AND wire_w_sink6_data_range658w(0);
+ wire_w_lg_sink6_valid683w(0) <= sink6_valid AND wire_w_sink6_data_range682w(0);
+ wire_w_lg_sink6_valid707w(0) <= sink6_valid AND wire_w_sink6_data_range706w(0);
+ wire_w_lg_sink6_valid731w(0) <= sink6_valid AND wire_w_sink6_data_range730w(0);
+ wire_w_lg_sink6_valid83w(0) <= sink6_valid AND wire_w_sink6_data_range82w(0);
+ wire_w_lg_sink6_valid755w(0) <= sink6_valid AND wire_w_sink6_data_range754w(0);
+ wire_w_lg_sink6_valid779w(0) <= sink6_valid AND wire_w_sink6_data_range778w(0);
+ wire_w_lg_sink6_valid803w(0) <= sink6_valid AND wire_w_sink6_data_range802w(0);
+ wire_w_lg_sink6_valid827w(0) <= sink6_valid AND wire_w_sink6_data_range826w(0);
+ wire_w_lg_sink6_valid851w(0) <= sink6_valid AND wire_w_sink6_data_range850w(0);
+ wire_w_lg_sink6_valid875w(0) <= sink6_valid AND wire_w_sink6_data_range874w(0);
+ wire_w_lg_sink6_valid899w(0) <= sink6_valid AND wire_w_sink6_data_range898w(0);
+ wire_w_lg_sink6_valid923w(0) <= sink6_valid AND wire_w_sink6_data_range922w(0);
+ wire_w_lg_sink6_valid947w(0) <= sink6_valid AND wire_w_sink6_data_range946w(0);
+ wire_w_lg_sink6_valid971w(0) <= sink6_valid AND wire_w_sink6_data_range970w(0);
+ wire_w_lg_sink6_valid107w(0) <= sink6_valid AND wire_w_sink6_data_range106w(0);
+ wire_w_lg_sink6_valid995w(0) <= sink6_valid AND wire_w_sink6_data_range994w(0);
+ wire_w_lg_sink6_valid1019w(0) <= sink6_valid AND wire_w_sink6_data_range1018w(0);
+ wire_w_lg_sink6_valid1043w(0) <= sink6_valid AND wire_w_sink6_data_range1042w(0);
+ wire_w_lg_sink6_valid1067w(0) <= sink6_valid AND wire_w_sink6_data_range1066w(0);
+ wire_w_lg_sink6_valid1091w(0) <= sink6_valid AND wire_w_sink6_data_range1090w(0);
+ wire_w_lg_sink6_valid1115w(0) <= sink6_valid AND wire_w_sink6_data_range1114w(0);
+ wire_w_lg_sink6_valid1139w(0) <= sink6_valid AND wire_w_sink6_data_range1138w(0);
+ wire_w_lg_sink6_valid1163w(0) <= sink6_valid AND wire_w_sink6_data_range1162w(0);
+ wire_w_lg_sink6_valid1187w(0) <= sink6_valid AND wire_w_sink6_data_range1186w(0);
+ wire_w_lg_sink6_valid1211w(0) <= sink6_valid AND wire_w_sink6_data_range1210w(0);
+ wire_w_lg_sink6_valid131w(0) <= sink6_valid AND wire_w_sink6_data_range130w(0);
+ wire_w_lg_sink6_valid1235w(0) <= sink6_valid AND wire_w_sink6_data_range1234w(0);
+ wire_w_lg_sink6_valid1259w(0) <= sink6_valid AND wire_w_sink6_data_range1258w(0);
+ wire_w_lg_sink6_valid1283w(0) <= sink6_valid AND wire_w_sink6_data_range1282w(0);
+ wire_w_lg_sink6_valid1307w(0) <= sink6_valid AND wire_w_sink6_data_range1306w(0);
+ wire_w_lg_sink6_valid1331w(0) <= sink6_valid AND wire_w_sink6_data_range1330w(0);
+ wire_w_lg_sink6_valid1355w(0) <= sink6_valid AND wire_w_sink6_data_range1354w(0);
+ wire_w_lg_sink6_valid1379w(0) <= sink6_valid AND wire_w_sink6_data_range1378w(0);
+ wire_w_lg_sink6_valid1403w(0) <= sink6_valid AND wire_w_sink6_data_range1402w(0);
+ wire_w_lg_sink6_valid1427w(0) <= sink6_valid AND wire_w_sink6_data_range1426w(0);
+ wire_w_lg_sink6_valid1451w(0) <= sink6_valid AND wire_w_sink6_data_range1450w(0);
+ wire_w_lg_sink6_valid155w(0) <= sink6_valid AND wire_w_sink6_data_range154w(0);
+ wire_w_lg_sink6_valid1475w(0) <= sink6_valid AND wire_w_sink6_data_range1474w(0);
+ wire_w_lg_sink6_valid1499w(0) <= sink6_valid AND wire_w_sink6_data_range1498w(0);
+ wire_w_lg_sink6_valid1523w(0) <= sink6_valid AND wire_w_sink6_data_range1522w(0);
+ wire_w_lg_sink6_valid1547w(0) <= sink6_valid AND wire_w_sink6_data_range1546w(0);
+ wire_w_lg_sink6_valid1571w(0) <= sink6_valid AND wire_w_sink6_data_range1570w(0);
+ wire_w_lg_sink6_valid1595w(0) <= sink6_valid AND wire_w_sink6_data_range1594w(0);
+ wire_w_lg_sink6_valid1619w(0) <= sink6_valid AND wire_w_sink6_data_range1618w(0);
+ wire_w_lg_sink6_valid1643w(0) <= sink6_valid AND wire_w_sink6_data_range1642w(0);
+ wire_w_lg_sink6_valid1667w(0) <= sink6_valid AND wire_w_sink6_data_range1666w(0);
+ wire_w_lg_sink6_valid179w(0) <= sink6_valid AND wire_w_sink6_data_range178w(0);
+ wire_w_lg_sink6_valid203w(0) <= sink6_valid AND wire_w_sink6_data_range202w(0);
+ wire_w_lg_sink6_valid227w(0) <= sink6_valid AND wire_w_sink6_data_range226w(0);
+ wire_w_lg_sink6_valid251w(0) <= sink6_valid AND wire_w_sink6_data_range250w(0);
+ wire_w_lg_sink7_valid1694w(0) <= sink7_valid AND wire_w_sink7_channel_range1693w(0);
+ wire_w_lg_sink7_valid1719w(0) <= sink7_valid AND wire_w_sink7_channel_range1718w(0);
+ wire_w_lg_sink7_valid1743w(0) <= sink7_valid AND wire_w_sink7_channel_range1742w(0);
+ wire_w_lg_sink7_valid1767w(0) <= sink7_valid AND wire_w_sink7_channel_range1766w(0);
+ wire_w_lg_sink7_valid1791w(0) <= sink7_valid AND wire_w_sink7_channel_range1790w(0);
+ wire_w_lg_sink7_valid1815w(0) <= sink7_valid AND wire_w_sink7_channel_range1814w(0);
+ wire_w_lg_sink7_valid1839w(0) <= sink7_valid AND wire_w_sink7_channel_range1838w(0);
+ wire_w_lg_sink7_valid1863w(0) <= sink7_valid AND wire_w_sink7_channel_range1862w(0);
+ wire_w_lg_sink7_valid37w(0) <= sink7_valid AND wire_w_sink7_data_range36w(0);
+ wire_w_lg_sink7_valid278w(0) <= sink7_valid AND wire_w_sink7_data_range277w(0);
+ wire_w_lg_sink7_valid302w(0) <= sink7_valid AND wire_w_sink7_data_range301w(0);
+ wire_w_lg_sink7_valid326w(0) <= sink7_valid AND wire_w_sink7_data_range325w(0);
+ wire_w_lg_sink7_valid350w(0) <= sink7_valid AND wire_w_sink7_data_range349w(0);
+ wire_w_lg_sink7_valid374w(0) <= sink7_valid AND wire_w_sink7_data_range373w(0);
+ wire_w_lg_sink7_valid398w(0) <= sink7_valid AND wire_w_sink7_data_range397w(0);
+ wire_w_lg_sink7_valid422w(0) <= sink7_valid AND wire_w_sink7_data_range421w(0);
+ wire_w_lg_sink7_valid446w(0) <= sink7_valid AND wire_w_sink7_data_range445w(0);
+ wire_w_lg_sink7_valid470w(0) <= sink7_valid AND wire_w_sink7_data_range469w(0);
+ wire_w_lg_sink7_valid494w(0) <= sink7_valid AND wire_w_sink7_data_range493w(0);
+ wire_w_lg_sink7_valid62w(0) <= sink7_valid AND wire_w_sink7_data_range61w(0);
+ wire_w_lg_sink7_valid518w(0) <= sink7_valid AND wire_w_sink7_data_range517w(0);
+ wire_w_lg_sink7_valid542w(0) <= sink7_valid AND wire_w_sink7_data_range541w(0);
+ wire_w_lg_sink7_valid566w(0) <= sink7_valid AND wire_w_sink7_data_range565w(0);
+ wire_w_lg_sink7_valid590w(0) <= sink7_valid AND wire_w_sink7_data_range589w(0);
+ wire_w_lg_sink7_valid614w(0) <= sink7_valid AND wire_w_sink7_data_range613w(0);
+ wire_w_lg_sink7_valid638w(0) <= sink7_valid AND wire_w_sink7_data_range637w(0);
+ wire_w_lg_sink7_valid662w(0) <= sink7_valid AND wire_w_sink7_data_range661w(0);
+ wire_w_lg_sink7_valid686w(0) <= sink7_valid AND wire_w_sink7_data_range685w(0);
+ wire_w_lg_sink7_valid710w(0) <= sink7_valid AND wire_w_sink7_data_range709w(0);
+ wire_w_lg_sink7_valid734w(0) <= sink7_valid AND wire_w_sink7_data_range733w(0);
+ wire_w_lg_sink7_valid86w(0) <= sink7_valid AND wire_w_sink7_data_range85w(0);
+ wire_w_lg_sink7_valid758w(0) <= sink7_valid AND wire_w_sink7_data_range757w(0);
+ wire_w_lg_sink7_valid782w(0) <= sink7_valid AND wire_w_sink7_data_range781w(0);
+ wire_w_lg_sink7_valid806w(0) <= sink7_valid AND wire_w_sink7_data_range805w(0);
+ wire_w_lg_sink7_valid830w(0) <= sink7_valid AND wire_w_sink7_data_range829w(0);
+ wire_w_lg_sink7_valid854w(0) <= sink7_valid AND wire_w_sink7_data_range853w(0);
+ wire_w_lg_sink7_valid878w(0) <= sink7_valid AND wire_w_sink7_data_range877w(0);
+ wire_w_lg_sink7_valid902w(0) <= sink7_valid AND wire_w_sink7_data_range901w(0);
+ wire_w_lg_sink7_valid926w(0) <= sink7_valid AND wire_w_sink7_data_range925w(0);
+ wire_w_lg_sink7_valid950w(0) <= sink7_valid AND wire_w_sink7_data_range949w(0);
+ wire_w_lg_sink7_valid974w(0) <= sink7_valid AND wire_w_sink7_data_range973w(0);
+ wire_w_lg_sink7_valid110w(0) <= sink7_valid AND wire_w_sink7_data_range109w(0);
+ wire_w_lg_sink7_valid998w(0) <= sink7_valid AND wire_w_sink7_data_range997w(0);
+ wire_w_lg_sink7_valid1022w(0) <= sink7_valid AND wire_w_sink7_data_range1021w(0);
+ wire_w_lg_sink7_valid1046w(0) <= sink7_valid AND wire_w_sink7_data_range1045w(0);
+ wire_w_lg_sink7_valid1070w(0) <= sink7_valid AND wire_w_sink7_data_range1069w(0);
+ wire_w_lg_sink7_valid1094w(0) <= sink7_valid AND wire_w_sink7_data_range1093w(0);
+ wire_w_lg_sink7_valid1118w(0) <= sink7_valid AND wire_w_sink7_data_range1117w(0);
+ wire_w_lg_sink7_valid1142w(0) <= sink7_valid AND wire_w_sink7_data_range1141w(0);
+ wire_w_lg_sink7_valid1166w(0) <= sink7_valid AND wire_w_sink7_data_range1165w(0);
+ wire_w_lg_sink7_valid1190w(0) <= sink7_valid AND wire_w_sink7_data_range1189w(0);
+ wire_w_lg_sink7_valid1214w(0) <= sink7_valid AND wire_w_sink7_data_range1213w(0);
+ wire_w_lg_sink7_valid134w(0) <= sink7_valid AND wire_w_sink7_data_range133w(0);
+ wire_w_lg_sink7_valid1238w(0) <= sink7_valid AND wire_w_sink7_data_range1237w(0);
+ wire_w_lg_sink7_valid1262w(0) <= sink7_valid AND wire_w_sink7_data_range1261w(0);
+ wire_w_lg_sink7_valid1286w(0) <= sink7_valid AND wire_w_sink7_data_range1285w(0);
+ wire_w_lg_sink7_valid1310w(0) <= sink7_valid AND wire_w_sink7_data_range1309w(0);
+ wire_w_lg_sink7_valid1334w(0) <= sink7_valid AND wire_w_sink7_data_range1333w(0);
+ wire_w_lg_sink7_valid1358w(0) <= sink7_valid AND wire_w_sink7_data_range1357w(0);
+ wire_w_lg_sink7_valid1382w(0) <= sink7_valid AND wire_w_sink7_data_range1381w(0);
+ wire_w_lg_sink7_valid1406w(0) <= sink7_valid AND wire_w_sink7_data_range1405w(0);
+ wire_w_lg_sink7_valid1430w(0) <= sink7_valid AND wire_w_sink7_data_range1429w(0);
+ wire_w_lg_sink7_valid1454w(0) <= sink7_valid AND wire_w_sink7_data_range1453w(0);
+ wire_w_lg_sink7_valid158w(0) <= sink7_valid AND wire_w_sink7_data_range157w(0);
+ wire_w_lg_sink7_valid1478w(0) <= sink7_valid AND wire_w_sink7_data_range1477w(0);
+ wire_w_lg_sink7_valid1502w(0) <= sink7_valid AND wire_w_sink7_data_range1501w(0);
+ wire_w_lg_sink7_valid1526w(0) <= sink7_valid AND wire_w_sink7_data_range1525w(0);
+ wire_w_lg_sink7_valid1550w(0) <= sink7_valid AND wire_w_sink7_data_range1549w(0);
+ wire_w_lg_sink7_valid1574w(0) <= sink7_valid AND wire_w_sink7_data_range1573w(0);
+ wire_w_lg_sink7_valid1598w(0) <= sink7_valid AND wire_w_sink7_data_range1597w(0);
+ wire_w_lg_sink7_valid1622w(0) <= sink7_valid AND wire_w_sink7_data_range1621w(0);
+ wire_w_lg_sink7_valid1646w(0) <= sink7_valid AND wire_w_sink7_data_range1645w(0);
+ wire_w_lg_sink7_valid1670w(0) <= sink7_valid AND wire_w_sink7_data_range1669w(0);
+ wire_w_lg_sink7_valid182w(0) <= sink7_valid AND wire_w_sink7_data_range181w(0);
+ wire_w_lg_sink7_valid206w(0) <= sink7_valid AND wire_w_sink7_data_range205w(0);
+ wire_w_lg_sink7_valid230w(0) <= sink7_valid AND wire_w_sink7_data_range229w(0);
+ wire_w_lg_sink7_valid254w(0) <= sink7_valid AND wire_w_sink7_data_range253w(0);
+ wire_w_lg_w_lg_sink0_valid1674w1677w(0) <= wire_w_lg_sink0_valid1674w(0) OR wire_w_lg_sink1_valid1676w(0);
+ wire_w_lg_w_lg_sink0_valid1699w1702w(0) <= wire_w_lg_sink0_valid1699w(0) OR wire_w_lg_sink1_valid1701w(0);
+ wire_w_lg_w_lg_sink0_valid1723w1726w(0) <= wire_w_lg_sink0_valid1723w(0) OR wire_w_lg_sink1_valid1725w(0);
+ wire_w_lg_w_lg_sink0_valid1747w1750w(0) <= wire_w_lg_sink0_valid1747w(0) OR wire_w_lg_sink1_valid1749w(0);
+ wire_w_lg_w_lg_sink0_valid1771w1774w(0) <= wire_w_lg_sink0_valid1771w(0) OR wire_w_lg_sink1_valid1773w(0);
+ wire_w_lg_w_lg_sink0_valid1795w1798w(0) <= wire_w_lg_sink0_valid1795w(0) OR wire_w_lg_sink1_valid1797w(0);
+ wire_w_lg_w_lg_sink0_valid1819w1822w(0) <= wire_w_lg_sink0_valid1819w(0) OR wire_w_lg_sink1_valid1821w(0);
+ wire_w_lg_w_lg_sink0_valid1843w1846w(0) <= wire_w_lg_sink0_valid1843w(0) OR wire_w_lg_sink1_valid1845w(0);
+ wire_w_lg_w_lg_sink0_valid17w20w(0) <= wire_w_lg_sink0_valid17w(0) OR wire_w_lg_sink1_valid19w(0);
+ wire_w_lg_w_lg_sink0_valid258w261w(0) <= wire_w_lg_sink0_valid258w(0) OR wire_w_lg_sink1_valid260w(0);
+ wire_w_lg_w_lg_sink0_valid282w285w(0) <= wire_w_lg_sink0_valid282w(0) OR wire_w_lg_sink1_valid284w(0);
+ wire_w_lg_w_lg_sink0_valid306w309w(0) <= wire_w_lg_sink0_valid306w(0) OR wire_w_lg_sink1_valid308w(0);
+ wire_w_lg_w_lg_sink0_valid330w333w(0) <= wire_w_lg_sink0_valid330w(0) OR wire_w_lg_sink1_valid332w(0);
+ wire_w_lg_w_lg_sink0_valid354w357w(0) <= wire_w_lg_sink0_valid354w(0) OR wire_w_lg_sink1_valid356w(0);
+ wire_w_lg_w_lg_sink0_valid378w381w(0) <= wire_w_lg_sink0_valid378w(0) OR wire_w_lg_sink1_valid380w(0);
+ wire_w_lg_w_lg_sink0_valid402w405w(0) <= wire_w_lg_sink0_valid402w(0) OR wire_w_lg_sink1_valid404w(0);
+ wire_w_lg_w_lg_sink0_valid426w429w(0) <= wire_w_lg_sink0_valid426w(0) OR wire_w_lg_sink1_valid428w(0);
+ wire_w_lg_w_lg_sink0_valid450w453w(0) <= wire_w_lg_sink0_valid450w(0) OR wire_w_lg_sink1_valid452w(0);
+ wire_w_lg_w_lg_sink0_valid474w477w(0) <= wire_w_lg_sink0_valid474w(0) OR wire_w_lg_sink1_valid476w(0);
+ wire_w_lg_w_lg_sink0_valid42w45w(0) <= wire_w_lg_sink0_valid42w(0) OR wire_w_lg_sink1_valid44w(0);
+ wire_w_lg_w_lg_sink0_valid498w501w(0) <= wire_w_lg_sink0_valid498w(0) OR wire_w_lg_sink1_valid500w(0);
+ wire_w_lg_w_lg_sink0_valid522w525w(0) <= wire_w_lg_sink0_valid522w(0) OR wire_w_lg_sink1_valid524w(0);
+ wire_w_lg_w_lg_sink0_valid546w549w(0) <= wire_w_lg_sink0_valid546w(0) OR wire_w_lg_sink1_valid548w(0);
+ wire_w_lg_w_lg_sink0_valid570w573w(0) <= wire_w_lg_sink0_valid570w(0) OR wire_w_lg_sink1_valid572w(0);
+ wire_w_lg_w_lg_sink0_valid594w597w(0) <= wire_w_lg_sink0_valid594w(0) OR wire_w_lg_sink1_valid596w(0);
+ wire_w_lg_w_lg_sink0_valid618w621w(0) <= wire_w_lg_sink0_valid618w(0) OR wire_w_lg_sink1_valid620w(0);
+ wire_w_lg_w_lg_sink0_valid642w645w(0) <= wire_w_lg_sink0_valid642w(0) OR wire_w_lg_sink1_valid644w(0);
+ wire_w_lg_w_lg_sink0_valid666w669w(0) <= wire_w_lg_sink0_valid666w(0) OR wire_w_lg_sink1_valid668w(0);
+ wire_w_lg_w_lg_sink0_valid690w693w(0) <= wire_w_lg_sink0_valid690w(0) OR wire_w_lg_sink1_valid692w(0);
+ wire_w_lg_w_lg_sink0_valid714w717w(0) <= wire_w_lg_sink0_valid714w(0) OR wire_w_lg_sink1_valid716w(0);
+ wire_w_lg_w_lg_sink0_valid66w69w(0) <= wire_w_lg_sink0_valid66w(0) OR wire_w_lg_sink1_valid68w(0);
+ wire_w_lg_w_lg_sink0_valid738w741w(0) <= wire_w_lg_sink0_valid738w(0) OR wire_w_lg_sink1_valid740w(0);
+ wire_w_lg_w_lg_sink0_valid762w765w(0) <= wire_w_lg_sink0_valid762w(0) OR wire_w_lg_sink1_valid764w(0);
+ wire_w_lg_w_lg_sink0_valid786w789w(0) <= wire_w_lg_sink0_valid786w(0) OR wire_w_lg_sink1_valid788w(0);
+ wire_w_lg_w_lg_sink0_valid810w813w(0) <= wire_w_lg_sink0_valid810w(0) OR wire_w_lg_sink1_valid812w(0);
+ wire_w_lg_w_lg_sink0_valid834w837w(0) <= wire_w_lg_sink0_valid834w(0) OR wire_w_lg_sink1_valid836w(0);
+ wire_w_lg_w_lg_sink0_valid858w861w(0) <= wire_w_lg_sink0_valid858w(0) OR wire_w_lg_sink1_valid860w(0);
+ wire_w_lg_w_lg_sink0_valid882w885w(0) <= wire_w_lg_sink0_valid882w(0) OR wire_w_lg_sink1_valid884w(0);
+ wire_w_lg_w_lg_sink0_valid906w909w(0) <= wire_w_lg_sink0_valid906w(0) OR wire_w_lg_sink1_valid908w(0);
+ wire_w_lg_w_lg_sink0_valid930w933w(0) <= wire_w_lg_sink0_valid930w(0) OR wire_w_lg_sink1_valid932w(0);
+ wire_w_lg_w_lg_sink0_valid954w957w(0) <= wire_w_lg_sink0_valid954w(0) OR wire_w_lg_sink1_valid956w(0);
+ wire_w_lg_w_lg_sink0_valid90w93w(0) <= wire_w_lg_sink0_valid90w(0) OR wire_w_lg_sink1_valid92w(0);
+ wire_w_lg_w_lg_sink0_valid978w981w(0) <= wire_w_lg_sink0_valid978w(0) OR wire_w_lg_sink1_valid980w(0);
+ wire_w_lg_w_lg_sink0_valid1002w1005w(0) <= wire_w_lg_sink0_valid1002w(0) OR wire_w_lg_sink1_valid1004w(0);
+ wire_w_lg_w_lg_sink0_valid1026w1029w(0) <= wire_w_lg_sink0_valid1026w(0) OR wire_w_lg_sink1_valid1028w(0);
+ wire_w_lg_w_lg_sink0_valid1050w1053w(0) <= wire_w_lg_sink0_valid1050w(0) OR wire_w_lg_sink1_valid1052w(0);
+ wire_w_lg_w_lg_sink0_valid1074w1077w(0) <= wire_w_lg_sink0_valid1074w(0) OR wire_w_lg_sink1_valid1076w(0);
+ wire_w_lg_w_lg_sink0_valid1098w1101w(0) <= wire_w_lg_sink0_valid1098w(0) OR wire_w_lg_sink1_valid1100w(0);
+ wire_w_lg_w_lg_sink0_valid1122w1125w(0) <= wire_w_lg_sink0_valid1122w(0) OR wire_w_lg_sink1_valid1124w(0);
+ wire_w_lg_w_lg_sink0_valid1146w1149w(0) <= wire_w_lg_sink0_valid1146w(0) OR wire_w_lg_sink1_valid1148w(0);
+ wire_w_lg_w_lg_sink0_valid1170w1173w(0) <= wire_w_lg_sink0_valid1170w(0) OR wire_w_lg_sink1_valid1172w(0);
+ wire_w_lg_w_lg_sink0_valid1194w1197w(0) <= wire_w_lg_sink0_valid1194w(0) OR wire_w_lg_sink1_valid1196w(0);
+ wire_w_lg_w_lg_sink0_valid114w117w(0) <= wire_w_lg_sink0_valid114w(0) OR wire_w_lg_sink1_valid116w(0);
+ wire_w_lg_w_lg_sink0_valid1218w1221w(0) <= wire_w_lg_sink0_valid1218w(0) OR wire_w_lg_sink1_valid1220w(0);
+ wire_w_lg_w_lg_sink0_valid1242w1245w(0) <= wire_w_lg_sink0_valid1242w(0) OR wire_w_lg_sink1_valid1244w(0);
+ wire_w_lg_w_lg_sink0_valid1266w1269w(0) <= wire_w_lg_sink0_valid1266w(0) OR wire_w_lg_sink1_valid1268w(0);
+ wire_w_lg_w_lg_sink0_valid1290w1293w(0) <= wire_w_lg_sink0_valid1290w(0) OR wire_w_lg_sink1_valid1292w(0);
+ wire_w_lg_w_lg_sink0_valid1314w1317w(0) <= wire_w_lg_sink0_valid1314w(0) OR wire_w_lg_sink1_valid1316w(0);
+ wire_w_lg_w_lg_sink0_valid1338w1341w(0) <= wire_w_lg_sink0_valid1338w(0) OR wire_w_lg_sink1_valid1340w(0);
+ wire_w_lg_w_lg_sink0_valid1362w1365w(0) <= wire_w_lg_sink0_valid1362w(0) OR wire_w_lg_sink1_valid1364w(0);
+ wire_w_lg_w_lg_sink0_valid1386w1389w(0) <= wire_w_lg_sink0_valid1386w(0) OR wire_w_lg_sink1_valid1388w(0);
+ wire_w_lg_w_lg_sink0_valid1410w1413w(0) <= wire_w_lg_sink0_valid1410w(0) OR wire_w_lg_sink1_valid1412w(0);
+ wire_w_lg_w_lg_sink0_valid1434w1437w(0) <= wire_w_lg_sink0_valid1434w(0) OR wire_w_lg_sink1_valid1436w(0);
+ wire_w_lg_w_lg_sink0_valid138w141w(0) <= wire_w_lg_sink0_valid138w(0) OR wire_w_lg_sink1_valid140w(0);
+ wire_w_lg_w_lg_sink0_valid1458w1461w(0) <= wire_w_lg_sink0_valid1458w(0) OR wire_w_lg_sink1_valid1460w(0);
+ wire_w_lg_w_lg_sink0_valid1482w1485w(0) <= wire_w_lg_sink0_valid1482w(0) OR wire_w_lg_sink1_valid1484w(0);
+ wire_w_lg_w_lg_sink0_valid1506w1509w(0) <= wire_w_lg_sink0_valid1506w(0) OR wire_w_lg_sink1_valid1508w(0);
+ wire_w_lg_w_lg_sink0_valid1530w1533w(0) <= wire_w_lg_sink0_valid1530w(0) OR wire_w_lg_sink1_valid1532w(0);
+ wire_w_lg_w_lg_sink0_valid1554w1557w(0) <= wire_w_lg_sink0_valid1554w(0) OR wire_w_lg_sink1_valid1556w(0);
+ wire_w_lg_w_lg_sink0_valid1578w1581w(0) <= wire_w_lg_sink0_valid1578w(0) OR wire_w_lg_sink1_valid1580w(0);
+ wire_w_lg_w_lg_sink0_valid1602w1605w(0) <= wire_w_lg_sink0_valid1602w(0) OR wire_w_lg_sink1_valid1604w(0);
+ wire_w_lg_w_lg_sink0_valid1626w1629w(0) <= wire_w_lg_sink0_valid1626w(0) OR wire_w_lg_sink1_valid1628w(0);
+ wire_w_lg_w_lg_sink0_valid1650w1653w(0) <= wire_w_lg_sink0_valid1650w(0) OR wire_w_lg_sink1_valid1652w(0);
+ wire_w_lg_w_lg_sink0_valid162w165w(0) <= wire_w_lg_sink0_valid162w(0) OR wire_w_lg_sink1_valid164w(0);
+ wire_w_lg_w_lg_sink0_valid186w189w(0) <= wire_w_lg_sink0_valid186w(0) OR wire_w_lg_sink1_valid188w(0);
+ wire_w_lg_w_lg_sink0_valid210w213w(0) <= wire_w_lg_sink0_valid210w(0) OR wire_w_lg_sink1_valid212w(0);
+ wire_w_lg_w_lg_sink0_valid234w237w(0) <= wire_w_lg_sink0_valid234w(0) OR wire_w_lg_sink1_valid236w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1674w1677w1680w(0) <= wire_w_lg_w_lg_sink0_valid1674w1677w(0) OR wire_w_lg_sink2_valid1679w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1699w1702w1705w(0) <= wire_w_lg_w_lg_sink0_valid1699w1702w(0) OR wire_w_lg_sink2_valid1704w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1723w1726w1729w(0) <= wire_w_lg_w_lg_sink0_valid1723w1726w(0) OR wire_w_lg_sink2_valid1728w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1747w1750w1753w(0) <= wire_w_lg_w_lg_sink0_valid1747w1750w(0) OR wire_w_lg_sink2_valid1752w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1771w1774w1777w(0) <= wire_w_lg_w_lg_sink0_valid1771w1774w(0) OR wire_w_lg_sink2_valid1776w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1795w1798w1801w(0) <= wire_w_lg_w_lg_sink0_valid1795w1798w(0) OR wire_w_lg_sink2_valid1800w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1819w1822w1825w(0) <= wire_w_lg_w_lg_sink0_valid1819w1822w(0) OR wire_w_lg_sink2_valid1824w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1843w1846w1849w(0) <= wire_w_lg_w_lg_sink0_valid1843w1846w(0) OR wire_w_lg_sink2_valid1848w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid17w20w23w(0) <= wire_w_lg_w_lg_sink0_valid17w20w(0) OR wire_w_lg_sink2_valid22w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid258w261w264w(0) <= wire_w_lg_w_lg_sink0_valid258w261w(0) OR wire_w_lg_sink2_valid263w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid282w285w288w(0) <= wire_w_lg_w_lg_sink0_valid282w285w(0) OR wire_w_lg_sink2_valid287w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid306w309w312w(0) <= wire_w_lg_w_lg_sink0_valid306w309w(0) OR wire_w_lg_sink2_valid311w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid330w333w336w(0) <= wire_w_lg_w_lg_sink0_valid330w333w(0) OR wire_w_lg_sink2_valid335w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid354w357w360w(0) <= wire_w_lg_w_lg_sink0_valid354w357w(0) OR wire_w_lg_sink2_valid359w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid378w381w384w(0) <= wire_w_lg_w_lg_sink0_valid378w381w(0) OR wire_w_lg_sink2_valid383w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid402w405w408w(0) <= wire_w_lg_w_lg_sink0_valid402w405w(0) OR wire_w_lg_sink2_valid407w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid426w429w432w(0) <= wire_w_lg_w_lg_sink0_valid426w429w(0) OR wire_w_lg_sink2_valid431w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid450w453w456w(0) <= wire_w_lg_w_lg_sink0_valid450w453w(0) OR wire_w_lg_sink2_valid455w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid474w477w480w(0) <= wire_w_lg_w_lg_sink0_valid474w477w(0) OR wire_w_lg_sink2_valid479w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid42w45w48w(0) <= wire_w_lg_w_lg_sink0_valid42w45w(0) OR wire_w_lg_sink2_valid47w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid498w501w504w(0) <= wire_w_lg_w_lg_sink0_valid498w501w(0) OR wire_w_lg_sink2_valid503w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid522w525w528w(0) <= wire_w_lg_w_lg_sink0_valid522w525w(0) OR wire_w_lg_sink2_valid527w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid546w549w552w(0) <= wire_w_lg_w_lg_sink0_valid546w549w(0) OR wire_w_lg_sink2_valid551w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid570w573w576w(0) <= wire_w_lg_w_lg_sink0_valid570w573w(0) OR wire_w_lg_sink2_valid575w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid594w597w600w(0) <= wire_w_lg_w_lg_sink0_valid594w597w(0) OR wire_w_lg_sink2_valid599w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid618w621w624w(0) <= wire_w_lg_w_lg_sink0_valid618w621w(0) OR wire_w_lg_sink2_valid623w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid642w645w648w(0) <= wire_w_lg_w_lg_sink0_valid642w645w(0) OR wire_w_lg_sink2_valid647w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid666w669w672w(0) <= wire_w_lg_w_lg_sink0_valid666w669w(0) OR wire_w_lg_sink2_valid671w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid690w693w696w(0) <= wire_w_lg_w_lg_sink0_valid690w693w(0) OR wire_w_lg_sink2_valid695w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid714w717w720w(0) <= wire_w_lg_w_lg_sink0_valid714w717w(0) OR wire_w_lg_sink2_valid719w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid66w69w72w(0) <= wire_w_lg_w_lg_sink0_valid66w69w(0) OR wire_w_lg_sink2_valid71w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid738w741w744w(0) <= wire_w_lg_w_lg_sink0_valid738w741w(0) OR wire_w_lg_sink2_valid743w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid762w765w768w(0) <= wire_w_lg_w_lg_sink0_valid762w765w(0) OR wire_w_lg_sink2_valid767w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid786w789w792w(0) <= wire_w_lg_w_lg_sink0_valid786w789w(0) OR wire_w_lg_sink2_valid791w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid810w813w816w(0) <= wire_w_lg_w_lg_sink0_valid810w813w(0) OR wire_w_lg_sink2_valid815w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid834w837w840w(0) <= wire_w_lg_w_lg_sink0_valid834w837w(0) OR wire_w_lg_sink2_valid839w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid858w861w864w(0) <= wire_w_lg_w_lg_sink0_valid858w861w(0) OR wire_w_lg_sink2_valid863w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid882w885w888w(0) <= wire_w_lg_w_lg_sink0_valid882w885w(0) OR wire_w_lg_sink2_valid887w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid906w909w912w(0) <= wire_w_lg_w_lg_sink0_valid906w909w(0) OR wire_w_lg_sink2_valid911w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid930w933w936w(0) <= wire_w_lg_w_lg_sink0_valid930w933w(0) OR wire_w_lg_sink2_valid935w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid954w957w960w(0) <= wire_w_lg_w_lg_sink0_valid954w957w(0) OR wire_w_lg_sink2_valid959w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid90w93w96w(0) <= wire_w_lg_w_lg_sink0_valid90w93w(0) OR wire_w_lg_sink2_valid95w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid978w981w984w(0) <= wire_w_lg_w_lg_sink0_valid978w981w(0) OR wire_w_lg_sink2_valid983w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1002w1005w1008w(0) <= wire_w_lg_w_lg_sink0_valid1002w1005w(0) OR wire_w_lg_sink2_valid1007w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1026w1029w1032w(0) <= wire_w_lg_w_lg_sink0_valid1026w1029w(0) OR wire_w_lg_sink2_valid1031w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1050w1053w1056w(0) <= wire_w_lg_w_lg_sink0_valid1050w1053w(0) OR wire_w_lg_sink2_valid1055w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1074w1077w1080w(0) <= wire_w_lg_w_lg_sink0_valid1074w1077w(0) OR wire_w_lg_sink2_valid1079w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1098w1101w1104w(0) <= wire_w_lg_w_lg_sink0_valid1098w1101w(0) OR wire_w_lg_sink2_valid1103w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1122w1125w1128w(0) <= wire_w_lg_w_lg_sink0_valid1122w1125w(0) OR wire_w_lg_sink2_valid1127w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1146w1149w1152w(0) <= wire_w_lg_w_lg_sink0_valid1146w1149w(0) OR wire_w_lg_sink2_valid1151w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1170w1173w1176w(0) <= wire_w_lg_w_lg_sink0_valid1170w1173w(0) OR wire_w_lg_sink2_valid1175w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1194w1197w1200w(0) <= wire_w_lg_w_lg_sink0_valid1194w1197w(0) OR wire_w_lg_sink2_valid1199w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid114w117w120w(0) <= wire_w_lg_w_lg_sink0_valid114w117w(0) OR wire_w_lg_sink2_valid119w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1218w1221w1224w(0) <= wire_w_lg_w_lg_sink0_valid1218w1221w(0) OR wire_w_lg_sink2_valid1223w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1242w1245w1248w(0) <= wire_w_lg_w_lg_sink0_valid1242w1245w(0) OR wire_w_lg_sink2_valid1247w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1266w1269w1272w(0) <= wire_w_lg_w_lg_sink0_valid1266w1269w(0) OR wire_w_lg_sink2_valid1271w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1290w1293w1296w(0) <= wire_w_lg_w_lg_sink0_valid1290w1293w(0) OR wire_w_lg_sink2_valid1295w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1314w1317w1320w(0) <= wire_w_lg_w_lg_sink0_valid1314w1317w(0) OR wire_w_lg_sink2_valid1319w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1338w1341w1344w(0) <= wire_w_lg_w_lg_sink0_valid1338w1341w(0) OR wire_w_lg_sink2_valid1343w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1362w1365w1368w(0) <= wire_w_lg_w_lg_sink0_valid1362w1365w(0) OR wire_w_lg_sink2_valid1367w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1386w1389w1392w(0) <= wire_w_lg_w_lg_sink0_valid1386w1389w(0) OR wire_w_lg_sink2_valid1391w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1410w1413w1416w(0) <= wire_w_lg_w_lg_sink0_valid1410w1413w(0) OR wire_w_lg_sink2_valid1415w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1434w1437w1440w(0) <= wire_w_lg_w_lg_sink0_valid1434w1437w(0) OR wire_w_lg_sink2_valid1439w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid138w141w144w(0) <= wire_w_lg_w_lg_sink0_valid138w141w(0) OR wire_w_lg_sink2_valid143w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1458w1461w1464w(0) <= wire_w_lg_w_lg_sink0_valid1458w1461w(0) OR wire_w_lg_sink2_valid1463w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1482w1485w1488w(0) <= wire_w_lg_w_lg_sink0_valid1482w1485w(0) OR wire_w_lg_sink2_valid1487w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1506w1509w1512w(0) <= wire_w_lg_w_lg_sink0_valid1506w1509w(0) OR wire_w_lg_sink2_valid1511w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1530w1533w1536w(0) <= wire_w_lg_w_lg_sink0_valid1530w1533w(0) OR wire_w_lg_sink2_valid1535w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1554w1557w1560w(0) <= wire_w_lg_w_lg_sink0_valid1554w1557w(0) OR wire_w_lg_sink2_valid1559w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1578w1581w1584w(0) <= wire_w_lg_w_lg_sink0_valid1578w1581w(0) OR wire_w_lg_sink2_valid1583w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1602w1605w1608w(0) <= wire_w_lg_w_lg_sink0_valid1602w1605w(0) OR wire_w_lg_sink2_valid1607w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1626w1629w1632w(0) <= wire_w_lg_w_lg_sink0_valid1626w1629w(0) OR wire_w_lg_sink2_valid1631w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1650w1653w1656w(0) <= wire_w_lg_w_lg_sink0_valid1650w1653w(0) OR wire_w_lg_sink2_valid1655w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid162w165w168w(0) <= wire_w_lg_w_lg_sink0_valid162w165w(0) OR wire_w_lg_sink2_valid167w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid186w189w192w(0) <= wire_w_lg_w_lg_sink0_valid186w189w(0) OR wire_w_lg_sink2_valid191w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid210w213w216w(0) <= wire_w_lg_w_lg_sink0_valid210w213w(0) OR wire_w_lg_sink2_valid215w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid234w237w240w(0) <= wire_w_lg_w_lg_sink0_valid234w237w(0) OR wire_w_lg_sink2_valid239w(0);
+ wire_w1683w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1674w1677w1680w(0) OR wire_w_lg_sink3_valid1682w(0);
+ wire_w1708w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1699w1702w1705w(0) OR wire_w_lg_sink3_valid1707w(0);
+ wire_w1732w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1723w1726w1729w(0) OR wire_w_lg_sink3_valid1731w(0);
+ wire_w1756w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1747w1750w1753w(0) OR wire_w_lg_sink3_valid1755w(0);
+ wire_w1780w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1771w1774w1777w(0) OR wire_w_lg_sink3_valid1779w(0);
+ wire_w1804w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1795w1798w1801w(0) OR wire_w_lg_sink3_valid1803w(0);
+ wire_w1828w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1819w1822w1825w(0) OR wire_w_lg_sink3_valid1827w(0);
+ wire_w1852w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1843w1846w1849w(0) OR wire_w_lg_sink3_valid1851w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid17w20w23w26w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid17w20w23w(0) OR wire_w_lg_sink3_valid25w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid258w261w264w267w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid258w261w264w(0) OR wire_w_lg_sink3_valid266w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid282w285w288w291w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid282w285w288w(0) OR wire_w_lg_sink3_valid290w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid306w309w312w315w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid306w309w312w(0) OR wire_w_lg_sink3_valid314w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid330w333w336w339w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid330w333w336w(0) OR wire_w_lg_sink3_valid338w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid354w357w360w363w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid354w357w360w(0) OR wire_w_lg_sink3_valid362w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid378w381w384w387w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid378w381w384w(0) OR wire_w_lg_sink3_valid386w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid402w405w408w411w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid402w405w408w(0) OR wire_w_lg_sink3_valid410w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid426w429w432w435w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid426w429w432w(0) OR wire_w_lg_sink3_valid434w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid450w453w456w459w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid450w453w456w(0) OR wire_w_lg_sink3_valid458w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid474w477w480w483w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid474w477w480w(0) OR wire_w_lg_sink3_valid482w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid42w45w48w51w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid42w45w48w(0) OR wire_w_lg_sink3_valid50w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid498w501w504w507w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid498w501w504w(0) OR wire_w_lg_sink3_valid506w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid522w525w528w531w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid522w525w528w(0) OR wire_w_lg_sink3_valid530w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid546w549w552w555w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid546w549w552w(0) OR wire_w_lg_sink3_valid554w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid570w573w576w579w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid570w573w576w(0) OR wire_w_lg_sink3_valid578w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid594w597w600w603w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid594w597w600w(0) OR wire_w_lg_sink3_valid602w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid618w621w624w627w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid618w621w624w(0) OR wire_w_lg_sink3_valid626w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid642w645w648w651w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid642w645w648w(0) OR wire_w_lg_sink3_valid650w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid666w669w672w675w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid666w669w672w(0) OR wire_w_lg_sink3_valid674w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid690w693w696w699w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid690w693w696w(0) OR wire_w_lg_sink3_valid698w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid714w717w720w723w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid714w717w720w(0) OR wire_w_lg_sink3_valid722w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid66w69w72w75w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid66w69w72w(0) OR wire_w_lg_sink3_valid74w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid738w741w744w747w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid738w741w744w(0) OR wire_w_lg_sink3_valid746w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid762w765w768w771w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid762w765w768w(0) OR wire_w_lg_sink3_valid770w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid786w789w792w795w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid786w789w792w(0) OR wire_w_lg_sink3_valid794w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid810w813w816w819w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid810w813w816w(0) OR wire_w_lg_sink3_valid818w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid834w837w840w843w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid834w837w840w(0) OR wire_w_lg_sink3_valid842w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid858w861w864w867w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid858w861w864w(0) OR wire_w_lg_sink3_valid866w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid882w885w888w891w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid882w885w888w(0) OR wire_w_lg_sink3_valid890w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid906w909w912w915w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid906w909w912w(0) OR wire_w_lg_sink3_valid914w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid930w933w936w939w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid930w933w936w(0) OR wire_w_lg_sink3_valid938w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid954w957w960w963w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid954w957w960w(0) OR wire_w_lg_sink3_valid962w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid90w93w96w99w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid90w93w96w(0) OR wire_w_lg_sink3_valid98w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid978w981w984w987w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid978w981w984w(0) OR wire_w_lg_sink3_valid986w(0);
+ wire_w1011w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1002w1005w1008w(0) OR wire_w_lg_sink3_valid1010w(0);
+ wire_w1035w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1026w1029w1032w(0) OR wire_w_lg_sink3_valid1034w(0);
+ wire_w1059w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1050w1053w1056w(0) OR wire_w_lg_sink3_valid1058w(0);
+ wire_w1083w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1074w1077w1080w(0) OR wire_w_lg_sink3_valid1082w(0);
+ wire_w1107w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1098w1101w1104w(0) OR wire_w_lg_sink3_valid1106w(0);
+ wire_w1131w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1122w1125w1128w(0) OR wire_w_lg_sink3_valid1130w(0);
+ wire_w1155w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1146w1149w1152w(0) OR wire_w_lg_sink3_valid1154w(0);
+ wire_w1179w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1170w1173w1176w(0) OR wire_w_lg_sink3_valid1178w(0);
+ wire_w1203w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1194w1197w1200w(0) OR wire_w_lg_sink3_valid1202w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid114w117w120w123w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid114w117w120w(0) OR wire_w_lg_sink3_valid122w(0);
+ wire_w1227w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1218w1221w1224w(0) OR wire_w_lg_sink3_valid1226w(0);
+ wire_w1251w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1242w1245w1248w(0) OR wire_w_lg_sink3_valid1250w(0);
+ wire_w1275w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1266w1269w1272w(0) OR wire_w_lg_sink3_valid1274w(0);
+ wire_w1299w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1290w1293w1296w(0) OR wire_w_lg_sink3_valid1298w(0);
+ wire_w1323w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1314w1317w1320w(0) OR wire_w_lg_sink3_valid1322w(0);
+ wire_w1347w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1338w1341w1344w(0) OR wire_w_lg_sink3_valid1346w(0);
+ wire_w1371w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1362w1365w1368w(0) OR wire_w_lg_sink3_valid1370w(0);
+ wire_w1395w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1386w1389w1392w(0) OR wire_w_lg_sink3_valid1394w(0);
+ wire_w1419w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1410w1413w1416w(0) OR wire_w_lg_sink3_valid1418w(0);
+ wire_w1443w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1434w1437w1440w(0) OR wire_w_lg_sink3_valid1442w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid138w141w144w147w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid138w141w144w(0) OR wire_w_lg_sink3_valid146w(0);
+ wire_w1467w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1458w1461w1464w(0) OR wire_w_lg_sink3_valid1466w(0);
+ wire_w1491w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1482w1485w1488w(0) OR wire_w_lg_sink3_valid1490w(0);
+ wire_w1515w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1506w1509w1512w(0) OR wire_w_lg_sink3_valid1514w(0);
+ wire_w1539w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1530w1533w1536w(0) OR wire_w_lg_sink3_valid1538w(0);
+ wire_w1563w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1554w1557w1560w(0) OR wire_w_lg_sink3_valid1562w(0);
+ wire_w1587w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1578w1581w1584w(0) OR wire_w_lg_sink3_valid1586w(0);
+ wire_w1611w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1602w1605w1608w(0) OR wire_w_lg_sink3_valid1610w(0);
+ wire_w1635w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1626w1629w1632w(0) OR wire_w_lg_sink3_valid1634w(0);
+ wire_w1659w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1650w1653w1656w(0) OR wire_w_lg_sink3_valid1658w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid162w165w168w171w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid162w165w168w(0) OR wire_w_lg_sink3_valid170w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid186w189w192w195w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid186w189w192w(0) OR wire_w_lg_sink3_valid194w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid210w213w216w219w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid210w213w216w(0) OR wire_w_lg_sink3_valid218w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid234w237w240w243w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid234w237w240w(0) OR wire_w_lg_sink3_valid242w(0);
+ wire_w_lg_w1683w1686w(0) <= wire_w1683w(0) OR wire_w_lg_sink4_valid1685w(0);
+ wire_w_lg_w1708w1711w(0) <= wire_w1708w(0) OR wire_w_lg_sink4_valid1710w(0);
+ wire_w_lg_w1732w1735w(0) <= wire_w1732w(0) OR wire_w_lg_sink4_valid1734w(0);
+ wire_w_lg_w1756w1759w(0) <= wire_w1756w(0) OR wire_w_lg_sink4_valid1758w(0);
+ wire_w_lg_w1780w1783w(0) <= wire_w1780w(0) OR wire_w_lg_sink4_valid1782w(0);
+ wire_w_lg_w1804w1807w(0) <= wire_w1804w(0) OR wire_w_lg_sink4_valid1806w(0);
+ wire_w_lg_w1828w1831w(0) <= wire_w1828w(0) OR wire_w_lg_sink4_valid1830w(0);
+ wire_w_lg_w1852w1855w(0) <= wire_w1852w(0) OR wire_w_lg_sink4_valid1854w(0);
+ wire_w29w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid17w20w23w26w(0) OR wire_w_lg_sink4_valid28w(0);
+ wire_w270w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid258w261w264w267w(0) OR wire_w_lg_sink4_valid269w(0);
+ wire_w294w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid282w285w288w291w(0) OR wire_w_lg_sink4_valid293w(0);
+ wire_w318w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid306w309w312w315w(0) OR wire_w_lg_sink4_valid317w(0);
+ wire_w342w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid330w333w336w339w(0) OR wire_w_lg_sink4_valid341w(0);
+ wire_w366w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid354w357w360w363w(0) OR wire_w_lg_sink4_valid365w(0);
+ wire_w390w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid378w381w384w387w(0) OR wire_w_lg_sink4_valid389w(0);
+ wire_w414w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid402w405w408w411w(0) OR wire_w_lg_sink4_valid413w(0);
+ wire_w438w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid426w429w432w435w(0) OR wire_w_lg_sink4_valid437w(0);
+ wire_w462w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid450w453w456w459w(0) OR wire_w_lg_sink4_valid461w(0);
+ wire_w486w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid474w477w480w483w(0) OR wire_w_lg_sink4_valid485w(0);
+ wire_w54w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid42w45w48w51w(0) OR wire_w_lg_sink4_valid53w(0);
+ wire_w510w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid498w501w504w507w(0) OR wire_w_lg_sink4_valid509w(0);
+ wire_w534w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid522w525w528w531w(0) OR wire_w_lg_sink4_valid533w(0);
+ wire_w558w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid546w549w552w555w(0) OR wire_w_lg_sink4_valid557w(0);
+ wire_w582w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid570w573w576w579w(0) OR wire_w_lg_sink4_valid581w(0);
+ wire_w606w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid594w597w600w603w(0) OR wire_w_lg_sink4_valid605w(0);
+ wire_w630w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid618w621w624w627w(0) OR wire_w_lg_sink4_valid629w(0);
+ wire_w654w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid642w645w648w651w(0) OR wire_w_lg_sink4_valid653w(0);
+ wire_w678w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid666w669w672w675w(0) OR wire_w_lg_sink4_valid677w(0);
+ wire_w702w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid690w693w696w699w(0) OR wire_w_lg_sink4_valid701w(0);
+ wire_w726w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid714w717w720w723w(0) OR wire_w_lg_sink4_valid725w(0);
+ wire_w78w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid66w69w72w75w(0) OR wire_w_lg_sink4_valid77w(0);
+ wire_w750w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid738w741w744w747w(0) OR wire_w_lg_sink4_valid749w(0);
+ wire_w774w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid762w765w768w771w(0) OR wire_w_lg_sink4_valid773w(0);
+ wire_w798w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid786w789w792w795w(0) OR wire_w_lg_sink4_valid797w(0);
+ wire_w822w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid810w813w816w819w(0) OR wire_w_lg_sink4_valid821w(0);
+ wire_w846w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid834w837w840w843w(0) OR wire_w_lg_sink4_valid845w(0);
+ wire_w870w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid858w861w864w867w(0) OR wire_w_lg_sink4_valid869w(0);
+ wire_w894w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid882w885w888w891w(0) OR wire_w_lg_sink4_valid893w(0);
+ wire_w918w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid906w909w912w915w(0) OR wire_w_lg_sink4_valid917w(0);
+ wire_w942w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid930w933w936w939w(0) OR wire_w_lg_sink4_valid941w(0);
+ wire_w966w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid954w957w960w963w(0) OR wire_w_lg_sink4_valid965w(0);
+ wire_w102w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid90w93w96w99w(0) OR wire_w_lg_sink4_valid101w(0);
+ wire_w990w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid978w981w984w987w(0) OR wire_w_lg_sink4_valid989w(0);
+ wire_w_lg_w1011w1014w(0) <= wire_w1011w(0) OR wire_w_lg_sink4_valid1013w(0);
+ wire_w_lg_w1035w1038w(0) <= wire_w1035w(0) OR wire_w_lg_sink4_valid1037w(0);
+ wire_w_lg_w1059w1062w(0) <= wire_w1059w(0) OR wire_w_lg_sink4_valid1061w(0);
+ wire_w_lg_w1083w1086w(0) <= wire_w1083w(0) OR wire_w_lg_sink4_valid1085w(0);
+ wire_w_lg_w1107w1110w(0) <= wire_w1107w(0) OR wire_w_lg_sink4_valid1109w(0);
+ wire_w_lg_w1131w1134w(0) <= wire_w1131w(0) OR wire_w_lg_sink4_valid1133w(0);
+ wire_w_lg_w1155w1158w(0) <= wire_w1155w(0) OR wire_w_lg_sink4_valid1157w(0);
+ wire_w_lg_w1179w1182w(0) <= wire_w1179w(0) OR wire_w_lg_sink4_valid1181w(0);
+ wire_w_lg_w1203w1206w(0) <= wire_w1203w(0) OR wire_w_lg_sink4_valid1205w(0);
+ wire_w126w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid114w117w120w123w(0) OR wire_w_lg_sink4_valid125w(0);
+ wire_w_lg_w1227w1230w(0) <= wire_w1227w(0) OR wire_w_lg_sink4_valid1229w(0);
+ wire_w_lg_w1251w1254w(0) <= wire_w1251w(0) OR wire_w_lg_sink4_valid1253w(0);
+ wire_w_lg_w1275w1278w(0) <= wire_w1275w(0) OR wire_w_lg_sink4_valid1277w(0);
+ wire_w_lg_w1299w1302w(0) <= wire_w1299w(0) OR wire_w_lg_sink4_valid1301w(0);
+ wire_w_lg_w1323w1326w(0) <= wire_w1323w(0) OR wire_w_lg_sink4_valid1325w(0);
+ wire_w_lg_w1347w1350w(0) <= wire_w1347w(0) OR wire_w_lg_sink4_valid1349w(0);
+ wire_w_lg_w1371w1374w(0) <= wire_w1371w(0) OR wire_w_lg_sink4_valid1373w(0);
+ wire_w_lg_w1395w1398w(0) <= wire_w1395w(0) OR wire_w_lg_sink4_valid1397w(0);
+ wire_w_lg_w1419w1422w(0) <= wire_w1419w(0) OR wire_w_lg_sink4_valid1421w(0);
+ wire_w_lg_w1443w1446w(0) <= wire_w1443w(0) OR wire_w_lg_sink4_valid1445w(0);
+ wire_w150w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid138w141w144w147w(0) OR wire_w_lg_sink4_valid149w(0);
+ wire_w_lg_w1467w1470w(0) <= wire_w1467w(0) OR wire_w_lg_sink4_valid1469w(0);
+ wire_w_lg_w1491w1494w(0) <= wire_w1491w(0) OR wire_w_lg_sink4_valid1493w(0);
+ wire_w_lg_w1515w1518w(0) <= wire_w1515w(0) OR wire_w_lg_sink4_valid1517w(0);
+ wire_w_lg_w1539w1542w(0) <= wire_w1539w(0) OR wire_w_lg_sink4_valid1541w(0);
+ wire_w_lg_w1563w1566w(0) <= wire_w1563w(0) OR wire_w_lg_sink4_valid1565w(0);
+ wire_w_lg_w1587w1590w(0) <= wire_w1587w(0) OR wire_w_lg_sink4_valid1589w(0);
+ wire_w_lg_w1611w1614w(0) <= wire_w1611w(0) OR wire_w_lg_sink4_valid1613w(0);
+ wire_w_lg_w1635w1638w(0) <= wire_w1635w(0) OR wire_w_lg_sink4_valid1637w(0);
+ wire_w_lg_w1659w1662w(0) <= wire_w1659w(0) OR wire_w_lg_sink4_valid1661w(0);
+ wire_w174w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid162w165w168w171w(0) OR wire_w_lg_sink4_valid173w(0);
+ wire_w198w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid186w189w192w195w(0) OR wire_w_lg_sink4_valid197w(0);
+ wire_w222w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid210w213w216w219w(0) OR wire_w_lg_sink4_valid221w(0);
+ wire_w246w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid234w237w240w243w(0) OR wire_w_lg_sink4_valid245w(0);
+ wire_w_lg_w_lg_w1683w1686w1689w(0) <= wire_w_lg_w1683w1686w(0) OR wire_w_lg_sink5_valid1688w(0);
+ wire_w_lg_w_lg_w1708w1711w1714w(0) <= wire_w_lg_w1708w1711w(0) OR wire_w_lg_sink5_valid1713w(0);
+ wire_w_lg_w_lg_w1732w1735w1738w(0) <= wire_w_lg_w1732w1735w(0) OR wire_w_lg_sink5_valid1737w(0);
+ wire_w_lg_w_lg_w1756w1759w1762w(0) <= wire_w_lg_w1756w1759w(0) OR wire_w_lg_sink5_valid1761w(0);
+ wire_w_lg_w_lg_w1780w1783w1786w(0) <= wire_w_lg_w1780w1783w(0) OR wire_w_lg_sink5_valid1785w(0);
+ wire_w_lg_w_lg_w1804w1807w1810w(0) <= wire_w_lg_w1804w1807w(0) OR wire_w_lg_sink5_valid1809w(0);
+ wire_w_lg_w_lg_w1828w1831w1834w(0) <= wire_w_lg_w1828w1831w(0) OR wire_w_lg_sink5_valid1833w(0);
+ wire_w_lg_w_lg_w1852w1855w1858w(0) <= wire_w_lg_w1852w1855w(0) OR wire_w_lg_sink5_valid1857w(0);
+ wire_w_lg_w29w32w(0) <= wire_w29w(0) OR wire_w_lg_sink5_valid31w(0);
+ wire_w_lg_w270w273w(0) <= wire_w270w(0) OR wire_w_lg_sink5_valid272w(0);
+ wire_w_lg_w294w297w(0) <= wire_w294w(0) OR wire_w_lg_sink5_valid296w(0);
+ wire_w_lg_w318w321w(0) <= wire_w318w(0) OR wire_w_lg_sink5_valid320w(0);
+ wire_w_lg_w342w345w(0) <= wire_w342w(0) OR wire_w_lg_sink5_valid344w(0);
+ wire_w_lg_w366w369w(0) <= wire_w366w(0) OR wire_w_lg_sink5_valid368w(0);
+ wire_w_lg_w390w393w(0) <= wire_w390w(0) OR wire_w_lg_sink5_valid392w(0);
+ wire_w_lg_w414w417w(0) <= wire_w414w(0) OR wire_w_lg_sink5_valid416w(0);
+ wire_w_lg_w438w441w(0) <= wire_w438w(0) OR wire_w_lg_sink5_valid440w(0);
+ wire_w_lg_w462w465w(0) <= wire_w462w(0) OR wire_w_lg_sink5_valid464w(0);
+ wire_w_lg_w486w489w(0) <= wire_w486w(0) OR wire_w_lg_sink5_valid488w(0);
+ wire_w_lg_w54w57w(0) <= wire_w54w(0) OR wire_w_lg_sink5_valid56w(0);
+ wire_w_lg_w510w513w(0) <= wire_w510w(0) OR wire_w_lg_sink5_valid512w(0);
+ wire_w_lg_w534w537w(0) <= wire_w534w(0) OR wire_w_lg_sink5_valid536w(0);
+ wire_w_lg_w558w561w(0) <= wire_w558w(0) OR wire_w_lg_sink5_valid560w(0);
+ wire_w_lg_w582w585w(0) <= wire_w582w(0) OR wire_w_lg_sink5_valid584w(0);
+ wire_w_lg_w606w609w(0) <= wire_w606w(0) OR wire_w_lg_sink5_valid608w(0);
+ wire_w_lg_w630w633w(0) <= wire_w630w(0) OR wire_w_lg_sink5_valid632w(0);
+ wire_w_lg_w654w657w(0) <= wire_w654w(0) OR wire_w_lg_sink5_valid656w(0);
+ wire_w_lg_w678w681w(0) <= wire_w678w(0) OR wire_w_lg_sink5_valid680w(0);
+ wire_w_lg_w702w705w(0) <= wire_w702w(0) OR wire_w_lg_sink5_valid704w(0);
+ wire_w_lg_w726w729w(0) <= wire_w726w(0) OR wire_w_lg_sink5_valid728w(0);
+ wire_w_lg_w78w81w(0) <= wire_w78w(0) OR wire_w_lg_sink5_valid80w(0);
+ wire_w_lg_w750w753w(0) <= wire_w750w(0) OR wire_w_lg_sink5_valid752w(0);
+ wire_w_lg_w774w777w(0) <= wire_w774w(0) OR wire_w_lg_sink5_valid776w(0);
+ wire_w_lg_w798w801w(0) <= wire_w798w(0) OR wire_w_lg_sink5_valid800w(0);
+ wire_w_lg_w822w825w(0) <= wire_w822w(0) OR wire_w_lg_sink5_valid824w(0);
+ wire_w_lg_w846w849w(0) <= wire_w846w(0) OR wire_w_lg_sink5_valid848w(0);
+ wire_w_lg_w870w873w(0) <= wire_w870w(0) OR wire_w_lg_sink5_valid872w(0);
+ wire_w_lg_w894w897w(0) <= wire_w894w(0) OR wire_w_lg_sink5_valid896w(0);
+ wire_w_lg_w918w921w(0) <= wire_w918w(0) OR wire_w_lg_sink5_valid920w(0);
+ wire_w_lg_w942w945w(0) <= wire_w942w(0) OR wire_w_lg_sink5_valid944w(0);
+ wire_w_lg_w966w969w(0) <= wire_w966w(0) OR wire_w_lg_sink5_valid968w(0);
+ wire_w_lg_w102w105w(0) <= wire_w102w(0) OR wire_w_lg_sink5_valid104w(0);
+ wire_w_lg_w990w993w(0) <= wire_w990w(0) OR wire_w_lg_sink5_valid992w(0);
+ wire_w_lg_w_lg_w1011w1014w1017w(0) <= wire_w_lg_w1011w1014w(0) OR wire_w_lg_sink5_valid1016w(0);
+ wire_w_lg_w_lg_w1035w1038w1041w(0) <= wire_w_lg_w1035w1038w(0) OR wire_w_lg_sink5_valid1040w(0);
+ wire_w_lg_w_lg_w1059w1062w1065w(0) <= wire_w_lg_w1059w1062w(0) OR wire_w_lg_sink5_valid1064w(0);
+ wire_w_lg_w_lg_w1083w1086w1089w(0) <= wire_w_lg_w1083w1086w(0) OR wire_w_lg_sink5_valid1088w(0);
+ wire_w_lg_w_lg_w1107w1110w1113w(0) <= wire_w_lg_w1107w1110w(0) OR wire_w_lg_sink5_valid1112w(0);
+ wire_w_lg_w_lg_w1131w1134w1137w(0) <= wire_w_lg_w1131w1134w(0) OR wire_w_lg_sink5_valid1136w(0);
+ wire_w_lg_w_lg_w1155w1158w1161w(0) <= wire_w_lg_w1155w1158w(0) OR wire_w_lg_sink5_valid1160w(0);
+ wire_w_lg_w_lg_w1179w1182w1185w(0) <= wire_w_lg_w1179w1182w(0) OR wire_w_lg_sink5_valid1184w(0);
+ wire_w_lg_w_lg_w1203w1206w1209w(0) <= wire_w_lg_w1203w1206w(0) OR wire_w_lg_sink5_valid1208w(0);
+ wire_w_lg_w126w129w(0) <= wire_w126w(0) OR wire_w_lg_sink5_valid128w(0);
+ wire_w_lg_w_lg_w1227w1230w1233w(0) <= wire_w_lg_w1227w1230w(0) OR wire_w_lg_sink5_valid1232w(0);
+ wire_w_lg_w_lg_w1251w1254w1257w(0) <= wire_w_lg_w1251w1254w(0) OR wire_w_lg_sink5_valid1256w(0);
+ wire_w_lg_w_lg_w1275w1278w1281w(0) <= wire_w_lg_w1275w1278w(0) OR wire_w_lg_sink5_valid1280w(0);
+ wire_w_lg_w_lg_w1299w1302w1305w(0) <= wire_w_lg_w1299w1302w(0) OR wire_w_lg_sink5_valid1304w(0);
+ wire_w_lg_w_lg_w1323w1326w1329w(0) <= wire_w_lg_w1323w1326w(0) OR wire_w_lg_sink5_valid1328w(0);
+ wire_w_lg_w_lg_w1347w1350w1353w(0) <= wire_w_lg_w1347w1350w(0) OR wire_w_lg_sink5_valid1352w(0);
+ wire_w_lg_w_lg_w1371w1374w1377w(0) <= wire_w_lg_w1371w1374w(0) OR wire_w_lg_sink5_valid1376w(0);
+ wire_w_lg_w_lg_w1395w1398w1401w(0) <= wire_w_lg_w1395w1398w(0) OR wire_w_lg_sink5_valid1400w(0);
+ wire_w_lg_w_lg_w1419w1422w1425w(0) <= wire_w_lg_w1419w1422w(0) OR wire_w_lg_sink5_valid1424w(0);
+ wire_w_lg_w_lg_w1443w1446w1449w(0) <= wire_w_lg_w1443w1446w(0) OR wire_w_lg_sink5_valid1448w(0);
+ wire_w_lg_w150w153w(0) <= wire_w150w(0) OR wire_w_lg_sink5_valid152w(0);
+ wire_w_lg_w_lg_w1467w1470w1473w(0) <= wire_w_lg_w1467w1470w(0) OR wire_w_lg_sink5_valid1472w(0);
+ wire_w_lg_w_lg_w1491w1494w1497w(0) <= wire_w_lg_w1491w1494w(0) OR wire_w_lg_sink5_valid1496w(0);
+ wire_w_lg_w_lg_w1515w1518w1521w(0) <= wire_w_lg_w1515w1518w(0) OR wire_w_lg_sink5_valid1520w(0);
+ wire_w_lg_w_lg_w1539w1542w1545w(0) <= wire_w_lg_w1539w1542w(0) OR wire_w_lg_sink5_valid1544w(0);
+ wire_w_lg_w_lg_w1563w1566w1569w(0) <= wire_w_lg_w1563w1566w(0) OR wire_w_lg_sink5_valid1568w(0);
+ wire_w_lg_w_lg_w1587w1590w1593w(0) <= wire_w_lg_w1587w1590w(0) OR wire_w_lg_sink5_valid1592w(0);
+ wire_w_lg_w_lg_w1611w1614w1617w(0) <= wire_w_lg_w1611w1614w(0) OR wire_w_lg_sink5_valid1616w(0);
+ wire_w_lg_w_lg_w1635w1638w1641w(0) <= wire_w_lg_w1635w1638w(0) OR wire_w_lg_sink5_valid1640w(0);
+ wire_w_lg_w_lg_w1659w1662w1665w(0) <= wire_w_lg_w1659w1662w(0) OR wire_w_lg_sink5_valid1664w(0);
+ wire_w_lg_w174w177w(0) <= wire_w174w(0) OR wire_w_lg_sink5_valid176w(0);
+ wire_w_lg_w198w201w(0) <= wire_w198w(0) OR wire_w_lg_sink5_valid200w(0);
+ wire_w_lg_w222w225w(0) <= wire_w222w(0) OR wire_w_lg_sink5_valid224w(0);
+ wire_w_lg_w246w249w(0) <= wire_w246w(0) OR wire_w_lg_sink5_valid248w(0);
+ wire_w_lg_w_lg_w_lg_w1683w1686w1689w1692w(0) <= wire_w_lg_w_lg_w1683w1686w1689w(0) OR wire_w_lg_sink6_valid1691w(0);
+ wire_w_lg_w_lg_w_lg_w1708w1711w1714w1717w(0) <= wire_w_lg_w_lg_w1708w1711w1714w(0) OR wire_w_lg_sink6_valid1716w(0);
+ wire_w_lg_w_lg_w_lg_w1732w1735w1738w1741w(0) <= wire_w_lg_w_lg_w1732w1735w1738w(0) OR wire_w_lg_sink6_valid1740w(0);
+ wire_w_lg_w_lg_w_lg_w1756w1759w1762w1765w(0) <= wire_w_lg_w_lg_w1756w1759w1762w(0) OR wire_w_lg_sink6_valid1764w(0);
+ wire_w_lg_w_lg_w_lg_w1780w1783w1786w1789w(0) <= wire_w_lg_w_lg_w1780w1783w1786w(0) OR wire_w_lg_sink6_valid1788w(0);
+ wire_w_lg_w_lg_w_lg_w1804w1807w1810w1813w(0) <= wire_w_lg_w_lg_w1804w1807w1810w(0) OR wire_w_lg_sink6_valid1812w(0);
+ wire_w_lg_w_lg_w_lg_w1828w1831w1834w1837w(0) <= wire_w_lg_w_lg_w1828w1831w1834w(0) OR wire_w_lg_sink6_valid1836w(0);
+ wire_w_lg_w_lg_w_lg_w1852w1855w1858w1861w(0) <= wire_w_lg_w_lg_w1852w1855w1858w(0) OR wire_w_lg_sink6_valid1860w(0);
+ wire_w_lg_w_lg_w29w32w35w(0) <= wire_w_lg_w29w32w(0) OR wire_w_lg_sink6_valid34w(0);
+ wire_w_lg_w_lg_w270w273w276w(0) <= wire_w_lg_w270w273w(0) OR wire_w_lg_sink6_valid275w(0);
+ wire_w_lg_w_lg_w294w297w300w(0) <= wire_w_lg_w294w297w(0) OR wire_w_lg_sink6_valid299w(0);
+ wire_w_lg_w_lg_w318w321w324w(0) <= wire_w_lg_w318w321w(0) OR wire_w_lg_sink6_valid323w(0);
+ wire_w_lg_w_lg_w342w345w348w(0) <= wire_w_lg_w342w345w(0) OR wire_w_lg_sink6_valid347w(0);
+ wire_w_lg_w_lg_w366w369w372w(0) <= wire_w_lg_w366w369w(0) OR wire_w_lg_sink6_valid371w(0);
+ wire_w_lg_w_lg_w390w393w396w(0) <= wire_w_lg_w390w393w(0) OR wire_w_lg_sink6_valid395w(0);
+ wire_w_lg_w_lg_w414w417w420w(0) <= wire_w_lg_w414w417w(0) OR wire_w_lg_sink6_valid419w(0);
+ wire_w_lg_w_lg_w438w441w444w(0) <= wire_w_lg_w438w441w(0) OR wire_w_lg_sink6_valid443w(0);
+ wire_w_lg_w_lg_w462w465w468w(0) <= wire_w_lg_w462w465w(0) OR wire_w_lg_sink6_valid467w(0);
+ wire_w_lg_w_lg_w486w489w492w(0) <= wire_w_lg_w486w489w(0) OR wire_w_lg_sink6_valid491w(0);
+ wire_w_lg_w_lg_w54w57w60w(0) <= wire_w_lg_w54w57w(0) OR wire_w_lg_sink6_valid59w(0);
+ wire_w_lg_w_lg_w510w513w516w(0) <= wire_w_lg_w510w513w(0) OR wire_w_lg_sink6_valid515w(0);
+ wire_w_lg_w_lg_w534w537w540w(0) <= wire_w_lg_w534w537w(0) OR wire_w_lg_sink6_valid539w(0);
+ wire_w_lg_w_lg_w558w561w564w(0) <= wire_w_lg_w558w561w(0) OR wire_w_lg_sink6_valid563w(0);
+ wire_w_lg_w_lg_w582w585w588w(0) <= wire_w_lg_w582w585w(0) OR wire_w_lg_sink6_valid587w(0);
+ wire_w_lg_w_lg_w606w609w612w(0) <= wire_w_lg_w606w609w(0) OR wire_w_lg_sink6_valid611w(0);
+ wire_w_lg_w_lg_w630w633w636w(0) <= wire_w_lg_w630w633w(0) OR wire_w_lg_sink6_valid635w(0);
+ wire_w_lg_w_lg_w654w657w660w(0) <= wire_w_lg_w654w657w(0) OR wire_w_lg_sink6_valid659w(0);
+ wire_w_lg_w_lg_w678w681w684w(0) <= wire_w_lg_w678w681w(0) OR wire_w_lg_sink6_valid683w(0);
+ wire_w_lg_w_lg_w702w705w708w(0) <= wire_w_lg_w702w705w(0) OR wire_w_lg_sink6_valid707w(0);
+ wire_w_lg_w_lg_w726w729w732w(0) <= wire_w_lg_w726w729w(0) OR wire_w_lg_sink6_valid731w(0);
+ wire_w_lg_w_lg_w78w81w84w(0) <= wire_w_lg_w78w81w(0) OR wire_w_lg_sink6_valid83w(0);
+ wire_w_lg_w_lg_w750w753w756w(0) <= wire_w_lg_w750w753w(0) OR wire_w_lg_sink6_valid755w(0);
+ wire_w_lg_w_lg_w774w777w780w(0) <= wire_w_lg_w774w777w(0) OR wire_w_lg_sink6_valid779w(0);
+ wire_w_lg_w_lg_w798w801w804w(0) <= wire_w_lg_w798w801w(0) OR wire_w_lg_sink6_valid803w(0);
+ wire_w_lg_w_lg_w822w825w828w(0) <= wire_w_lg_w822w825w(0) OR wire_w_lg_sink6_valid827w(0);
+ wire_w_lg_w_lg_w846w849w852w(0) <= wire_w_lg_w846w849w(0) OR wire_w_lg_sink6_valid851w(0);
+ wire_w_lg_w_lg_w870w873w876w(0) <= wire_w_lg_w870w873w(0) OR wire_w_lg_sink6_valid875w(0);
+ wire_w_lg_w_lg_w894w897w900w(0) <= wire_w_lg_w894w897w(0) OR wire_w_lg_sink6_valid899w(0);
+ wire_w_lg_w_lg_w918w921w924w(0) <= wire_w_lg_w918w921w(0) OR wire_w_lg_sink6_valid923w(0);
+ wire_w_lg_w_lg_w942w945w948w(0) <= wire_w_lg_w942w945w(0) OR wire_w_lg_sink6_valid947w(0);
+ wire_w_lg_w_lg_w966w969w972w(0) <= wire_w_lg_w966w969w(0) OR wire_w_lg_sink6_valid971w(0);
+ wire_w_lg_w_lg_w102w105w108w(0) <= wire_w_lg_w102w105w(0) OR wire_w_lg_sink6_valid107w(0);
+ wire_w_lg_w_lg_w990w993w996w(0) <= wire_w_lg_w990w993w(0) OR wire_w_lg_sink6_valid995w(0);
+ wire_w_lg_w_lg_w_lg_w1011w1014w1017w1020w(0) <= wire_w_lg_w_lg_w1011w1014w1017w(0) OR wire_w_lg_sink6_valid1019w(0);
+ wire_w_lg_w_lg_w_lg_w1035w1038w1041w1044w(0) <= wire_w_lg_w_lg_w1035w1038w1041w(0) OR wire_w_lg_sink6_valid1043w(0);
+ wire_w_lg_w_lg_w_lg_w1059w1062w1065w1068w(0) <= wire_w_lg_w_lg_w1059w1062w1065w(0) OR wire_w_lg_sink6_valid1067w(0);
+ wire_w_lg_w_lg_w_lg_w1083w1086w1089w1092w(0) <= wire_w_lg_w_lg_w1083w1086w1089w(0) OR wire_w_lg_sink6_valid1091w(0);
+ wire_w_lg_w_lg_w_lg_w1107w1110w1113w1116w(0) <= wire_w_lg_w_lg_w1107w1110w1113w(0) OR wire_w_lg_sink6_valid1115w(0);
+ wire_w_lg_w_lg_w_lg_w1131w1134w1137w1140w(0) <= wire_w_lg_w_lg_w1131w1134w1137w(0) OR wire_w_lg_sink6_valid1139w(0);
+ wire_w_lg_w_lg_w_lg_w1155w1158w1161w1164w(0) <= wire_w_lg_w_lg_w1155w1158w1161w(0) OR wire_w_lg_sink6_valid1163w(0);
+ wire_w_lg_w_lg_w_lg_w1179w1182w1185w1188w(0) <= wire_w_lg_w_lg_w1179w1182w1185w(0) OR wire_w_lg_sink6_valid1187w(0);
+ wire_w_lg_w_lg_w_lg_w1203w1206w1209w1212w(0) <= wire_w_lg_w_lg_w1203w1206w1209w(0) OR wire_w_lg_sink6_valid1211w(0);
+ wire_w_lg_w_lg_w126w129w132w(0) <= wire_w_lg_w126w129w(0) OR wire_w_lg_sink6_valid131w(0);
+ wire_w_lg_w_lg_w_lg_w1227w1230w1233w1236w(0) <= wire_w_lg_w_lg_w1227w1230w1233w(0) OR wire_w_lg_sink6_valid1235w(0);
+ wire_w_lg_w_lg_w_lg_w1251w1254w1257w1260w(0) <= wire_w_lg_w_lg_w1251w1254w1257w(0) OR wire_w_lg_sink6_valid1259w(0);
+ wire_w_lg_w_lg_w_lg_w1275w1278w1281w1284w(0) <= wire_w_lg_w_lg_w1275w1278w1281w(0) OR wire_w_lg_sink6_valid1283w(0);
+ wire_w_lg_w_lg_w_lg_w1299w1302w1305w1308w(0) <= wire_w_lg_w_lg_w1299w1302w1305w(0) OR wire_w_lg_sink6_valid1307w(0);
+ wire_w_lg_w_lg_w_lg_w1323w1326w1329w1332w(0) <= wire_w_lg_w_lg_w1323w1326w1329w(0) OR wire_w_lg_sink6_valid1331w(0);
+ wire_w_lg_w_lg_w_lg_w1347w1350w1353w1356w(0) <= wire_w_lg_w_lg_w1347w1350w1353w(0) OR wire_w_lg_sink6_valid1355w(0);
+ wire_w_lg_w_lg_w_lg_w1371w1374w1377w1380w(0) <= wire_w_lg_w_lg_w1371w1374w1377w(0) OR wire_w_lg_sink6_valid1379w(0);
+ wire_w_lg_w_lg_w_lg_w1395w1398w1401w1404w(0) <= wire_w_lg_w_lg_w1395w1398w1401w(0) OR wire_w_lg_sink6_valid1403w(0);
+ wire_w_lg_w_lg_w_lg_w1419w1422w1425w1428w(0) <= wire_w_lg_w_lg_w1419w1422w1425w(0) OR wire_w_lg_sink6_valid1427w(0);
+ wire_w_lg_w_lg_w_lg_w1443w1446w1449w1452w(0) <= wire_w_lg_w_lg_w1443w1446w1449w(0) OR wire_w_lg_sink6_valid1451w(0);
+ wire_w_lg_w_lg_w150w153w156w(0) <= wire_w_lg_w150w153w(0) OR wire_w_lg_sink6_valid155w(0);
+ wire_w_lg_w_lg_w_lg_w1467w1470w1473w1476w(0) <= wire_w_lg_w_lg_w1467w1470w1473w(0) OR wire_w_lg_sink6_valid1475w(0);
+ wire_w_lg_w_lg_w_lg_w1491w1494w1497w1500w(0) <= wire_w_lg_w_lg_w1491w1494w1497w(0) OR wire_w_lg_sink6_valid1499w(0);
+ wire_w_lg_w_lg_w_lg_w1515w1518w1521w1524w(0) <= wire_w_lg_w_lg_w1515w1518w1521w(0) OR wire_w_lg_sink6_valid1523w(0);
+ wire_w_lg_w_lg_w_lg_w1539w1542w1545w1548w(0) <= wire_w_lg_w_lg_w1539w1542w1545w(0) OR wire_w_lg_sink6_valid1547w(0);
+ wire_w_lg_w_lg_w_lg_w1563w1566w1569w1572w(0) <= wire_w_lg_w_lg_w1563w1566w1569w(0) OR wire_w_lg_sink6_valid1571w(0);
+ wire_w_lg_w_lg_w_lg_w1587w1590w1593w1596w(0) <= wire_w_lg_w_lg_w1587w1590w1593w(0) OR wire_w_lg_sink6_valid1595w(0);
+ wire_w_lg_w_lg_w_lg_w1611w1614w1617w1620w(0) <= wire_w_lg_w_lg_w1611w1614w1617w(0) OR wire_w_lg_sink6_valid1619w(0);
+ wire_w_lg_w_lg_w_lg_w1635w1638w1641w1644w(0) <= wire_w_lg_w_lg_w1635w1638w1641w(0) OR wire_w_lg_sink6_valid1643w(0);
+ wire_w_lg_w_lg_w_lg_w1659w1662w1665w1668w(0) <= wire_w_lg_w_lg_w1659w1662w1665w(0) OR wire_w_lg_sink6_valid1667w(0);
+ wire_w_lg_w_lg_w174w177w180w(0) <= wire_w_lg_w174w177w(0) OR wire_w_lg_sink6_valid179w(0);
+ wire_w_lg_w_lg_w198w201w204w(0) <= wire_w_lg_w198w201w(0) OR wire_w_lg_sink6_valid203w(0);
+ wire_w_lg_w_lg_w222w225w228w(0) <= wire_w_lg_w222w225w(0) OR wire_w_lg_sink6_valid227w(0);
+ wire_w_lg_w_lg_w246w249w252w(0) <= wire_w_lg_w246w249w(0) OR wire_w_lg_sink6_valid251w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1683w1686w1689w1692w1695w(0) <= wire_w_lg_w_lg_w_lg_w1683w1686w1689w1692w(0) OR wire_w_lg_sink7_valid1694w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1708w1711w1714w1717w1720w(0) <= wire_w_lg_w_lg_w_lg_w1708w1711w1714w1717w(0) OR wire_w_lg_sink7_valid1719w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1732w1735w1738w1741w1744w(0) <= wire_w_lg_w_lg_w_lg_w1732w1735w1738w1741w(0) OR wire_w_lg_sink7_valid1743w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1756w1759w1762w1765w1768w(0) <= wire_w_lg_w_lg_w_lg_w1756w1759w1762w1765w(0) OR wire_w_lg_sink7_valid1767w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1780w1783w1786w1789w1792w(0) <= wire_w_lg_w_lg_w_lg_w1780w1783w1786w1789w(0) OR wire_w_lg_sink7_valid1791w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1804w1807w1810w1813w1816w(0) <= wire_w_lg_w_lg_w_lg_w1804w1807w1810w1813w(0) OR wire_w_lg_sink7_valid1815w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1828w1831w1834w1837w1840w(0) <= wire_w_lg_w_lg_w_lg_w1828w1831w1834w1837w(0) OR wire_w_lg_sink7_valid1839w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1852w1855w1858w1861w1864w(0) <= wire_w_lg_w_lg_w_lg_w1852w1855w1858w1861w(0) OR wire_w_lg_sink7_valid1863w(0);
+ wire_w_lg_w_lg_w_lg_w29w32w35w38w(0) <= wire_w_lg_w_lg_w29w32w35w(0) OR wire_w_lg_sink7_valid37w(0);
+ wire_w_lg_w_lg_w_lg_w270w273w276w279w(0) <= wire_w_lg_w_lg_w270w273w276w(0) OR wire_w_lg_sink7_valid278w(0);
+ wire_w_lg_w_lg_w_lg_w294w297w300w303w(0) <= wire_w_lg_w_lg_w294w297w300w(0) OR wire_w_lg_sink7_valid302w(0);
+ wire_w_lg_w_lg_w_lg_w318w321w324w327w(0) <= wire_w_lg_w_lg_w318w321w324w(0) OR wire_w_lg_sink7_valid326w(0);
+ wire_w_lg_w_lg_w_lg_w342w345w348w351w(0) <= wire_w_lg_w_lg_w342w345w348w(0) OR wire_w_lg_sink7_valid350w(0);
+ wire_w_lg_w_lg_w_lg_w366w369w372w375w(0) <= wire_w_lg_w_lg_w366w369w372w(0) OR wire_w_lg_sink7_valid374w(0);
+ wire_w_lg_w_lg_w_lg_w390w393w396w399w(0) <= wire_w_lg_w_lg_w390w393w396w(0) OR wire_w_lg_sink7_valid398w(0);
+ wire_w_lg_w_lg_w_lg_w414w417w420w423w(0) <= wire_w_lg_w_lg_w414w417w420w(0) OR wire_w_lg_sink7_valid422w(0);
+ wire_w_lg_w_lg_w_lg_w438w441w444w447w(0) <= wire_w_lg_w_lg_w438w441w444w(0) OR wire_w_lg_sink7_valid446w(0);
+ wire_w_lg_w_lg_w_lg_w462w465w468w471w(0) <= wire_w_lg_w_lg_w462w465w468w(0) OR wire_w_lg_sink7_valid470w(0);
+ wire_w_lg_w_lg_w_lg_w486w489w492w495w(0) <= wire_w_lg_w_lg_w486w489w492w(0) OR wire_w_lg_sink7_valid494w(0);
+ wire_w_lg_w_lg_w_lg_w54w57w60w63w(0) <= wire_w_lg_w_lg_w54w57w60w(0) OR wire_w_lg_sink7_valid62w(0);
+ wire_w_lg_w_lg_w_lg_w510w513w516w519w(0) <= wire_w_lg_w_lg_w510w513w516w(0) OR wire_w_lg_sink7_valid518w(0);
+ wire_w_lg_w_lg_w_lg_w534w537w540w543w(0) <= wire_w_lg_w_lg_w534w537w540w(0) OR wire_w_lg_sink7_valid542w(0);
+ wire_w_lg_w_lg_w_lg_w558w561w564w567w(0) <= wire_w_lg_w_lg_w558w561w564w(0) OR wire_w_lg_sink7_valid566w(0);
+ wire_w_lg_w_lg_w_lg_w582w585w588w591w(0) <= wire_w_lg_w_lg_w582w585w588w(0) OR wire_w_lg_sink7_valid590w(0);
+ wire_w_lg_w_lg_w_lg_w606w609w612w615w(0) <= wire_w_lg_w_lg_w606w609w612w(0) OR wire_w_lg_sink7_valid614w(0);
+ wire_w_lg_w_lg_w_lg_w630w633w636w639w(0) <= wire_w_lg_w_lg_w630w633w636w(0) OR wire_w_lg_sink7_valid638w(0);
+ wire_w_lg_w_lg_w_lg_w654w657w660w663w(0) <= wire_w_lg_w_lg_w654w657w660w(0) OR wire_w_lg_sink7_valid662w(0);
+ wire_w_lg_w_lg_w_lg_w678w681w684w687w(0) <= wire_w_lg_w_lg_w678w681w684w(0) OR wire_w_lg_sink7_valid686w(0);
+ wire_w_lg_w_lg_w_lg_w702w705w708w711w(0) <= wire_w_lg_w_lg_w702w705w708w(0) OR wire_w_lg_sink7_valid710w(0);
+ wire_w_lg_w_lg_w_lg_w726w729w732w735w(0) <= wire_w_lg_w_lg_w726w729w732w(0) OR wire_w_lg_sink7_valid734w(0);
+ wire_w_lg_w_lg_w_lg_w78w81w84w87w(0) <= wire_w_lg_w_lg_w78w81w84w(0) OR wire_w_lg_sink7_valid86w(0);
+ wire_w_lg_w_lg_w_lg_w750w753w756w759w(0) <= wire_w_lg_w_lg_w750w753w756w(0) OR wire_w_lg_sink7_valid758w(0);
+ wire_w_lg_w_lg_w_lg_w774w777w780w783w(0) <= wire_w_lg_w_lg_w774w777w780w(0) OR wire_w_lg_sink7_valid782w(0);
+ wire_w_lg_w_lg_w_lg_w798w801w804w807w(0) <= wire_w_lg_w_lg_w798w801w804w(0) OR wire_w_lg_sink7_valid806w(0);
+ wire_w_lg_w_lg_w_lg_w822w825w828w831w(0) <= wire_w_lg_w_lg_w822w825w828w(0) OR wire_w_lg_sink7_valid830w(0);
+ wire_w_lg_w_lg_w_lg_w846w849w852w855w(0) <= wire_w_lg_w_lg_w846w849w852w(0) OR wire_w_lg_sink7_valid854w(0);
+ wire_w_lg_w_lg_w_lg_w870w873w876w879w(0) <= wire_w_lg_w_lg_w870w873w876w(0) OR wire_w_lg_sink7_valid878w(0);
+ wire_w_lg_w_lg_w_lg_w894w897w900w903w(0) <= wire_w_lg_w_lg_w894w897w900w(0) OR wire_w_lg_sink7_valid902w(0);
+ wire_w_lg_w_lg_w_lg_w918w921w924w927w(0) <= wire_w_lg_w_lg_w918w921w924w(0) OR wire_w_lg_sink7_valid926w(0);
+ wire_w_lg_w_lg_w_lg_w942w945w948w951w(0) <= wire_w_lg_w_lg_w942w945w948w(0) OR wire_w_lg_sink7_valid950w(0);
+ wire_w_lg_w_lg_w_lg_w966w969w972w975w(0) <= wire_w_lg_w_lg_w966w969w972w(0) OR wire_w_lg_sink7_valid974w(0);
+ wire_w_lg_w_lg_w_lg_w102w105w108w111w(0) <= wire_w_lg_w_lg_w102w105w108w(0) OR wire_w_lg_sink7_valid110w(0);
+ wire_w_lg_w_lg_w_lg_w990w993w996w999w(0) <= wire_w_lg_w_lg_w990w993w996w(0) OR wire_w_lg_sink7_valid998w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1011w1014w1017w1020w1023w(0) <= wire_w_lg_w_lg_w_lg_w1011w1014w1017w1020w(0) OR wire_w_lg_sink7_valid1022w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1035w1038w1041w1044w1047w(0) <= wire_w_lg_w_lg_w_lg_w1035w1038w1041w1044w(0) OR wire_w_lg_sink7_valid1046w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1059w1062w1065w1068w1071w(0) <= wire_w_lg_w_lg_w_lg_w1059w1062w1065w1068w(0) OR wire_w_lg_sink7_valid1070w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1083w1086w1089w1092w1095w(0) <= wire_w_lg_w_lg_w_lg_w1083w1086w1089w1092w(0) OR wire_w_lg_sink7_valid1094w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1107w1110w1113w1116w1119w(0) <= wire_w_lg_w_lg_w_lg_w1107w1110w1113w1116w(0) OR wire_w_lg_sink7_valid1118w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1131w1134w1137w1140w1143w(0) <= wire_w_lg_w_lg_w_lg_w1131w1134w1137w1140w(0) OR wire_w_lg_sink7_valid1142w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1155w1158w1161w1164w1167w(0) <= wire_w_lg_w_lg_w_lg_w1155w1158w1161w1164w(0) OR wire_w_lg_sink7_valid1166w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1179w1182w1185w1188w1191w(0) <= wire_w_lg_w_lg_w_lg_w1179w1182w1185w1188w(0) OR wire_w_lg_sink7_valid1190w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1203w1206w1209w1212w1215w(0) <= wire_w_lg_w_lg_w_lg_w1203w1206w1209w1212w(0) OR wire_w_lg_sink7_valid1214w(0);
+ wire_w_lg_w_lg_w_lg_w126w129w132w135w(0) <= wire_w_lg_w_lg_w126w129w132w(0) OR wire_w_lg_sink7_valid134w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1227w1230w1233w1236w1239w(0) <= wire_w_lg_w_lg_w_lg_w1227w1230w1233w1236w(0) OR wire_w_lg_sink7_valid1238w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1251w1254w1257w1260w1263w(0) <= wire_w_lg_w_lg_w_lg_w1251w1254w1257w1260w(0) OR wire_w_lg_sink7_valid1262w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1275w1278w1281w1284w1287w(0) <= wire_w_lg_w_lg_w_lg_w1275w1278w1281w1284w(0) OR wire_w_lg_sink7_valid1286w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1299w1302w1305w1308w1311w(0) <= wire_w_lg_w_lg_w_lg_w1299w1302w1305w1308w(0) OR wire_w_lg_sink7_valid1310w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1323w1326w1329w1332w1335w(0) <= wire_w_lg_w_lg_w_lg_w1323w1326w1329w1332w(0) OR wire_w_lg_sink7_valid1334w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1347w1350w1353w1356w1359w(0) <= wire_w_lg_w_lg_w_lg_w1347w1350w1353w1356w(0) OR wire_w_lg_sink7_valid1358w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1371w1374w1377w1380w1383w(0) <= wire_w_lg_w_lg_w_lg_w1371w1374w1377w1380w(0) OR wire_w_lg_sink7_valid1382w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1395w1398w1401w1404w1407w(0) <= wire_w_lg_w_lg_w_lg_w1395w1398w1401w1404w(0) OR wire_w_lg_sink7_valid1406w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1419w1422w1425w1428w1431w(0) <= wire_w_lg_w_lg_w_lg_w1419w1422w1425w1428w(0) OR wire_w_lg_sink7_valid1430w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1443w1446w1449w1452w1455w(0) <= wire_w_lg_w_lg_w_lg_w1443w1446w1449w1452w(0) OR wire_w_lg_sink7_valid1454w(0);
+ wire_w_lg_w_lg_w_lg_w150w153w156w159w(0) <= wire_w_lg_w_lg_w150w153w156w(0) OR wire_w_lg_sink7_valid158w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1467w1470w1473w1476w1479w(0) <= wire_w_lg_w_lg_w_lg_w1467w1470w1473w1476w(0) OR wire_w_lg_sink7_valid1478w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1491w1494w1497w1500w1503w(0) <= wire_w_lg_w_lg_w_lg_w1491w1494w1497w1500w(0) OR wire_w_lg_sink7_valid1502w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1515w1518w1521w1524w1527w(0) <= wire_w_lg_w_lg_w_lg_w1515w1518w1521w1524w(0) OR wire_w_lg_sink7_valid1526w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1539w1542w1545w1548w1551w(0) <= wire_w_lg_w_lg_w_lg_w1539w1542w1545w1548w(0) OR wire_w_lg_sink7_valid1550w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1563w1566w1569w1572w1575w(0) <= wire_w_lg_w_lg_w_lg_w1563w1566w1569w1572w(0) OR wire_w_lg_sink7_valid1574w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1587w1590w1593w1596w1599w(0) <= wire_w_lg_w_lg_w_lg_w1587w1590w1593w1596w(0) OR wire_w_lg_sink7_valid1598w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1611w1614w1617w1620w1623w(0) <= wire_w_lg_w_lg_w_lg_w1611w1614w1617w1620w(0) OR wire_w_lg_sink7_valid1622w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1635w1638w1641w1644w1647w(0) <= wire_w_lg_w_lg_w_lg_w1635w1638w1641w1644w(0) OR wire_w_lg_sink7_valid1646w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_w1659w1662w1665w1668w1671w(0) <= wire_w_lg_w_lg_w_lg_w1659w1662w1665w1668w(0) OR wire_w_lg_sink7_valid1670w(0);
+ wire_w_lg_w_lg_w_lg_w174w177w180w183w(0) <= wire_w_lg_w_lg_w174w177w180w(0) OR wire_w_lg_sink7_valid182w(0);
+ wire_w_lg_w_lg_w_lg_w198w201w204w207w(0) <= wire_w_lg_w_lg_w198w201w204w(0) OR wire_w_lg_sink7_valid206w(0);
+ wire_w_lg_w_lg_w_lg_w222w225w228w231w(0) <= wire_w_lg_w_lg_w222w225w228w(0) OR wire_w_lg_sink7_valid230w(0);
+ wire_w_lg_w_lg_w_lg_w246w249w252w255w(0) <= wire_w_lg_w_lg_w246w249w252w(0) OR wire_w_lg_sink7_valid254w(0);
+ s_wire_altera_merlin_multiplexer_0002_wideor1_31_dataout <= (((((((sink0_valid OR sink1_valid) OR sink2_valid) OR sink3_valid) OR sink4_valid) OR sink5_valid) OR sink6_valid) OR sink7_valid);
+ sink0_ready <= (sink0_valid AND src_ready);
+ sink1_ready <= (sink1_valid AND src_ready);
+ sink2_ready <= (sink2_valid AND src_ready);
+ sink3_ready <= (sink3_valid AND src_ready);
+ sink4_ready <= (sink4_valid AND src_ready);
+ sink5_ready <= (sink5_valid AND src_ready);
+ sink6_ready <= (sink6_valid AND src_ready);
+ sink7_ready <= (sink7_valid AND src_ready);
+ src_channel <= ( wire_w_lg_w_lg_w_lg_w_lg_w1852w1855w1858w1861w1864w & wire_w_lg_w_lg_w_lg_w_lg_w1828w1831w1834w1837w1840w & wire_w_lg_w_lg_w_lg_w_lg_w1804w1807w1810w1813w1816w & wire_w_lg_w_lg_w_lg_w_lg_w1780w1783w1786w1789w1792w & wire_w_lg_w_lg_w_lg_w_lg_w1756w1759w1762w1765w1768w & wire_w_lg_w_lg_w_lg_w_lg_w1732w1735w1738w1741w1744w & wire_w_lg_w_lg_w_lg_w_lg_w1708w1711w1714w1717w1720w & wire_w_lg_w_lg_w_lg_w_lg_w1683w1686w1689w1692w1695w);
+ src_data <= ( wire_w_lg_w_lg_w_lg_w_lg_w1659w1662w1665w1668w1671w & wire_w_lg_w_lg_w_lg_w_lg_w1635w1638w1641w1644w1647w & wire_w_lg_w_lg_w_lg_w_lg_w1611w1614w1617w1620w1623w & wire_w_lg_w_lg_w_lg_w_lg_w1587w1590w1593w1596w1599w & wire_w_lg_w_lg_w_lg_w_lg_w1563w1566w1569w1572w1575w & wire_w_lg_w_lg_w_lg_w_lg_w1539w1542w1545w1548w1551w & wire_w_lg_w_lg_w_lg_w_lg_w1515w1518w1521w1524w1527w & wire_w_lg_w_lg_w_lg_w_lg_w1491w1494w1497w1500w1503w & wire_w_lg_w_lg_w_lg_w_lg_w1467w1470w1473w1476w1479w & wire_w_lg_w_lg_w_lg_w_lg_w1443w1446w1449w1452w1455w & wire_w_lg_w_lg_w_lg_w_lg_w1419w1422w1425w1428w1431w & wire_w_lg_w_lg_w_lg_w_lg_w1395w1398w1401w1404w1407w & wire_w_lg_w_lg_w_lg_w_lg_w1371w1374w1377w1380w1383w & wire_w_lg_w_lg_w_lg_w_lg_w1347w1350w1353w1356w1359w & wire_w_lg_w_lg_w_lg_w_lg_w1323w1326w1329w1332w1335w & wire_w_lg_w_lg_w_lg_w_lg_w1299w1302w1305w1308w1311w & wire_w_lg_w_lg_w_lg_w_lg_w1275w1278w1281w1284w1287w & wire_w_lg_w_lg_w_lg_w_lg_w1251w1254w1257w1260w1263w & wire_w_lg_w_lg_w_lg_w_lg_w1227w1230w1233w1236w1239w & wire_w_lg_w_lg_w_lg_w_lg_w1203w1206w1209w1212w1215w & wire_w_lg_w_lg_w_lg_w_lg_w1179w1182w1185w1188w1191w & wire_w_lg_w_lg_w_lg_w_lg_w1155w1158w1161w1164w1167w & wire_w_lg_w_lg_w_lg_w_lg_w1131w1134w1137w1140w1143w & wire_w_lg_w_lg_w_lg_w_lg_w1107w1110w1113w1116w1119w & wire_w_lg_w_lg_w_lg_w_lg_w1083w1086w1089w1092w1095w & wire_w_lg_w_lg_w_lg_w_lg_w1059w1062w1065w1068w1071w & wire_w_lg_w_lg_w_lg_w_lg_w1035w1038w1041w1044w1047w & wire_w_lg_w_lg_w_lg_w_lg_w1011w1014w1017w1020w1023w & wire_w_lg_w_lg_w_lg_w990w993w996w999w & wire_w_lg_w_lg_w_lg_w966w969w972w975w & wire_w_lg_w_lg_w_lg_w942w945w948w951w & wire_w_lg_w_lg_w_lg_w918w921w924w927w & wire_w_lg_w_lg_w_lg_w894w897w900w903w & wire_w_lg_w_lg_w_lg_w870w873w876w879w & wire_w_lg_w_lg_w_lg_w846w849w852w855w & wire_w_lg_w_lg_w_lg_w822w825w828w831w & wire_w_lg_w_lg_w_lg_w798w801w804w807w & wire_w_lg_w_lg_w_lg_w774w777w780w783w & wire_w_lg_w_lg_w_lg_w750w753w756w759w & wire_w_lg_w_lg_w_lg_w726w729w732w735w & wire_w_lg_w_lg_w_lg_w702w705w708w711w & wire_w_lg_w_lg_w_lg_w678w681w684w687w
+ & wire_w_lg_w_lg_w_lg_w654w657w660w663w & wire_w_lg_w_lg_w_lg_w630w633w636w639w & wire_w_lg_w_lg_w_lg_w606w609w612w615w & wire_w_lg_w_lg_w_lg_w582w585w588w591w & wire_w_lg_w_lg_w_lg_w558w561w564w567w & wire_w_lg_w_lg_w_lg_w534w537w540w543w & wire_w_lg_w_lg_w_lg_w510w513w516w519w & wire_w_lg_w_lg_w_lg_w486w489w492w495w & wire_w_lg_w_lg_w_lg_w462w465w468w471w & wire_w_lg_w_lg_w_lg_w438w441w444w447w & wire_w_lg_w_lg_w_lg_w414w417w420w423w & wire_w_lg_w_lg_w_lg_w390w393w396w399w & wire_w_lg_w_lg_w_lg_w366w369w372w375w & wire_w_lg_w_lg_w_lg_w342w345w348w351w & wire_w_lg_w_lg_w_lg_w318w321w324w327w & wire_w_lg_w_lg_w_lg_w294w297w300w303w & wire_w_lg_w_lg_w_lg_w270w273w276w279w & wire_w_lg_w_lg_w_lg_w246w249w252w255w & wire_w_lg_w_lg_w_lg_w222w225w228w231w & wire_w_lg_w_lg_w_lg_w198w201w204w207w & wire_w_lg_w_lg_w_lg_w174w177w180w183w & wire_w_lg_w_lg_w_lg_w150w153w156w159w & wire_w_lg_w_lg_w_lg_w126w129w132w135w & wire_w_lg_w_lg_w_lg_w102w105w108w111w & wire_w_lg_w_lg_w_lg_w78w81w84w87w & wire_w_lg_w_lg_w_lg_w54w57w60w63w & wire_w_lg_w_lg_w_lg_w29w32w35w38w);
+ src_endofpacket <= ((((((((sink0_valid AND sink0_endofpacket) OR (sink1_valid AND sink1_endofpacket)) OR (sink2_valid AND sink2_endofpacket)) OR (sink3_valid AND sink3_endofpacket)) OR (sink4_valid AND sink4_endofpacket)) OR (sink5_valid AND sink5_endofpacket)) OR (sink6_valid AND sink6_endofpacket)) OR (sink7_valid AND sink7_endofpacket));
+ src_startofpacket <= ((((((((sink0_valid AND sink0_startofpacket) OR (sink1_valid AND sink1_startofpacket)) OR (sink2_valid AND sink2_startofpacket)) OR (sink3_valid AND sink3_startofpacket)) OR (sink4_valid AND sink4_startofpacket)) OR (sink5_valid AND sink5_startofpacket)) OR (sink6_valid AND sink6_startofpacket)) OR (sink7_valid AND sink7_startofpacket));
+ src_valid <= s_wire_altera_merlin_multiplexer_0002_wideor1_31_dataout;
+ wire_w_sink0_channel_range1673w(0) <= sink0_channel(0);
+ wire_w_sink0_channel_range1698w(0) <= sink0_channel(1);
+ wire_w_sink0_channel_range1722w(0) <= sink0_channel(2);
+ wire_w_sink0_channel_range1746w(0) <= sink0_channel(3);
+ wire_w_sink0_channel_range1770w(0) <= sink0_channel(4);
+ wire_w_sink0_channel_range1794w(0) <= sink0_channel(5);
+ wire_w_sink0_channel_range1818w(0) <= sink0_channel(6);
+ wire_w_sink0_channel_range1842w(0) <= sink0_channel(7);
+ wire_w_sink0_data_range16w(0) <= sink0_data(0);
+ wire_w_sink0_data_range257w(0) <= sink0_data(10);
+ wire_w_sink0_data_range281w(0) <= sink0_data(11);
+ wire_w_sink0_data_range305w(0) <= sink0_data(12);
+ wire_w_sink0_data_range329w(0) <= sink0_data(13);
+ wire_w_sink0_data_range353w(0) <= sink0_data(14);
+ wire_w_sink0_data_range377w(0) <= sink0_data(15);
+ wire_w_sink0_data_range401w(0) <= sink0_data(16);
+ wire_w_sink0_data_range425w(0) <= sink0_data(17);
+ wire_w_sink0_data_range449w(0) <= sink0_data(18);
+ wire_w_sink0_data_range473w(0) <= sink0_data(19);
+ wire_w_sink0_data_range41w(0) <= sink0_data(1);
+ wire_w_sink0_data_range497w(0) <= sink0_data(20);
+ wire_w_sink0_data_range521w(0) <= sink0_data(21);
+ wire_w_sink0_data_range545w(0) <= sink0_data(22);
+ wire_w_sink0_data_range569w(0) <= sink0_data(23);
+ wire_w_sink0_data_range593w(0) <= sink0_data(24);
+ wire_w_sink0_data_range617w(0) <= sink0_data(25);
+ wire_w_sink0_data_range641w(0) <= sink0_data(26);
+ wire_w_sink0_data_range665w(0) <= sink0_data(27);
+ wire_w_sink0_data_range689w(0) <= sink0_data(28);
+ wire_w_sink0_data_range713w(0) <= sink0_data(29);
+ wire_w_sink0_data_range65w(0) <= sink0_data(2);
+ wire_w_sink0_data_range737w(0) <= sink0_data(30);
+ wire_w_sink0_data_range761w(0) <= sink0_data(31);
+ wire_w_sink0_data_range785w(0) <= sink0_data(32);
+ wire_w_sink0_data_range809w(0) <= sink0_data(33);
+ wire_w_sink0_data_range833w(0) <= sink0_data(34);
+ wire_w_sink0_data_range857w(0) <= sink0_data(35);
+ wire_w_sink0_data_range881w(0) <= sink0_data(36);
+ wire_w_sink0_data_range905w(0) <= sink0_data(37);
+ wire_w_sink0_data_range929w(0) <= sink0_data(38);
+ wire_w_sink0_data_range953w(0) <= sink0_data(39);
+ wire_w_sink0_data_range89w(0) <= sink0_data(3);
+ wire_w_sink0_data_range977w(0) <= sink0_data(40);
+ wire_w_sink0_data_range1001w(0) <= sink0_data(41);
+ wire_w_sink0_data_range1025w(0) <= sink0_data(42);
+ wire_w_sink0_data_range1049w(0) <= sink0_data(43);
+ wire_w_sink0_data_range1073w(0) <= sink0_data(44);
+ wire_w_sink0_data_range1097w(0) <= sink0_data(45);
+ wire_w_sink0_data_range1121w(0) <= sink0_data(46);
+ wire_w_sink0_data_range1145w(0) <= sink0_data(47);
+ wire_w_sink0_data_range1169w(0) <= sink0_data(48);
+ wire_w_sink0_data_range1193w(0) <= sink0_data(49);
+ wire_w_sink0_data_range113w(0) <= sink0_data(4);
+ wire_w_sink0_data_range1217w(0) <= sink0_data(50);
+ wire_w_sink0_data_range1241w(0) <= sink0_data(51);
+ wire_w_sink0_data_range1265w(0) <= sink0_data(52);
+ wire_w_sink0_data_range1289w(0) <= sink0_data(53);
+ wire_w_sink0_data_range1313w(0) <= sink0_data(54);
+ wire_w_sink0_data_range1337w(0) <= sink0_data(55);
+ wire_w_sink0_data_range1361w(0) <= sink0_data(56);
+ wire_w_sink0_data_range1385w(0) <= sink0_data(57);
+ wire_w_sink0_data_range1409w(0) <= sink0_data(58);
+ wire_w_sink0_data_range1433w(0) <= sink0_data(59);
+ wire_w_sink0_data_range137w(0) <= sink0_data(5);
+ wire_w_sink0_data_range1457w(0) <= sink0_data(60);
+ wire_w_sink0_data_range1481w(0) <= sink0_data(61);
+ wire_w_sink0_data_range1505w(0) <= sink0_data(62);
+ wire_w_sink0_data_range1529w(0) <= sink0_data(63);
+ wire_w_sink0_data_range1553w(0) <= sink0_data(64);
+ wire_w_sink0_data_range1577w(0) <= sink0_data(65);
+ wire_w_sink0_data_range1601w(0) <= sink0_data(66);
+ wire_w_sink0_data_range1625w(0) <= sink0_data(67);
+ wire_w_sink0_data_range1649w(0) <= sink0_data(68);
+ wire_w_sink0_data_range161w(0) <= sink0_data(6);
+ wire_w_sink0_data_range185w(0) <= sink0_data(7);
+ wire_w_sink0_data_range209w(0) <= sink0_data(8);
+ wire_w_sink0_data_range233w(0) <= sink0_data(9);
+ wire_w_sink1_channel_range1675w(0) <= sink1_channel(0);
+ wire_w_sink1_channel_range1700w(0) <= sink1_channel(1);
+ wire_w_sink1_channel_range1724w(0) <= sink1_channel(2);
+ wire_w_sink1_channel_range1748w(0) <= sink1_channel(3);
+ wire_w_sink1_channel_range1772w(0) <= sink1_channel(4);
+ wire_w_sink1_channel_range1796w(0) <= sink1_channel(5);
+ wire_w_sink1_channel_range1820w(0) <= sink1_channel(6);
+ wire_w_sink1_channel_range1844w(0) <= sink1_channel(7);
+ wire_w_sink1_data_range18w(0) <= sink1_data(0);
+ wire_w_sink1_data_range259w(0) <= sink1_data(10);
+ wire_w_sink1_data_range283w(0) <= sink1_data(11);
+ wire_w_sink1_data_range307w(0) <= sink1_data(12);
+ wire_w_sink1_data_range331w(0) <= sink1_data(13);
+ wire_w_sink1_data_range355w(0) <= sink1_data(14);
+ wire_w_sink1_data_range379w(0) <= sink1_data(15);
+ wire_w_sink1_data_range403w(0) <= sink1_data(16);
+ wire_w_sink1_data_range427w(0) <= sink1_data(17);
+ wire_w_sink1_data_range451w(0) <= sink1_data(18);
+ wire_w_sink1_data_range475w(0) <= sink1_data(19);
+ wire_w_sink1_data_range43w(0) <= sink1_data(1);
+ wire_w_sink1_data_range499w(0) <= sink1_data(20);
+ wire_w_sink1_data_range523w(0) <= sink1_data(21);
+ wire_w_sink1_data_range547w(0) <= sink1_data(22);
+ wire_w_sink1_data_range571w(0) <= sink1_data(23);
+ wire_w_sink1_data_range595w(0) <= sink1_data(24);
+ wire_w_sink1_data_range619w(0) <= sink1_data(25);
+ wire_w_sink1_data_range643w(0) <= sink1_data(26);
+ wire_w_sink1_data_range667w(0) <= sink1_data(27);
+ wire_w_sink1_data_range691w(0) <= sink1_data(28);
+ wire_w_sink1_data_range715w(0) <= sink1_data(29);
+ wire_w_sink1_data_range67w(0) <= sink1_data(2);
+ wire_w_sink1_data_range739w(0) <= sink1_data(30);
+ wire_w_sink1_data_range763w(0) <= sink1_data(31);
+ wire_w_sink1_data_range787w(0) <= sink1_data(32);
+ wire_w_sink1_data_range811w(0) <= sink1_data(33);
+ wire_w_sink1_data_range835w(0) <= sink1_data(34);
+ wire_w_sink1_data_range859w(0) <= sink1_data(35);
+ wire_w_sink1_data_range883w(0) <= sink1_data(36);
+ wire_w_sink1_data_range907w(0) <= sink1_data(37);
+ wire_w_sink1_data_range931w(0) <= sink1_data(38);
+ wire_w_sink1_data_range955w(0) <= sink1_data(39);
+ wire_w_sink1_data_range91w(0) <= sink1_data(3);
+ wire_w_sink1_data_range979w(0) <= sink1_data(40);
+ wire_w_sink1_data_range1003w(0) <= sink1_data(41);
+ wire_w_sink1_data_range1027w(0) <= sink1_data(42);
+ wire_w_sink1_data_range1051w(0) <= sink1_data(43);
+ wire_w_sink1_data_range1075w(0) <= sink1_data(44);
+ wire_w_sink1_data_range1099w(0) <= sink1_data(45);
+ wire_w_sink1_data_range1123w(0) <= sink1_data(46);
+ wire_w_sink1_data_range1147w(0) <= sink1_data(47);
+ wire_w_sink1_data_range1171w(0) <= sink1_data(48);
+ wire_w_sink1_data_range1195w(0) <= sink1_data(49);
+ wire_w_sink1_data_range115w(0) <= sink1_data(4);
+ wire_w_sink1_data_range1219w(0) <= sink1_data(50);
+ wire_w_sink1_data_range1243w(0) <= sink1_data(51);
+ wire_w_sink1_data_range1267w(0) <= sink1_data(52);
+ wire_w_sink1_data_range1291w(0) <= sink1_data(53);
+ wire_w_sink1_data_range1315w(0) <= sink1_data(54);
+ wire_w_sink1_data_range1339w(0) <= sink1_data(55);
+ wire_w_sink1_data_range1363w(0) <= sink1_data(56);
+ wire_w_sink1_data_range1387w(0) <= sink1_data(57);
+ wire_w_sink1_data_range1411w(0) <= sink1_data(58);
+ wire_w_sink1_data_range1435w(0) <= sink1_data(59);
+ wire_w_sink1_data_range139w(0) <= sink1_data(5);
+ wire_w_sink1_data_range1459w(0) <= sink1_data(60);
+ wire_w_sink1_data_range1483w(0) <= sink1_data(61);
+ wire_w_sink1_data_range1507w(0) <= sink1_data(62);
+ wire_w_sink1_data_range1531w(0) <= sink1_data(63);
+ wire_w_sink1_data_range1555w(0) <= sink1_data(64);
+ wire_w_sink1_data_range1579w(0) <= sink1_data(65);
+ wire_w_sink1_data_range1603w(0) <= sink1_data(66);
+ wire_w_sink1_data_range1627w(0) <= sink1_data(67);
+ wire_w_sink1_data_range1651w(0) <= sink1_data(68);
+ wire_w_sink1_data_range163w(0) <= sink1_data(6);
+ wire_w_sink1_data_range187w(0) <= sink1_data(7);
+ wire_w_sink1_data_range211w(0) <= sink1_data(8);
+ wire_w_sink1_data_range235w(0) <= sink1_data(9);
+ wire_w_sink2_channel_range1678w(0) <= sink2_channel(0);
+ wire_w_sink2_channel_range1703w(0) <= sink2_channel(1);
+ wire_w_sink2_channel_range1727w(0) <= sink2_channel(2);
+ wire_w_sink2_channel_range1751w(0) <= sink2_channel(3);
+ wire_w_sink2_channel_range1775w(0) <= sink2_channel(4);
+ wire_w_sink2_channel_range1799w(0) <= sink2_channel(5);
+ wire_w_sink2_channel_range1823w(0) <= sink2_channel(6);
+ wire_w_sink2_channel_range1847w(0) <= sink2_channel(7);
+ wire_w_sink2_data_range21w(0) <= sink2_data(0);
+ wire_w_sink2_data_range262w(0) <= sink2_data(10);
+ wire_w_sink2_data_range286w(0) <= sink2_data(11);
+ wire_w_sink2_data_range310w(0) <= sink2_data(12);
+ wire_w_sink2_data_range334w(0) <= sink2_data(13);
+ wire_w_sink2_data_range358w(0) <= sink2_data(14);
+ wire_w_sink2_data_range382w(0) <= sink2_data(15);
+ wire_w_sink2_data_range406w(0) <= sink2_data(16);
+ wire_w_sink2_data_range430w(0) <= sink2_data(17);
+ wire_w_sink2_data_range454w(0) <= sink2_data(18);
+ wire_w_sink2_data_range478w(0) <= sink2_data(19);
+ wire_w_sink2_data_range46w(0) <= sink2_data(1);
+ wire_w_sink2_data_range502w(0) <= sink2_data(20);
+ wire_w_sink2_data_range526w(0) <= sink2_data(21);
+ wire_w_sink2_data_range550w(0) <= sink2_data(22);
+ wire_w_sink2_data_range574w(0) <= sink2_data(23);
+ wire_w_sink2_data_range598w(0) <= sink2_data(24);
+ wire_w_sink2_data_range622w(0) <= sink2_data(25);
+ wire_w_sink2_data_range646w(0) <= sink2_data(26);
+ wire_w_sink2_data_range670w(0) <= sink2_data(27);
+ wire_w_sink2_data_range694w(0) <= sink2_data(28);
+ wire_w_sink2_data_range718w(0) <= sink2_data(29);
+ wire_w_sink2_data_range70w(0) <= sink2_data(2);
+ wire_w_sink2_data_range742w(0) <= sink2_data(30);
+ wire_w_sink2_data_range766w(0) <= sink2_data(31);
+ wire_w_sink2_data_range790w(0) <= sink2_data(32);
+ wire_w_sink2_data_range814w(0) <= sink2_data(33);
+ wire_w_sink2_data_range838w(0) <= sink2_data(34);
+ wire_w_sink2_data_range862w(0) <= sink2_data(35);
+ wire_w_sink2_data_range886w(0) <= sink2_data(36);
+ wire_w_sink2_data_range910w(0) <= sink2_data(37);
+ wire_w_sink2_data_range934w(0) <= sink2_data(38);
+ wire_w_sink2_data_range958w(0) <= sink2_data(39);
+ wire_w_sink2_data_range94w(0) <= sink2_data(3);
+ wire_w_sink2_data_range982w(0) <= sink2_data(40);
+ wire_w_sink2_data_range1006w(0) <= sink2_data(41);
+ wire_w_sink2_data_range1030w(0) <= sink2_data(42);
+ wire_w_sink2_data_range1054w(0) <= sink2_data(43);
+ wire_w_sink2_data_range1078w(0) <= sink2_data(44);
+ wire_w_sink2_data_range1102w(0) <= sink2_data(45);
+ wire_w_sink2_data_range1126w(0) <= sink2_data(46);
+ wire_w_sink2_data_range1150w(0) <= sink2_data(47);
+ wire_w_sink2_data_range1174w(0) <= sink2_data(48);
+ wire_w_sink2_data_range1198w(0) <= sink2_data(49);
+ wire_w_sink2_data_range118w(0) <= sink2_data(4);
+ wire_w_sink2_data_range1222w(0) <= sink2_data(50);
+ wire_w_sink2_data_range1246w(0) <= sink2_data(51);
+ wire_w_sink2_data_range1270w(0) <= sink2_data(52);
+ wire_w_sink2_data_range1294w(0) <= sink2_data(53);
+ wire_w_sink2_data_range1318w(0) <= sink2_data(54);
+ wire_w_sink2_data_range1342w(0) <= sink2_data(55);
+ wire_w_sink2_data_range1366w(0) <= sink2_data(56);
+ wire_w_sink2_data_range1390w(0) <= sink2_data(57);
+ wire_w_sink2_data_range1414w(0) <= sink2_data(58);
+ wire_w_sink2_data_range1438w(0) <= sink2_data(59);
+ wire_w_sink2_data_range142w(0) <= sink2_data(5);
+ wire_w_sink2_data_range1462w(0) <= sink2_data(60);
+ wire_w_sink2_data_range1486w(0) <= sink2_data(61);
+ wire_w_sink2_data_range1510w(0) <= sink2_data(62);
+ wire_w_sink2_data_range1534w(0) <= sink2_data(63);
+ wire_w_sink2_data_range1558w(0) <= sink2_data(64);
+ wire_w_sink2_data_range1582w(0) <= sink2_data(65);
+ wire_w_sink2_data_range1606w(0) <= sink2_data(66);
+ wire_w_sink2_data_range1630w(0) <= sink2_data(67);
+ wire_w_sink2_data_range1654w(0) <= sink2_data(68);
+ wire_w_sink2_data_range166w(0) <= sink2_data(6);
+ wire_w_sink2_data_range190w(0) <= sink2_data(7);
+ wire_w_sink2_data_range214w(0) <= sink2_data(8);
+ wire_w_sink2_data_range238w(0) <= sink2_data(9);
+ wire_w_sink3_channel_range1681w(0) <= sink3_channel(0);
+ wire_w_sink3_channel_range1706w(0) <= sink3_channel(1);
+ wire_w_sink3_channel_range1730w(0) <= sink3_channel(2);
+ wire_w_sink3_channel_range1754w(0) <= sink3_channel(3);
+ wire_w_sink3_channel_range1778w(0) <= sink3_channel(4);
+ wire_w_sink3_channel_range1802w(0) <= sink3_channel(5);
+ wire_w_sink3_channel_range1826w(0) <= sink3_channel(6);
+ wire_w_sink3_channel_range1850w(0) <= sink3_channel(7);
+ wire_w_sink3_data_range24w(0) <= sink3_data(0);
+ wire_w_sink3_data_range265w(0) <= sink3_data(10);
+ wire_w_sink3_data_range289w(0) <= sink3_data(11);
+ wire_w_sink3_data_range313w(0) <= sink3_data(12);
+ wire_w_sink3_data_range337w(0) <= sink3_data(13);
+ wire_w_sink3_data_range361w(0) <= sink3_data(14);
+ wire_w_sink3_data_range385w(0) <= sink3_data(15);
+ wire_w_sink3_data_range409w(0) <= sink3_data(16);
+ wire_w_sink3_data_range433w(0) <= sink3_data(17);
+ wire_w_sink3_data_range457w(0) <= sink3_data(18);
+ wire_w_sink3_data_range481w(0) <= sink3_data(19);
+ wire_w_sink3_data_range49w(0) <= sink3_data(1);
+ wire_w_sink3_data_range505w(0) <= sink3_data(20);
+ wire_w_sink3_data_range529w(0) <= sink3_data(21);
+ wire_w_sink3_data_range553w(0) <= sink3_data(22);
+ wire_w_sink3_data_range577w(0) <= sink3_data(23);
+ wire_w_sink3_data_range601w(0) <= sink3_data(24);
+ wire_w_sink3_data_range625w(0) <= sink3_data(25);
+ wire_w_sink3_data_range649w(0) <= sink3_data(26);
+ wire_w_sink3_data_range673w(0) <= sink3_data(27);
+ wire_w_sink3_data_range697w(0) <= sink3_data(28);
+ wire_w_sink3_data_range721w(0) <= sink3_data(29);
+ wire_w_sink3_data_range73w(0) <= sink3_data(2);
+ wire_w_sink3_data_range745w(0) <= sink3_data(30);
+ wire_w_sink3_data_range769w(0) <= sink3_data(31);
+ wire_w_sink3_data_range793w(0) <= sink3_data(32);
+ wire_w_sink3_data_range817w(0) <= sink3_data(33);
+ wire_w_sink3_data_range841w(0) <= sink3_data(34);
+ wire_w_sink3_data_range865w(0) <= sink3_data(35);
+ wire_w_sink3_data_range889w(0) <= sink3_data(36);
+ wire_w_sink3_data_range913w(0) <= sink3_data(37);
+ wire_w_sink3_data_range937w(0) <= sink3_data(38);
+ wire_w_sink3_data_range961w(0) <= sink3_data(39);
+ wire_w_sink3_data_range97w(0) <= sink3_data(3);
+ wire_w_sink3_data_range985w(0) <= sink3_data(40);
+ wire_w_sink3_data_range1009w(0) <= sink3_data(41);
+ wire_w_sink3_data_range1033w(0) <= sink3_data(42);
+ wire_w_sink3_data_range1057w(0) <= sink3_data(43);
+ wire_w_sink3_data_range1081w(0) <= sink3_data(44);
+ wire_w_sink3_data_range1105w(0) <= sink3_data(45);
+ wire_w_sink3_data_range1129w(0) <= sink3_data(46);
+ wire_w_sink3_data_range1153w(0) <= sink3_data(47);
+ wire_w_sink3_data_range1177w(0) <= sink3_data(48);
+ wire_w_sink3_data_range1201w(0) <= sink3_data(49);
+ wire_w_sink3_data_range121w(0) <= sink3_data(4);
+ wire_w_sink3_data_range1225w(0) <= sink3_data(50);
+ wire_w_sink3_data_range1249w(0) <= sink3_data(51);
+ wire_w_sink3_data_range1273w(0) <= sink3_data(52);
+ wire_w_sink3_data_range1297w(0) <= sink3_data(53);
+ wire_w_sink3_data_range1321w(0) <= sink3_data(54);
+ wire_w_sink3_data_range1345w(0) <= sink3_data(55);
+ wire_w_sink3_data_range1369w(0) <= sink3_data(56);
+ wire_w_sink3_data_range1393w(0) <= sink3_data(57);
+ wire_w_sink3_data_range1417w(0) <= sink3_data(58);
+ wire_w_sink3_data_range1441w(0) <= sink3_data(59);
+ wire_w_sink3_data_range145w(0) <= sink3_data(5);
+ wire_w_sink3_data_range1465w(0) <= sink3_data(60);
+ wire_w_sink3_data_range1489w(0) <= sink3_data(61);
+ wire_w_sink3_data_range1513w(0) <= sink3_data(62);
+ wire_w_sink3_data_range1537w(0) <= sink3_data(63);
+ wire_w_sink3_data_range1561w(0) <= sink3_data(64);
+ wire_w_sink3_data_range1585w(0) <= sink3_data(65);
+ wire_w_sink3_data_range1609w(0) <= sink3_data(66);
+ wire_w_sink3_data_range1633w(0) <= sink3_data(67);
+ wire_w_sink3_data_range1657w(0) <= sink3_data(68);
+ wire_w_sink3_data_range169w(0) <= sink3_data(6);
+ wire_w_sink3_data_range193w(0) <= sink3_data(7);
+ wire_w_sink3_data_range217w(0) <= sink3_data(8);
+ wire_w_sink3_data_range241w(0) <= sink3_data(9);
+ wire_w_sink4_channel_range1684w(0) <= sink4_channel(0);
+ wire_w_sink4_channel_range1709w(0) <= sink4_channel(1);
+ wire_w_sink4_channel_range1733w(0) <= sink4_channel(2);
+ wire_w_sink4_channel_range1757w(0) <= sink4_channel(3);
+ wire_w_sink4_channel_range1781w(0) <= sink4_channel(4);
+ wire_w_sink4_channel_range1805w(0) <= sink4_channel(5);
+ wire_w_sink4_channel_range1829w(0) <= sink4_channel(6);
+ wire_w_sink4_channel_range1853w(0) <= sink4_channel(7);
+ wire_w_sink4_data_range27w(0) <= sink4_data(0);
+ wire_w_sink4_data_range268w(0) <= sink4_data(10);
+ wire_w_sink4_data_range292w(0) <= sink4_data(11);
+ wire_w_sink4_data_range316w(0) <= sink4_data(12);
+ wire_w_sink4_data_range340w(0) <= sink4_data(13);
+ wire_w_sink4_data_range364w(0) <= sink4_data(14);
+ wire_w_sink4_data_range388w(0) <= sink4_data(15);
+ wire_w_sink4_data_range412w(0) <= sink4_data(16);
+ wire_w_sink4_data_range436w(0) <= sink4_data(17);
+ wire_w_sink4_data_range460w(0) <= sink4_data(18);
+ wire_w_sink4_data_range484w(0) <= sink4_data(19);
+ wire_w_sink4_data_range52w(0) <= sink4_data(1);
+ wire_w_sink4_data_range508w(0) <= sink4_data(20);
+ wire_w_sink4_data_range532w(0) <= sink4_data(21);
+ wire_w_sink4_data_range556w(0) <= sink4_data(22);
+ wire_w_sink4_data_range580w(0) <= sink4_data(23);
+ wire_w_sink4_data_range604w(0) <= sink4_data(24);
+ wire_w_sink4_data_range628w(0) <= sink4_data(25);
+ wire_w_sink4_data_range652w(0) <= sink4_data(26);
+ wire_w_sink4_data_range676w(0) <= sink4_data(27);
+ wire_w_sink4_data_range700w(0) <= sink4_data(28);
+ wire_w_sink4_data_range724w(0) <= sink4_data(29);
+ wire_w_sink4_data_range76w(0) <= sink4_data(2);
+ wire_w_sink4_data_range748w(0) <= sink4_data(30);
+ wire_w_sink4_data_range772w(0) <= sink4_data(31);
+ wire_w_sink4_data_range796w(0) <= sink4_data(32);
+ wire_w_sink4_data_range820w(0) <= sink4_data(33);
+ wire_w_sink4_data_range844w(0) <= sink4_data(34);
+ wire_w_sink4_data_range868w(0) <= sink4_data(35);
+ wire_w_sink4_data_range892w(0) <= sink4_data(36);
+ wire_w_sink4_data_range916w(0) <= sink4_data(37);
+ wire_w_sink4_data_range940w(0) <= sink4_data(38);
+ wire_w_sink4_data_range964w(0) <= sink4_data(39);
+ wire_w_sink4_data_range100w(0) <= sink4_data(3);
+ wire_w_sink4_data_range988w(0) <= sink4_data(40);
+ wire_w_sink4_data_range1012w(0) <= sink4_data(41);
+ wire_w_sink4_data_range1036w(0) <= sink4_data(42);
+ wire_w_sink4_data_range1060w(0) <= sink4_data(43);
+ wire_w_sink4_data_range1084w(0) <= sink4_data(44);
+ wire_w_sink4_data_range1108w(0) <= sink4_data(45);
+ wire_w_sink4_data_range1132w(0) <= sink4_data(46);
+ wire_w_sink4_data_range1156w(0) <= sink4_data(47);
+ wire_w_sink4_data_range1180w(0) <= sink4_data(48);
+ wire_w_sink4_data_range1204w(0) <= sink4_data(49);
+ wire_w_sink4_data_range124w(0) <= sink4_data(4);
+ wire_w_sink4_data_range1228w(0) <= sink4_data(50);
+ wire_w_sink4_data_range1252w(0) <= sink4_data(51);
+ wire_w_sink4_data_range1276w(0) <= sink4_data(52);
+ wire_w_sink4_data_range1300w(0) <= sink4_data(53);
+ wire_w_sink4_data_range1324w(0) <= sink4_data(54);
+ wire_w_sink4_data_range1348w(0) <= sink4_data(55);
+ wire_w_sink4_data_range1372w(0) <= sink4_data(56);
+ wire_w_sink4_data_range1396w(0) <= sink4_data(57);
+ wire_w_sink4_data_range1420w(0) <= sink4_data(58);
+ wire_w_sink4_data_range1444w(0) <= sink4_data(59);
+ wire_w_sink4_data_range148w(0) <= sink4_data(5);
+ wire_w_sink4_data_range1468w(0) <= sink4_data(60);
+ wire_w_sink4_data_range1492w(0) <= sink4_data(61);
+ wire_w_sink4_data_range1516w(0) <= sink4_data(62);
+ wire_w_sink4_data_range1540w(0) <= sink4_data(63);
+ wire_w_sink4_data_range1564w(0) <= sink4_data(64);
+ wire_w_sink4_data_range1588w(0) <= sink4_data(65);
+ wire_w_sink4_data_range1612w(0) <= sink4_data(66);
+ wire_w_sink4_data_range1636w(0) <= sink4_data(67);
+ wire_w_sink4_data_range1660w(0) <= sink4_data(68);
+ wire_w_sink4_data_range172w(0) <= sink4_data(6);
+ wire_w_sink4_data_range196w(0) <= sink4_data(7);
+ wire_w_sink4_data_range220w(0) <= sink4_data(8);
+ wire_w_sink4_data_range244w(0) <= sink4_data(9);
+ wire_w_sink5_channel_range1687w(0) <= sink5_channel(0);
+ wire_w_sink5_channel_range1712w(0) <= sink5_channel(1);
+ wire_w_sink5_channel_range1736w(0) <= sink5_channel(2);
+ wire_w_sink5_channel_range1760w(0) <= sink5_channel(3);
+ wire_w_sink5_channel_range1784w(0) <= sink5_channel(4);
+ wire_w_sink5_channel_range1808w(0) <= sink5_channel(5);
+ wire_w_sink5_channel_range1832w(0) <= sink5_channel(6);
+ wire_w_sink5_channel_range1856w(0) <= sink5_channel(7);
+ wire_w_sink5_data_range30w(0) <= sink5_data(0);
+ wire_w_sink5_data_range271w(0) <= sink5_data(10);
+ wire_w_sink5_data_range295w(0) <= sink5_data(11);
+ wire_w_sink5_data_range319w(0) <= sink5_data(12);
+ wire_w_sink5_data_range343w(0) <= sink5_data(13);
+ wire_w_sink5_data_range367w(0) <= sink5_data(14);
+ wire_w_sink5_data_range391w(0) <= sink5_data(15);
+ wire_w_sink5_data_range415w(0) <= sink5_data(16);
+ wire_w_sink5_data_range439w(0) <= sink5_data(17);
+ wire_w_sink5_data_range463w(0) <= sink5_data(18);
+ wire_w_sink5_data_range487w(0) <= sink5_data(19);
+ wire_w_sink5_data_range55w(0) <= sink5_data(1);
+ wire_w_sink5_data_range511w(0) <= sink5_data(20);
+ wire_w_sink5_data_range535w(0) <= sink5_data(21);
+ wire_w_sink5_data_range559w(0) <= sink5_data(22);
+ wire_w_sink5_data_range583w(0) <= sink5_data(23);
+ wire_w_sink5_data_range607w(0) <= sink5_data(24);
+ wire_w_sink5_data_range631w(0) <= sink5_data(25);
+ wire_w_sink5_data_range655w(0) <= sink5_data(26);
+ wire_w_sink5_data_range679w(0) <= sink5_data(27);
+ wire_w_sink5_data_range703w(0) <= sink5_data(28);
+ wire_w_sink5_data_range727w(0) <= sink5_data(29);
+ wire_w_sink5_data_range79w(0) <= sink5_data(2);
+ wire_w_sink5_data_range751w(0) <= sink5_data(30);
+ wire_w_sink5_data_range775w(0) <= sink5_data(31);
+ wire_w_sink5_data_range799w(0) <= sink5_data(32);
+ wire_w_sink5_data_range823w(0) <= sink5_data(33);
+ wire_w_sink5_data_range847w(0) <= sink5_data(34);
+ wire_w_sink5_data_range871w(0) <= sink5_data(35);
+ wire_w_sink5_data_range895w(0) <= sink5_data(36);
+ wire_w_sink5_data_range919w(0) <= sink5_data(37);
+ wire_w_sink5_data_range943w(0) <= sink5_data(38);
+ wire_w_sink5_data_range967w(0) <= sink5_data(39);
+ wire_w_sink5_data_range103w(0) <= sink5_data(3);
+ wire_w_sink5_data_range991w(0) <= sink5_data(40);
+ wire_w_sink5_data_range1015w(0) <= sink5_data(41);
+ wire_w_sink5_data_range1039w(0) <= sink5_data(42);
+ wire_w_sink5_data_range1063w(0) <= sink5_data(43);
+ wire_w_sink5_data_range1087w(0) <= sink5_data(44);
+ wire_w_sink5_data_range1111w(0) <= sink5_data(45);
+ wire_w_sink5_data_range1135w(0) <= sink5_data(46);
+ wire_w_sink5_data_range1159w(0) <= sink5_data(47);
+ wire_w_sink5_data_range1183w(0) <= sink5_data(48);
+ wire_w_sink5_data_range1207w(0) <= sink5_data(49);
+ wire_w_sink5_data_range127w(0) <= sink5_data(4);
+ wire_w_sink5_data_range1231w(0) <= sink5_data(50);
+ wire_w_sink5_data_range1255w(0) <= sink5_data(51);
+ wire_w_sink5_data_range1279w(0) <= sink5_data(52);
+ wire_w_sink5_data_range1303w(0) <= sink5_data(53);
+ wire_w_sink5_data_range1327w(0) <= sink5_data(54);
+ wire_w_sink5_data_range1351w(0) <= sink5_data(55);
+ wire_w_sink5_data_range1375w(0) <= sink5_data(56);
+ wire_w_sink5_data_range1399w(0) <= sink5_data(57);
+ wire_w_sink5_data_range1423w(0) <= sink5_data(58);
+ wire_w_sink5_data_range1447w(0) <= sink5_data(59);
+ wire_w_sink5_data_range151w(0) <= sink5_data(5);
+ wire_w_sink5_data_range1471w(0) <= sink5_data(60);
+ wire_w_sink5_data_range1495w(0) <= sink5_data(61);
+ wire_w_sink5_data_range1519w(0) <= sink5_data(62);
+ wire_w_sink5_data_range1543w(0) <= sink5_data(63);
+ wire_w_sink5_data_range1567w(0) <= sink5_data(64);
+ wire_w_sink5_data_range1591w(0) <= sink5_data(65);
+ wire_w_sink5_data_range1615w(0) <= sink5_data(66);
+ wire_w_sink5_data_range1639w(0) <= sink5_data(67);
+ wire_w_sink5_data_range1663w(0) <= sink5_data(68);
+ wire_w_sink5_data_range175w(0) <= sink5_data(6);
+ wire_w_sink5_data_range199w(0) <= sink5_data(7);
+ wire_w_sink5_data_range223w(0) <= sink5_data(8);
+ wire_w_sink5_data_range247w(0) <= sink5_data(9);
+ wire_w_sink6_channel_range1690w(0) <= sink6_channel(0);
+ wire_w_sink6_channel_range1715w(0) <= sink6_channel(1);
+ wire_w_sink6_channel_range1739w(0) <= sink6_channel(2);
+ wire_w_sink6_channel_range1763w(0) <= sink6_channel(3);
+ wire_w_sink6_channel_range1787w(0) <= sink6_channel(4);
+ wire_w_sink6_channel_range1811w(0) <= sink6_channel(5);
+ wire_w_sink6_channel_range1835w(0) <= sink6_channel(6);
+ wire_w_sink6_channel_range1859w(0) <= sink6_channel(7);
+ wire_w_sink6_data_range33w(0) <= sink6_data(0);
+ wire_w_sink6_data_range274w(0) <= sink6_data(10);
+ wire_w_sink6_data_range298w(0) <= sink6_data(11);
+ wire_w_sink6_data_range322w(0) <= sink6_data(12);
+ wire_w_sink6_data_range346w(0) <= sink6_data(13);
+ wire_w_sink6_data_range370w(0) <= sink6_data(14);
+ wire_w_sink6_data_range394w(0) <= sink6_data(15);
+ wire_w_sink6_data_range418w(0) <= sink6_data(16);
+ wire_w_sink6_data_range442w(0) <= sink6_data(17);
+ wire_w_sink6_data_range466w(0) <= sink6_data(18);
+ wire_w_sink6_data_range490w(0) <= sink6_data(19);
+ wire_w_sink6_data_range58w(0) <= sink6_data(1);
+ wire_w_sink6_data_range514w(0) <= sink6_data(20);
+ wire_w_sink6_data_range538w(0) <= sink6_data(21);
+ wire_w_sink6_data_range562w(0) <= sink6_data(22);
+ wire_w_sink6_data_range586w(0) <= sink6_data(23);
+ wire_w_sink6_data_range610w(0) <= sink6_data(24);
+ wire_w_sink6_data_range634w(0) <= sink6_data(25);
+ wire_w_sink6_data_range658w(0) <= sink6_data(26);
+ wire_w_sink6_data_range682w(0) <= sink6_data(27);
+ wire_w_sink6_data_range706w(0) <= sink6_data(28);
+ wire_w_sink6_data_range730w(0) <= sink6_data(29);
+ wire_w_sink6_data_range82w(0) <= sink6_data(2);
+ wire_w_sink6_data_range754w(0) <= sink6_data(30);
+ wire_w_sink6_data_range778w(0) <= sink6_data(31);
+ wire_w_sink6_data_range802w(0) <= sink6_data(32);
+ wire_w_sink6_data_range826w(0) <= sink6_data(33);
+ wire_w_sink6_data_range850w(0) <= sink6_data(34);
+ wire_w_sink6_data_range874w(0) <= sink6_data(35);
+ wire_w_sink6_data_range898w(0) <= sink6_data(36);
+ wire_w_sink6_data_range922w(0) <= sink6_data(37);
+ wire_w_sink6_data_range946w(0) <= sink6_data(38);
+ wire_w_sink6_data_range970w(0) <= sink6_data(39);
+ wire_w_sink6_data_range106w(0) <= sink6_data(3);
+ wire_w_sink6_data_range994w(0) <= sink6_data(40);
+ wire_w_sink6_data_range1018w(0) <= sink6_data(41);
+ wire_w_sink6_data_range1042w(0) <= sink6_data(42);
+ wire_w_sink6_data_range1066w(0) <= sink6_data(43);
+ wire_w_sink6_data_range1090w(0) <= sink6_data(44);
+ wire_w_sink6_data_range1114w(0) <= sink6_data(45);
+ wire_w_sink6_data_range1138w(0) <= sink6_data(46);
+ wire_w_sink6_data_range1162w(0) <= sink6_data(47);
+ wire_w_sink6_data_range1186w(0) <= sink6_data(48);
+ wire_w_sink6_data_range1210w(0) <= sink6_data(49);
+ wire_w_sink6_data_range130w(0) <= sink6_data(4);
+ wire_w_sink6_data_range1234w(0) <= sink6_data(50);
+ wire_w_sink6_data_range1258w(0) <= sink6_data(51);
+ wire_w_sink6_data_range1282w(0) <= sink6_data(52);
+ wire_w_sink6_data_range1306w(0) <= sink6_data(53);
+ wire_w_sink6_data_range1330w(0) <= sink6_data(54);
+ wire_w_sink6_data_range1354w(0) <= sink6_data(55);
+ wire_w_sink6_data_range1378w(0) <= sink6_data(56);
+ wire_w_sink6_data_range1402w(0) <= sink6_data(57);
+ wire_w_sink6_data_range1426w(0) <= sink6_data(58);
+ wire_w_sink6_data_range1450w(0) <= sink6_data(59);
+ wire_w_sink6_data_range154w(0) <= sink6_data(5);
+ wire_w_sink6_data_range1474w(0) <= sink6_data(60);
+ wire_w_sink6_data_range1498w(0) <= sink6_data(61);
+ wire_w_sink6_data_range1522w(0) <= sink6_data(62);
+ wire_w_sink6_data_range1546w(0) <= sink6_data(63);
+ wire_w_sink6_data_range1570w(0) <= sink6_data(64);
+ wire_w_sink6_data_range1594w(0) <= sink6_data(65);
+ wire_w_sink6_data_range1618w(0) <= sink6_data(66);
+ wire_w_sink6_data_range1642w(0) <= sink6_data(67);
+ wire_w_sink6_data_range1666w(0) <= sink6_data(68);
+ wire_w_sink6_data_range178w(0) <= sink6_data(6);
+ wire_w_sink6_data_range202w(0) <= sink6_data(7);
+ wire_w_sink6_data_range226w(0) <= sink6_data(8);
+ wire_w_sink6_data_range250w(0) <= sink6_data(9);
+ wire_w_sink7_channel_range1693w(0) <= sink7_channel(0);
+ wire_w_sink7_channel_range1718w(0) <= sink7_channel(1);
+ wire_w_sink7_channel_range1742w(0) <= sink7_channel(2);
+ wire_w_sink7_channel_range1766w(0) <= sink7_channel(3);
+ wire_w_sink7_channel_range1790w(0) <= sink7_channel(4);
+ wire_w_sink7_channel_range1814w(0) <= sink7_channel(5);
+ wire_w_sink7_channel_range1838w(0) <= sink7_channel(6);
+ wire_w_sink7_channel_range1862w(0) <= sink7_channel(7);
+ wire_w_sink7_data_range36w(0) <= sink7_data(0);
+ wire_w_sink7_data_range277w(0) <= sink7_data(10);
+ wire_w_sink7_data_range301w(0) <= sink7_data(11);
+ wire_w_sink7_data_range325w(0) <= sink7_data(12);
+ wire_w_sink7_data_range349w(0) <= sink7_data(13);
+ wire_w_sink7_data_range373w(0) <= sink7_data(14);
+ wire_w_sink7_data_range397w(0) <= sink7_data(15);
+ wire_w_sink7_data_range421w(0) <= sink7_data(16);
+ wire_w_sink7_data_range445w(0) <= sink7_data(17);
+ wire_w_sink7_data_range469w(0) <= sink7_data(18);
+ wire_w_sink7_data_range493w(0) <= sink7_data(19);
+ wire_w_sink7_data_range61w(0) <= sink7_data(1);
+ wire_w_sink7_data_range517w(0) <= sink7_data(20);
+ wire_w_sink7_data_range541w(0) <= sink7_data(21);
+ wire_w_sink7_data_range565w(0) <= sink7_data(22);
+ wire_w_sink7_data_range589w(0) <= sink7_data(23);
+ wire_w_sink7_data_range613w(0) <= sink7_data(24);
+ wire_w_sink7_data_range637w(0) <= sink7_data(25);
+ wire_w_sink7_data_range661w(0) <= sink7_data(26);
+ wire_w_sink7_data_range685w(0) <= sink7_data(27);
+ wire_w_sink7_data_range709w(0) <= sink7_data(28);
+ wire_w_sink7_data_range733w(0) <= sink7_data(29);
+ wire_w_sink7_data_range85w(0) <= sink7_data(2);
+ wire_w_sink7_data_range757w(0) <= sink7_data(30);
+ wire_w_sink7_data_range781w(0) <= sink7_data(31);
+ wire_w_sink7_data_range805w(0) <= sink7_data(32);
+ wire_w_sink7_data_range829w(0) <= sink7_data(33);
+ wire_w_sink7_data_range853w(0) <= sink7_data(34);
+ wire_w_sink7_data_range877w(0) <= sink7_data(35);
+ wire_w_sink7_data_range901w(0) <= sink7_data(36);
+ wire_w_sink7_data_range925w(0) <= sink7_data(37);
+ wire_w_sink7_data_range949w(0) <= sink7_data(38);
+ wire_w_sink7_data_range973w(0) <= sink7_data(39);
+ wire_w_sink7_data_range109w(0) <= sink7_data(3);
+ wire_w_sink7_data_range997w(0) <= sink7_data(40);
+ wire_w_sink7_data_range1021w(0) <= sink7_data(41);
+ wire_w_sink7_data_range1045w(0) <= sink7_data(42);
+ wire_w_sink7_data_range1069w(0) <= sink7_data(43);
+ wire_w_sink7_data_range1093w(0) <= sink7_data(44);
+ wire_w_sink7_data_range1117w(0) <= sink7_data(45);
+ wire_w_sink7_data_range1141w(0) <= sink7_data(46);
+ wire_w_sink7_data_range1165w(0) <= sink7_data(47);
+ wire_w_sink7_data_range1189w(0) <= sink7_data(48);
+ wire_w_sink7_data_range1213w(0) <= sink7_data(49);
+ wire_w_sink7_data_range133w(0) <= sink7_data(4);
+ wire_w_sink7_data_range1237w(0) <= sink7_data(50);
+ wire_w_sink7_data_range1261w(0) <= sink7_data(51);
+ wire_w_sink7_data_range1285w(0) <= sink7_data(52);
+ wire_w_sink7_data_range1309w(0) <= sink7_data(53);
+ wire_w_sink7_data_range1333w(0) <= sink7_data(54);
+ wire_w_sink7_data_range1357w(0) <= sink7_data(55);
+ wire_w_sink7_data_range1381w(0) <= sink7_data(56);
+ wire_w_sink7_data_range1405w(0) <= sink7_data(57);
+ wire_w_sink7_data_range1429w(0) <= sink7_data(58);
+ wire_w_sink7_data_range1453w(0) <= sink7_data(59);
+ wire_w_sink7_data_range157w(0) <= sink7_data(5);
+ wire_w_sink7_data_range1477w(0) <= sink7_data(60);
+ wire_w_sink7_data_range1501w(0) <= sink7_data(61);
+ wire_w_sink7_data_range1525w(0) <= sink7_data(62);
+ wire_w_sink7_data_range1549w(0) <= sink7_data(63);
+ wire_w_sink7_data_range1573w(0) <= sink7_data(64);
+ wire_w_sink7_data_range1597w(0) <= sink7_data(65);
+ wire_w_sink7_data_range1621w(0) <= sink7_data(66);
+ wire_w_sink7_data_range1645w(0) <= sink7_data(67);
+ wire_w_sink7_data_range1669w(0) <= sink7_data(68);
+ wire_w_sink7_data_range181w(0) <= sink7_data(6);
+ wire_w_sink7_data_range205w(0) <= sink7_data(7);
+ wire_w_sink7_data_range229w(0) <= sink7_data(8);
+ wire_w_sink7_data_range253w(0) <= sink7_data(9);
+
+ END RTL; --altera_merlin_multiplexer_0002
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_multiplexer/altera_merlin_multiplexer_0003.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_multiplexer/altera_merlin_multiplexer_0003.vho
new file mode 100644
index 0000000000000000000000000000000000000000..0e0831ec374f43d39a7ebe7808da3b2dd960d182
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_multiplexer/altera_merlin_multiplexer_0003.vho
@@ -0,0 +1,3150 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_multiplexer_0003 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ reset : IN STD_LOGIC;
+ sink0_channel : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+ sink0_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ sink0_endofpacket : IN STD_LOGIC;
+ sink0_ready : OUT STD_LOGIC;
+ sink0_startofpacket : IN STD_LOGIC;
+ sink0_valid : IN STD_LOGIC;
+ sink1_channel : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+ sink1_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ sink1_endofpacket : IN STD_LOGIC;
+ sink1_ready : OUT STD_LOGIC;
+ sink1_startofpacket : IN STD_LOGIC;
+ sink1_valid : IN STD_LOGIC;
+ sink2_channel : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+ sink2_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ sink2_endofpacket : IN STD_LOGIC;
+ sink2_ready : OUT STD_LOGIC;
+ sink2_startofpacket : IN STD_LOGIC;
+ sink2_valid : IN STD_LOGIC;
+ sink3_channel : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+ sink3_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ sink3_endofpacket : IN STD_LOGIC;
+ sink3_ready : OUT STD_LOGIC;
+ sink3_startofpacket : IN STD_LOGIC;
+ sink3_valid : IN STD_LOGIC;
+ sink4_channel : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+ sink4_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ sink4_endofpacket : IN STD_LOGIC;
+ sink4_ready : OUT STD_LOGIC;
+ sink4_startofpacket : IN STD_LOGIC;
+ sink4_valid : IN STD_LOGIC;
+ sink5_channel : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+ sink5_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ sink5_endofpacket : IN STD_LOGIC;
+ sink5_ready : OUT STD_LOGIC;
+ sink5_startofpacket : IN STD_LOGIC;
+ sink5_valid : IN STD_LOGIC;
+ sink6_channel : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+ sink6_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ sink6_endofpacket : IN STD_LOGIC;
+ sink6_ready : OUT STD_LOGIC;
+ sink6_startofpacket : IN STD_LOGIC;
+ sink6_valid : IN STD_LOGIC;
+ src_channel : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
+ src_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ src_endofpacket : OUT STD_LOGIC;
+ src_ready : IN STD_LOGIC;
+ src_startofpacket : OUT STD_LOGIC;
+ src_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_multiplexer_0003;
+
+ ARCHITECTURE RTL OF altera_merlin_multiplexer_0003 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL wire_w_lg_sink0_valid1465w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1487w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1508w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1529w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1550w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1571w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1592w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid15w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid226w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid247w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid268w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid289w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid310w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid331w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid352w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid373w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid394w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid415w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid436w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid457w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid478w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid499w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid520w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid541w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid562w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid583w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid604w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid625w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid58w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid646w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid667w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid688w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid709w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid730w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid751w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid772w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid793w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid814w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid835w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid79w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid856w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid877w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid898w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid919w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid940w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid961w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid982w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1003w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1024w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1045w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1066w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1087w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1129w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1150w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1171w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1192w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1213w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1234w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1255w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid121w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1276w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1297w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1318w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1339w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1360w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1381w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1402w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1423w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid1444w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid142w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid163w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid184w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink0_valid205w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1467w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1489w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1510w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1531w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1552w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1573w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1594w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid17w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid228w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid249w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid270w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid312w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid333w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid354w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid375w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid396w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid417w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid39w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid438w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid459w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid480w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid501w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid522w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid543w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid564w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid585w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid606w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid627w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid648w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid669w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid690w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid711w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid732w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid753w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid774w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid795w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid816w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid837w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid81w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid858w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid879w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid900w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid921w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid942w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid963w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid984w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1005w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1026w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1047w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1068w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1089w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1152w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1173w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1194w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1215w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1236w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1257w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid123w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1278w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1299w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1320w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1341w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1362w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1383w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1404w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1425w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid1446w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid144w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid165w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid186w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink1_valid207w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1470w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1492w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1513w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1534w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1555w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1576w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1597w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid20w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid231w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid252w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid273w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid294w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid315w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid336w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid357w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid378w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid399w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid420w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid441w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid462w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid483w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid504w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid525w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid546w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid567w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid588w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid609w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid630w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid63w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid651w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid672w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid693w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid714w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid735w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid756w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid777w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid798w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid819w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid840w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid84w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid861w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid882w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid903w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid924w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid945w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid966w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid987w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1008w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1029w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1050w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1071w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1092w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1134w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1155w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1176w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1197w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1218w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1239w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1260w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid126w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1281w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1302w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1323w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1344w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1365w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1386w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1407w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1428w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid1449w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid147w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid168w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid189w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink2_valid210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1473w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1495w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1516w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1537w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1558w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1579w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1600w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid23w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid234w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid255w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid276w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid297w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid318w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid339w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid360w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid381w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid402w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid423w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid45w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid444w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid465w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid486w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid507w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid528w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid549w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid570w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid591w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid612w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid633w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid66w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid654w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid675w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid696w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid717w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid738w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid759w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid780w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid801w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid822w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid843w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid87w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid864w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid885w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid906w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid927w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid948w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid969w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid990w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1011w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1032w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1053w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1074w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1095w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1116w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1137w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1158w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1200w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1221w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1242w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1263w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid129w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1284w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1305w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1326w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1347w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1368w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1389w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1410w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1431w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid1452w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid150w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid171w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid192w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink3_valid213w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1476w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1498w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1519w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1540w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1561w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1582w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1603w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid26w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid237w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid258w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid279w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid300w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid321w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid342w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid363w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid384w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid405w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid426w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid48w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid447w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid468w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid489w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid510w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid531w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid552w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid573w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid594w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid615w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid636w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid69w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid657w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid678w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid699w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid720w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid741w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid762w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid783w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid804w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid825w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid846w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid90w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid867w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid888w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid909w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid930w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid951w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid972w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid993w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1014w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1035w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1056w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid111w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1077w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1098w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1140w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1161w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1182w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1203w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1224w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1245w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1266w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid132w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1287w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1308w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1329w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1350w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1371w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1392w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1413w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1434w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid1455w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid153w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid174w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid195w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink4_valid216w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1479w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1501w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1522w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1543w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1564w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1585w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1606w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid29w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid240w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid261w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid282w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid303w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid324w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid345w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid366w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid387w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid408w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid429w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid51w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid450w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid471w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid492w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid513w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid534w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid555w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid576w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid597w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid618w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid639w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid72w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid660w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid681w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid702w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid723w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid744w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid765w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid786w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid807w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid828w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid849w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid93w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid870w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid891w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid912w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid933w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid954w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid975w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid996w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1017w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1038w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1059w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid114w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1080w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1122w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1143w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1164w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1185w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1206w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1227w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1248w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1269w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid135w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1290w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1311w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1332w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1353w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1374w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1395w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1416w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1437w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid1458w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid156w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid177w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid198w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink5_valid219w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1482w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1504w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1525w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1546w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1567w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1588w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1609w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid32w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid243w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid264w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid285w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid306w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid327w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid348w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid369w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid390w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid411w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid432w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid54w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid453w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid474w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid495w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid516w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid537w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid558w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid579w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid600w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid642w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid663w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid684w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid705w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid726w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid747w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid768w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid789w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid810w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid831w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid852w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid96w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid873w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid894w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid915w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid936w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid957w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid978w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid999w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1020w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1041w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1062w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid117w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1083w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1104w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1125w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1146w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1167w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1188w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1230w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1251w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1272w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid138w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1293w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1314w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1335w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1356w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1377w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1398w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1419w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1440w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid1461w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid159w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid180w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid201w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_sink6_valid222w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1465w1468w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1487w1490w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1508w1511w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1529w1532w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1550w1553w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1571w1574w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1592w1595w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid15w18w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid226w229w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid247w250w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid268w271w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid289w292w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid310w313w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid331w334w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid352w355w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid373w376w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid394w397w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid415w418w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid37w40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid436w439w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid457w460w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid478w481w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid499w502w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid520w523w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid541w544w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid562w565w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid583w586w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid604w607w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid625w628w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid58w61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid646w649w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid667w670w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid688w691w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid709w712w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid730w733w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid751w754w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid772w775w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid793w796w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid814w817w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid835w838w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid79w82w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid856w859w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid877w880w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid898w901w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid919w922w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid940w943w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid961w964w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid982w985w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1003w1006w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1024w1027w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1045w1048w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid100w103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1066w1069w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1087w1090w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1108w1111w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1129w1132w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1150w1153w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1171w1174w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1192w1195w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1213w1216w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1234w1237w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1255w1258w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid121w124w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1276w1279w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1297w1300w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1318w1321w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1339w1342w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1360w1363w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1381w1384w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1402w1405w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1423w1426w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid1444w1447w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid142w145w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid163w166w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid184w187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_sink0_valid205w208w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1465w1468w1471w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1487w1490w1493w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1508w1511w1514w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1529w1532w1535w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1550w1553w1556w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1571w1574w1577w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1592w1595w1598w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid15w18w21w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid226w229w232w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid247w250w253w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid268w271w274w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid289w292w295w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid310w313w316w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid331w334w337w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid352w355w358w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid373w376w379w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid394w397w400w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid415w418w421w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid37w40w43w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid436w439w442w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid457w460w463w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid478w481w484w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid499w502w505w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid520w523w526w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid541w544w547w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid562w565w568w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid583w586w589w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid604w607w610w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid625w628w631w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid58w61w64w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid646w649w652w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid667w670w673w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid688w691w694w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid709w712w715w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid730w733w736w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid751w754w757w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid772w775w778w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid793w796w799w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid814w817w820w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid835w838w841w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid79w82w85w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid856w859w862w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid877w880w883w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid898w901w904w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid919w922w925w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid940w943w946w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid961w964w967w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid982w985w988w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1003w1006w1009w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1024w1027w1030w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1045w1048w1051w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid100w103w106w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1066w1069w1072w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1087w1090w1093w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1108w1111w1114w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1129w1132w1135w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1150w1153w1156w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1171w1174w1177w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1192w1195w1198w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1213w1216w1219w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1234w1237w1240w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1255w1258w1261w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid121w124w127w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1276w1279w1282w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1297w1300w1303w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1318w1321w1324w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1339w1342w1345w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1360w1363w1366w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1381w1384w1387w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1402w1405w1408w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1423w1426w1429w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid1444w1447w1450w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid142w145w148w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid163w166w169w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid184w187w190w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_sink0_valid205w208w211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1474w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1496w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1517w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1538w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1559w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1580w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1601w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid15w18w21w24w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid226w229w232w235w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid247w250w253w256w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid268w271w274w277w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid289w292w295w298w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid310w313w316w319w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid331w334w337w340w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid352w355w358w361w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid373w376w379w382w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid394w397w400w403w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid415w418w421w424w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid37w40w43w46w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid436w439w442w445w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid457w460w463w466w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid478w481w484w487w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid499w502w505w508w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid520w523w526w529w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid541w544w547w550w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid562w565w568w571w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid583w586w589w592w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid604w607w610w613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid625w628w631w634w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid58w61w64w67w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid646w649w652w655w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid667w670w673w676w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid688w691w694w697w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid709w712w715w718w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid730w733w736w739w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid751w754w757w760w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid772w775w778w781w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid793w796w799w802w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid814w817w820w823w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid835w838w841w844w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid79w82w85w88w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid856w859w862w865w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid877w880w883w886w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid898w901w904w907w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid919w922w925w928w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid940w943w946w949w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid961w964w967w970w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid982w985w988w991w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1012w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1033w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1054w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid100w103w106w109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1075w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1096w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1117w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1138w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1159w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1180w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1201w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1222w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1243w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1264w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid121w124w127w130w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1285w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1306w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1327w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1348w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1369w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1390w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1411w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1432w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w1453w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid142w145w148w151w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid163w166w169w172w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid184w187w190w193w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sink0_valid205w208w211w214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1474w1477w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1496w1499w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1517w1520w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1538w1541w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1559w1562w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1580w1583w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1601w1604w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w27w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w238w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w259w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w280w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w301w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w322w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w343w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w364w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w385w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w406w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w427w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w49w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w448w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w469w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w490w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w511w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w532w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w553w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w574w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w595w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w616w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w637w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w70w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w658w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w679w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w700w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w721w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w742w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w763w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w784w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w805w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w826w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w847w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w91w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w868w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w889w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w910w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w931w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w952w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w973w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w994w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1012w1015w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1033w1036w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1054w1057w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w112w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1075w1078w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1096w1099w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1117w1120w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1138w1141w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1159w1162w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1180w1183w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1201w1204w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1222w1225w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1243w1246w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1264w1267w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w133w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1285w1288w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1306w1309w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1327w1330w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1348w1351w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1369w1372w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1390w1393w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1411w1414w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1432w1435w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w1453w1456w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w154w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w175w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w196w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w217w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1474w1477w1480w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1496w1499w1502w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1517w1520w1523w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1538w1541w1544w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1559w1562w1565w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1580w1583w1586w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1601w1604w1607w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w27w30w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w238w241w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w259w262w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w280w283w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w301w304w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w322w325w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w343w346w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w364w367w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w385w388w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w406w409w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w427w430w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w49w52w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w448w451w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w469w472w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w490w493w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w511w514w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w532w535w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w553w556w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w574w577w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w595w598w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w616w619w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w637w640w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w70w73w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w658w661w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w679w682w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w700w703w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w721w724w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w742w745w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w763w766w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w784w787w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w805w808w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w826w829w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w847w850w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w91w94w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w868w871w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w889w892w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w910w913w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w931w934w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w952w955w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w973w976w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w994w997w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1012w1015w1018w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1033w1036w1039w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1054w1057w1060w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w112w115w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1075w1078w1081w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1096w1099w1102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1117w1120w1123w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1138w1141w1144w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1159w1162w1165w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1180w1183w1186w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1201w1204w1207w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1222w1225w1228w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1243w1246w1249w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1264w1267w1270w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w133w136w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1285w1288w1291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1306w1309w1312w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1327w1330w1333w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1348w1351w1354w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1369w1372w1375w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1390w1393w1396w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1411w1414w1417w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1432w1435w1438w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w1453w1456w1459w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w154w157w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w175w178w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w196w199w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w217w220w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1474w1477w1480w1483w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1496w1499w1502w1505w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1517w1520w1523w1526w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1538w1541w1544w1547w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1559w1562w1565w1568w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1580w1583w1586w1589w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1601w1604w1607w1610w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w27w30w33w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w238w241w244w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w259w262w265w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w280w283w286w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w301w304w307w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w322w325w328w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w343w346w349w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w364w367w370w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w385w388w391w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w406w409w412w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w427w430w433w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w49w52w55w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w448w451w454w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w469w472w475w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w490w493w496w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w511w514w517w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w532w535w538w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w553w556w559w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w574w577w580w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w595w598w601w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w616w619w622w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w637w640w643w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w70w73w76w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w658w661w664w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w679w682w685w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w700w703w706w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w721w724w727w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w742w745w748w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w763w766w769w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w784w787w790w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w805w808w811w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w826w829w832w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w847w850w853w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w91w94w97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w868w871w874w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w889w892w895w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w910w913w916w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w931w934w937w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w952w955w958w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w973w976w979w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w994w997w1000w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1012w1015w1018w1021w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1033w1036w1039w1042w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1054w1057w1060w1063w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w112w115w118w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1075w1078w1081w1084w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1096w1099w1102w1105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1117w1120w1123w1126w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1138w1141w1144w1147w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1159w1162w1165w1168w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1180w1183w1186w1189w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1201w1204w1207w1210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1222w1225w1228w1231w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1243w1246w1249w1252w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1264w1267w1270w1273w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w133w136w139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1285w1288w1291w1294w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1306w1309w1312w1315w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1327w1330w1333w1336w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1348w1351w1354w1357w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1369w1372w1375w1378w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1390w1393w1396w1399w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1411w1414w1417w1420w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1432w1435w1438w1441w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_lg_w1453w1456w1459w1462w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w154w157w160w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w175w178w181w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w196w199w202w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w217w220w223w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_merlin_multiplexer_0003_wideor1_28_dataout : STD_LOGIC;
+ SIGNAL wire_w_sink0_channel_range1464w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_channel_range1486w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_channel_range1507w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_channel_range1528w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_channel_range1549w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_channel_range1570w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_channel_range1591w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range14w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range225w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range246w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range267w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range288w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range309w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range330w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range351w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range372w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range393w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range414w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range435w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range456w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range477w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range498w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range519w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range540w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range561w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range582w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range603w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range624w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range57w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range645w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range666w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range687w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range708w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range729w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range750w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range771w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range792w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range813w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range834w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range78w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range855w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range876w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range897w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range918w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range939w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range960w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range981w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1002w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1023w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1044w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range99w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1065w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1086w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1128w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1149w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1170w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1191w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1212w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1233w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1254w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range120w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1275w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1296w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1317w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1338w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1359w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1380w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1401w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1422w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range1443w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range141w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range162w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range183w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink0_data_range204w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_channel_range1466w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_channel_range1488w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_channel_range1509w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_channel_range1530w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_channel_range1551w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_channel_range1572w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_channel_range1593w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range16w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range227w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range248w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range269w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range290w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range311w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range332w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range353w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range374w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range395w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range416w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range38w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range437w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range458w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range479w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range500w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range521w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range542w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range563w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range584w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range605w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range626w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range59w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range647w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range668w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range689w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range710w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range731w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range752w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range773w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range794w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range815w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range836w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range80w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range857w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range878w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range899w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range920w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range941w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range962w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range983w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1004w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1025w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1046w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1067w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1088w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1130w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1151w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1172w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1193w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1235w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1256w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range122w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1277w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1298w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1319w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1340w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1361w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1382w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1403w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1424w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range1445w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range143w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range164w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range185w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink1_data_range206w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_channel_range1469w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_channel_range1491w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_channel_range1512w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_channel_range1533w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_channel_range1554w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_channel_range1575w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_channel_range1596w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range19w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range230w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range251w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range272w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range293w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range314w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range335w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range356w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range377w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range398w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range419w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range440w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range461w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range482w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range503w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range524w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range545w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range566w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range587w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range608w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range629w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range650w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range671w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range692w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range713w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range734w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range755w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range776w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range797w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range818w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range839w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range83w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range860w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range881w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range902w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range923w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range944w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range965w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range986w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1007w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1028w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1049w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range104w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1070w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1091w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1112w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1133w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1154w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1175w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1196w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1217w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1238w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1259w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range125w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1280w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1301w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1322w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1343w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1364w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1385w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1406w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1427w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range1448w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range146w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range167w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range188w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink2_data_range209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_channel_range1472w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_channel_range1494w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_channel_range1515w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_channel_range1536w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_channel_range1557w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_channel_range1578w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_channel_range1599w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range22w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range233w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range254w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range275w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range296w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range317w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range338w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range359w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range380w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range401w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range422w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range44w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range443w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range464w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range485w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range506w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range527w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range548w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range569w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range590w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range611w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range632w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range65w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range653w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range674w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range695w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range716w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range737w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range758w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range779w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range800w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range821w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range842w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range86w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range863w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range884w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range905w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range926w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range947w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range968w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range989w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1010w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1031w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1052w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1073w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1094w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1115w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1136w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1157w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1178w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1199w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1220w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1241w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1262w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range128w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1283w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1304w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1325w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1346w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1367w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1388w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1409w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1430w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range1451w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range149w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range170w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range191w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink3_data_range212w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_channel_range1475w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_channel_range1497w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_channel_range1518w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_channel_range1539w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_channel_range1560w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_channel_range1581w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_channel_range1602w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range25w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range236w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range257w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range278w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range299w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range320w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range341w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range362w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range383w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range404w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range425w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range47w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range446w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range467w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range488w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range509w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range530w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range551w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range572w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range593w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range614w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range635w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range68w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range656w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range677w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range698w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range719w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range740w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range761w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range782w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range803w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range824w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range845w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range89w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range866w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range887w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range908w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range929w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range950w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range971w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range992w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1013w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1034w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1055w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1076w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1097w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1118w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1160w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1181w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1202w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1223w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1244w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1265w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1286w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1307w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1328w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1349w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1370w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1391w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1412w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1433w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range1454w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range152w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range173w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range194w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink4_data_range215w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_channel_range1478w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_channel_range1500w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_channel_range1521w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_channel_range1542w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_channel_range1563w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_channel_range1584w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_channel_range1605w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range28w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range239w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range260w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range281w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range302w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range323w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range344w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range365w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range386w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range407w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range428w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range50w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range449w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range470w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range491w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range512w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range533w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range554w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range575w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range596w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range617w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range638w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range71w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range659w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range701w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range722w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range743w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range764w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range785w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range806w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range827w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range848w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range92w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range869w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range890w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range911w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range932w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range953w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range974w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range995w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1016w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1037w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1058w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1079w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1121w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1142w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1163w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1184w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1205w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1226w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1247w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1268w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range134w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1289w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1310w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1331w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1352w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1373w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1394w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1415w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1436w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range1457w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range155w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range176w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range197w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink5_data_range218w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_channel_range1481w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_channel_range1503w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_channel_range1524w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_channel_range1545w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_channel_range1566w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_channel_range1587w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_channel_range1608w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range31w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range242w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range263w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range284w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range305w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range326w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range347w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range368w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range389w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range410w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range431w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range53w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range452w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range473w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range494w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range515w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range536w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range557w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range578w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range599w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range620w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range641w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range74w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range662w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range683w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range704w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range725w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range746w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range767w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range788w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range809w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range830w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range851w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range95w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range872w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range893w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range914w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range935w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range956w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range977w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range998w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1019w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1040w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1061w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range116w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1082w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1124w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1145w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1166w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1208w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1229w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1250w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1271w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range137w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1292w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1313w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1334w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1355w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1376w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1397w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1418w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1439w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range1460w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range158w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range200w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink6_data_range221w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+ wire_w_lg_sink0_valid1465w(0) <= sink0_valid AND wire_w_sink0_channel_range1464w(0);
+ wire_w_lg_sink0_valid1487w(0) <= sink0_valid AND wire_w_sink0_channel_range1486w(0);
+ wire_w_lg_sink0_valid1508w(0) <= sink0_valid AND wire_w_sink0_channel_range1507w(0);
+ wire_w_lg_sink0_valid1529w(0) <= sink0_valid AND wire_w_sink0_channel_range1528w(0);
+ wire_w_lg_sink0_valid1550w(0) <= sink0_valid AND wire_w_sink0_channel_range1549w(0);
+ wire_w_lg_sink0_valid1571w(0) <= sink0_valid AND wire_w_sink0_channel_range1570w(0);
+ wire_w_lg_sink0_valid1592w(0) <= sink0_valid AND wire_w_sink0_channel_range1591w(0);
+ wire_w_lg_sink0_valid15w(0) <= sink0_valid AND wire_w_sink0_data_range14w(0);
+ wire_w_lg_sink0_valid226w(0) <= sink0_valid AND wire_w_sink0_data_range225w(0);
+ wire_w_lg_sink0_valid247w(0) <= sink0_valid AND wire_w_sink0_data_range246w(0);
+ wire_w_lg_sink0_valid268w(0) <= sink0_valid AND wire_w_sink0_data_range267w(0);
+ wire_w_lg_sink0_valid289w(0) <= sink0_valid AND wire_w_sink0_data_range288w(0);
+ wire_w_lg_sink0_valid310w(0) <= sink0_valid AND wire_w_sink0_data_range309w(0);
+ wire_w_lg_sink0_valid331w(0) <= sink0_valid AND wire_w_sink0_data_range330w(0);
+ wire_w_lg_sink0_valid352w(0) <= sink0_valid AND wire_w_sink0_data_range351w(0);
+ wire_w_lg_sink0_valid373w(0) <= sink0_valid AND wire_w_sink0_data_range372w(0);
+ wire_w_lg_sink0_valid394w(0) <= sink0_valid AND wire_w_sink0_data_range393w(0);
+ wire_w_lg_sink0_valid415w(0) <= sink0_valid AND wire_w_sink0_data_range414w(0);
+ wire_w_lg_sink0_valid37w(0) <= sink0_valid AND wire_w_sink0_data_range36w(0);
+ wire_w_lg_sink0_valid436w(0) <= sink0_valid AND wire_w_sink0_data_range435w(0);
+ wire_w_lg_sink0_valid457w(0) <= sink0_valid AND wire_w_sink0_data_range456w(0);
+ wire_w_lg_sink0_valid478w(0) <= sink0_valid AND wire_w_sink0_data_range477w(0);
+ wire_w_lg_sink0_valid499w(0) <= sink0_valid AND wire_w_sink0_data_range498w(0);
+ wire_w_lg_sink0_valid520w(0) <= sink0_valid AND wire_w_sink0_data_range519w(0);
+ wire_w_lg_sink0_valid541w(0) <= sink0_valid AND wire_w_sink0_data_range540w(0);
+ wire_w_lg_sink0_valid562w(0) <= sink0_valid AND wire_w_sink0_data_range561w(0);
+ wire_w_lg_sink0_valid583w(0) <= sink0_valid AND wire_w_sink0_data_range582w(0);
+ wire_w_lg_sink0_valid604w(0) <= sink0_valid AND wire_w_sink0_data_range603w(0);
+ wire_w_lg_sink0_valid625w(0) <= sink0_valid AND wire_w_sink0_data_range624w(0);
+ wire_w_lg_sink0_valid58w(0) <= sink0_valid AND wire_w_sink0_data_range57w(0);
+ wire_w_lg_sink0_valid646w(0) <= sink0_valid AND wire_w_sink0_data_range645w(0);
+ wire_w_lg_sink0_valid667w(0) <= sink0_valid AND wire_w_sink0_data_range666w(0);
+ wire_w_lg_sink0_valid688w(0) <= sink0_valid AND wire_w_sink0_data_range687w(0);
+ wire_w_lg_sink0_valid709w(0) <= sink0_valid AND wire_w_sink0_data_range708w(0);
+ wire_w_lg_sink0_valid730w(0) <= sink0_valid AND wire_w_sink0_data_range729w(0);
+ wire_w_lg_sink0_valid751w(0) <= sink0_valid AND wire_w_sink0_data_range750w(0);
+ wire_w_lg_sink0_valid772w(0) <= sink0_valid AND wire_w_sink0_data_range771w(0);
+ wire_w_lg_sink0_valid793w(0) <= sink0_valid AND wire_w_sink0_data_range792w(0);
+ wire_w_lg_sink0_valid814w(0) <= sink0_valid AND wire_w_sink0_data_range813w(0);
+ wire_w_lg_sink0_valid835w(0) <= sink0_valid AND wire_w_sink0_data_range834w(0);
+ wire_w_lg_sink0_valid79w(0) <= sink0_valid AND wire_w_sink0_data_range78w(0);
+ wire_w_lg_sink0_valid856w(0) <= sink0_valid AND wire_w_sink0_data_range855w(0);
+ wire_w_lg_sink0_valid877w(0) <= sink0_valid AND wire_w_sink0_data_range876w(0);
+ wire_w_lg_sink0_valid898w(0) <= sink0_valid AND wire_w_sink0_data_range897w(0);
+ wire_w_lg_sink0_valid919w(0) <= sink0_valid AND wire_w_sink0_data_range918w(0);
+ wire_w_lg_sink0_valid940w(0) <= sink0_valid AND wire_w_sink0_data_range939w(0);
+ wire_w_lg_sink0_valid961w(0) <= sink0_valid AND wire_w_sink0_data_range960w(0);
+ wire_w_lg_sink0_valid982w(0) <= sink0_valid AND wire_w_sink0_data_range981w(0);
+ wire_w_lg_sink0_valid1003w(0) <= sink0_valid AND wire_w_sink0_data_range1002w(0);
+ wire_w_lg_sink0_valid1024w(0) <= sink0_valid AND wire_w_sink0_data_range1023w(0);
+ wire_w_lg_sink0_valid1045w(0) <= sink0_valid AND wire_w_sink0_data_range1044w(0);
+ wire_w_lg_sink0_valid100w(0) <= sink0_valid AND wire_w_sink0_data_range99w(0);
+ wire_w_lg_sink0_valid1066w(0) <= sink0_valid AND wire_w_sink0_data_range1065w(0);
+ wire_w_lg_sink0_valid1087w(0) <= sink0_valid AND wire_w_sink0_data_range1086w(0);
+ wire_w_lg_sink0_valid1108w(0) <= sink0_valid AND wire_w_sink0_data_range1107w(0);
+ wire_w_lg_sink0_valid1129w(0) <= sink0_valid AND wire_w_sink0_data_range1128w(0);
+ wire_w_lg_sink0_valid1150w(0) <= sink0_valid AND wire_w_sink0_data_range1149w(0);
+ wire_w_lg_sink0_valid1171w(0) <= sink0_valid AND wire_w_sink0_data_range1170w(0);
+ wire_w_lg_sink0_valid1192w(0) <= sink0_valid AND wire_w_sink0_data_range1191w(0);
+ wire_w_lg_sink0_valid1213w(0) <= sink0_valid AND wire_w_sink0_data_range1212w(0);
+ wire_w_lg_sink0_valid1234w(0) <= sink0_valid AND wire_w_sink0_data_range1233w(0);
+ wire_w_lg_sink0_valid1255w(0) <= sink0_valid AND wire_w_sink0_data_range1254w(0);
+ wire_w_lg_sink0_valid121w(0) <= sink0_valid AND wire_w_sink0_data_range120w(0);
+ wire_w_lg_sink0_valid1276w(0) <= sink0_valid AND wire_w_sink0_data_range1275w(0);
+ wire_w_lg_sink0_valid1297w(0) <= sink0_valid AND wire_w_sink0_data_range1296w(0);
+ wire_w_lg_sink0_valid1318w(0) <= sink0_valid AND wire_w_sink0_data_range1317w(0);
+ wire_w_lg_sink0_valid1339w(0) <= sink0_valid AND wire_w_sink0_data_range1338w(0);
+ wire_w_lg_sink0_valid1360w(0) <= sink0_valid AND wire_w_sink0_data_range1359w(0);
+ wire_w_lg_sink0_valid1381w(0) <= sink0_valid AND wire_w_sink0_data_range1380w(0);
+ wire_w_lg_sink0_valid1402w(0) <= sink0_valid AND wire_w_sink0_data_range1401w(0);
+ wire_w_lg_sink0_valid1423w(0) <= sink0_valid AND wire_w_sink0_data_range1422w(0);
+ wire_w_lg_sink0_valid1444w(0) <= sink0_valid AND wire_w_sink0_data_range1443w(0);
+ wire_w_lg_sink0_valid142w(0) <= sink0_valid AND wire_w_sink0_data_range141w(0);
+ wire_w_lg_sink0_valid163w(0) <= sink0_valid AND wire_w_sink0_data_range162w(0);
+ wire_w_lg_sink0_valid184w(0) <= sink0_valid AND wire_w_sink0_data_range183w(0);
+ wire_w_lg_sink0_valid205w(0) <= sink0_valid AND wire_w_sink0_data_range204w(0);
+ wire_w_lg_sink1_valid1467w(0) <= sink1_valid AND wire_w_sink1_channel_range1466w(0);
+ wire_w_lg_sink1_valid1489w(0) <= sink1_valid AND wire_w_sink1_channel_range1488w(0);
+ wire_w_lg_sink1_valid1510w(0) <= sink1_valid AND wire_w_sink1_channel_range1509w(0);
+ wire_w_lg_sink1_valid1531w(0) <= sink1_valid AND wire_w_sink1_channel_range1530w(0);
+ wire_w_lg_sink1_valid1552w(0) <= sink1_valid AND wire_w_sink1_channel_range1551w(0);
+ wire_w_lg_sink1_valid1573w(0) <= sink1_valid AND wire_w_sink1_channel_range1572w(0);
+ wire_w_lg_sink1_valid1594w(0) <= sink1_valid AND wire_w_sink1_channel_range1593w(0);
+ wire_w_lg_sink1_valid17w(0) <= sink1_valid AND wire_w_sink1_data_range16w(0);
+ wire_w_lg_sink1_valid228w(0) <= sink1_valid AND wire_w_sink1_data_range227w(0);
+ wire_w_lg_sink1_valid249w(0) <= sink1_valid AND wire_w_sink1_data_range248w(0);
+ wire_w_lg_sink1_valid270w(0) <= sink1_valid AND wire_w_sink1_data_range269w(0);
+ wire_w_lg_sink1_valid291w(0) <= sink1_valid AND wire_w_sink1_data_range290w(0);
+ wire_w_lg_sink1_valid312w(0) <= sink1_valid AND wire_w_sink1_data_range311w(0);
+ wire_w_lg_sink1_valid333w(0) <= sink1_valid AND wire_w_sink1_data_range332w(0);
+ wire_w_lg_sink1_valid354w(0) <= sink1_valid AND wire_w_sink1_data_range353w(0);
+ wire_w_lg_sink1_valid375w(0) <= sink1_valid AND wire_w_sink1_data_range374w(0);
+ wire_w_lg_sink1_valid396w(0) <= sink1_valid AND wire_w_sink1_data_range395w(0);
+ wire_w_lg_sink1_valid417w(0) <= sink1_valid AND wire_w_sink1_data_range416w(0);
+ wire_w_lg_sink1_valid39w(0) <= sink1_valid AND wire_w_sink1_data_range38w(0);
+ wire_w_lg_sink1_valid438w(0) <= sink1_valid AND wire_w_sink1_data_range437w(0);
+ wire_w_lg_sink1_valid459w(0) <= sink1_valid AND wire_w_sink1_data_range458w(0);
+ wire_w_lg_sink1_valid480w(0) <= sink1_valid AND wire_w_sink1_data_range479w(0);
+ wire_w_lg_sink1_valid501w(0) <= sink1_valid AND wire_w_sink1_data_range500w(0);
+ wire_w_lg_sink1_valid522w(0) <= sink1_valid AND wire_w_sink1_data_range521w(0);
+ wire_w_lg_sink1_valid543w(0) <= sink1_valid AND wire_w_sink1_data_range542w(0);
+ wire_w_lg_sink1_valid564w(0) <= sink1_valid AND wire_w_sink1_data_range563w(0);
+ wire_w_lg_sink1_valid585w(0) <= sink1_valid AND wire_w_sink1_data_range584w(0);
+ wire_w_lg_sink1_valid606w(0) <= sink1_valid AND wire_w_sink1_data_range605w(0);
+ wire_w_lg_sink1_valid627w(0) <= sink1_valid AND wire_w_sink1_data_range626w(0);
+ wire_w_lg_sink1_valid60w(0) <= sink1_valid AND wire_w_sink1_data_range59w(0);
+ wire_w_lg_sink1_valid648w(0) <= sink1_valid AND wire_w_sink1_data_range647w(0);
+ wire_w_lg_sink1_valid669w(0) <= sink1_valid AND wire_w_sink1_data_range668w(0);
+ wire_w_lg_sink1_valid690w(0) <= sink1_valid AND wire_w_sink1_data_range689w(0);
+ wire_w_lg_sink1_valid711w(0) <= sink1_valid AND wire_w_sink1_data_range710w(0);
+ wire_w_lg_sink1_valid732w(0) <= sink1_valid AND wire_w_sink1_data_range731w(0);
+ wire_w_lg_sink1_valid753w(0) <= sink1_valid AND wire_w_sink1_data_range752w(0);
+ wire_w_lg_sink1_valid774w(0) <= sink1_valid AND wire_w_sink1_data_range773w(0);
+ wire_w_lg_sink1_valid795w(0) <= sink1_valid AND wire_w_sink1_data_range794w(0);
+ wire_w_lg_sink1_valid816w(0) <= sink1_valid AND wire_w_sink1_data_range815w(0);
+ wire_w_lg_sink1_valid837w(0) <= sink1_valid AND wire_w_sink1_data_range836w(0);
+ wire_w_lg_sink1_valid81w(0) <= sink1_valid AND wire_w_sink1_data_range80w(0);
+ wire_w_lg_sink1_valid858w(0) <= sink1_valid AND wire_w_sink1_data_range857w(0);
+ wire_w_lg_sink1_valid879w(0) <= sink1_valid AND wire_w_sink1_data_range878w(0);
+ wire_w_lg_sink1_valid900w(0) <= sink1_valid AND wire_w_sink1_data_range899w(0);
+ wire_w_lg_sink1_valid921w(0) <= sink1_valid AND wire_w_sink1_data_range920w(0);
+ wire_w_lg_sink1_valid942w(0) <= sink1_valid AND wire_w_sink1_data_range941w(0);
+ wire_w_lg_sink1_valid963w(0) <= sink1_valid AND wire_w_sink1_data_range962w(0);
+ wire_w_lg_sink1_valid984w(0) <= sink1_valid AND wire_w_sink1_data_range983w(0);
+ wire_w_lg_sink1_valid1005w(0) <= sink1_valid AND wire_w_sink1_data_range1004w(0);
+ wire_w_lg_sink1_valid1026w(0) <= sink1_valid AND wire_w_sink1_data_range1025w(0);
+ wire_w_lg_sink1_valid1047w(0) <= sink1_valid AND wire_w_sink1_data_range1046w(0);
+ wire_w_lg_sink1_valid102w(0) <= sink1_valid AND wire_w_sink1_data_range101w(0);
+ wire_w_lg_sink1_valid1068w(0) <= sink1_valid AND wire_w_sink1_data_range1067w(0);
+ wire_w_lg_sink1_valid1089w(0) <= sink1_valid AND wire_w_sink1_data_range1088w(0);
+ wire_w_lg_sink1_valid1110w(0) <= sink1_valid AND wire_w_sink1_data_range1109w(0);
+ wire_w_lg_sink1_valid1131w(0) <= sink1_valid AND wire_w_sink1_data_range1130w(0);
+ wire_w_lg_sink1_valid1152w(0) <= sink1_valid AND wire_w_sink1_data_range1151w(0);
+ wire_w_lg_sink1_valid1173w(0) <= sink1_valid AND wire_w_sink1_data_range1172w(0);
+ wire_w_lg_sink1_valid1194w(0) <= sink1_valid AND wire_w_sink1_data_range1193w(0);
+ wire_w_lg_sink1_valid1215w(0) <= sink1_valid AND wire_w_sink1_data_range1214w(0);
+ wire_w_lg_sink1_valid1236w(0) <= sink1_valid AND wire_w_sink1_data_range1235w(0);
+ wire_w_lg_sink1_valid1257w(0) <= sink1_valid AND wire_w_sink1_data_range1256w(0);
+ wire_w_lg_sink1_valid123w(0) <= sink1_valid AND wire_w_sink1_data_range122w(0);
+ wire_w_lg_sink1_valid1278w(0) <= sink1_valid AND wire_w_sink1_data_range1277w(0);
+ wire_w_lg_sink1_valid1299w(0) <= sink1_valid AND wire_w_sink1_data_range1298w(0);
+ wire_w_lg_sink1_valid1320w(0) <= sink1_valid AND wire_w_sink1_data_range1319w(0);
+ wire_w_lg_sink1_valid1341w(0) <= sink1_valid AND wire_w_sink1_data_range1340w(0);
+ wire_w_lg_sink1_valid1362w(0) <= sink1_valid AND wire_w_sink1_data_range1361w(0);
+ wire_w_lg_sink1_valid1383w(0) <= sink1_valid AND wire_w_sink1_data_range1382w(0);
+ wire_w_lg_sink1_valid1404w(0) <= sink1_valid AND wire_w_sink1_data_range1403w(0);
+ wire_w_lg_sink1_valid1425w(0) <= sink1_valid AND wire_w_sink1_data_range1424w(0);
+ wire_w_lg_sink1_valid1446w(0) <= sink1_valid AND wire_w_sink1_data_range1445w(0);
+ wire_w_lg_sink1_valid144w(0) <= sink1_valid AND wire_w_sink1_data_range143w(0);
+ wire_w_lg_sink1_valid165w(0) <= sink1_valid AND wire_w_sink1_data_range164w(0);
+ wire_w_lg_sink1_valid186w(0) <= sink1_valid AND wire_w_sink1_data_range185w(0);
+ wire_w_lg_sink1_valid207w(0) <= sink1_valid AND wire_w_sink1_data_range206w(0);
+ wire_w_lg_sink2_valid1470w(0) <= sink2_valid AND wire_w_sink2_channel_range1469w(0);
+ wire_w_lg_sink2_valid1492w(0) <= sink2_valid AND wire_w_sink2_channel_range1491w(0);
+ wire_w_lg_sink2_valid1513w(0) <= sink2_valid AND wire_w_sink2_channel_range1512w(0);
+ wire_w_lg_sink2_valid1534w(0) <= sink2_valid AND wire_w_sink2_channel_range1533w(0);
+ wire_w_lg_sink2_valid1555w(0) <= sink2_valid AND wire_w_sink2_channel_range1554w(0);
+ wire_w_lg_sink2_valid1576w(0) <= sink2_valid AND wire_w_sink2_channel_range1575w(0);
+ wire_w_lg_sink2_valid1597w(0) <= sink2_valid AND wire_w_sink2_channel_range1596w(0);
+ wire_w_lg_sink2_valid20w(0) <= sink2_valid AND wire_w_sink2_data_range19w(0);
+ wire_w_lg_sink2_valid231w(0) <= sink2_valid AND wire_w_sink2_data_range230w(0);
+ wire_w_lg_sink2_valid252w(0) <= sink2_valid AND wire_w_sink2_data_range251w(0);
+ wire_w_lg_sink2_valid273w(0) <= sink2_valid AND wire_w_sink2_data_range272w(0);
+ wire_w_lg_sink2_valid294w(0) <= sink2_valid AND wire_w_sink2_data_range293w(0);
+ wire_w_lg_sink2_valid315w(0) <= sink2_valid AND wire_w_sink2_data_range314w(0);
+ wire_w_lg_sink2_valid336w(0) <= sink2_valid AND wire_w_sink2_data_range335w(0);
+ wire_w_lg_sink2_valid357w(0) <= sink2_valid AND wire_w_sink2_data_range356w(0);
+ wire_w_lg_sink2_valid378w(0) <= sink2_valid AND wire_w_sink2_data_range377w(0);
+ wire_w_lg_sink2_valid399w(0) <= sink2_valid AND wire_w_sink2_data_range398w(0);
+ wire_w_lg_sink2_valid420w(0) <= sink2_valid AND wire_w_sink2_data_range419w(0);
+ wire_w_lg_sink2_valid42w(0) <= sink2_valid AND wire_w_sink2_data_range41w(0);
+ wire_w_lg_sink2_valid441w(0) <= sink2_valid AND wire_w_sink2_data_range440w(0);
+ wire_w_lg_sink2_valid462w(0) <= sink2_valid AND wire_w_sink2_data_range461w(0);
+ wire_w_lg_sink2_valid483w(0) <= sink2_valid AND wire_w_sink2_data_range482w(0);
+ wire_w_lg_sink2_valid504w(0) <= sink2_valid AND wire_w_sink2_data_range503w(0);
+ wire_w_lg_sink2_valid525w(0) <= sink2_valid AND wire_w_sink2_data_range524w(0);
+ wire_w_lg_sink2_valid546w(0) <= sink2_valid AND wire_w_sink2_data_range545w(0);
+ wire_w_lg_sink2_valid567w(0) <= sink2_valid AND wire_w_sink2_data_range566w(0);
+ wire_w_lg_sink2_valid588w(0) <= sink2_valid AND wire_w_sink2_data_range587w(0);
+ wire_w_lg_sink2_valid609w(0) <= sink2_valid AND wire_w_sink2_data_range608w(0);
+ wire_w_lg_sink2_valid630w(0) <= sink2_valid AND wire_w_sink2_data_range629w(0);
+ wire_w_lg_sink2_valid63w(0) <= sink2_valid AND wire_w_sink2_data_range62w(0);
+ wire_w_lg_sink2_valid651w(0) <= sink2_valid AND wire_w_sink2_data_range650w(0);
+ wire_w_lg_sink2_valid672w(0) <= sink2_valid AND wire_w_sink2_data_range671w(0);
+ wire_w_lg_sink2_valid693w(0) <= sink2_valid AND wire_w_sink2_data_range692w(0);
+ wire_w_lg_sink2_valid714w(0) <= sink2_valid AND wire_w_sink2_data_range713w(0);
+ wire_w_lg_sink2_valid735w(0) <= sink2_valid AND wire_w_sink2_data_range734w(0);
+ wire_w_lg_sink2_valid756w(0) <= sink2_valid AND wire_w_sink2_data_range755w(0);
+ wire_w_lg_sink2_valid777w(0) <= sink2_valid AND wire_w_sink2_data_range776w(0);
+ wire_w_lg_sink2_valid798w(0) <= sink2_valid AND wire_w_sink2_data_range797w(0);
+ wire_w_lg_sink2_valid819w(0) <= sink2_valid AND wire_w_sink2_data_range818w(0);
+ wire_w_lg_sink2_valid840w(0) <= sink2_valid AND wire_w_sink2_data_range839w(0);
+ wire_w_lg_sink2_valid84w(0) <= sink2_valid AND wire_w_sink2_data_range83w(0);
+ wire_w_lg_sink2_valid861w(0) <= sink2_valid AND wire_w_sink2_data_range860w(0);
+ wire_w_lg_sink2_valid882w(0) <= sink2_valid AND wire_w_sink2_data_range881w(0);
+ wire_w_lg_sink2_valid903w(0) <= sink2_valid AND wire_w_sink2_data_range902w(0);
+ wire_w_lg_sink2_valid924w(0) <= sink2_valid AND wire_w_sink2_data_range923w(0);
+ wire_w_lg_sink2_valid945w(0) <= sink2_valid AND wire_w_sink2_data_range944w(0);
+ wire_w_lg_sink2_valid966w(0) <= sink2_valid AND wire_w_sink2_data_range965w(0);
+ wire_w_lg_sink2_valid987w(0) <= sink2_valid AND wire_w_sink2_data_range986w(0);
+ wire_w_lg_sink2_valid1008w(0) <= sink2_valid AND wire_w_sink2_data_range1007w(0);
+ wire_w_lg_sink2_valid1029w(0) <= sink2_valid AND wire_w_sink2_data_range1028w(0);
+ wire_w_lg_sink2_valid1050w(0) <= sink2_valid AND wire_w_sink2_data_range1049w(0);
+ wire_w_lg_sink2_valid105w(0) <= sink2_valid AND wire_w_sink2_data_range104w(0);
+ wire_w_lg_sink2_valid1071w(0) <= sink2_valid AND wire_w_sink2_data_range1070w(0);
+ wire_w_lg_sink2_valid1092w(0) <= sink2_valid AND wire_w_sink2_data_range1091w(0);
+ wire_w_lg_sink2_valid1113w(0) <= sink2_valid AND wire_w_sink2_data_range1112w(0);
+ wire_w_lg_sink2_valid1134w(0) <= sink2_valid AND wire_w_sink2_data_range1133w(0);
+ wire_w_lg_sink2_valid1155w(0) <= sink2_valid AND wire_w_sink2_data_range1154w(0);
+ wire_w_lg_sink2_valid1176w(0) <= sink2_valid AND wire_w_sink2_data_range1175w(0);
+ wire_w_lg_sink2_valid1197w(0) <= sink2_valid AND wire_w_sink2_data_range1196w(0);
+ wire_w_lg_sink2_valid1218w(0) <= sink2_valid AND wire_w_sink2_data_range1217w(0);
+ wire_w_lg_sink2_valid1239w(0) <= sink2_valid AND wire_w_sink2_data_range1238w(0);
+ wire_w_lg_sink2_valid1260w(0) <= sink2_valid AND wire_w_sink2_data_range1259w(0);
+ wire_w_lg_sink2_valid126w(0) <= sink2_valid AND wire_w_sink2_data_range125w(0);
+ wire_w_lg_sink2_valid1281w(0) <= sink2_valid AND wire_w_sink2_data_range1280w(0);
+ wire_w_lg_sink2_valid1302w(0) <= sink2_valid AND wire_w_sink2_data_range1301w(0);
+ wire_w_lg_sink2_valid1323w(0) <= sink2_valid AND wire_w_sink2_data_range1322w(0);
+ wire_w_lg_sink2_valid1344w(0) <= sink2_valid AND wire_w_sink2_data_range1343w(0);
+ wire_w_lg_sink2_valid1365w(0) <= sink2_valid AND wire_w_sink2_data_range1364w(0);
+ wire_w_lg_sink2_valid1386w(0) <= sink2_valid AND wire_w_sink2_data_range1385w(0);
+ wire_w_lg_sink2_valid1407w(0) <= sink2_valid AND wire_w_sink2_data_range1406w(0);
+ wire_w_lg_sink2_valid1428w(0) <= sink2_valid AND wire_w_sink2_data_range1427w(0);
+ wire_w_lg_sink2_valid1449w(0) <= sink2_valid AND wire_w_sink2_data_range1448w(0);
+ wire_w_lg_sink2_valid147w(0) <= sink2_valid AND wire_w_sink2_data_range146w(0);
+ wire_w_lg_sink2_valid168w(0) <= sink2_valid AND wire_w_sink2_data_range167w(0);
+ wire_w_lg_sink2_valid189w(0) <= sink2_valid AND wire_w_sink2_data_range188w(0);
+ wire_w_lg_sink2_valid210w(0) <= sink2_valid AND wire_w_sink2_data_range209w(0);
+ wire_w_lg_sink3_valid1473w(0) <= sink3_valid AND wire_w_sink3_channel_range1472w(0);
+ wire_w_lg_sink3_valid1495w(0) <= sink3_valid AND wire_w_sink3_channel_range1494w(0);
+ wire_w_lg_sink3_valid1516w(0) <= sink3_valid AND wire_w_sink3_channel_range1515w(0);
+ wire_w_lg_sink3_valid1537w(0) <= sink3_valid AND wire_w_sink3_channel_range1536w(0);
+ wire_w_lg_sink3_valid1558w(0) <= sink3_valid AND wire_w_sink3_channel_range1557w(0);
+ wire_w_lg_sink3_valid1579w(0) <= sink3_valid AND wire_w_sink3_channel_range1578w(0);
+ wire_w_lg_sink3_valid1600w(0) <= sink3_valid AND wire_w_sink3_channel_range1599w(0);
+ wire_w_lg_sink3_valid23w(0) <= sink3_valid AND wire_w_sink3_data_range22w(0);
+ wire_w_lg_sink3_valid234w(0) <= sink3_valid AND wire_w_sink3_data_range233w(0);
+ wire_w_lg_sink3_valid255w(0) <= sink3_valid AND wire_w_sink3_data_range254w(0);
+ wire_w_lg_sink3_valid276w(0) <= sink3_valid AND wire_w_sink3_data_range275w(0);
+ wire_w_lg_sink3_valid297w(0) <= sink3_valid AND wire_w_sink3_data_range296w(0);
+ wire_w_lg_sink3_valid318w(0) <= sink3_valid AND wire_w_sink3_data_range317w(0);
+ wire_w_lg_sink3_valid339w(0) <= sink3_valid AND wire_w_sink3_data_range338w(0);
+ wire_w_lg_sink3_valid360w(0) <= sink3_valid AND wire_w_sink3_data_range359w(0);
+ wire_w_lg_sink3_valid381w(0) <= sink3_valid AND wire_w_sink3_data_range380w(0);
+ wire_w_lg_sink3_valid402w(0) <= sink3_valid AND wire_w_sink3_data_range401w(0);
+ wire_w_lg_sink3_valid423w(0) <= sink3_valid AND wire_w_sink3_data_range422w(0);
+ wire_w_lg_sink3_valid45w(0) <= sink3_valid AND wire_w_sink3_data_range44w(0);
+ wire_w_lg_sink3_valid444w(0) <= sink3_valid AND wire_w_sink3_data_range443w(0);
+ wire_w_lg_sink3_valid465w(0) <= sink3_valid AND wire_w_sink3_data_range464w(0);
+ wire_w_lg_sink3_valid486w(0) <= sink3_valid AND wire_w_sink3_data_range485w(0);
+ wire_w_lg_sink3_valid507w(0) <= sink3_valid AND wire_w_sink3_data_range506w(0);
+ wire_w_lg_sink3_valid528w(0) <= sink3_valid AND wire_w_sink3_data_range527w(0);
+ wire_w_lg_sink3_valid549w(0) <= sink3_valid AND wire_w_sink3_data_range548w(0);
+ wire_w_lg_sink3_valid570w(0) <= sink3_valid AND wire_w_sink3_data_range569w(0);
+ wire_w_lg_sink3_valid591w(0) <= sink3_valid AND wire_w_sink3_data_range590w(0);
+ wire_w_lg_sink3_valid612w(0) <= sink3_valid AND wire_w_sink3_data_range611w(0);
+ wire_w_lg_sink3_valid633w(0) <= sink3_valid AND wire_w_sink3_data_range632w(0);
+ wire_w_lg_sink3_valid66w(0) <= sink3_valid AND wire_w_sink3_data_range65w(0);
+ wire_w_lg_sink3_valid654w(0) <= sink3_valid AND wire_w_sink3_data_range653w(0);
+ wire_w_lg_sink3_valid675w(0) <= sink3_valid AND wire_w_sink3_data_range674w(0);
+ wire_w_lg_sink3_valid696w(0) <= sink3_valid AND wire_w_sink3_data_range695w(0);
+ wire_w_lg_sink3_valid717w(0) <= sink3_valid AND wire_w_sink3_data_range716w(0);
+ wire_w_lg_sink3_valid738w(0) <= sink3_valid AND wire_w_sink3_data_range737w(0);
+ wire_w_lg_sink3_valid759w(0) <= sink3_valid AND wire_w_sink3_data_range758w(0);
+ wire_w_lg_sink3_valid780w(0) <= sink3_valid AND wire_w_sink3_data_range779w(0);
+ wire_w_lg_sink3_valid801w(0) <= sink3_valid AND wire_w_sink3_data_range800w(0);
+ wire_w_lg_sink3_valid822w(0) <= sink3_valid AND wire_w_sink3_data_range821w(0);
+ wire_w_lg_sink3_valid843w(0) <= sink3_valid AND wire_w_sink3_data_range842w(0);
+ wire_w_lg_sink3_valid87w(0) <= sink3_valid AND wire_w_sink3_data_range86w(0);
+ wire_w_lg_sink3_valid864w(0) <= sink3_valid AND wire_w_sink3_data_range863w(0);
+ wire_w_lg_sink3_valid885w(0) <= sink3_valid AND wire_w_sink3_data_range884w(0);
+ wire_w_lg_sink3_valid906w(0) <= sink3_valid AND wire_w_sink3_data_range905w(0);
+ wire_w_lg_sink3_valid927w(0) <= sink3_valid AND wire_w_sink3_data_range926w(0);
+ wire_w_lg_sink3_valid948w(0) <= sink3_valid AND wire_w_sink3_data_range947w(0);
+ wire_w_lg_sink3_valid969w(0) <= sink3_valid AND wire_w_sink3_data_range968w(0);
+ wire_w_lg_sink3_valid990w(0) <= sink3_valid AND wire_w_sink3_data_range989w(0);
+ wire_w_lg_sink3_valid1011w(0) <= sink3_valid AND wire_w_sink3_data_range1010w(0);
+ wire_w_lg_sink3_valid1032w(0) <= sink3_valid AND wire_w_sink3_data_range1031w(0);
+ wire_w_lg_sink3_valid1053w(0) <= sink3_valid AND wire_w_sink3_data_range1052w(0);
+ wire_w_lg_sink3_valid108w(0) <= sink3_valid AND wire_w_sink3_data_range107w(0);
+ wire_w_lg_sink3_valid1074w(0) <= sink3_valid AND wire_w_sink3_data_range1073w(0);
+ wire_w_lg_sink3_valid1095w(0) <= sink3_valid AND wire_w_sink3_data_range1094w(0);
+ wire_w_lg_sink3_valid1116w(0) <= sink3_valid AND wire_w_sink3_data_range1115w(0);
+ wire_w_lg_sink3_valid1137w(0) <= sink3_valid AND wire_w_sink3_data_range1136w(0);
+ wire_w_lg_sink3_valid1158w(0) <= sink3_valid AND wire_w_sink3_data_range1157w(0);
+ wire_w_lg_sink3_valid1179w(0) <= sink3_valid AND wire_w_sink3_data_range1178w(0);
+ wire_w_lg_sink3_valid1200w(0) <= sink3_valid AND wire_w_sink3_data_range1199w(0);
+ wire_w_lg_sink3_valid1221w(0) <= sink3_valid AND wire_w_sink3_data_range1220w(0);
+ wire_w_lg_sink3_valid1242w(0) <= sink3_valid AND wire_w_sink3_data_range1241w(0);
+ wire_w_lg_sink3_valid1263w(0) <= sink3_valid AND wire_w_sink3_data_range1262w(0);
+ wire_w_lg_sink3_valid129w(0) <= sink3_valid AND wire_w_sink3_data_range128w(0);
+ wire_w_lg_sink3_valid1284w(0) <= sink3_valid AND wire_w_sink3_data_range1283w(0);
+ wire_w_lg_sink3_valid1305w(0) <= sink3_valid AND wire_w_sink3_data_range1304w(0);
+ wire_w_lg_sink3_valid1326w(0) <= sink3_valid AND wire_w_sink3_data_range1325w(0);
+ wire_w_lg_sink3_valid1347w(0) <= sink3_valid AND wire_w_sink3_data_range1346w(0);
+ wire_w_lg_sink3_valid1368w(0) <= sink3_valid AND wire_w_sink3_data_range1367w(0);
+ wire_w_lg_sink3_valid1389w(0) <= sink3_valid AND wire_w_sink3_data_range1388w(0);
+ wire_w_lg_sink3_valid1410w(0) <= sink3_valid AND wire_w_sink3_data_range1409w(0);
+ wire_w_lg_sink3_valid1431w(0) <= sink3_valid AND wire_w_sink3_data_range1430w(0);
+ wire_w_lg_sink3_valid1452w(0) <= sink3_valid AND wire_w_sink3_data_range1451w(0);
+ wire_w_lg_sink3_valid150w(0) <= sink3_valid AND wire_w_sink3_data_range149w(0);
+ wire_w_lg_sink3_valid171w(0) <= sink3_valid AND wire_w_sink3_data_range170w(0);
+ wire_w_lg_sink3_valid192w(0) <= sink3_valid AND wire_w_sink3_data_range191w(0);
+ wire_w_lg_sink3_valid213w(0) <= sink3_valid AND wire_w_sink3_data_range212w(0);
+ wire_w_lg_sink4_valid1476w(0) <= sink4_valid AND wire_w_sink4_channel_range1475w(0);
+ wire_w_lg_sink4_valid1498w(0) <= sink4_valid AND wire_w_sink4_channel_range1497w(0);
+ wire_w_lg_sink4_valid1519w(0) <= sink4_valid AND wire_w_sink4_channel_range1518w(0);
+ wire_w_lg_sink4_valid1540w(0) <= sink4_valid AND wire_w_sink4_channel_range1539w(0);
+ wire_w_lg_sink4_valid1561w(0) <= sink4_valid AND wire_w_sink4_channel_range1560w(0);
+ wire_w_lg_sink4_valid1582w(0) <= sink4_valid AND wire_w_sink4_channel_range1581w(0);
+ wire_w_lg_sink4_valid1603w(0) <= sink4_valid AND wire_w_sink4_channel_range1602w(0);
+ wire_w_lg_sink4_valid26w(0) <= sink4_valid AND wire_w_sink4_data_range25w(0);
+ wire_w_lg_sink4_valid237w(0) <= sink4_valid AND wire_w_sink4_data_range236w(0);
+ wire_w_lg_sink4_valid258w(0) <= sink4_valid AND wire_w_sink4_data_range257w(0);
+ wire_w_lg_sink4_valid279w(0) <= sink4_valid AND wire_w_sink4_data_range278w(0);
+ wire_w_lg_sink4_valid300w(0) <= sink4_valid AND wire_w_sink4_data_range299w(0);
+ wire_w_lg_sink4_valid321w(0) <= sink4_valid AND wire_w_sink4_data_range320w(0);
+ wire_w_lg_sink4_valid342w(0) <= sink4_valid AND wire_w_sink4_data_range341w(0);
+ wire_w_lg_sink4_valid363w(0) <= sink4_valid AND wire_w_sink4_data_range362w(0);
+ wire_w_lg_sink4_valid384w(0) <= sink4_valid AND wire_w_sink4_data_range383w(0);
+ wire_w_lg_sink4_valid405w(0) <= sink4_valid AND wire_w_sink4_data_range404w(0);
+ wire_w_lg_sink4_valid426w(0) <= sink4_valid AND wire_w_sink4_data_range425w(0);
+ wire_w_lg_sink4_valid48w(0) <= sink4_valid AND wire_w_sink4_data_range47w(0);
+ wire_w_lg_sink4_valid447w(0) <= sink4_valid AND wire_w_sink4_data_range446w(0);
+ wire_w_lg_sink4_valid468w(0) <= sink4_valid AND wire_w_sink4_data_range467w(0);
+ wire_w_lg_sink4_valid489w(0) <= sink4_valid AND wire_w_sink4_data_range488w(0);
+ wire_w_lg_sink4_valid510w(0) <= sink4_valid AND wire_w_sink4_data_range509w(0);
+ wire_w_lg_sink4_valid531w(0) <= sink4_valid AND wire_w_sink4_data_range530w(0);
+ wire_w_lg_sink4_valid552w(0) <= sink4_valid AND wire_w_sink4_data_range551w(0);
+ wire_w_lg_sink4_valid573w(0) <= sink4_valid AND wire_w_sink4_data_range572w(0);
+ wire_w_lg_sink4_valid594w(0) <= sink4_valid AND wire_w_sink4_data_range593w(0);
+ wire_w_lg_sink4_valid615w(0) <= sink4_valid AND wire_w_sink4_data_range614w(0);
+ wire_w_lg_sink4_valid636w(0) <= sink4_valid AND wire_w_sink4_data_range635w(0);
+ wire_w_lg_sink4_valid69w(0) <= sink4_valid AND wire_w_sink4_data_range68w(0);
+ wire_w_lg_sink4_valid657w(0) <= sink4_valid AND wire_w_sink4_data_range656w(0);
+ wire_w_lg_sink4_valid678w(0) <= sink4_valid AND wire_w_sink4_data_range677w(0);
+ wire_w_lg_sink4_valid699w(0) <= sink4_valid AND wire_w_sink4_data_range698w(0);
+ wire_w_lg_sink4_valid720w(0) <= sink4_valid AND wire_w_sink4_data_range719w(0);
+ wire_w_lg_sink4_valid741w(0) <= sink4_valid AND wire_w_sink4_data_range740w(0);
+ wire_w_lg_sink4_valid762w(0) <= sink4_valid AND wire_w_sink4_data_range761w(0);
+ wire_w_lg_sink4_valid783w(0) <= sink4_valid AND wire_w_sink4_data_range782w(0);
+ wire_w_lg_sink4_valid804w(0) <= sink4_valid AND wire_w_sink4_data_range803w(0);
+ wire_w_lg_sink4_valid825w(0) <= sink4_valid AND wire_w_sink4_data_range824w(0);
+ wire_w_lg_sink4_valid846w(0) <= sink4_valid AND wire_w_sink4_data_range845w(0);
+ wire_w_lg_sink4_valid90w(0) <= sink4_valid AND wire_w_sink4_data_range89w(0);
+ wire_w_lg_sink4_valid867w(0) <= sink4_valid AND wire_w_sink4_data_range866w(0);
+ wire_w_lg_sink4_valid888w(0) <= sink4_valid AND wire_w_sink4_data_range887w(0);
+ wire_w_lg_sink4_valid909w(0) <= sink4_valid AND wire_w_sink4_data_range908w(0);
+ wire_w_lg_sink4_valid930w(0) <= sink4_valid AND wire_w_sink4_data_range929w(0);
+ wire_w_lg_sink4_valid951w(0) <= sink4_valid AND wire_w_sink4_data_range950w(0);
+ wire_w_lg_sink4_valid972w(0) <= sink4_valid AND wire_w_sink4_data_range971w(0);
+ wire_w_lg_sink4_valid993w(0) <= sink4_valid AND wire_w_sink4_data_range992w(0);
+ wire_w_lg_sink4_valid1014w(0) <= sink4_valid AND wire_w_sink4_data_range1013w(0);
+ wire_w_lg_sink4_valid1035w(0) <= sink4_valid AND wire_w_sink4_data_range1034w(0);
+ wire_w_lg_sink4_valid1056w(0) <= sink4_valid AND wire_w_sink4_data_range1055w(0);
+ wire_w_lg_sink4_valid111w(0) <= sink4_valid AND wire_w_sink4_data_range110w(0);
+ wire_w_lg_sink4_valid1077w(0) <= sink4_valid AND wire_w_sink4_data_range1076w(0);
+ wire_w_lg_sink4_valid1098w(0) <= sink4_valid AND wire_w_sink4_data_range1097w(0);
+ wire_w_lg_sink4_valid1119w(0) <= sink4_valid AND wire_w_sink4_data_range1118w(0);
+ wire_w_lg_sink4_valid1140w(0) <= sink4_valid AND wire_w_sink4_data_range1139w(0);
+ wire_w_lg_sink4_valid1161w(0) <= sink4_valid AND wire_w_sink4_data_range1160w(0);
+ wire_w_lg_sink4_valid1182w(0) <= sink4_valid AND wire_w_sink4_data_range1181w(0);
+ wire_w_lg_sink4_valid1203w(0) <= sink4_valid AND wire_w_sink4_data_range1202w(0);
+ wire_w_lg_sink4_valid1224w(0) <= sink4_valid AND wire_w_sink4_data_range1223w(0);
+ wire_w_lg_sink4_valid1245w(0) <= sink4_valid AND wire_w_sink4_data_range1244w(0);
+ wire_w_lg_sink4_valid1266w(0) <= sink4_valid AND wire_w_sink4_data_range1265w(0);
+ wire_w_lg_sink4_valid132w(0) <= sink4_valid AND wire_w_sink4_data_range131w(0);
+ wire_w_lg_sink4_valid1287w(0) <= sink4_valid AND wire_w_sink4_data_range1286w(0);
+ wire_w_lg_sink4_valid1308w(0) <= sink4_valid AND wire_w_sink4_data_range1307w(0);
+ wire_w_lg_sink4_valid1329w(0) <= sink4_valid AND wire_w_sink4_data_range1328w(0);
+ wire_w_lg_sink4_valid1350w(0) <= sink4_valid AND wire_w_sink4_data_range1349w(0);
+ wire_w_lg_sink4_valid1371w(0) <= sink4_valid AND wire_w_sink4_data_range1370w(0);
+ wire_w_lg_sink4_valid1392w(0) <= sink4_valid AND wire_w_sink4_data_range1391w(0);
+ wire_w_lg_sink4_valid1413w(0) <= sink4_valid AND wire_w_sink4_data_range1412w(0);
+ wire_w_lg_sink4_valid1434w(0) <= sink4_valid AND wire_w_sink4_data_range1433w(0);
+ wire_w_lg_sink4_valid1455w(0) <= sink4_valid AND wire_w_sink4_data_range1454w(0);
+ wire_w_lg_sink4_valid153w(0) <= sink4_valid AND wire_w_sink4_data_range152w(0);
+ wire_w_lg_sink4_valid174w(0) <= sink4_valid AND wire_w_sink4_data_range173w(0);
+ wire_w_lg_sink4_valid195w(0) <= sink4_valid AND wire_w_sink4_data_range194w(0);
+ wire_w_lg_sink4_valid216w(0) <= sink4_valid AND wire_w_sink4_data_range215w(0);
+ wire_w_lg_sink5_valid1479w(0) <= sink5_valid AND wire_w_sink5_channel_range1478w(0);
+ wire_w_lg_sink5_valid1501w(0) <= sink5_valid AND wire_w_sink5_channel_range1500w(0);
+ wire_w_lg_sink5_valid1522w(0) <= sink5_valid AND wire_w_sink5_channel_range1521w(0);
+ wire_w_lg_sink5_valid1543w(0) <= sink5_valid AND wire_w_sink5_channel_range1542w(0);
+ wire_w_lg_sink5_valid1564w(0) <= sink5_valid AND wire_w_sink5_channel_range1563w(0);
+ wire_w_lg_sink5_valid1585w(0) <= sink5_valid AND wire_w_sink5_channel_range1584w(0);
+ wire_w_lg_sink5_valid1606w(0) <= sink5_valid AND wire_w_sink5_channel_range1605w(0);
+ wire_w_lg_sink5_valid29w(0) <= sink5_valid AND wire_w_sink5_data_range28w(0);
+ wire_w_lg_sink5_valid240w(0) <= sink5_valid AND wire_w_sink5_data_range239w(0);
+ wire_w_lg_sink5_valid261w(0) <= sink5_valid AND wire_w_sink5_data_range260w(0);
+ wire_w_lg_sink5_valid282w(0) <= sink5_valid AND wire_w_sink5_data_range281w(0);
+ wire_w_lg_sink5_valid303w(0) <= sink5_valid AND wire_w_sink5_data_range302w(0);
+ wire_w_lg_sink5_valid324w(0) <= sink5_valid AND wire_w_sink5_data_range323w(0);
+ wire_w_lg_sink5_valid345w(0) <= sink5_valid AND wire_w_sink5_data_range344w(0);
+ wire_w_lg_sink5_valid366w(0) <= sink5_valid AND wire_w_sink5_data_range365w(0);
+ wire_w_lg_sink5_valid387w(0) <= sink5_valid AND wire_w_sink5_data_range386w(0);
+ wire_w_lg_sink5_valid408w(0) <= sink5_valid AND wire_w_sink5_data_range407w(0);
+ wire_w_lg_sink5_valid429w(0) <= sink5_valid AND wire_w_sink5_data_range428w(0);
+ wire_w_lg_sink5_valid51w(0) <= sink5_valid AND wire_w_sink5_data_range50w(0);
+ wire_w_lg_sink5_valid450w(0) <= sink5_valid AND wire_w_sink5_data_range449w(0);
+ wire_w_lg_sink5_valid471w(0) <= sink5_valid AND wire_w_sink5_data_range470w(0);
+ wire_w_lg_sink5_valid492w(0) <= sink5_valid AND wire_w_sink5_data_range491w(0);
+ wire_w_lg_sink5_valid513w(0) <= sink5_valid AND wire_w_sink5_data_range512w(0);
+ wire_w_lg_sink5_valid534w(0) <= sink5_valid AND wire_w_sink5_data_range533w(0);
+ wire_w_lg_sink5_valid555w(0) <= sink5_valid AND wire_w_sink5_data_range554w(0);
+ wire_w_lg_sink5_valid576w(0) <= sink5_valid AND wire_w_sink5_data_range575w(0);
+ wire_w_lg_sink5_valid597w(0) <= sink5_valid AND wire_w_sink5_data_range596w(0);
+ wire_w_lg_sink5_valid618w(0) <= sink5_valid AND wire_w_sink5_data_range617w(0);
+ wire_w_lg_sink5_valid639w(0) <= sink5_valid AND wire_w_sink5_data_range638w(0);
+ wire_w_lg_sink5_valid72w(0) <= sink5_valid AND wire_w_sink5_data_range71w(0);
+ wire_w_lg_sink5_valid660w(0) <= sink5_valid AND wire_w_sink5_data_range659w(0);
+ wire_w_lg_sink5_valid681w(0) <= sink5_valid AND wire_w_sink5_data_range680w(0);
+ wire_w_lg_sink5_valid702w(0) <= sink5_valid AND wire_w_sink5_data_range701w(0);
+ wire_w_lg_sink5_valid723w(0) <= sink5_valid AND wire_w_sink5_data_range722w(0);
+ wire_w_lg_sink5_valid744w(0) <= sink5_valid AND wire_w_sink5_data_range743w(0);
+ wire_w_lg_sink5_valid765w(0) <= sink5_valid AND wire_w_sink5_data_range764w(0);
+ wire_w_lg_sink5_valid786w(0) <= sink5_valid AND wire_w_sink5_data_range785w(0);
+ wire_w_lg_sink5_valid807w(0) <= sink5_valid AND wire_w_sink5_data_range806w(0);
+ wire_w_lg_sink5_valid828w(0) <= sink5_valid AND wire_w_sink5_data_range827w(0);
+ wire_w_lg_sink5_valid849w(0) <= sink5_valid AND wire_w_sink5_data_range848w(0);
+ wire_w_lg_sink5_valid93w(0) <= sink5_valid AND wire_w_sink5_data_range92w(0);
+ wire_w_lg_sink5_valid870w(0) <= sink5_valid AND wire_w_sink5_data_range869w(0);
+ wire_w_lg_sink5_valid891w(0) <= sink5_valid AND wire_w_sink5_data_range890w(0);
+ wire_w_lg_sink5_valid912w(0) <= sink5_valid AND wire_w_sink5_data_range911w(0);
+ wire_w_lg_sink5_valid933w(0) <= sink5_valid AND wire_w_sink5_data_range932w(0);
+ wire_w_lg_sink5_valid954w(0) <= sink5_valid AND wire_w_sink5_data_range953w(0);
+ wire_w_lg_sink5_valid975w(0) <= sink5_valid AND wire_w_sink5_data_range974w(0);
+ wire_w_lg_sink5_valid996w(0) <= sink5_valid AND wire_w_sink5_data_range995w(0);
+ wire_w_lg_sink5_valid1017w(0) <= sink5_valid AND wire_w_sink5_data_range1016w(0);
+ wire_w_lg_sink5_valid1038w(0) <= sink5_valid AND wire_w_sink5_data_range1037w(0);
+ wire_w_lg_sink5_valid1059w(0) <= sink5_valid AND wire_w_sink5_data_range1058w(0);
+ wire_w_lg_sink5_valid114w(0) <= sink5_valid AND wire_w_sink5_data_range113w(0);
+ wire_w_lg_sink5_valid1080w(0) <= sink5_valid AND wire_w_sink5_data_range1079w(0);
+ wire_w_lg_sink5_valid1101w(0) <= sink5_valid AND wire_w_sink5_data_range1100w(0);
+ wire_w_lg_sink5_valid1122w(0) <= sink5_valid AND wire_w_sink5_data_range1121w(0);
+ wire_w_lg_sink5_valid1143w(0) <= sink5_valid AND wire_w_sink5_data_range1142w(0);
+ wire_w_lg_sink5_valid1164w(0) <= sink5_valid AND wire_w_sink5_data_range1163w(0);
+ wire_w_lg_sink5_valid1185w(0) <= sink5_valid AND wire_w_sink5_data_range1184w(0);
+ wire_w_lg_sink5_valid1206w(0) <= sink5_valid AND wire_w_sink5_data_range1205w(0);
+ wire_w_lg_sink5_valid1227w(0) <= sink5_valid AND wire_w_sink5_data_range1226w(0);
+ wire_w_lg_sink5_valid1248w(0) <= sink5_valid AND wire_w_sink5_data_range1247w(0);
+ wire_w_lg_sink5_valid1269w(0) <= sink5_valid AND wire_w_sink5_data_range1268w(0);
+ wire_w_lg_sink5_valid135w(0) <= sink5_valid AND wire_w_sink5_data_range134w(0);
+ wire_w_lg_sink5_valid1290w(0) <= sink5_valid AND wire_w_sink5_data_range1289w(0);
+ wire_w_lg_sink5_valid1311w(0) <= sink5_valid AND wire_w_sink5_data_range1310w(0);
+ wire_w_lg_sink5_valid1332w(0) <= sink5_valid AND wire_w_sink5_data_range1331w(0);
+ wire_w_lg_sink5_valid1353w(0) <= sink5_valid AND wire_w_sink5_data_range1352w(0);
+ wire_w_lg_sink5_valid1374w(0) <= sink5_valid AND wire_w_sink5_data_range1373w(0);
+ wire_w_lg_sink5_valid1395w(0) <= sink5_valid AND wire_w_sink5_data_range1394w(0);
+ wire_w_lg_sink5_valid1416w(0) <= sink5_valid AND wire_w_sink5_data_range1415w(0);
+ wire_w_lg_sink5_valid1437w(0) <= sink5_valid AND wire_w_sink5_data_range1436w(0);
+ wire_w_lg_sink5_valid1458w(0) <= sink5_valid AND wire_w_sink5_data_range1457w(0);
+ wire_w_lg_sink5_valid156w(0) <= sink5_valid AND wire_w_sink5_data_range155w(0);
+ wire_w_lg_sink5_valid177w(0) <= sink5_valid AND wire_w_sink5_data_range176w(0);
+ wire_w_lg_sink5_valid198w(0) <= sink5_valid AND wire_w_sink5_data_range197w(0);
+ wire_w_lg_sink5_valid219w(0) <= sink5_valid AND wire_w_sink5_data_range218w(0);
+ wire_w_lg_sink6_valid1482w(0) <= sink6_valid AND wire_w_sink6_channel_range1481w(0);
+ wire_w_lg_sink6_valid1504w(0) <= sink6_valid AND wire_w_sink6_channel_range1503w(0);
+ wire_w_lg_sink6_valid1525w(0) <= sink6_valid AND wire_w_sink6_channel_range1524w(0);
+ wire_w_lg_sink6_valid1546w(0) <= sink6_valid AND wire_w_sink6_channel_range1545w(0);
+ wire_w_lg_sink6_valid1567w(0) <= sink6_valid AND wire_w_sink6_channel_range1566w(0);
+ wire_w_lg_sink6_valid1588w(0) <= sink6_valid AND wire_w_sink6_channel_range1587w(0);
+ wire_w_lg_sink6_valid1609w(0) <= sink6_valid AND wire_w_sink6_channel_range1608w(0);
+ wire_w_lg_sink6_valid32w(0) <= sink6_valid AND wire_w_sink6_data_range31w(0);
+ wire_w_lg_sink6_valid243w(0) <= sink6_valid AND wire_w_sink6_data_range242w(0);
+ wire_w_lg_sink6_valid264w(0) <= sink6_valid AND wire_w_sink6_data_range263w(0);
+ wire_w_lg_sink6_valid285w(0) <= sink6_valid AND wire_w_sink6_data_range284w(0);
+ wire_w_lg_sink6_valid306w(0) <= sink6_valid AND wire_w_sink6_data_range305w(0);
+ wire_w_lg_sink6_valid327w(0) <= sink6_valid AND wire_w_sink6_data_range326w(0);
+ wire_w_lg_sink6_valid348w(0) <= sink6_valid AND wire_w_sink6_data_range347w(0);
+ wire_w_lg_sink6_valid369w(0) <= sink6_valid AND wire_w_sink6_data_range368w(0);
+ wire_w_lg_sink6_valid390w(0) <= sink6_valid AND wire_w_sink6_data_range389w(0);
+ wire_w_lg_sink6_valid411w(0) <= sink6_valid AND wire_w_sink6_data_range410w(0);
+ wire_w_lg_sink6_valid432w(0) <= sink6_valid AND wire_w_sink6_data_range431w(0);
+ wire_w_lg_sink6_valid54w(0) <= sink6_valid AND wire_w_sink6_data_range53w(0);
+ wire_w_lg_sink6_valid453w(0) <= sink6_valid AND wire_w_sink6_data_range452w(0);
+ wire_w_lg_sink6_valid474w(0) <= sink6_valid AND wire_w_sink6_data_range473w(0);
+ wire_w_lg_sink6_valid495w(0) <= sink6_valid AND wire_w_sink6_data_range494w(0);
+ wire_w_lg_sink6_valid516w(0) <= sink6_valid AND wire_w_sink6_data_range515w(0);
+ wire_w_lg_sink6_valid537w(0) <= sink6_valid AND wire_w_sink6_data_range536w(0);
+ wire_w_lg_sink6_valid558w(0) <= sink6_valid AND wire_w_sink6_data_range557w(0);
+ wire_w_lg_sink6_valid579w(0) <= sink6_valid AND wire_w_sink6_data_range578w(0);
+ wire_w_lg_sink6_valid600w(0) <= sink6_valid AND wire_w_sink6_data_range599w(0);
+ wire_w_lg_sink6_valid621w(0) <= sink6_valid AND wire_w_sink6_data_range620w(0);
+ wire_w_lg_sink6_valid642w(0) <= sink6_valid AND wire_w_sink6_data_range641w(0);
+ wire_w_lg_sink6_valid75w(0) <= sink6_valid AND wire_w_sink6_data_range74w(0);
+ wire_w_lg_sink6_valid663w(0) <= sink6_valid AND wire_w_sink6_data_range662w(0);
+ wire_w_lg_sink6_valid684w(0) <= sink6_valid AND wire_w_sink6_data_range683w(0);
+ wire_w_lg_sink6_valid705w(0) <= sink6_valid AND wire_w_sink6_data_range704w(0);
+ wire_w_lg_sink6_valid726w(0) <= sink6_valid AND wire_w_sink6_data_range725w(0);
+ wire_w_lg_sink6_valid747w(0) <= sink6_valid AND wire_w_sink6_data_range746w(0);
+ wire_w_lg_sink6_valid768w(0) <= sink6_valid AND wire_w_sink6_data_range767w(0);
+ wire_w_lg_sink6_valid789w(0) <= sink6_valid AND wire_w_sink6_data_range788w(0);
+ wire_w_lg_sink6_valid810w(0) <= sink6_valid AND wire_w_sink6_data_range809w(0);
+ wire_w_lg_sink6_valid831w(0) <= sink6_valid AND wire_w_sink6_data_range830w(0);
+ wire_w_lg_sink6_valid852w(0) <= sink6_valid AND wire_w_sink6_data_range851w(0);
+ wire_w_lg_sink6_valid96w(0) <= sink6_valid AND wire_w_sink6_data_range95w(0);
+ wire_w_lg_sink6_valid873w(0) <= sink6_valid AND wire_w_sink6_data_range872w(0);
+ wire_w_lg_sink6_valid894w(0) <= sink6_valid AND wire_w_sink6_data_range893w(0);
+ wire_w_lg_sink6_valid915w(0) <= sink6_valid AND wire_w_sink6_data_range914w(0);
+ wire_w_lg_sink6_valid936w(0) <= sink6_valid AND wire_w_sink6_data_range935w(0);
+ wire_w_lg_sink6_valid957w(0) <= sink6_valid AND wire_w_sink6_data_range956w(0);
+ wire_w_lg_sink6_valid978w(0) <= sink6_valid AND wire_w_sink6_data_range977w(0);
+ wire_w_lg_sink6_valid999w(0) <= sink6_valid AND wire_w_sink6_data_range998w(0);
+ wire_w_lg_sink6_valid1020w(0) <= sink6_valid AND wire_w_sink6_data_range1019w(0);
+ wire_w_lg_sink6_valid1041w(0) <= sink6_valid AND wire_w_sink6_data_range1040w(0);
+ wire_w_lg_sink6_valid1062w(0) <= sink6_valid AND wire_w_sink6_data_range1061w(0);
+ wire_w_lg_sink6_valid117w(0) <= sink6_valid AND wire_w_sink6_data_range116w(0);
+ wire_w_lg_sink6_valid1083w(0) <= sink6_valid AND wire_w_sink6_data_range1082w(0);
+ wire_w_lg_sink6_valid1104w(0) <= sink6_valid AND wire_w_sink6_data_range1103w(0);
+ wire_w_lg_sink6_valid1125w(0) <= sink6_valid AND wire_w_sink6_data_range1124w(0);
+ wire_w_lg_sink6_valid1146w(0) <= sink6_valid AND wire_w_sink6_data_range1145w(0);
+ wire_w_lg_sink6_valid1167w(0) <= sink6_valid AND wire_w_sink6_data_range1166w(0);
+ wire_w_lg_sink6_valid1188w(0) <= sink6_valid AND wire_w_sink6_data_range1187w(0);
+ wire_w_lg_sink6_valid1209w(0) <= sink6_valid AND wire_w_sink6_data_range1208w(0);
+ wire_w_lg_sink6_valid1230w(0) <= sink6_valid AND wire_w_sink6_data_range1229w(0);
+ wire_w_lg_sink6_valid1251w(0) <= sink6_valid AND wire_w_sink6_data_range1250w(0);
+ wire_w_lg_sink6_valid1272w(0) <= sink6_valid AND wire_w_sink6_data_range1271w(0);
+ wire_w_lg_sink6_valid138w(0) <= sink6_valid AND wire_w_sink6_data_range137w(0);
+ wire_w_lg_sink6_valid1293w(0) <= sink6_valid AND wire_w_sink6_data_range1292w(0);
+ wire_w_lg_sink6_valid1314w(0) <= sink6_valid AND wire_w_sink6_data_range1313w(0);
+ wire_w_lg_sink6_valid1335w(0) <= sink6_valid AND wire_w_sink6_data_range1334w(0);
+ wire_w_lg_sink6_valid1356w(0) <= sink6_valid AND wire_w_sink6_data_range1355w(0);
+ wire_w_lg_sink6_valid1377w(0) <= sink6_valid AND wire_w_sink6_data_range1376w(0);
+ wire_w_lg_sink6_valid1398w(0) <= sink6_valid AND wire_w_sink6_data_range1397w(0);
+ wire_w_lg_sink6_valid1419w(0) <= sink6_valid AND wire_w_sink6_data_range1418w(0);
+ wire_w_lg_sink6_valid1440w(0) <= sink6_valid AND wire_w_sink6_data_range1439w(0);
+ wire_w_lg_sink6_valid1461w(0) <= sink6_valid AND wire_w_sink6_data_range1460w(0);
+ wire_w_lg_sink6_valid159w(0) <= sink6_valid AND wire_w_sink6_data_range158w(0);
+ wire_w_lg_sink6_valid180w(0) <= sink6_valid AND wire_w_sink6_data_range179w(0);
+ wire_w_lg_sink6_valid201w(0) <= sink6_valid AND wire_w_sink6_data_range200w(0);
+ wire_w_lg_sink6_valid222w(0) <= sink6_valid AND wire_w_sink6_data_range221w(0);
+ wire_w_lg_w_lg_sink0_valid1465w1468w(0) <= wire_w_lg_sink0_valid1465w(0) OR wire_w_lg_sink1_valid1467w(0);
+ wire_w_lg_w_lg_sink0_valid1487w1490w(0) <= wire_w_lg_sink0_valid1487w(0) OR wire_w_lg_sink1_valid1489w(0);
+ wire_w_lg_w_lg_sink0_valid1508w1511w(0) <= wire_w_lg_sink0_valid1508w(0) OR wire_w_lg_sink1_valid1510w(0);
+ wire_w_lg_w_lg_sink0_valid1529w1532w(0) <= wire_w_lg_sink0_valid1529w(0) OR wire_w_lg_sink1_valid1531w(0);
+ wire_w_lg_w_lg_sink0_valid1550w1553w(0) <= wire_w_lg_sink0_valid1550w(0) OR wire_w_lg_sink1_valid1552w(0);
+ wire_w_lg_w_lg_sink0_valid1571w1574w(0) <= wire_w_lg_sink0_valid1571w(0) OR wire_w_lg_sink1_valid1573w(0);
+ wire_w_lg_w_lg_sink0_valid1592w1595w(0) <= wire_w_lg_sink0_valid1592w(0) OR wire_w_lg_sink1_valid1594w(0);
+ wire_w_lg_w_lg_sink0_valid15w18w(0) <= wire_w_lg_sink0_valid15w(0) OR wire_w_lg_sink1_valid17w(0);
+ wire_w_lg_w_lg_sink0_valid226w229w(0) <= wire_w_lg_sink0_valid226w(0) OR wire_w_lg_sink1_valid228w(0);
+ wire_w_lg_w_lg_sink0_valid247w250w(0) <= wire_w_lg_sink0_valid247w(0) OR wire_w_lg_sink1_valid249w(0);
+ wire_w_lg_w_lg_sink0_valid268w271w(0) <= wire_w_lg_sink0_valid268w(0) OR wire_w_lg_sink1_valid270w(0);
+ wire_w_lg_w_lg_sink0_valid289w292w(0) <= wire_w_lg_sink0_valid289w(0) OR wire_w_lg_sink1_valid291w(0);
+ wire_w_lg_w_lg_sink0_valid310w313w(0) <= wire_w_lg_sink0_valid310w(0) OR wire_w_lg_sink1_valid312w(0);
+ wire_w_lg_w_lg_sink0_valid331w334w(0) <= wire_w_lg_sink0_valid331w(0) OR wire_w_lg_sink1_valid333w(0);
+ wire_w_lg_w_lg_sink0_valid352w355w(0) <= wire_w_lg_sink0_valid352w(0) OR wire_w_lg_sink1_valid354w(0);
+ wire_w_lg_w_lg_sink0_valid373w376w(0) <= wire_w_lg_sink0_valid373w(0) OR wire_w_lg_sink1_valid375w(0);
+ wire_w_lg_w_lg_sink0_valid394w397w(0) <= wire_w_lg_sink0_valid394w(0) OR wire_w_lg_sink1_valid396w(0);
+ wire_w_lg_w_lg_sink0_valid415w418w(0) <= wire_w_lg_sink0_valid415w(0) OR wire_w_lg_sink1_valid417w(0);
+ wire_w_lg_w_lg_sink0_valid37w40w(0) <= wire_w_lg_sink0_valid37w(0) OR wire_w_lg_sink1_valid39w(0);
+ wire_w_lg_w_lg_sink0_valid436w439w(0) <= wire_w_lg_sink0_valid436w(0) OR wire_w_lg_sink1_valid438w(0);
+ wire_w_lg_w_lg_sink0_valid457w460w(0) <= wire_w_lg_sink0_valid457w(0) OR wire_w_lg_sink1_valid459w(0);
+ wire_w_lg_w_lg_sink0_valid478w481w(0) <= wire_w_lg_sink0_valid478w(0) OR wire_w_lg_sink1_valid480w(0);
+ wire_w_lg_w_lg_sink0_valid499w502w(0) <= wire_w_lg_sink0_valid499w(0) OR wire_w_lg_sink1_valid501w(0);
+ wire_w_lg_w_lg_sink0_valid520w523w(0) <= wire_w_lg_sink0_valid520w(0) OR wire_w_lg_sink1_valid522w(0);
+ wire_w_lg_w_lg_sink0_valid541w544w(0) <= wire_w_lg_sink0_valid541w(0) OR wire_w_lg_sink1_valid543w(0);
+ wire_w_lg_w_lg_sink0_valid562w565w(0) <= wire_w_lg_sink0_valid562w(0) OR wire_w_lg_sink1_valid564w(0);
+ wire_w_lg_w_lg_sink0_valid583w586w(0) <= wire_w_lg_sink0_valid583w(0) OR wire_w_lg_sink1_valid585w(0);
+ wire_w_lg_w_lg_sink0_valid604w607w(0) <= wire_w_lg_sink0_valid604w(0) OR wire_w_lg_sink1_valid606w(0);
+ wire_w_lg_w_lg_sink0_valid625w628w(0) <= wire_w_lg_sink0_valid625w(0) OR wire_w_lg_sink1_valid627w(0);
+ wire_w_lg_w_lg_sink0_valid58w61w(0) <= wire_w_lg_sink0_valid58w(0) OR wire_w_lg_sink1_valid60w(0);
+ wire_w_lg_w_lg_sink0_valid646w649w(0) <= wire_w_lg_sink0_valid646w(0) OR wire_w_lg_sink1_valid648w(0);
+ wire_w_lg_w_lg_sink0_valid667w670w(0) <= wire_w_lg_sink0_valid667w(0) OR wire_w_lg_sink1_valid669w(0);
+ wire_w_lg_w_lg_sink0_valid688w691w(0) <= wire_w_lg_sink0_valid688w(0) OR wire_w_lg_sink1_valid690w(0);
+ wire_w_lg_w_lg_sink0_valid709w712w(0) <= wire_w_lg_sink0_valid709w(0) OR wire_w_lg_sink1_valid711w(0);
+ wire_w_lg_w_lg_sink0_valid730w733w(0) <= wire_w_lg_sink0_valid730w(0) OR wire_w_lg_sink1_valid732w(0);
+ wire_w_lg_w_lg_sink0_valid751w754w(0) <= wire_w_lg_sink0_valid751w(0) OR wire_w_lg_sink1_valid753w(0);
+ wire_w_lg_w_lg_sink0_valid772w775w(0) <= wire_w_lg_sink0_valid772w(0) OR wire_w_lg_sink1_valid774w(0);
+ wire_w_lg_w_lg_sink0_valid793w796w(0) <= wire_w_lg_sink0_valid793w(0) OR wire_w_lg_sink1_valid795w(0);
+ wire_w_lg_w_lg_sink0_valid814w817w(0) <= wire_w_lg_sink0_valid814w(0) OR wire_w_lg_sink1_valid816w(0);
+ wire_w_lg_w_lg_sink0_valid835w838w(0) <= wire_w_lg_sink0_valid835w(0) OR wire_w_lg_sink1_valid837w(0);
+ wire_w_lg_w_lg_sink0_valid79w82w(0) <= wire_w_lg_sink0_valid79w(0) OR wire_w_lg_sink1_valid81w(0);
+ wire_w_lg_w_lg_sink0_valid856w859w(0) <= wire_w_lg_sink0_valid856w(0) OR wire_w_lg_sink1_valid858w(0);
+ wire_w_lg_w_lg_sink0_valid877w880w(0) <= wire_w_lg_sink0_valid877w(0) OR wire_w_lg_sink1_valid879w(0);
+ wire_w_lg_w_lg_sink0_valid898w901w(0) <= wire_w_lg_sink0_valid898w(0) OR wire_w_lg_sink1_valid900w(0);
+ wire_w_lg_w_lg_sink0_valid919w922w(0) <= wire_w_lg_sink0_valid919w(0) OR wire_w_lg_sink1_valid921w(0);
+ wire_w_lg_w_lg_sink0_valid940w943w(0) <= wire_w_lg_sink0_valid940w(0) OR wire_w_lg_sink1_valid942w(0);
+ wire_w_lg_w_lg_sink0_valid961w964w(0) <= wire_w_lg_sink0_valid961w(0) OR wire_w_lg_sink1_valid963w(0);
+ wire_w_lg_w_lg_sink0_valid982w985w(0) <= wire_w_lg_sink0_valid982w(0) OR wire_w_lg_sink1_valid984w(0);
+ wire_w_lg_w_lg_sink0_valid1003w1006w(0) <= wire_w_lg_sink0_valid1003w(0) OR wire_w_lg_sink1_valid1005w(0);
+ wire_w_lg_w_lg_sink0_valid1024w1027w(0) <= wire_w_lg_sink0_valid1024w(0) OR wire_w_lg_sink1_valid1026w(0);
+ wire_w_lg_w_lg_sink0_valid1045w1048w(0) <= wire_w_lg_sink0_valid1045w(0) OR wire_w_lg_sink1_valid1047w(0);
+ wire_w_lg_w_lg_sink0_valid100w103w(0) <= wire_w_lg_sink0_valid100w(0) OR wire_w_lg_sink1_valid102w(0);
+ wire_w_lg_w_lg_sink0_valid1066w1069w(0) <= wire_w_lg_sink0_valid1066w(0) OR wire_w_lg_sink1_valid1068w(0);
+ wire_w_lg_w_lg_sink0_valid1087w1090w(0) <= wire_w_lg_sink0_valid1087w(0) OR wire_w_lg_sink1_valid1089w(0);
+ wire_w_lg_w_lg_sink0_valid1108w1111w(0) <= wire_w_lg_sink0_valid1108w(0) OR wire_w_lg_sink1_valid1110w(0);
+ wire_w_lg_w_lg_sink0_valid1129w1132w(0) <= wire_w_lg_sink0_valid1129w(0) OR wire_w_lg_sink1_valid1131w(0);
+ wire_w_lg_w_lg_sink0_valid1150w1153w(0) <= wire_w_lg_sink0_valid1150w(0) OR wire_w_lg_sink1_valid1152w(0);
+ wire_w_lg_w_lg_sink0_valid1171w1174w(0) <= wire_w_lg_sink0_valid1171w(0) OR wire_w_lg_sink1_valid1173w(0);
+ wire_w_lg_w_lg_sink0_valid1192w1195w(0) <= wire_w_lg_sink0_valid1192w(0) OR wire_w_lg_sink1_valid1194w(0);
+ wire_w_lg_w_lg_sink0_valid1213w1216w(0) <= wire_w_lg_sink0_valid1213w(0) OR wire_w_lg_sink1_valid1215w(0);
+ wire_w_lg_w_lg_sink0_valid1234w1237w(0) <= wire_w_lg_sink0_valid1234w(0) OR wire_w_lg_sink1_valid1236w(0);
+ wire_w_lg_w_lg_sink0_valid1255w1258w(0) <= wire_w_lg_sink0_valid1255w(0) OR wire_w_lg_sink1_valid1257w(0);
+ wire_w_lg_w_lg_sink0_valid121w124w(0) <= wire_w_lg_sink0_valid121w(0) OR wire_w_lg_sink1_valid123w(0);
+ wire_w_lg_w_lg_sink0_valid1276w1279w(0) <= wire_w_lg_sink0_valid1276w(0) OR wire_w_lg_sink1_valid1278w(0);
+ wire_w_lg_w_lg_sink0_valid1297w1300w(0) <= wire_w_lg_sink0_valid1297w(0) OR wire_w_lg_sink1_valid1299w(0);
+ wire_w_lg_w_lg_sink0_valid1318w1321w(0) <= wire_w_lg_sink0_valid1318w(0) OR wire_w_lg_sink1_valid1320w(0);
+ wire_w_lg_w_lg_sink0_valid1339w1342w(0) <= wire_w_lg_sink0_valid1339w(0) OR wire_w_lg_sink1_valid1341w(0);
+ wire_w_lg_w_lg_sink0_valid1360w1363w(0) <= wire_w_lg_sink0_valid1360w(0) OR wire_w_lg_sink1_valid1362w(0);
+ wire_w_lg_w_lg_sink0_valid1381w1384w(0) <= wire_w_lg_sink0_valid1381w(0) OR wire_w_lg_sink1_valid1383w(0);
+ wire_w_lg_w_lg_sink0_valid1402w1405w(0) <= wire_w_lg_sink0_valid1402w(0) OR wire_w_lg_sink1_valid1404w(0);
+ wire_w_lg_w_lg_sink0_valid1423w1426w(0) <= wire_w_lg_sink0_valid1423w(0) OR wire_w_lg_sink1_valid1425w(0);
+ wire_w_lg_w_lg_sink0_valid1444w1447w(0) <= wire_w_lg_sink0_valid1444w(0) OR wire_w_lg_sink1_valid1446w(0);
+ wire_w_lg_w_lg_sink0_valid142w145w(0) <= wire_w_lg_sink0_valid142w(0) OR wire_w_lg_sink1_valid144w(0);
+ wire_w_lg_w_lg_sink0_valid163w166w(0) <= wire_w_lg_sink0_valid163w(0) OR wire_w_lg_sink1_valid165w(0);
+ wire_w_lg_w_lg_sink0_valid184w187w(0) <= wire_w_lg_sink0_valid184w(0) OR wire_w_lg_sink1_valid186w(0);
+ wire_w_lg_w_lg_sink0_valid205w208w(0) <= wire_w_lg_sink0_valid205w(0) OR wire_w_lg_sink1_valid207w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1465w1468w1471w(0) <= wire_w_lg_w_lg_sink0_valid1465w1468w(0) OR wire_w_lg_sink2_valid1470w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1487w1490w1493w(0) <= wire_w_lg_w_lg_sink0_valid1487w1490w(0) OR wire_w_lg_sink2_valid1492w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1508w1511w1514w(0) <= wire_w_lg_w_lg_sink0_valid1508w1511w(0) OR wire_w_lg_sink2_valid1513w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1529w1532w1535w(0) <= wire_w_lg_w_lg_sink0_valid1529w1532w(0) OR wire_w_lg_sink2_valid1534w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1550w1553w1556w(0) <= wire_w_lg_w_lg_sink0_valid1550w1553w(0) OR wire_w_lg_sink2_valid1555w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1571w1574w1577w(0) <= wire_w_lg_w_lg_sink0_valid1571w1574w(0) OR wire_w_lg_sink2_valid1576w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1592w1595w1598w(0) <= wire_w_lg_w_lg_sink0_valid1592w1595w(0) OR wire_w_lg_sink2_valid1597w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid15w18w21w(0) <= wire_w_lg_w_lg_sink0_valid15w18w(0) OR wire_w_lg_sink2_valid20w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid226w229w232w(0) <= wire_w_lg_w_lg_sink0_valid226w229w(0) OR wire_w_lg_sink2_valid231w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid247w250w253w(0) <= wire_w_lg_w_lg_sink0_valid247w250w(0) OR wire_w_lg_sink2_valid252w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid268w271w274w(0) <= wire_w_lg_w_lg_sink0_valid268w271w(0) OR wire_w_lg_sink2_valid273w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid289w292w295w(0) <= wire_w_lg_w_lg_sink0_valid289w292w(0) OR wire_w_lg_sink2_valid294w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid310w313w316w(0) <= wire_w_lg_w_lg_sink0_valid310w313w(0) OR wire_w_lg_sink2_valid315w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid331w334w337w(0) <= wire_w_lg_w_lg_sink0_valid331w334w(0) OR wire_w_lg_sink2_valid336w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid352w355w358w(0) <= wire_w_lg_w_lg_sink0_valid352w355w(0) OR wire_w_lg_sink2_valid357w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid373w376w379w(0) <= wire_w_lg_w_lg_sink0_valid373w376w(0) OR wire_w_lg_sink2_valid378w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid394w397w400w(0) <= wire_w_lg_w_lg_sink0_valid394w397w(0) OR wire_w_lg_sink2_valid399w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid415w418w421w(0) <= wire_w_lg_w_lg_sink0_valid415w418w(0) OR wire_w_lg_sink2_valid420w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid37w40w43w(0) <= wire_w_lg_w_lg_sink0_valid37w40w(0) OR wire_w_lg_sink2_valid42w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid436w439w442w(0) <= wire_w_lg_w_lg_sink0_valid436w439w(0) OR wire_w_lg_sink2_valid441w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid457w460w463w(0) <= wire_w_lg_w_lg_sink0_valid457w460w(0) OR wire_w_lg_sink2_valid462w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid478w481w484w(0) <= wire_w_lg_w_lg_sink0_valid478w481w(0) OR wire_w_lg_sink2_valid483w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid499w502w505w(0) <= wire_w_lg_w_lg_sink0_valid499w502w(0) OR wire_w_lg_sink2_valid504w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid520w523w526w(0) <= wire_w_lg_w_lg_sink0_valid520w523w(0) OR wire_w_lg_sink2_valid525w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid541w544w547w(0) <= wire_w_lg_w_lg_sink0_valid541w544w(0) OR wire_w_lg_sink2_valid546w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid562w565w568w(0) <= wire_w_lg_w_lg_sink0_valid562w565w(0) OR wire_w_lg_sink2_valid567w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid583w586w589w(0) <= wire_w_lg_w_lg_sink0_valid583w586w(0) OR wire_w_lg_sink2_valid588w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid604w607w610w(0) <= wire_w_lg_w_lg_sink0_valid604w607w(0) OR wire_w_lg_sink2_valid609w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid625w628w631w(0) <= wire_w_lg_w_lg_sink0_valid625w628w(0) OR wire_w_lg_sink2_valid630w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid58w61w64w(0) <= wire_w_lg_w_lg_sink0_valid58w61w(0) OR wire_w_lg_sink2_valid63w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid646w649w652w(0) <= wire_w_lg_w_lg_sink0_valid646w649w(0) OR wire_w_lg_sink2_valid651w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid667w670w673w(0) <= wire_w_lg_w_lg_sink0_valid667w670w(0) OR wire_w_lg_sink2_valid672w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid688w691w694w(0) <= wire_w_lg_w_lg_sink0_valid688w691w(0) OR wire_w_lg_sink2_valid693w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid709w712w715w(0) <= wire_w_lg_w_lg_sink0_valid709w712w(0) OR wire_w_lg_sink2_valid714w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid730w733w736w(0) <= wire_w_lg_w_lg_sink0_valid730w733w(0) OR wire_w_lg_sink2_valid735w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid751w754w757w(0) <= wire_w_lg_w_lg_sink0_valid751w754w(0) OR wire_w_lg_sink2_valid756w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid772w775w778w(0) <= wire_w_lg_w_lg_sink0_valid772w775w(0) OR wire_w_lg_sink2_valid777w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid793w796w799w(0) <= wire_w_lg_w_lg_sink0_valid793w796w(0) OR wire_w_lg_sink2_valid798w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid814w817w820w(0) <= wire_w_lg_w_lg_sink0_valid814w817w(0) OR wire_w_lg_sink2_valid819w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid835w838w841w(0) <= wire_w_lg_w_lg_sink0_valid835w838w(0) OR wire_w_lg_sink2_valid840w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid79w82w85w(0) <= wire_w_lg_w_lg_sink0_valid79w82w(0) OR wire_w_lg_sink2_valid84w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid856w859w862w(0) <= wire_w_lg_w_lg_sink0_valid856w859w(0) OR wire_w_lg_sink2_valid861w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid877w880w883w(0) <= wire_w_lg_w_lg_sink0_valid877w880w(0) OR wire_w_lg_sink2_valid882w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid898w901w904w(0) <= wire_w_lg_w_lg_sink0_valid898w901w(0) OR wire_w_lg_sink2_valid903w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid919w922w925w(0) <= wire_w_lg_w_lg_sink0_valid919w922w(0) OR wire_w_lg_sink2_valid924w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid940w943w946w(0) <= wire_w_lg_w_lg_sink0_valid940w943w(0) OR wire_w_lg_sink2_valid945w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid961w964w967w(0) <= wire_w_lg_w_lg_sink0_valid961w964w(0) OR wire_w_lg_sink2_valid966w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid982w985w988w(0) <= wire_w_lg_w_lg_sink0_valid982w985w(0) OR wire_w_lg_sink2_valid987w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1003w1006w1009w(0) <= wire_w_lg_w_lg_sink0_valid1003w1006w(0) OR wire_w_lg_sink2_valid1008w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1024w1027w1030w(0) <= wire_w_lg_w_lg_sink0_valid1024w1027w(0) OR wire_w_lg_sink2_valid1029w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1045w1048w1051w(0) <= wire_w_lg_w_lg_sink0_valid1045w1048w(0) OR wire_w_lg_sink2_valid1050w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid100w103w106w(0) <= wire_w_lg_w_lg_sink0_valid100w103w(0) OR wire_w_lg_sink2_valid105w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1066w1069w1072w(0) <= wire_w_lg_w_lg_sink0_valid1066w1069w(0) OR wire_w_lg_sink2_valid1071w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1087w1090w1093w(0) <= wire_w_lg_w_lg_sink0_valid1087w1090w(0) OR wire_w_lg_sink2_valid1092w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1108w1111w1114w(0) <= wire_w_lg_w_lg_sink0_valid1108w1111w(0) OR wire_w_lg_sink2_valid1113w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1129w1132w1135w(0) <= wire_w_lg_w_lg_sink0_valid1129w1132w(0) OR wire_w_lg_sink2_valid1134w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1150w1153w1156w(0) <= wire_w_lg_w_lg_sink0_valid1150w1153w(0) OR wire_w_lg_sink2_valid1155w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1171w1174w1177w(0) <= wire_w_lg_w_lg_sink0_valid1171w1174w(0) OR wire_w_lg_sink2_valid1176w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1192w1195w1198w(0) <= wire_w_lg_w_lg_sink0_valid1192w1195w(0) OR wire_w_lg_sink2_valid1197w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1213w1216w1219w(0) <= wire_w_lg_w_lg_sink0_valid1213w1216w(0) OR wire_w_lg_sink2_valid1218w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1234w1237w1240w(0) <= wire_w_lg_w_lg_sink0_valid1234w1237w(0) OR wire_w_lg_sink2_valid1239w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1255w1258w1261w(0) <= wire_w_lg_w_lg_sink0_valid1255w1258w(0) OR wire_w_lg_sink2_valid1260w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid121w124w127w(0) <= wire_w_lg_w_lg_sink0_valid121w124w(0) OR wire_w_lg_sink2_valid126w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1276w1279w1282w(0) <= wire_w_lg_w_lg_sink0_valid1276w1279w(0) OR wire_w_lg_sink2_valid1281w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1297w1300w1303w(0) <= wire_w_lg_w_lg_sink0_valid1297w1300w(0) OR wire_w_lg_sink2_valid1302w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1318w1321w1324w(0) <= wire_w_lg_w_lg_sink0_valid1318w1321w(0) OR wire_w_lg_sink2_valid1323w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1339w1342w1345w(0) <= wire_w_lg_w_lg_sink0_valid1339w1342w(0) OR wire_w_lg_sink2_valid1344w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1360w1363w1366w(0) <= wire_w_lg_w_lg_sink0_valid1360w1363w(0) OR wire_w_lg_sink2_valid1365w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1381w1384w1387w(0) <= wire_w_lg_w_lg_sink0_valid1381w1384w(0) OR wire_w_lg_sink2_valid1386w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1402w1405w1408w(0) <= wire_w_lg_w_lg_sink0_valid1402w1405w(0) OR wire_w_lg_sink2_valid1407w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1423w1426w1429w(0) <= wire_w_lg_w_lg_sink0_valid1423w1426w(0) OR wire_w_lg_sink2_valid1428w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid1444w1447w1450w(0) <= wire_w_lg_w_lg_sink0_valid1444w1447w(0) OR wire_w_lg_sink2_valid1449w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid142w145w148w(0) <= wire_w_lg_w_lg_sink0_valid142w145w(0) OR wire_w_lg_sink2_valid147w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid163w166w169w(0) <= wire_w_lg_w_lg_sink0_valid163w166w(0) OR wire_w_lg_sink2_valid168w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid184w187w190w(0) <= wire_w_lg_w_lg_sink0_valid184w187w(0) OR wire_w_lg_sink2_valid189w(0);
+ wire_w_lg_w_lg_w_lg_sink0_valid205w208w211w(0) <= wire_w_lg_w_lg_sink0_valid205w208w(0) OR wire_w_lg_sink2_valid210w(0);
+ wire_w1474w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1465w1468w1471w(0) OR wire_w_lg_sink3_valid1473w(0);
+ wire_w1496w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1487w1490w1493w(0) OR wire_w_lg_sink3_valid1495w(0);
+ wire_w1517w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1508w1511w1514w(0) OR wire_w_lg_sink3_valid1516w(0);
+ wire_w1538w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1529w1532w1535w(0) OR wire_w_lg_sink3_valid1537w(0);
+ wire_w1559w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1550w1553w1556w(0) OR wire_w_lg_sink3_valid1558w(0);
+ wire_w1580w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1571w1574w1577w(0) OR wire_w_lg_sink3_valid1579w(0);
+ wire_w1601w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1592w1595w1598w(0) OR wire_w_lg_sink3_valid1600w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid15w18w21w24w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid15w18w21w(0) OR wire_w_lg_sink3_valid23w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid226w229w232w235w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid226w229w232w(0) OR wire_w_lg_sink3_valid234w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid247w250w253w256w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid247w250w253w(0) OR wire_w_lg_sink3_valid255w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid268w271w274w277w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid268w271w274w(0) OR wire_w_lg_sink3_valid276w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid289w292w295w298w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid289w292w295w(0) OR wire_w_lg_sink3_valid297w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid310w313w316w319w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid310w313w316w(0) OR wire_w_lg_sink3_valid318w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid331w334w337w340w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid331w334w337w(0) OR wire_w_lg_sink3_valid339w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid352w355w358w361w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid352w355w358w(0) OR wire_w_lg_sink3_valid360w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid373w376w379w382w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid373w376w379w(0) OR wire_w_lg_sink3_valid381w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid394w397w400w403w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid394w397w400w(0) OR wire_w_lg_sink3_valid402w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid415w418w421w424w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid415w418w421w(0) OR wire_w_lg_sink3_valid423w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid37w40w43w46w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid37w40w43w(0) OR wire_w_lg_sink3_valid45w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid436w439w442w445w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid436w439w442w(0) OR wire_w_lg_sink3_valid444w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid457w460w463w466w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid457w460w463w(0) OR wire_w_lg_sink3_valid465w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid478w481w484w487w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid478w481w484w(0) OR wire_w_lg_sink3_valid486w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid499w502w505w508w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid499w502w505w(0) OR wire_w_lg_sink3_valid507w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid520w523w526w529w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid520w523w526w(0) OR wire_w_lg_sink3_valid528w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid541w544w547w550w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid541w544w547w(0) OR wire_w_lg_sink3_valid549w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid562w565w568w571w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid562w565w568w(0) OR wire_w_lg_sink3_valid570w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid583w586w589w592w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid583w586w589w(0) OR wire_w_lg_sink3_valid591w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid604w607w610w613w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid604w607w610w(0) OR wire_w_lg_sink3_valid612w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid625w628w631w634w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid625w628w631w(0) OR wire_w_lg_sink3_valid633w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid58w61w64w67w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid58w61w64w(0) OR wire_w_lg_sink3_valid66w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid646w649w652w655w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid646w649w652w(0) OR wire_w_lg_sink3_valid654w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid667w670w673w676w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid667w670w673w(0) OR wire_w_lg_sink3_valid675w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid688w691w694w697w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid688w691w694w(0) OR wire_w_lg_sink3_valid696w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid709w712w715w718w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid709w712w715w(0) OR wire_w_lg_sink3_valid717w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid730w733w736w739w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid730w733w736w(0) OR wire_w_lg_sink3_valid738w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid751w754w757w760w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid751w754w757w(0) OR wire_w_lg_sink3_valid759w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid772w775w778w781w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid772w775w778w(0) OR wire_w_lg_sink3_valid780w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid793w796w799w802w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid793w796w799w(0) OR wire_w_lg_sink3_valid801w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid814w817w820w823w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid814w817w820w(0) OR wire_w_lg_sink3_valid822w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid835w838w841w844w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid835w838w841w(0) OR wire_w_lg_sink3_valid843w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid79w82w85w88w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid79w82w85w(0) OR wire_w_lg_sink3_valid87w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid856w859w862w865w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid856w859w862w(0) OR wire_w_lg_sink3_valid864w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid877w880w883w886w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid877w880w883w(0) OR wire_w_lg_sink3_valid885w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid898w901w904w907w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid898w901w904w(0) OR wire_w_lg_sink3_valid906w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid919w922w925w928w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid919w922w925w(0) OR wire_w_lg_sink3_valid927w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid940w943w946w949w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid940w943w946w(0) OR wire_w_lg_sink3_valid948w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid961w964w967w970w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid961w964w967w(0) OR wire_w_lg_sink3_valid969w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid982w985w988w991w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid982w985w988w(0) OR wire_w_lg_sink3_valid990w(0);
+ wire_w1012w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1003w1006w1009w(0) OR wire_w_lg_sink3_valid1011w(0);
+ wire_w1033w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1024w1027w1030w(0) OR wire_w_lg_sink3_valid1032w(0);
+ wire_w1054w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1045w1048w1051w(0) OR wire_w_lg_sink3_valid1053w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid100w103w106w109w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid100w103w106w(0) OR wire_w_lg_sink3_valid108w(0);
+ wire_w1075w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1066w1069w1072w(0) OR wire_w_lg_sink3_valid1074w(0);
+ wire_w1096w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1087w1090w1093w(0) OR wire_w_lg_sink3_valid1095w(0);
+ wire_w1117w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1108w1111w1114w(0) OR wire_w_lg_sink3_valid1116w(0);
+ wire_w1138w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1129w1132w1135w(0) OR wire_w_lg_sink3_valid1137w(0);
+ wire_w1159w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1150w1153w1156w(0) OR wire_w_lg_sink3_valid1158w(0);
+ wire_w1180w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1171w1174w1177w(0) OR wire_w_lg_sink3_valid1179w(0);
+ wire_w1201w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1192w1195w1198w(0) OR wire_w_lg_sink3_valid1200w(0);
+ wire_w1222w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1213w1216w1219w(0) OR wire_w_lg_sink3_valid1221w(0);
+ wire_w1243w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1234w1237w1240w(0) OR wire_w_lg_sink3_valid1242w(0);
+ wire_w1264w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1255w1258w1261w(0) OR wire_w_lg_sink3_valid1263w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid121w124w127w130w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid121w124w127w(0) OR wire_w_lg_sink3_valid129w(0);
+ wire_w1285w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1276w1279w1282w(0) OR wire_w_lg_sink3_valid1284w(0);
+ wire_w1306w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1297w1300w1303w(0) OR wire_w_lg_sink3_valid1305w(0);
+ wire_w1327w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1318w1321w1324w(0) OR wire_w_lg_sink3_valid1326w(0);
+ wire_w1348w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1339w1342w1345w(0) OR wire_w_lg_sink3_valid1347w(0);
+ wire_w1369w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1360w1363w1366w(0) OR wire_w_lg_sink3_valid1368w(0);
+ wire_w1390w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1381w1384w1387w(0) OR wire_w_lg_sink3_valid1389w(0);
+ wire_w1411w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1402w1405w1408w(0) OR wire_w_lg_sink3_valid1410w(0);
+ wire_w1432w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1423w1426w1429w(0) OR wire_w_lg_sink3_valid1431w(0);
+ wire_w1453w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid1444w1447w1450w(0) OR wire_w_lg_sink3_valid1452w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid142w145w148w151w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid142w145w148w(0) OR wire_w_lg_sink3_valid150w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid163w166w169w172w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid163w166w169w(0) OR wire_w_lg_sink3_valid171w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid184w187w190w193w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid184w187w190w(0) OR wire_w_lg_sink3_valid192w(0);
+ wire_w_lg_w_lg_w_lg_w_lg_sink0_valid205w208w211w214w(0) <= wire_w_lg_w_lg_w_lg_sink0_valid205w208w211w(0) OR wire_w_lg_sink3_valid213w(0);
+ wire_w_lg_w1474w1477w(0) <= wire_w1474w(0) OR wire_w_lg_sink4_valid1476w(0);
+ wire_w_lg_w1496w1499w(0) <= wire_w1496w(0) OR wire_w_lg_sink4_valid1498w(0);
+ wire_w_lg_w1517w1520w(0) <= wire_w1517w(0) OR wire_w_lg_sink4_valid1519w(0);
+ wire_w_lg_w1538w1541w(0) <= wire_w1538w(0) OR wire_w_lg_sink4_valid1540w(0);
+ wire_w_lg_w1559w1562w(0) <= wire_w1559w(0) OR wire_w_lg_sink4_valid1561w(0);
+ wire_w_lg_w1580w1583w(0) <= wire_w1580w(0) OR wire_w_lg_sink4_valid1582w(0);
+ wire_w_lg_w1601w1604w(0) <= wire_w1601w(0) OR wire_w_lg_sink4_valid1603w(0);
+ wire_w27w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid15w18w21w24w(0) OR wire_w_lg_sink4_valid26w(0);
+ wire_w238w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid226w229w232w235w(0) OR wire_w_lg_sink4_valid237w(0);
+ wire_w259w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid247w250w253w256w(0) OR wire_w_lg_sink4_valid258w(0);
+ wire_w280w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid268w271w274w277w(0) OR wire_w_lg_sink4_valid279w(0);
+ wire_w301w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid289w292w295w298w(0) OR wire_w_lg_sink4_valid300w(0);
+ wire_w322w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid310w313w316w319w(0) OR wire_w_lg_sink4_valid321w(0);
+ wire_w343w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid331w334w337w340w(0) OR wire_w_lg_sink4_valid342w(0);
+ wire_w364w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid352w355w358w361w(0) OR wire_w_lg_sink4_valid363w(0);
+ wire_w385w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid373w376w379w382w(0) OR wire_w_lg_sink4_valid384w(0);
+ wire_w406w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid394w397w400w403w(0) OR wire_w_lg_sink4_valid405w(0);
+ wire_w427w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid415w418w421w424w(0) OR wire_w_lg_sink4_valid426w(0);
+ wire_w49w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid37w40w43w46w(0) OR wire_w_lg_sink4_valid48w(0);
+ wire_w448w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid436w439w442w445w(0) OR wire_w_lg_sink4_valid447w(0);
+ wire_w469w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid457w460w463w466w(0) OR wire_w_lg_sink4_valid468w(0);
+ wire_w490w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid478w481w484w487w(0) OR wire_w_lg_sink4_valid489w(0);
+ wire_w511w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid499w502w505w508w(0) OR wire_w_lg_sink4_valid510w(0);
+ wire_w532w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid520w523w526w529w(0) OR wire_w_lg_sink4_valid531w(0);
+ wire_w553w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid541w544w547w550w(0) OR wire_w_lg_sink4_valid552w(0);
+ wire_w574w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid562w565w568w571w(0) OR wire_w_lg_sink4_valid573w(0);
+ wire_w595w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid583w586w589w592w(0) OR wire_w_lg_sink4_valid594w(0);
+ wire_w616w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid604w607w610w613w(0) OR wire_w_lg_sink4_valid615w(0);
+ wire_w637w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid625w628w631w634w(0) OR wire_w_lg_sink4_valid636w(0);
+ wire_w70w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid58w61w64w67w(0) OR wire_w_lg_sink4_valid69w(0);
+ wire_w658w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid646w649w652w655w(0) OR wire_w_lg_sink4_valid657w(0);
+ wire_w679w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid667w670w673w676w(0) OR wire_w_lg_sink4_valid678w(0);
+ wire_w700w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid688w691w694w697w(0) OR wire_w_lg_sink4_valid699w(0);
+ wire_w721w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid709w712w715w718w(0) OR wire_w_lg_sink4_valid720w(0);
+ wire_w742w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid730w733w736w739w(0) OR wire_w_lg_sink4_valid741w(0);
+ wire_w763w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid751w754w757w760w(0) OR wire_w_lg_sink4_valid762w(0);
+ wire_w784w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid772w775w778w781w(0) OR wire_w_lg_sink4_valid783w(0);
+ wire_w805w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid793w796w799w802w(0) OR wire_w_lg_sink4_valid804w(0);
+ wire_w826w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid814w817w820w823w(0) OR wire_w_lg_sink4_valid825w(0);
+ wire_w847w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid835w838w841w844w(0) OR wire_w_lg_sink4_valid846w(0);
+ wire_w91w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid79w82w85w88w(0) OR wire_w_lg_sink4_valid90w(0);
+ wire_w868w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid856w859w862w865w(0) OR wire_w_lg_sink4_valid867w(0);
+ wire_w889w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid877w880w883w886w(0) OR wire_w_lg_sink4_valid888w(0);
+ wire_w910w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid898w901w904w907w(0) OR wire_w_lg_sink4_valid909w(0);
+ wire_w931w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid919w922w925w928w(0) OR wire_w_lg_sink4_valid930w(0);
+ wire_w952w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid940w943w946w949w(0) OR wire_w_lg_sink4_valid951w(0);
+ wire_w973w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid961w964w967w970w(0) OR wire_w_lg_sink4_valid972w(0);
+ wire_w994w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid982w985w988w991w(0) OR wire_w_lg_sink4_valid993w(0);
+ wire_w_lg_w1012w1015w(0) <= wire_w1012w(0) OR wire_w_lg_sink4_valid1014w(0);
+ wire_w_lg_w1033w1036w(0) <= wire_w1033w(0) OR wire_w_lg_sink4_valid1035w(0);
+ wire_w_lg_w1054w1057w(0) <= wire_w1054w(0) OR wire_w_lg_sink4_valid1056w(0);
+ wire_w112w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid100w103w106w109w(0) OR wire_w_lg_sink4_valid111w(0);
+ wire_w_lg_w1075w1078w(0) <= wire_w1075w(0) OR wire_w_lg_sink4_valid1077w(0);
+ wire_w_lg_w1096w1099w(0) <= wire_w1096w(0) OR wire_w_lg_sink4_valid1098w(0);
+ wire_w_lg_w1117w1120w(0) <= wire_w1117w(0) OR wire_w_lg_sink4_valid1119w(0);
+ wire_w_lg_w1138w1141w(0) <= wire_w1138w(0) OR wire_w_lg_sink4_valid1140w(0);
+ wire_w_lg_w1159w1162w(0) <= wire_w1159w(0) OR wire_w_lg_sink4_valid1161w(0);
+ wire_w_lg_w1180w1183w(0) <= wire_w1180w(0) OR wire_w_lg_sink4_valid1182w(0);
+ wire_w_lg_w1201w1204w(0) <= wire_w1201w(0) OR wire_w_lg_sink4_valid1203w(0);
+ wire_w_lg_w1222w1225w(0) <= wire_w1222w(0) OR wire_w_lg_sink4_valid1224w(0);
+ wire_w_lg_w1243w1246w(0) <= wire_w1243w(0) OR wire_w_lg_sink4_valid1245w(0);
+ wire_w_lg_w1264w1267w(0) <= wire_w1264w(0) OR wire_w_lg_sink4_valid1266w(0);
+ wire_w133w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid121w124w127w130w(0) OR wire_w_lg_sink4_valid132w(0);
+ wire_w_lg_w1285w1288w(0) <= wire_w1285w(0) OR wire_w_lg_sink4_valid1287w(0);
+ wire_w_lg_w1306w1309w(0) <= wire_w1306w(0) OR wire_w_lg_sink4_valid1308w(0);
+ wire_w_lg_w1327w1330w(0) <= wire_w1327w(0) OR wire_w_lg_sink4_valid1329w(0);
+ wire_w_lg_w1348w1351w(0) <= wire_w1348w(0) OR wire_w_lg_sink4_valid1350w(0);
+ wire_w_lg_w1369w1372w(0) <= wire_w1369w(0) OR wire_w_lg_sink4_valid1371w(0);
+ wire_w_lg_w1390w1393w(0) <= wire_w1390w(0) OR wire_w_lg_sink4_valid1392w(0);
+ wire_w_lg_w1411w1414w(0) <= wire_w1411w(0) OR wire_w_lg_sink4_valid1413w(0);
+ wire_w_lg_w1432w1435w(0) <= wire_w1432w(0) OR wire_w_lg_sink4_valid1434w(0);
+ wire_w_lg_w1453w1456w(0) <= wire_w1453w(0) OR wire_w_lg_sink4_valid1455w(0);
+ wire_w154w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid142w145w148w151w(0) OR wire_w_lg_sink4_valid153w(0);
+ wire_w175w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid163w166w169w172w(0) OR wire_w_lg_sink4_valid174w(0);
+ wire_w196w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid184w187w190w193w(0) OR wire_w_lg_sink4_valid195w(0);
+ wire_w217w(0) <= wire_w_lg_w_lg_w_lg_w_lg_sink0_valid205w208w211w214w(0) OR wire_w_lg_sink4_valid216w(0);
+ wire_w_lg_w_lg_w1474w1477w1480w(0) <= wire_w_lg_w1474w1477w(0) OR wire_w_lg_sink5_valid1479w(0);
+ wire_w_lg_w_lg_w1496w1499w1502w(0) <= wire_w_lg_w1496w1499w(0) OR wire_w_lg_sink5_valid1501w(0);
+ wire_w_lg_w_lg_w1517w1520w1523w(0) <= wire_w_lg_w1517w1520w(0) OR wire_w_lg_sink5_valid1522w(0);
+ wire_w_lg_w_lg_w1538w1541w1544w(0) <= wire_w_lg_w1538w1541w(0) OR wire_w_lg_sink5_valid1543w(0);
+ wire_w_lg_w_lg_w1559w1562w1565w(0) <= wire_w_lg_w1559w1562w(0) OR wire_w_lg_sink5_valid1564w(0);
+ wire_w_lg_w_lg_w1580w1583w1586w(0) <= wire_w_lg_w1580w1583w(0) OR wire_w_lg_sink5_valid1585w(0);
+ wire_w_lg_w_lg_w1601w1604w1607w(0) <= wire_w_lg_w1601w1604w(0) OR wire_w_lg_sink5_valid1606w(0);
+ wire_w_lg_w27w30w(0) <= wire_w27w(0) OR wire_w_lg_sink5_valid29w(0);
+ wire_w_lg_w238w241w(0) <= wire_w238w(0) OR wire_w_lg_sink5_valid240w(0);
+ wire_w_lg_w259w262w(0) <= wire_w259w(0) OR wire_w_lg_sink5_valid261w(0);
+ wire_w_lg_w280w283w(0) <= wire_w280w(0) OR wire_w_lg_sink5_valid282w(0);
+ wire_w_lg_w301w304w(0) <= wire_w301w(0) OR wire_w_lg_sink5_valid303w(0);
+ wire_w_lg_w322w325w(0) <= wire_w322w(0) OR wire_w_lg_sink5_valid324w(0);
+ wire_w_lg_w343w346w(0) <= wire_w343w(0) OR wire_w_lg_sink5_valid345w(0);
+ wire_w_lg_w364w367w(0) <= wire_w364w(0) OR wire_w_lg_sink5_valid366w(0);
+ wire_w_lg_w385w388w(0) <= wire_w385w(0) OR wire_w_lg_sink5_valid387w(0);
+ wire_w_lg_w406w409w(0) <= wire_w406w(0) OR wire_w_lg_sink5_valid408w(0);
+ wire_w_lg_w427w430w(0) <= wire_w427w(0) OR wire_w_lg_sink5_valid429w(0);
+ wire_w_lg_w49w52w(0) <= wire_w49w(0) OR wire_w_lg_sink5_valid51w(0);
+ wire_w_lg_w448w451w(0) <= wire_w448w(0) OR wire_w_lg_sink5_valid450w(0);
+ wire_w_lg_w469w472w(0) <= wire_w469w(0) OR wire_w_lg_sink5_valid471w(0);
+ wire_w_lg_w490w493w(0) <= wire_w490w(0) OR wire_w_lg_sink5_valid492w(0);
+ wire_w_lg_w511w514w(0) <= wire_w511w(0) OR wire_w_lg_sink5_valid513w(0);
+ wire_w_lg_w532w535w(0) <= wire_w532w(0) OR wire_w_lg_sink5_valid534w(0);
+ wire_w_lg_w553w556w(0) <= wire_w553w(0) OR wire_w_lg_sink5_valid555w(0);
+ wire_w_lg_w574w577w(0) <= wire_w574w(0) OR wire_w_lg_sink5_valid576w(0);
+ wire_w_lg_w595w598w(0) <= wire_w595w(0) OR wire_w_lg_sink5_valid597w(0);
+ wire_w_lg_w616w619w(0) <= wire_w616w(0) OR wire_w_lg_sink5_valid618w(0);
+ wire_w_lg_w637w640w(0) <= wire_w637w(0) OR wire_w_lg_sink5_valid639w(0);
+ wire_w_lg_w70w73w(0) <= wire_w70w(0) OR wire_w_lg_sink5_valid72w(0);
+ wire_w_lg_w658w661w(0) <= wire_w658w(0) OR wire_w_lg_sink5_valid660w(0);
+ wire_w_lg_w679w682w(0) <= wire_w679w(0) OR wire_w_lg_sink5_valid681w(0);
+ wire_w_lg_w700w703w(0) <= wire_w700w(0) OR wire_w_lg_sink5_valid702w(0);
+ wire_w_lg_w721w724w(0) <= wire_w721w(0) OR wire_w_lg_sink5_valid723w(0);
+ wire_w_lg_w742w745w(0) <= wire_w742w(0) OR wire_w_lg_sink5_valid744w(0);
+ wire_w_lg_w763w766w(0) <= wire_w763w(0) OR wire_w_lg_sink5_valid765w(0);
+ wire_w_lg_w784w787w(0) <= wire_w784w(0) OR wire_w_lg_sink5_valid786w(0);
+ wire_w_lg_w805w808w(0) <= wire_w805w(0) OR wire_w_lg_sink5_valid807w(0);
+ wire_w_lg_w826w829w(0) <= wire_w826w(0) OR wire_w_lg_sink5_valid828w(0);
+ wire_w_lg_w847w850w(0) <= wire_w847w(0) OR wire_w_lg_sink5_valid849w(0);
+ wire_w_lg_w91w94w(0) <= wire_w91w(0) OR wire_w_lg_sink5_valid93w(0);
+ wire_w_lg_w868w871w(0) <= wire_w868w(0) OR wire_w_lg_sink5_valid870w(0);
+ wire_w_lg_w889w892w(0) <= wire_w889w(0) OR wire_w_lg_sink5_valid891w(0);
+ wire_w_lg_w910w913w(0) <= wire_w910w(0) OR wire_w_lg_sink5_valid912w(0);
+ wire_w_lg_w931w934w(0) <= wire_w931w(0) OR wire_w_lg_sink5_valid933w(0);
+ wire_w_lg_w952w955w(0) <= wire_w952w(0) OR wire_w_lg_sink5_valid954w(0);
+ wire_w_lg_w973w976w(0) <= wire_w973w(0) OR wire_w_lg_sink5_valid975w(0);
+ wire_w_lg_w994w997w(0) <= wire_w994w(0) OR wire_w_lg_sink5_valid996w(0);
+ wire_w_lg_w_lg_w1012w1015w1018w(0) <= wire_w_lg_w1012w1015w(0) OR wire_w_lg_sink5_valid1017w(0);
+ wire_w_lg_w_lg_w1033w1036w1039w(0) <= wire_w_lg_w1033w1036w(0) OR wire_w_lg_sink5_valid1038w(0);
+ wire_w_lg_w_lg_w1054w1057w1060w(0) <= wire_w_lg_w1054w1057w(0) OR wire_w_lg_sink5_valid1059w(0);
+ wire_w_lg_w112w115w(0) <= wire_w112w(0) OR wire_w_lg_sink5_valid114w(0);
+ wire_w_lg_w_lg_w1075w1078w1081w(0) <= wire_w_lg_w1075w1078w(0) OR wire_w_lg_sink5_valid1080w(0);
+ wire_w_lg_w_lg_w1096w1099w1102w(0) <= wire_w_lg_w1096w1099w(0) OR wire_w_lg_sink5_valid1101w(0);
+ wire_w_lg_w_lg_w1117w1120w1123w(0) <= wire_w_lg_w1117w1120w(0) OR wire_w_lg_sink5_valid1122w(0);
+ wire_w_lg_w_lg_w1138w1141w1144w(0) <= wire_w_lg_w1138w1141w(0) OR wire_w_lg_sink5_valid1143w(0);
+ wire_w_lg_w_lg_w1159w1162w1165w(0) <= wire_w_lg_w1159w1162w(0) OR wire_w_lg_sink5_valid1164w(0);
+ wire_w_lg_w_lg_w1180w1183w1186w(0) <= wire_w_lg_w1180w1183w(0) OR wire_w_lg_sink5_valid1185w(0);
+ wire_w_lg_w_lg_w1201w1204w1207w(0) <= wire_w_lg_w1201w1204w(0) OR wire_w_lg_sink5_valid1206w(0);
+ wire_w_lg_w_lg_w1222w1225w1228w(0) <= wire_w_lg_w1222w1225w(0) OR wire_w_lg_sink5_valid1227w(0);
+ wire_w_lg_w_lg_w1243w1246w1249w(0) <= wire_w_lg_w1243w1246w(0) OR wire_w_lg_sink5_valid1248w(0);
+ wire_w_lg_w_lg_w1264w1267w1270w(0) <= wire_w_lg_w1264w1267w(0) OR wire_w_lg_sink5_valid1269w(0);
+ wire_w_lg_w133w136w(0) <= wire_w133w(0) OR wire_w_lg_sink5_valid135w(0);
+ wire_w_lg_w_lg_w1285w1288w1291w(0) <= wire_w_lg_w1285w1288w(0) OR wire_w_lg_sink5_valid1290w(0);
+ wire_w_lg_w_lg_w1306w1309w1312w(0) <= wire_w_lg_w1306w1309w(0) OR wire_w_lg_sink5_valid1311w(0);
+ wire_w_lg_w_lg_w1327w1330w1333w(0) <= wire_w_lg_w1327w1330w(0) OR wire_w_lg_sink5_valid1332w(0);
+ wire_w_lg_w_lg_w1348w1351w1354w(0) <= wire_w_lg_w1348w1351w(0) OR wire_w_lg_sink5_valid1353w(0);
+ wire_w_lg_w_lg_w1369w1372w1375w(0) <= wire_w_lg_w1369w1372w(0) OR wire_w_lg_sink5_valid1374w(0);
+ wire_w_lg_w_lg_w1390w1393w1396w(0) <= wire_w_lg_w1390w1393w(0) OR wire_w_lg_sink5_valid1395w(0);
+ wire_w_lg_w_lg_w1411w1414w1417w(0) <= wire_w_lg_w1411w1414w(0) OR wire_w_lg_sink5_valid1416w(0);
+ wire_w_lg_w_lg_w1432w1435w1438w(0) <= wire_w_lg_w1432w1435w(0) OR wire_w_lg_sink5_valid1437w(0);
+ wire_w_lg_w_lg_w1453w1456w1459w(0) <= wire_w_lg_w1453w1456w(0) OR wire_w_lg_sink5_valid1458w(0);
+ wire_w_lg_w154w157w(0) <= wire_w154w(0) OR wire_w_lg_sink5_valid156w(0);
+ wire_w_lg_w175w178w(0) <= wire_w175w(0) OR wire_w_lg_sink5_valid177w(0);
+ wire_w_lg_w196w199w(0) <= wire_w196w(0) OR wire_w_lg_sink5_valid198w(0);
+ wire_w_lg_w217w220w(0) <= wire_w217w(0) OR wire_w_lg_sink5_valid219w(0);
+ wire_w_lg_w_lg_w_lg_w1474w1477w1480w1483w(0) <= wire_w_lg_w_lg_w1474w1477w1480w(0) OR wire_w_lg_sink6_valid1482w(0);
+ wire_w_lg_w_lg_w_lg_w1496w1499w1502w1505w(0) <= wire_w_lg_w_lg_w1496w1499w1502w(0) OR wire_w_lg_sink6_valid1504w(0);
+ wire_w_lg_w_lg_w_lg_w1517w1520w1523w1526w(0) <= wire_w_lg_w_lg_w1517w1520w1523w(0) OR wire_w_lg_sink6_valid1525w(0);
+ wire_w_lg_w_lg_w_lg_w1538w1541w1544w1547w(0) <= wire_w_lg_w_lg_w1538w1541w1544w(0) OR wire_w_lg_sink6_valid1546w(0);
+ wire_w_lg_w_lg_w_lg_w1559w1562w1565w1568w(0) <= wire_w_lg_w_lg_w1559w1562w1565w(0) OR wire_w_lg_sink6_valid1567w(0);
+ wire_w_lg_w_lg_w_lg_w1580w1583w1586w1589w(0) <= wire_w_lg_w_lg_w1580w1583w1586w(0) OR wire_w_lg_sink6_valid1588w(0);
+ wire_w_lg_w_lg_w_lg_w1601w1604w1607w1610w(0) <= wire_w_lg_w_lg_w1601w1604w1607w(0) OR wire_w_lg_sink6_valid1609w(0);
+ wire_w_lg_w_lg_w27w30w33w(0) <= wire_w_lg_w27w30w(0) OR wire_w_lg_sink6_valid32w(0);
+ wire_w_lg_w_lg_w238w241w244w(0) <= wire_w_lg_w238w241w(0) OR wire_w_lg_sink6_valid243w(0);
+ wire_w_lg_w_lg_w259w262w265w(0) <= wire_w_lg_w259w262w(0) OR wire_w_lg_sink6_valid264w(0);
+ wire_w_lg_w_lg_w280w283w286w(0) <= wire_w_lg_w280w283w(0) OR wire_w_lg_sink6_valid285w(0);
+ wire_w_lg_w_lg_w301w304w307w(0) <= wire_w_lg_w301w304w(0) OR wire_w_lg_sink6_valid306w(0);
+ wire_w_lg_w_lg_w322w325w328w(0) <= wire_w_lg_w322w325w(0) OR wire_w_lg_sink6_valid327w(0);
+ wire_w_lg_w_lg_w343w346w349w(0) <= wire_w_lg_w343w346w(0) OR wire_w_lg_sink6_valid348w(0);
+ wire_w_lg_w_lg_w364w367w370w(0) <= wire_w_lg_w364w367w(0) OR wire_w_lg_sink6_valid369w(0);
+ wire_w_lg_w_lg_w385w388w391w(0) <= wire_w_lg_w385w388w(0) OR wire_w_lg_sink6_valid390w(0);
+ wire_w_lg_w_lg_w406w409w412w(0) <= wire_w_lg_w406w409w(0) OR wire_w_lg_sink6_valid411w(0);
+ wire_w_lg_w_lg_w427w430w433w(0) <= wire_w_lg_w427w430w(0) OR wire_w_lg_sink6_valid432w(0);
+ wire_w_lg_w_lg_w49w52w55w(0) <= wire_w_lg_w49w52w(0) OR wire_w_lg_sink6_valid54w(0);
+ wire_w_lg_w_lg_w448w451w454w(0) <= wire_w_lg_w448w451w(0) OR wire_w_lg_sink6_valid453w(0);
+ wire_w_lg_w_lg_w469w472w475w(0) <= wire_w_lg_w469w472w(0) OR wire_w_lg_sink6_valid474w(0);
+ wire_w_lg_w_lg_w490w493w496w(0) <= wire_w_lg_w490w493w(0) OR wire_w_lg_sink6_valid495w(0);
+ wire_w_lg_w_lg_w511w514w517w(0) <= wire_w_lg_w511w514w(0) OR wire_w_lg_sink6_valid516w(0);
+ wire_w_lg_w_lg_w532w535w538w(0) <= wire_w_lg_w532w535w(0) OR wire_w_lg_sink6_valid537w(0);
+ wire_w_lg_w_lg_w553w556w559w(0) <= wire_w_lg_w553w556w(0) OR wire_w_lg_sink6_valid558w(0);
+ wire_w_lg_w_lg_w574w577w580w(0) <= wire_w_lg_w574w577w(0) OR wire_w_lg_sink6_valid579w(0);
+ wire_w_lg_w_lg_w595w598w601w(0) <= wire_w_lg_w595w598w(0) OR wire_w_lg_sink6_valid600w(0);
+ wire_w_lg_w_lg_w616w619w622w(0) <= wire_w_lg_w616w619w(0) OR wire_w_lg_sink6_valid621w(0);
+ wire_w_lg_w_lg_w637w640w643w(0) <= wire_w_lg_w637w640w(0) OR wire_w_lg_sink6_valid642w(0);
+ wire_w_lg_w_lg_w70w73w76w(0) <= wire_w_lg_w70w73w(0) OR wire_w_lg_sink6_valid75w(0);
+ wire_w_lg_w_lg_w658w661w664w(0) <= wire_w_lg_w658w661w(0) OR wire_w_lg_sink6_valid663w(0);
+ wire_w_lg_w_lg_w679w682w685w(0) <= wire_w_lg_w679w682w(0) OR wire_w_lg_sink6_valid684w(0);
+ wire_w_lg_w_lg_w700w703w706w(0) <= wire_w_lg_w700w703w(0) OR wire_w_lg_sink6_valid705w(0);
+ wire_w_lg_w_lg_w721w724w727w(0) <= wire_w_lg_w721w724w(0) OR wire_w_lg_sink6_valid726w(0);
+ wire_w_lg_w_lg_w742w745w748w(0) <= wire_w_lg_w742w745w(0) OR wire_w_lg_sink6_valid747w(0);
+ wire_w_lg_w_lg_w763w766w769w(0) <= wire_w_lg_w763w766w(0) OR wire_w_lg_sink6_valid768w(0);
+ wire_w_lg_w_lg_w784w787w790w(0) <= wire_w_lg_w784w787w(0) OR wire_w_lg_sink6_valid789w(0);
+ wire_w_lg_w_lg_w805w808w811w(0) <= wire_w_lg_w805w808w(0) OR wire_w_lg_sink6_valid810w(0);
+ wire_w_lg_w_lg_w826w829w832w(0) <= wire_w_lg_w826w829w(0) OR wire_w_lg_sink6_valid831w(0);
+ wire_w_lg_w_lg_w847w850w853w(0) <= wire_w_lg_w847w850w(0) OR wire_w_lg_sink6_valid852w(0);
+ wire_w_lg_w_lg_w91w94w97w(0) <= wire_w_lg_w91w94w(0) OR wire_w_lg_sink6_valid96w(0);
+ wire_w_lg_w_lg_w868w871w874w(0) <= wire_w_lg_w868w871w(0) OR wire_w_lg_sink6_valid873w(0);
+ wire_w_lg_w_lg_w889w892w895w(0) <= wire_w_lg_w889w892w(0) OR wire_w_lg_sink6_valid894w(0);
+ wire_w_lg_w_lg_w910w913w916w(0) <= wire_w_lg_w910w913w(0) OR wire_w_lg_sink6_valid915w(0);
+ wire_w_lg_w_lg_w931w934w937w(0) <= wire_w_lg_w931w934w(0) OR wire_w_lg_sink6_valid936w(0);
+ wire_w_lg_w_lg_w952w955w958w(0) <= wire_w_lg_w952w955w(0) OR wire_w_lg_sink6_valid957w(0);
+ wire_w_lg_w_lg_w973w976w979w(0) <= wire_w_lg_w973w976w(0) OR wire_w_lg_sink6_valid978w(0);
+ wire_w_lg_w_lg_w994w997w1000w(0) <= wire_w_lg_w994w997w(0) OR wire_w_lg_sink6_valid999w(0);
+ wire_w_lg_w_lg_w_lg_w1012w1015w1018w1021w(0) <= wire_w_lg_w_lg_w1012w1015w1018w(0) OR wire_w_lg_sink6_valid1020w(0);
+ wire_w_lg_w_lg_w_lg_w1033w1036w1039w1042w(0) <= wire_w_lg_w_lg_w1033w1036w1039w(0) OR wire_w_lg_sink6_valid1041w(0);
+ wire_w_lg_w_lg_w_lg_w1054w1057w1060w1063w(0) <= wire_w_lg_w_lg_w1054w1057w1060w(0) OR wire_w_lg_sink6_valid1062w(0);
+ wire_w_lg_w_lg_w112w115w118w(0) <= wire_w_lg_w112w115w(0) OR wire_w_lg_sink6_valid117w(0);
+ wire_w_lg_w_lg_w_lg_w1075w1078w1081w1084w(0) <= wire_w_lg_w_lg_w1075w1078w1081w(0) OR wire_w_lg_sink6_valid1083w(0);
+ wire_w_lg_w_lg_w_lg_w1096w1099w1102w1105w(0) <= wire_w_lg_w_lg_w1096w1099w1102w(0) OR wire_w_lg_sink6_valid1104w(0);
+ wire_w_lg_w_lg_w_lg_w1117w1120w1123w1126w(0) <= wire_w_lg_w_lg_w1117w1120w1123w(0) OR wire_w_lg_sink6_valid1125w(0);
+ wire_w_lg_w_lg_w_lg_w1138w1141w1144w1147w(0) <= wire_w_lg_w_lg_w1138w1141w1144w(0) OR wire_w_lg_sink6_valid1146w(0);
+ wire_w_lg_w_lg_w_lg_w1159w1162w1165w1168w(0) <= wire_w_lg_w_lg_w1159w1162w1165w(0) OR wire_w_lg_sink6_valid1167w(0);
+ wire_w_lg_w_lg_w_lg_w1180w1183w1186w1189w(0) <= wire_w_lg_w_lg_w1180w1183w1186w(0) OR wire_w_lg_sink6_valid1188w(0);
+ wire_w_lg_w_lg_w_lg_w1201w1204w1207w1210w(0) <= wire_w_lg_w_lg_w1201w1204w1207w(0) OR wire_w_lg_sink6_valid1209w(0);
+ wire_w_lg_w_lg_w_lg_w1222w1225w1228w1231w(0) <= wire_w_lg_w_lg_w1222w1225w1228w(0) OR wire_w_lg_sink6_valid1230w(0);
+ wire_w_lg_w_lg_w_lg_w1243w1246w1249w1252w(0) <= wire_w_lg_w_lg_w1243w1246w1249w(0) OR wire_w_lg_sink6_valid1251w(0);
+ wire_w_lg_w_lg_w_lg_w1264w1267w1270w1273w(0) <= wire_w_lg_w_lg_w1264w1267w1270w(0) OR wire_w_lg_sink6_valid1272w(0);
+ wire_w_lg_w_lg_w133w136w139w(0) <= wire_w_lg_w133w136w(0) OR wire_w_lg_sink6_valid138w(0);
+ wire_w_lg_w_lg_w_lg_w1285w1288w1291w1294w(0) <= wire_w_lg_w_lg_w1285w1288w1291w(0) OR wire_w_lg_sink6_valid1293w(0);
+ wire_w_lg_w_lg_w_lg_w1306w1309w1312w1315w(0) <= wire_w_lg_w_lg_w1306w1309w1312w(0) OR wire_w_lg_sink6_valid1314w(0);
+ wire_w_lg_w_lg_w_lg_w1327w1330w1333w1336w(0) <= wire_w_lg_w_lg_w1327w1330w1333w(0) OR wire_w_lg_sink6_valid1335w(0);
+ wire_w_lg_w_lg_w_lg_w1348w1351w1354w1357w(0) <= wire_w_lg_w_lg_w1348w1351w1354w(0) OR wire_w_lg_sink6_valid1356w(0);
+ wire_w_lg_w_lg_w_lg_w1369w1372w1375w1378w(0) <= wire_w_lg_w_lg_w1369w1372w1375w(0) OR wire_w_lg_sink6_valid1377w(0);
+ wire_w_lg_w_lg_w_lg_w1390w1393w1396w1399w(0) <= wire_w_lg_w_lg_w1390w1393w1396w(0) OR wire_w_lg_sink6_valid1398w(0);
+ wire_w_lg_w_lg_w_lg_w1411w1414w1417w1420w(0) <= wire_w_lg_w_lg_w1411w1414w1417w(0) OR wire_w_lg_sink6_valid1419w(0);
+ wire_w_lg_w_lg_w_lg_w1432w1435w1438w1441w(0) <= wire_w_lg_w_lg_w1432w1435w1438w(0) OR wire_w_lg_sink6_valid1440w(0);
+ wire_w_lg_w_lg_w_lg_w1453w1456w1459w1462w(0) <= wire_w_lg_w_lg_w1453w1456w1459w(0) OR wire_w_lg_sink6_valid1461w(0);
+ wire_w_lg_w_lg_w154w157w160w(0) <= wire_w_lg_w154w157w(0) OR wire_w_lg_sink6_valid159w(0);
+ wire_w_lg_w_lg_w175w178w181w(0) <= wire_w_lg_w175w178w(0) OR wire_w_lg_sink6_valid180w(0);
+ wire_w_lg_w_lg_w196w199w202w(0) <= wire_w_lg_w196w199w(0) OR wire_w_lg_sink6_valid201w(0);
+ wire_w_lg_w_lg_w217w220w223w(0) <= wire_w_lg_w217w220w(0) OR wire_w_lg_sink6_valid222w(0);
+ s_wire_altera_merlin_multiplexer_0003_wideor1_28_dataout <= ((((((sink0_valid OR sink1_valid) OR sink2_valid) OR sink3_valid) OR sink4_valid) OR sink5_valid) OR sink6_valid);
+ sink0_ready <= (sink0_valid AND src_ready);
+ sink1_ready <= (sink1_valid AND src_ready);
+ sink2_ready <= (sink2_valid AND src_ready);
+ sink3_ready <= (sink3_valid AND src_ready);
+ sink4_ready <= (sink4_valid AND src_ready);
+ sink5_ready <= (sink5_valid AND src_ready);
+ sink6_ready <= (sink6_valid AND src_ready);
+ src_channel <= ( wire_w_lg_w_lg_w_lg_w1601w1604w1607w1610w & wire_w_lg_w_lg_w_lg_w1580w1583w1586w1589w & wire_w_lg_w_lg_w_lg_w1559w1562w1565w1568w & wire_w_lg_w_lg_w_lg_w1538w1541w1544w1547w & wire_w_lg_w_lg_w_lg_w1517w1520w1523w1526w & wire_w_lg_w_lg_w_lg_w1496w1499w1502w1505w & wire_w_lg_w_lg_w_lg_w1474w1477w1480w1483w);
+ src_data <= ( wire_w_lg_w_lg_w_lg_w1453w1456w1459w1462w & wire_w_lg_w_lg_w_lg_w1432w1435w1438w1441w & wire_w_lg_w_lg_w_lg_w1411w1414w1417w1420w & wire_w_lg_w_lg_w_lg_w1390w1393w1396w1399w & wire_w_lg_w_lg_w_lg_w1369w1372w1375w1378w & wire_w_lg_w_lg_w_lg_w1348w1351w1354w1357w & wire_w_lg_w_lg_w_lg_w1327w1330w1333w1336w & wire_w_lg_w_lg_w_lg_w1306w1309w1312w1315w & wire_w_lg_w_lg_w_lg_w1285w1288w1291w1294w & wire_w_lg_w_lg_w_lg_w1264w1267w1270w1273w & wire_w_lg_w_lg_w_lg_w1243w1246w1249w1252w & wire_w_lg_w_lg_w_lg_w1222w1225w1228w1231w & wire_w_lg_w_lg_w_lg_w1201w1204w1207w1210w & wire_w_lg_w_lg_w_lg_w1180w1183w1186w1189w & wire_w_lg_w_lg_w_lg_w1159w1162w1165w1168w & wire_w_lg_w_lg_w_lg_w1138w1141w1144w1147w & wire_w_lg_w_lg_w_lg_w1117w1120w1123w1126w & wire_w_lg_w_lg_w_lg_w1096w1099w1102w1105w & wire_w_lg_w_lg_w_lg_w1075w1078w1081w1084w & wire_w_lg_w_lg_w_lg_w1054w1057w1060w1063w & wire_w_lg_w_lg_w_lg_w1033w1036w1039w1042w & wire_w_lg_w_lg_w_lg_w1012w1015w1018w1021w & wire_w_lg_w_lg_w994w997w1000w & wire_w_lg_w_lg_w973w976w979w & wire_w_lg_w_lg_w952w955w958w & wire_w_lg_w_lg_w931w934w937w & wire_w_lg_w_lg_w910w913w916w & wire_w_lg_w_lg_w889w892w895w & wire_w_lg_w_lg_w868w871w874w & wire_w_lg_w_lg_w847w850w853w & wire_w_lg_w_lg_w826w829w832w & wire_w_lg_w_lg_w805w808w811w & wire_w_lg_w_lg_w784w787w790w & wire_w_lg_w_lg_w763w766w769w & wire_w_lg_w_lg_w742w745w748w & wire_w_lg_w_lg_w721w724w727w & wire_w_lg_w_lg_w700w703w706w & wire_w_lg_w_lg_w679w682w685w & wire_w_lg_w_lg_w658w661w664w & wire_w_lg_w_lg_w637w640w643w & wire_w_lg_w_lg_w616w619w622w & wire_w_lg_w_lg_w595w598w601w & wire_w_lg_w_lg_w574w577w580w & wire_w_lg_w_lg_w553w556w559w & wire_w_lg_w_lg_w532w535w538w & wire_w_lg_w_lg_w511w514w517w & wire_w_lg_w_lg_w490w493w496w & wire_w_lg_w_lg_w469w472w475w & wire_w_lg_w_lg_w448w451w454w & wire_w_lg_w_lg_w427w430w433w & wire_w_lg_w_lg_w406w409w412w & wire_w_lg_w_lg_w385w388w391w & wire_w_lg_w_lg_w364w367w370w & wire_w_lg_w_lg_w343w346w349w & wire_w_lg_w_lg_w322w325w328w & wire_w_lg_w_lg_w301w304w307w & wire_w_lg_w_lg_w280w283w286w
+ & wire_w_lg_w_lg_w259w262w265w & wire_w_lg_w_lg_w238w241w244w & wire_w_lg_w_lg_w217w220w223w & wire_w_lg_w_lg_w196w199w202w & wire_w_lg_w_lg_w175w178w181w & wire_w_lg_w_lg_w154w157w160w & wire_w_lg_w_lg_w133w136w139w & wire_w_lg_w_lg_w112w115w118w & wire_w_lg_w_lg_w91w94w97w & wire_w_lg_w_lg_w70w73w76w & wire_w_lg_w_lg_w49w52w55w & wire_w_lg_w_lg_w27w30w33w);
+ src_endofpacket <= (((((((sink0_valid AND sink0_endofpacket) OR (sink1_valid AND sink1_endofpacket)) OR (sink2_valid AND sink2_endofpacket)) OR (sink3_valid AND sink3_endofpacket)) OR (sink4_valid AND sink4_endofpacket)) OR (sink5_valid AND sink5_endofpacket)) OR (sink6_valid AND sink6_endofpacket));
+ src_startofpacket <= (((((((sink0_valid AND sink0_startofpacket) OR (sink1_valid AND sink1_startofpacket)) OR (sink2_valid AND sink2_startofpacket)) OR (sink3_valid AND sink3_startofpacket)) OR (sink4_valid AND sink4_startofpacket)) OR (sink5_valid AND sink5_startofpacket)) OR (sink6_valid AND sink6_startofpacket));
+ src_valid <= s_wire_altera_merlin_multiplexer_0003_wideor1_28_dataout;
+ wire_w_sink0_channel_range1464w(0) <= sink0_channel(0);
+ wire_w_sink0_channel_range1486w(0) <= sink0_channel(1);
+ wire_w_sink0_channel_range1507w(0) <= sink0_channel(2);
+ wire_w_sink0_channel_range1528w(0) <= sink0_channel(3);
+ wire_w_sink0_channel_range1549w(0) <= sink0_channel(4);
+ wire_w_sink0_channel_range1570w(0) <= sink0_channel(5);
+ wire_w_sink0_channel_range1591w(0) <= sink0_channel(6);
+ wire_w_sink0_data_range14w(0) <= sink0_data(0);
+ wire_w_sink0_data_range225w(0) <= sink0_data(10);
+ wire_w_sink0_data_range246w(0) <= sink0_data(11);
+ wire_w_sink0_data_range267w(0) <= sink0_data(12);
+ wire_w_sink0_data_range288w(0) <= sink0_data(13);
+ wire_w_sink0_data_range309w(0) <= sink0_data(14);
+ wire_w_sink0_data_range330w(0) <= sink0_data(15);
+ wire_w_sink0_data_range351w(0) <= sink0_data(16);
+ wire_w_sink0_data_range372w(0) <= sink0_data(17);
+ wire_w_sink0_data_range393w(0) <= sink0_data(18);
+ wire_w_sink0_data_range414w(0) <= sink0_data(19);
+ wire_w_sink0_data_range36w(0) <= sink0_data(1);
+ wire_w_sink0_data_range435w(0) <= sink0_data(20);
+ wire_w_sink0_data_range456w(0) <= sink0_data(21);
+ wire_w_sink0_data_range477w(0) <= sink0_data(22);
+ wire_w_sink0_data_range498w(0) <= sink0_data(23);
+ wire_w_sink0_data_range519w(0) <= sink0_data(24);
+ wire_w_sink0_data_range540w(0) <= sink0_data(25);
+ wire_w_sink0_data_range561w(0) <= sink0_data(26);
+ wire_w_sink0_data_range582w(0) <= sink0_data(27);
+ wire_w_sink0_data_range603w(0) <= sink0_data(28);
+ wire_w_sink0_data_range624w(0) <= sink0_data(29);
+ wire_w_sink0_data_range57w(0) <= sink0_data(2);
+ wire_w_sink0_data_range645w(0) <= sink0_data(30);
+ wire_w_sink0_data_range666w(0) <= sink0_data(31);
+ wire_w_sink0_data_range687w(0) <= sink0_data(32);
+ wire_w_sink0_data_range708w(0) <= sink0_data(33);
+ wire_w_sink0_data_range729w(0) <= sink0_data(34);
+ wire_w_sink0_data_range750w(0) <= sink0_data(35);
+ wire_w_sink0_data_range771w(0) <= sink0_data(36);
+ wire_w_sink0_data_range792w(0) <= sink0_data(37);
+ wire_w_sink0_data_range813w(0) <= sink0_data(38);
+ wire_w_sink0_data_range834w(0) <= sink0_data(39);
+ wire_w_sink0_data_range78w(0) <= sink0_data(3);
+ wire_w_sink0_data_range855w(0) <= sink0_data(40);
+ wire_w_sink0_data_range876w(0) <= sink0_data(41);
+ wire_w_sink0_data_range897w(0) <= sink0_data(42);
+ wire_w_sink0_data_range918w(0) <= sink0_data(43);
+ wire_w_sink0_data_range939w(0) <= sink0_data(44);
+ wire_w_sink0_data_range960w(0) <= sink0_data(45);
+ wire_w_sink0_data_range981w(0) <= sink0_data(46);
+ wire_w_sink0_data_range1002w(0) <= sink0_data(47);
+ wire_w_sink0_data_range1023w(0) <= sink0_data(48);
+ wire_w_sink0_data_range1044w(0) <= sink0_data(49);
+ wire_w_sink0_data_range99w(0) <= sink0_data(4);
+ wire_w_sink0_data_range1065w(0) <= sink0_data(50);
+ wire_w_sink0_data_range1086w(0) <= sink0_data(51);
+ wire_w_sink0_data_range1107w(0) <= sink0_data(52);
+ wire_w_sink0_data_range1128w(0) <= sink0_data(53);
+ wire_w_sink0_data_range1149w(0) <= sink0_data(54);
+ wire_w_sink0_data_range1170w(0) <= sink0_data(55);
+ wire_w_sink0_data_range1191w(0) <= sink0_data(56);
+ wire_w_sink0_data_range1212w(0) <= sink0_data(57);
+ wire_w_sink0_data_range1233w(0) <= sink0_data(58);
+ wire_w_sink0_data_range1254w(0) <= sink0_data(59);
+ wire_w_sink0_data_range120w(0) <= sink0_data(5);
+ wire_w_sink0_data_range1275w(0) <= sink0_data(60);
+ wire_w_sink0_data_range1296w(0) <= sink0_data(61);
+ wire_w_sink0_data_range1317w(0) <= sink0_data(62);
+ wire_w_sink0_data_range1338w(0) <= sink0_data(63);
+ wire_w_sink0_data_range1359w(0) <= sink0_data(64);
+ wire_w_sink0_data_range1380w(0) <= sink0_data(65);
+ wire_w_sink0_data_range1401w(0) <= sink0_data(66);
+ wire_w_sink0_data_range1422w(0) <= sink0_data(67);
+ wire_w_sink0_data_range1443w(0) <= sink0_data(68);
+ wire_w_sink0_data_range141w(0) <= sink0_data(6);
+ wire_w_sink0_data_range162w(0) <= sink0_data(7);
+ wire_w_sink0_data_range183w(0) <= sink0_data(8);
+ wire_w_sink0_data_range204w(0) <= sink0_data(9);
+ wire_w_sink1_channel_range1466w(0) <= sink1_channel(0);
+ wire_w_sink1_channel_range1488w(0) <= sink1_channel(1);
+ wire_w_sink1_channel_range1509w(0) <= sink1_channel(2);
+ wire_w_sink1_channel_range1530w(0) <= sink1_channel(3);
+ wire_w_sink1_channel_range1551w(0) <= sink1_channel(4);
+ wire_w_sink1_channel_range1572w(0) <= sink1_channel(5);
+ wire_w_sink1_channel_range1593w(0) <= sink1_channel(6);
+ wire_w_sink1_data_range16w(0) <= sink1_data(0);
+ wire_w_sink1_data_range227w(0) <= sink1_data(10);
+ wire_w_sink1_data_range248w(0) <= sink1_data(11);
+ wire_w_sink1_data_range269w(0) <= sink1_data(12);
+ wire_w_sink1_data_range290w(0) <= sink1_data(13);
+ wire_w_sink1_data_range311w(0) <= sink1_data(14);
+ wire_w_sink1_data_range332w(0) <= sink1_data(15);
+ wire_w_sink1_data_range353w(0) <= sink1_data(16);
+ wire_w_sink1_data_range374w(0) <= sink1_data(17);
+ wire_w_sink1_data_range395w(0) <= sink1_data(18);
+ wire_w_sink1_data_range416w(0) <= sink1_data(19);
+ wire_w_sink1_data_range38w(0) <= sink1_data(1);
+ wire_w_sink1_data_range437w(0) <= sink1_data(20);
+ wire_w_sink1_data_range458w(0) <= sink1_data(21);
+ wire_w_sink1_data_range479w(0) <= sink1_data(22);
+ wire_w_sink1_data_range500w(0) <= sink1_data(23);
+ wire_w_sink1_data_range521w(0) <= sink1_data(24);
+ wire_w_sink1_data_range542w(0) <= sink1_data(25);
+ wire_w_sink1_data_range563w(0) <= sink1_data(26);
+ wire_w_sink1_data_range584w(0) <= sink1_data(27);
+ wire_w_sink1_data_range605w(0) <= sink1_data(28);
+ wire_w_sink1_data_range626w(0) <= sink1_data(29);
+ wire_w_sink1_data_range59w(0) <= sink1_data(2);
+ wire_w_sink1_data_range647w(0) <= sink1_data(30);
+ wire_w_sink1_data_range668w(0) <= sink1_data(31);
+ wire_w_sink1_data_range689w(0) <= sink1_data(32);
+ wire_w_sink1_data_range710w(0) <= sink1_data(33);
+ wire_w_sink1_data_range731w(0) <= sink1_data(34);
+ wire_w_sink1_data_range752w(0) <= sink1_data(35);
+ wire_w_sink1_data_range773w(0) <= sink1_data(36);
+ wire_w_sink1_data_range794w(0) <= sink1_data(37);
+ wire_w_sink1_data_range815w(0) <= sink1_data(38);
+ wire_w_sink1_data_range836w(0) <= sink1_data(39);
+ wire_w_sink1_data_range80w(0) <= sink1_data(3);
+ wire_w_sink1_data_range857w(0) <= sink1_data(40);
+ wire_w_sink1_data_range878w(0) <= sink1_data(41);
+ wire_w_sink1_data_range899w(0) <= sink1_data(42);
+ wire_w_sink1_data_range920w(0) <= sink1_data(43);
+ wire_w_sink1_data_range941w(0) <= sink1_data(44);
+ wire_w_sink1_data_range962w(0) <= sink1_data(45);
+ wire_w_sink1_data_range983w(0) <= sink1_data(46);
+ wire_w_sink1_data_range1004w(0) <= sink1_data(47);
+ wire_w_sink1_data_range1025w(0) <= sink1_data(48);
+ wire_w_sink1_data_range1046w(0) <= sink1_data(49);
+ wire_w_sink1_data_range101w(0) <= sink1_data(4);
+ wire_w_sink1_data_range1067w(0) <= sink1_data(50);
+ wire_w_sink1_data_range1088w(0) <= sink1_data(51);
+ wire_w_sink1_data_range1109w(0) <= sink1_data(52);
+ wire_w_sink1_data_range1130w(0) <= sink1_data(53);
+ wire_w_sink1_data_range1151w(0) <= sink1_data(54);
+ wire_w_sink1_data_range1172w(0) <= sink1_data(55);
+ wire_w_sink1_data_range1193w(0) <= sink1_data(56);
+ wire_w_sink1_data_range1214w(0) <= sink1_data(57);
+ wire_w_sink1_data_range1235w(0) <= sink1_data(58);
+ wire_w_sink1_data_range1256w(0) <= sink1_data(59);
+ wire_w_sink1_data_range122w(0) <= sink1_data(5);
+ wire_w_sink1_data_range1277w(0) <= sink1_data(60);
+ wire_w_sink1_data_range1298w(0) <= sink1_data(61);
+ wire_w_sink1_data_range1319w(0) <= sink1_data(62);
+ wire_w_sink1_data_range1340w(0) <= sink1_data(63);
+ wire_w_sink1_data_range1361w(0) <= sink1_data(64);
+ wire_w_sink1_data_range1382w(0) <= sink1_data(65);
+ wire_w_sink1_data_range1403w(0) <= sink1_data(66);
+ wire_w_sink1_data_range1424w(0) <= sink1_data(67);
+ wire_w_sink1_data_range1445w(0) <= sink1_data(68);
+ wire_w_sink1_data_range143w(0) <= sink1_data(6);
+ wire_w_sink1_data_range164w(0) <= sink1_data(7);
+ wire_w_sink1_data_range185w(0) <= sink1_data(8);
+ wire_w_sink1_data_range206w(0) <= sink1_data(9);
+ wire_w_sink2_channel_range1469w(0) <= sink2_channel(0);
+ wire_w_sink2_channel_range1491w(0) <= sink2_channel(1);
+ wire_w_sink2_channel_range1512w(0) <= sink2_channel(2);
+ wire_w_sink2_channel_range1533w(0) <= sink2_channel(3);
+ wire_w_sink2_channel_range1554w(0) <= sink2_channel(4);
+ wire_w_sink2_channel_range1575w(0) <= sink2_channel(5);
+ wire_w_sink2_channel_range1596w(0) <= sink2_channel(6);
+ wire_w_sink2_data_range19w(0) <= sink2_data(0);
+ wire_w_sink2_data_range230w(0) <= sink2_data(10);
+ wire_w_sink2_data_range251w(0) <= sink2_data(11);
+ wire_w_sink2_data_range272w(0) <= sink2_data(12);
+ wire_w_sink2_data_range293w(0) <= sink2_data(13);
+ wire_w_sink2_data_range314w(0) <= sink2_data(14);
+ wire_w_sink2_data_range335w(0) <= sink2_data(15);
+ wire_w_sink2_data_range356w(0) <= sink2_data(16);
+ wire_w_sink2_data_range377w(0) <= sink2_data(17);
+ wire_w_sink2_data_range398w(0) <= sink2_data(18);
+ wire_w_sink2_data_range419w(0) <= sink2_data(19);
+ wire_w_sink2_data_range41w(0) <= sink2_data(1);
+ wire_w_sink2_data_range440w(0) <= sink2_data(20);
+ wire_w_sink2_data_range461w(0) <= sink2_data(21);
+ wire_w_sink2_data_range482w(0) <= sink2_data(22);
+ wire_w_sink2_data_range503w(0) <= sink2_data(23);
+ wire_w_sink2_data_range524w(0) <= sink2_data(24);
+ wire_w_sink2_data_range545w(0) <= sink2_data(25);
+ wire_w_sink2_data_range566w(0) <= sink2_data(26);
+ wire_w_sink2_data_range587w(0) <= sink2_data(27);
+ wire_w_sink2_data_range608w(0) <= sink2_data(28);
+ wire_w_sink2_data_range629w(0) <= sink2_data(29);
+ wire_w_sink2_data_range62w(0) <= sink2_data(2);
+ wire_w_sink2_data_range650w(0) <= sink2_data(30);
+ wire_w_sink2_data_range671w(0) <= sink2_data(31);
+ wire_w_sink2_data_range692w(0) <= sink2_data(32);
+ wire_w_sink2_data_range713w(0) <= sink2_data(33);
+ wire_w_sink2_data_range734w(0) <= sink2_data(34);
+ wire_w_sink2_data_range755w(0) <= sink2_data(35);
+ wire_w_sink2_data_range776w(0) <= sink2_data(36);
+ wire_w_sink2_data_range797w(0) <= sink2_data(37);
+ wire_w_sink2_data_range818w(0) <= sink2_data(38);
+ wire_w_sink2_data_range839w(0) <= sink2_data(39);
+ wire_w_sink2_data_range83w(0) <= sink2_data(3);
+ wire_w_sink2_data_range860w(0) <= sink2_data(40);
+ wire_w_sink2_data_range881w(0) <= sink2_data(41);
+ wire_w_sink2_data_range902w(0) <= sink2_data(42);
+ wire_w_sink2_data_range923w(0) <= sink2_data(43);
+ wire_w_sink2_data_range944w(0) <= sink2_data(44);
+ wire_w_sink2_data_range965w(0) <= sink2_data(45);
+ wire_w_sink2_data_range986w(0) <= sink2_data(46);
+ wire_w_sink2_data_range1007w(0) <= sink2_data(47);
+ wire_w_sink2_data_range1028w(0) <= sink2_data(48);
+ wire_w_sink2_data_range1049w(0) <= sink2_data(49);
+ wire_w_sink2_data_range104w(0) <= sink2_data(4);
+ wire_w_sink2_data_range1070w(0) <= sink2_data(50);
+ wire_w_sink2_data_range1091w(0) <= sink2_data(51);
+ wire_w_sink2_data_range1112w(0) <= sink2_data(52);
+ wire_w_sink2_data_range1133w(0) <= sink2_data(53);
+ wire_w_sink2_data_range1154w(0) <= sink2_data(54);
+ wire_w_sink2_data_range1175w(0) <= sink2_data(55);
+ wire_w_sink2_data_range1196w(0) <= sink2_data(56);
+ wire_w_sink2_data_range1217w(0) <= sink2_data(57);
+ wire_w_sink2_data_range1238w(0) <= sink2_data(58);
+ wire_w_sink2_data_range1259w(0) <= sink2_data(59);
+ wire_w_sink2_data_range125w(0) <= sink2_data(5);
+ wire_w_sink2_data_range1280w(0) <= sink2_data(60);
+ wire_w_sink2_data_range1301w(0) <= sink2_data(61);
+ wire_w_sink2_data_range1322w(0) <= sink2_data(62);
+ wire_w_sink2_data_range1343w(0) <= sink2_data(63);
+ wire_w_sink2_data_range1364w(0) <= sink2_data(64);
+ wire_w_sink2_data_range1385w(0) <= sink2_data(65);
+ wire_w_sink2_data_range1406w(0) <= sink2_data(66);
+ wire_w_sink2_data_range1427w(0) <= sink2_data(67);
+ wire_w_sink2_data_range1448w(0) <= sink2_data(68);
+ wire_w_sink2_data_range146w(0) <= sink2_data(6);
+ wire_w_sink2_data_range167w(0) <= sink2_data(7);
+ wire_w_sink2_data_range188w(0) <= sink2_data(8);
+ wire_w_sink2_data_range209w(0) <= sink2_data(9);
+ wire_w_sink3_channel_range1472w(0) <= sink3_channel(0);
+ wire_w_sink3_channel_range1494w(0) <= sink3_channel(1);
+ wire_w_sink3_channel_range1515w(0) <= sink3_channel(2);
+ wire_w_sink3_channel_range1536w(0) <= sink3_channel(3);
+ wire_w_sink3_channel_range1557w(0) <= sink3_channel(4);
+ wire_w_sink3_channel_range1578w(0) <= sink3_channel(5);
+ wire_w_sink3_channel_range1599w(0) <= sink3_channel(6);
+ wire_w_sink3_data_range22w(0) <= sink3_data(0);
+ wire_w_sink3_data_range233w(0) <= sink3_data(10);
+ wire_w_sink3_data_range254w(0) <= sink3_data(11);
+ wire_w_sink3_data_range275w(0) <= sink3_data(12);
+ wire_w_sink3_data_range296w(0) <= sink3_data(13);
+ wire_w_sink3_data_range317w(0) <= sink3_data(14);
+ wire_w_sink3_data_range338w(0) <= sink3_data(15);
+ wire_w_sink3_data_range359w(0) <= sink3_data(16);
+ wire_w_sink3_data_range380w(0) <= sink3_data(17);
+ wire_w_sink3_data_range401w(0) <= sink3_data(18);
+ wire_w_sink3_data_range422w(0) <= sink3_data(19);
+ wire_w_sink3_data_range44w(0) <= sink3_data(1);
+ wire_w_sink3_data_range443w(0) <= sink3_data(20);
+ wire_w_sink3_data_range464w(0) <= sink3_data(21);
+ wire_w_sink3_data_range485w(0) <= sink3_data(22);
+ wire_w_sink3_data_range506w(0) <= sink3_data(23);
+ wire_w_sink3_data_range527w(0) <= sink3_data(24);
+ wire_w_sink3_data_range548w(0) <= sink3_data(25);
+ wire_w_sink3_data_range569w(0) <= sink3_data(26);
+ wire_w_sink3_data_range590w(0) <= sink3_data(27);
+ wire_w_sink3_data_range611w(0) <= sink3_data(28);
+ wire_w_sink3_data_range632w(0) <= sink3_data(29);
+ wire_w_sink3_data_range65w(0) <= sink3_data(2);
+ wire_w_sink3_data_range653w(0) <= sink3_data(30);
+ wire_w_sink3_data_range674w(0) <= sink3_data(31);
+ wire_w_sink3_data_range695w(0) <= sink3_data(32);
+ wire_w_sink3_data_range716w(0) <= sink3_data(33);
+ wire_w_sink3_data_range737w(0) <= sink3_data(34);
+ wire_w_sink3_data_range758w(0) <= sink3_data(35);
+ wire_w_sink3_data_range779w(0) <= sink3_data(36);
+ wire_w_sink3_data_range800w(0) <= sink3_data(37);
+ wire_w_sink3_data_range821w(0) <= sink3_data(38);
+ wire_w_sink3_data_range842w(0) <= sink3_data(39);
+ wire_w_sink3_data_range86w(0) <= sink3_data(3);
+ wire_w_sink3_data_range863w(0) <= sink3_data(40);
+ wire_w_sink3_data_range884w(0) <= sink3_data(41);
+ wire_w_sink3_data_range905w(0) <= sink3_data(42);
+ wire_w_sink3_data_range926w(0) <= sink3_data(43);
+ wire_w_sink3_data_range947w(0) <= sink3_data(44);
+ wire_w_sink3_data_range968w(0) <= sink3_data(45);
+ wire_w_sink3_data_range989w(0) <= sink3_data(46);
+ wire_w_sink3_data_range1010w(0) <= sink3_data(47);
+ wire_w_sink3_data_range1031w(0) <= sink3_data(48);
+ wire_w_sink3_data_range1052w(0) <= sink3_data(49);
+ wire_w_sink3_data_range107w(0) <= sink3_data(4);
+ wire_w_sink3_data_range1073w(0) <= sink3_data(50);
+ wire_w_sink3_data_range1094w(0) <= sink3_data(51);
+ wire_w_sink3_data_range1115w(0) <= sink3_data(52);
+ wire_w_sink3_data_range1136w(0) <= sink3_data(53);
+ wire_w_sink3_data_range1157w(0) <= sink3_data(54);
+ wire_w_sink3_data_range1178w(0) <= sink3_data(55);
+ wire_w_sink3_data_range1199w(0) <= sink3_data(56);
+ wire_w_sink3_data_range1220w(0) <= sink3_data(57);
+ wire_w_sink3_data_range1241w(0) <= sink3_data(58);
+ wire_w_sink3_data_range1262w(0) <= sink3_data(59);
+ wire_w_sink3_data_range128w(0) <= sink3_data(5);
+ wire_w_sink3_data_range1283w(0) <= sink3_data(60);
+ wire_w_sink3_data_range1304w(0) <= sink3_data(61);
+ wire_w_sink3_data_range1325w(0) <= sink3_data(62);
+ wire_w_sink3_data_range1346w(0) <= sink3_data(63);
+ wire_w_sink3_data_range1367w(0) <= sink3_data(64);
+ wire_w_sink3_data_range1388w(0) <= sink3_data(65);
+ wire_w_sink3_data_range1409w(0) <= sink3_data(66);
+ wire_w_sink3_data_range1430w(0) <= sink3_data(67);
+ wire_w_sink3_data_range1451w(0) <= sink3_data(68);
+ wire_w_sink3_data_range149w(0) <= sink3_data(6);
+ wire_w_sink3_data_range170w(0) <= sink3_data(7);
+ wire_w_sink3_data_range191w(0) <= sink3_data(8);
+ wire_w_sink3_data_range212w(0) <= sink3_data(9);
+ wire_w_sink4_channel_range1475w(0) <= sink4_channel(0);
+ wire_w_sink4_channel_range1497w(0) <= sink4_channel(1);
+ wire_w_sink4_channel_range1518w(0) <= sink4_channel(2);
+ wire_w_sink4_channel_range1539w(0) <= sink4_channel(3);
+ wire_w_sink4_channel_range1560w(0) <= sink4_channel(4);
+ wire_w_sink4_channel_range1581w(0) <= sink4_channel(5);
+ wire_w_sink4_channel_range1602w(0) <= sink4_channel(6);
+ wire_w_sink4_data_range25w(0) <= sink4_data(0);
+ wire_w_sink4_data_range236w(0) <= sink4_data(10);
+ wire_w_sink4_data_range257w(0) <= sink4_data(11);
+ wire_w_sink4_data_range278w(0) <= sink4_data(12);
+ wire_w_sink4_data_range299w(0) <= sink4_data(13);
+ wire_w_sink4_data_range320w(0) <= sink4_data(14);
+ wire_w_sink4_data_range341w(0) <= sink4_data(15);
+ wire_w_sink4_data_range362w(0) <= sink4_data(16);
+ wire_w_sink4_data_range383w(0) <= sink4_data(17);
+ wire_w_sink4_data_range404w(0) <= sink4_data(18);
+ wire_w_sink4_data_range425w(0) <= sink4_data(19);
+ wire_w_sink4_data_range47w(0) <= sink4_data(1);
+ wire_w_sink4_data_range446w(0) <= sink4_data(20);
+ wire_w_sink4_data_range467w(0) <= sink4_data(21);
+ wire_w_sink4_data_range488w(0) <= sink4_data(22);
+ wire_w_sink4_data_range509w(0) <= sink4_data(23);
+ wire_w_sink4_data_range530w(0) <= sink4_data(24);
+ wire_w_sink4_data_range551w(0) <= sink4_data(25);
+ wire_w_sink4_data_range572w(0) <= sink4_data(26);
+ wire_w_sink4_data_range593w(0) <= sink4_data(27);
+ wire_w_sink4_data_range614w(0) <= sink4_data(28);
+ wire_w_sink4_data_range635w(0) <= sink4_data(29);
+ wire_w_sink4_data_range68w(0) <= sink4_data(2);
+ wire_w_sink4_data_range656w(0) <= sink4_data(30);
+ wire_w_sink4_data_range677w(0) <= sink4_data(31);
+ wire_w_sink4_data_range698w(0) <= sink4_data(32);
+ wire_w_sink4_data_range719w(0) <= sink4_data(33);
+ wire_w_sink4_data_range740w(0) <= sink4_data(34);
+ wire_w_sink4_data_range761w(0) <= sink4_data(35);
+ wire_w_sink4_data_range782w(0) <= sink4_data(36);
+ wire_w_sink4_data_range803w(0) <= sink4_data(37);
+ wire_w_sink4_data_range824w(0) <= sink4_data(38);
+ wire_w_sink4_data_range845w(0) <= sink4_data(39);
+ wire_w_sink4_data_range89w(0) <= sink4_data(3);
+ wire_w_sink4_data_range866w(0) <= sink4_data(40);
+ wire_w_sink4_data_range887w(0) <= sink4_data(41);
+ wire_w_sink4_data_range908w(0) <= sink4_data(42);
+ wire_w_sink4_data_range929w(0) <= sink4_data(43);
+ wire_w_sink4_data_range950w(0) <= sink4_data(44);
+ wire_w_sink4_data_range971w(0) <= sink4_data(45);
+ wire_w_sink4_data_range992w(0) <= sink4_data(46);
+ wire_w_sink4_data_range1013w(0) <= sink4_data(47);
+ wire_w_sink4_data_range1034w(0) <= sink4_data(48);
+ wire_w_sink4_data_range1055w(0) <= sink4_data(49);
+ wire_w_sink4_data_range110w(0) <= sink4_data(4);
+ wire_w_sink4_data_range1076w(0) <= sink4_data(50);
+ wire_w_sink4_data_range1097w(0) <= sink4_data(51);
+ wire_w_sink4_data_range1118w(0) <= sink4_data(52);
+ wire_w_sink4_data_range1139w(0) <= sink4_data(53);
+ wire_w_sink4_data_range1160w(0) <= sink4_data(54);
+ wire_w_sink4_data_range1181w(0) <= sink4_data(55);
+ wire_w_sink4_data_range1202w(0) <= sink4_data(56);
+ wire_w_sink4_data_range1223w(0) <= sink4_data(57);
+ wire_w_sink4_data_range1244w(0) <= sink4_data(58);
+ wire_w_sink4_data_range1265w(0) <= sink4_data(59);
+ wire_w_sink4_data_range131w(0) <= sink4_data(5);
+ wire_w_sink4_data_range1286w(0) <= sink4_data(60);
+ wire_w_sink4_data_range1307w(0) <= sink4_data(61);
+ wire_w_sink4_data_range1328w(0) <= sink4_data(62);
+ wire_w_sink4_data_range1349w(0) <= sink4_data(63);
+ wire_w_sink4_data_range1370w(0) <= sink4_data(64);
+ wire_w_sink4_data_range1391w(0) <= sink4_data(65);
+ wire_w_sink4_data_range1412w(0) <= sink4_data(66);
+ wire_w_sink4_data_range1433w(0) <= sink4_data(67);
+ wire_w_sink4_data_range1454w(0) <= sink4_data(68);
+ wire_w_sink4_data_range152w(0) <= sink4_data(6);
+ wire_w_sink4_data_range173w(0) <= sink4_data(7);
+ wire_w_sink4_data_range194w(0) <= sink4_data(8);
+ wire_w_sink4_data_range215w(0) <= sink4_data(9);
+ wire_w_sink5_channel_range1478w(0) <= sink5_channel(0);
+ wire_w_sink5_channel_range1500w(0) <= sink5_channel(1);
+ wire_w_sink5_channel_range1521w(0) <= sink5_channel(2);
+ wire_w_sink5_channel_range1542w(0) <= sink5_channel(3);
+ wire_w_sink5_channel_range1563w(0) <= sink5_channel(4);
+ wire_w_sink5_channel_range1584w(0) <= sink5_channel(5);
+ wire_w_sink5_channel_range1605w(0) <= sink5_channel(6);
+ wire_w_sink5_data_range28w(0) <= sink5_data(0);
+ wire_w_sink5_data_range239w(0) <= sink5_data(10);
+ wire_w_sink5_data_range260w(0) <= sink5_data(11);
+ wire_w_sink5_data_range281w(0) <= sink5_data(12);
+ wire_w_sink5_data_range302w(0) <= sink5_data(13);
+ wire_w_sink5_data_range323w(0) <= sink5_data(14);
+ wire_w_sink5_data_range344w(0) <= sink5_data(15);
+ wire_w_sink5_data_range365w(0) <= sink5_data(16);
+ wire_w_sink5_data_range386w(0) <= sink5_data(17);
+ wire_w_sink5_data_range407w(0) <= sink5_data(18);
+ wire_w_sink5_data_range428w(0) <= sink5_data(19);
+ wire_w_sink5_data_range50w(0) <= sink5_data(1);
+ wire_w_sink5_data_range449w(0) <= sink5_data(20);
+ wire_w_sink5_data_range470w(0) <= sink5_data(21);
+ wire_w_sink5_data_range491w(0) <= sink5_data(22);
+ wire_w_sink5_data_range512w(0) <= sink5_data(23);
+ wire_w_sink5_data_range533w(0) <= sink5_data(24);
+ wire_w_sink5_data_range554w(0) <= sink5_data(25);
+ wire_w_sink5_data_range575w(0) <= sink5_data(26);
+ wire_w_sink5_data_range596w(0) <= sink5_data(27);
+ wire_w_sink5_data_range617w(0) <= sink5_data(28);
+ wire_w_sink5_data_range638w(0) <= sink5_data(29);
+ wire_w_sink5_data_range71w(0) <= sink5_data(2);
+ wire_w_sink5_data_range659w(0) <= sink5_data(30);
+ wire_w_sink5_data_range680w(0) <= sink5_data(31);
+ wire_w_sink5_data_range701w(0) <= sink5_data(32);
+ wire_w_sink5_data_range722w(0) <= sink5_data(33);
+ wire_w_sink5_data_range743w(0) <= sink5_data(34);
+ wire_w_sink5_data_range764w(0) <= sink5_data(35);
+ wire_w_sink5_data_range785w(0) <= sink5_data(36);
+ wire_w_sink5_data_range806w(0) <= sink5_data(37);
+ wire_w_sink5_data_range827w(0) <= sink5_data(38);
+ wire_w_sink5_data_range848w(0) <= sink5_data(39);
+ wire_w_sink5_data_range92w(0) <= sink5_data(3);
+ wire_w_sink5_data_range869w(0) <= sink5_data(40);
+ wire_w_sink5_data_range890w(0) <= sink5_data(41);
+ wire_w_sink5_data_range911w(0) <= sink5_data(42);
+ wire_w_sink5_data_range932w(0) <= sink5_data(43);
+ wire_w_sink5_data_range953w(0) <= sink5_data(44);
+ wire_w_sink5_data_range974w(0) <= sink5_data(45);
+ wire_w_sink5_data_range995w(0) <= sink5_data(46);
+ wire_w_sink5_data_range1016w(0) <= sink5_data(47);
+ wire_w_sink5_data_range1037w(0) <= sink5_data(48);
+ wire_w_sink5_data_range1058w(0) <= sink5_data(49);
+ wire_w_sink5_data_range113w(0) <= sink5_data(4);
+ wire_w_sink5_data_range1079w(0) <= sink5_data(50);
+ wire_w_sink5_data_range1100w(0) <= sink5_data(51);
+ wire_w_sink5_data_range1121w(0) <= sink5_data(52);
+ wire_w_sink5_data_range1142w(0) <= sink5_data(53);
+ wire_w_sink5_data_range1163w(0) <= sink5_data(54);
+ wire_w_sink5_data_range1184w(0) <= sink5_data(55);
+ wire_w_sink5_data_range1205w(0) <= sink5_data(56);
+ wire_w_sink5_data_range1226w(0) <= sink5_data(57);
+ wire_w_sink5_data_range1247w(0) <= sink5_data(58);
+ wire_w_sink5_data_range1268w(0) <= sink5_data(59);
+ wire_w_sink5_data_range134w(0) <= sink5_data(5);
+ wire_w_sink5_data_range1289w(0) <= sink5_data(60);
+ wire_w_sink5_data_range1310w(0) <= sink5_data(61);
+ wire_w_sink5_data_range1331w(0) <= sink5_data(62);
+ wire_w_sink5_data_range1352w(0) <= sink5_data(63);
+ wire_w_sink5_data_range1373w(0) <= sink5_data(64);
+ wire_w_sink5_data_range1394w(0) <= sink5_data(65);
+ wire_w_sink5_data_range1415w(0) <= sink5_data(66);
+ wire_w_sink5_data_range1436w(0) <= sink5_data(67);
+ wire_w_sink5_data_range1457w(0) <= sink5_data(68);
+ wire_w_sink5_data_range155w(0) <= sink5_data(6);
+ wire_w_sink5_data_range176w(0) <= sink5_data(7);
+ wire_w_sink5_data_range197w(0) <= sink5_data(8);
+ wire_w_sink5_data_range218w(0) <= sink5_data(9);
+ wire_w_sink6_channel_range1481w(0) <= sink6_channel(0);
+ wire_w_sink6_channel_range1503w(0) <= sink6_channel(1);
+ wire_w_sink6_channel_range1524w(0) <= sink6_channel(2);
+ wire_w_sink6_channel_range1545w(0) <= sink6_channel(3);
+ wire_w_sink6_channel_range1566w(0) <= sink6_channel(4);
+ wire_w_sink6_channel_range1587w(0) <= sink6_channel(5);
+ wire_w_sink6_channel_range1608w(0) <= sink6_channel(6);
+ wire_w_sink6_data_range31w(0) <= sink6_data(0);
+ wire_w_sink6_data_range242w(0) <= sink6_data(10);
+ wire_w_sink6_data_range263w(0) <= sink6_data(11);
+ wire_w_sink6_data_range284w(0) <= sink6_data(12);
+ wire_w_sink6_data_range305w(0) <= sink6_data(13);
+ wire_w_sink6_data_range326w(0) <= sink6_data(14);
+ wire_w_sink6_data_range347w(0) <= sink6_data(15);
+ wire_w_sink6_data_range368w(0) <= sink6_data(16);
+ wire_w_sink6_data_range389w(0) <= sink6_data(17);
+ wire_w_sink6_data_range410w(0) <= sink6_data(18);
+ wire_w_sink6_data_range431w(0) <= sink6_data(19);
+ wire_w_sink6_data_range53w(0) <= sink6_data(1);
+ wire_w_sink6_data_range452w(0) <= sink6_data(20);
+ wire_w_sink6_data_range473w(0) <= sink6_data(21);
+ wire_w_sink6_data_range494w(0) <= sink6_data(22);
+ wire_w_sink6_data_range515w(0) <= sink6_data(23);
+ wire_w_sink6_data_range536w(0) <= sink6_data(24);
+ wire_w_sink6_data_range557w(0) <= sink6_data(25);
+ wire_w_sink6_data_range578w(0) <= sink6_data(26);
+ wire_w_sink6_data_range599w(0) <= sink6_data(27);
+ wire_w_sink6_data_range620w(0) <= sink6_data(28);
+ wire_w_sink6_data_range641w(0) <= sink6_data(29);
+ wire_w_sink6_data_range74w(0) <= sink6_data(2);
+ wire_w_sink6_data_range662w(0) <= sink6_data(30);
+ wire_w_sink6_data_range683w(0) <= sink6_data(31);
+ wire_w_sink6_data_range704w(0) <= sink6_data(32);
+ wire_w_sink6_data_range725w(0) <= sink6_data(33);
+ wire_w_sink6_data_range746w(0) <= sink6_data(34);
+ wire_w_sink6_data_range767w(0) <= sink6_data(35);
+ wire_w_sink6_data_range788w(0) <= sink6_data(36);
+ wire_w_sink6_data_range809w(0) <= sink6_data(37);
+ wire_w_sink6_data_range830w(0) <= sink6_data(38);
+ wire_w_sink6_data_range851w(0) <= sink6_data(39);
+ wire_w_sink6_data_range95w(0) <= sink6_data(3);
+ wire_w_sink6_data_range872w(0) <= sink6_data(40);
+ wire_w_sink6_data_range893w(0) <= sink6_data(41);
+ wire_w_sink6_data_range914w(0) <= sink6_data(42);
+ wire_w_sink6_data_range935w(0) <= sink6_data(43);
+ wire_w_sink6_data_range956w(0) <= sink6_data(44);
+ wire_w_sink6_data_range977w(0) <= sink6_data(45);
+ wire_w_sink6_data_range998w(0) <= sink6_data(46);
+ wire_w_sink6_data_range1019w(0) <= sink6_data(47);
+ wire_w_sink6_data_range1040w(0) <= sink6_data(48);
+ wire_w_sink6_data_range1061w(0) <= sink6_data(49);
+ wire_w_sink6_data_range116w(0) <= sink6_data(4);
+ wire_w_sink6_data_range1082w(0) <= sink6_data(50);
+ wire_w_sink6_data_range1103w(0) <= sink6_data(51);
+ wire_w_sink6_data_range1124w(0) <= sink6_data(52);
+ wire_w_sink6_data_range1145w(0) <= sink6_data(53);
+ wire_w_sink6_data_range1166w(0) <= sink6_data(54);
+ wire_w_sink6_data_range1187w(0) <= sink6_data(55);
+ wire_w_sink6_data_range1208w(0) <= sink6_data(56);
+ wire_w_sink6_data_range1229w(0) <= sink6_data(57);
+ wire_w_sink6_data_range1250w(0) <= sink6_data(58);
+ wire_w_sink6_data_range1271w(0) <= sink6_data(59);
+ wire_w_sink6_data_range137w(0) <= sink6_data(5);
+ wire_w_sink6_data_range1292w(0) <= sink6_data(60);
+ wire_w_sink6_data_range1313w(0) <= sink6_data(61);
+ wire_w_sink6_data_range1334w(0) <= sink6_data(62);
+ wire_w_sink6_data_range1355w(0) <= sink6_data(63);
+ wire_w_sink6_data_range1376w(0) <= sink6_data(64);
+ wire_w_sink6_data_range1397w(0) <= sink6_data(65);
+ wire_w_sink6_data_range1418w(0) <= sink6_data(66);
+ wire_w_sink6_data_range1439w(0) <= sink6_data(67);
+ wire_w_sink6_data_range1460w(0) <= sink6_data(68);
+ wire_w_sink6_data_range158w(0) <= sink6_data(6);
+ wire_w_sink6_data_range179w(0) <= sink6_data(7);
+ wire_w_sink6_data_range200w(0) <= sink6_data(8);
+ wire_w_sink6_data_range221w(0) <= sink6_data(9);
+
+ END RTL; --altera_merlin_multiplexer_0003
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_router/altera_merlin_router_0001.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_router/altera_merlin_router_0001.vho
new file mode 100644
index 0000000000000000000000000000000000000000..7e0f4c2ca2a6c299c04b1122e346afbbeaa76416
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_router/altera_merlin_router_0001.vho
@@ -0,0 +1,68 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_router_0001 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ reset : IN STD_LOGIC;
+ sink_data : IN STD_LOGIC_VECTOR (65 DOWNTO 0);
+ sink_endofpacket : IN STD_LOGIC;
+ sink_ready : OUT STD_LOGIC;
+ sink_startofpacket : IN STD_LOGIC;
+ sink_valid : IN STD_LOGIC;
+ src_channel : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+ src_data : OUT STD_LOGIC_VECTOR (65 DOWNTO 0);
+ src_endofpacket : OUT STD_LOGIC;
+ src_ready : IN STD_LOGIC;
+ src_startofpacket : OUT STD_LOGIC;
+ src_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_router_0001;
+
+ ARCHITECTURE RTL OF altera_merlin_router_0001 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL wire_w_lg_w_sink_data_range151w193w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_sink_data_range151w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+ wire_w_lg_w_sink_data_range151w193w(0) <= NOT wire_w_sink_data_range151w(0);
+ sink_ready <= src_ready;
+ src_channel <= ( wire_w_lg_w_sink_data_range151w193w & sink_data(50));
+ src_data <= ( sink_data(65) & wire_w_lg_w_sink_data_range151w193w & sink_data(63 DOWNTO 0));
+ src_endofpacket <= sink_endofpacket;
+ src_startofpacket <= sink_startofpacket;
+ src_valid <= sink_valid;
+ wire_w_sink_data_range151w(0) <= sink_data(50);
+
+ END RTL; --altera_merlin_router_0001
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_router/altera_merlin_router_0002.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_router/altera_merlin_router_0002.vho
new file mode 100644
index 0000000000000000000000000000000000000000..743bd2e587a2d95c530f3c3666d3694cfe1e1e71
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_router/altera_merlin_router_0002.vho
@@ -0,0 +1,64 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_router_0002 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ reset : IN STD_LOGIC;
+ sink_data : IN STD_LOGIC_VECTOR (65 DOWNTO 0);
+ sink_endofpacket : IN STD_LOGIC;
+ sink_ready : OUT STD_LOGIC;
+ sink_startofpacket : IN STD_LOGIC;
+ sink_valid : IN STD_LOGIC;
+ src_channel : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+ src_data : OUT STD_LOGIC_VECTOR (65 DOWNTO 0);
+ src_endofpacket : OUT STD_LOGIC;
+ src_ready : IN STD_LOGIC;
+ src_startofpacket : OUT STD_LOGIC;
+ src_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_router_0002;
+
+ ARCHITECTURE RTL OF altera_merlin_router_0002 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ BEGIN
+
+ sink_ready <= src_ready;
+ src_channel <= ( "0" & "1");
+ src_data <= ( sink_data(65 DOWNTO 0));
+ src_endofpacket <= sink_endofpacket;
+ src_startofpacket <= sink_startofpacket;
+ src_valid <= sink_valid;
+
+ END RTL; --altera_merlin_router_0002
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_router/altera_merlin_router_0003.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_router/altera_merlin_router_0003.vho
new file mode 100644
index 0000000000000000000000000000000000000000..4bce1fd34ca952fcf9ee115aba8a90f9f6b1f934
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_router/altera_merlin_router_0003.vho
@@ -0,0 +1,194 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources = mux21 56
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_router_0003 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ reset : IN STD_LOGIC;
+ sink_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ sink_endofpacket : IN STD_LOGIC;
+ sink_ready : OUT STD_LOGIC;
+ sink_startofpacket : IN STD_LOGIC;
+ sink_valid : IN STD_LOGIC;
+ src_channel : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ src_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ src_endofpacket : OUT STD_LOGIC;
+ src_ready : IN STD_LOGIC;
+ src_startofpacket : OUT STD_LOGIC;
+ src_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_router_0003;
+
+ ARCHITECTURE RTL OF altera_merlin_router_0003 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_15m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_22m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_27m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_33m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_34m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_39m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_44m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_45m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_46m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_51m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_53m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_56m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_57m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_58m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_63m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_65m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_67m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_68m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_69m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_70m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_75m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_77m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_78m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_79m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_80m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_81m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_82m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_87m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_88m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_89m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_90m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_91m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_92m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_93m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_channel_94m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_data_23m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_data_24m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_data_25m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_data_35m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_data_36m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_data_37m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_data_47m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_data_48m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_data_49m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_data_59m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_data_60m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_data_61m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_data_71m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_data_72m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_data_73m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_data_83m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_data_84m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_data_85m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_data_95m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_data_96m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0003_src_data_97m_dataout : STD_LOGIC;
+ SIGNAL wire_w1w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_merlin_router_0003_src_channel_0_297_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_router_0003_src_channel_1_330_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_router_0003_src_channel_2_363_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_router_0003_src_channel_3_396_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_router_0003_src_channel_4_429_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_router_0003_src_channel_5_462_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_router_0003_src_channel_6_495_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_router_0003_src_channel_7_528_dataout : STD_LOGIC;
+ BEGIN
+
+ wire_w1w(0) <= NOT s_wire_altera_merlin_router_0003_src_channel_0_297_dataout;
+ s_wire_altera_merlin_router_0003_src_channel_0_297_dataout <= (((((((((((NOT sink_data(39)) AND (NOT sink_data(40))) AND (NOT sink_data(41))) AND (NOT sink_data(42))) AND (NOT sink_data(43))) AND (NOT sink_data(44))) AND (NOT sink_data(45))) AND (NOT sink_data(46))) AND (NOT sink_data(47))) AND (NOT sink_data(48))) AND (NOT sink_data(49)));
+ s_wire_altera_merlin_router_0003_src_channel_1_330_dataout <= (((((((((((NOT sink_data(39)) AND (NOT sink_data(40))) AND (NOT sink_data(41))) AND (NOT sink_data(42))) AND (NOT sink_data(43))) AND sink_data(44)) AND (NOT sink_data(45))) AND (NOT sink_data(46))) AND (NOT sink_data(47))) AND (NOT sink_data(48))) AND (NOT sink_data(49)));
+ s_wire_altera_merlin_router_0003_src_channel_2_363_dataout <= (((((((((((NOT sink_data(39)) AND (NOT sink_data(40))) AND (NOT sink_data(41))) AND (NOT sink_data(42))) AND (NOT sink_data(43))) AND (NOT sink_data(44))) AND sink_data(45)) AND (NOT sink_data(46))) AND (NOT sink_data(47))) AND (NOT sink_data(48))) AND (NOT sink_data(49)));
+ s_wire_altera_merlin_router_0003_src_channel_3_396_dataout <= (((((((((((NOT sink_data(39)) AND (NOT sink_data(40))) AND (NOT sink_data(41))) AND (NOT sink_data(42))) AND (NOT sink_data(43))) AND sink_data(44)) AND sink_data(45)) AND (NOT sink_data(46))) AND (NOT sink_data(47))) AND (NOT sink_data(48))) AND (NOT sink_data(49)));
+ s_wire_altera_merlin_router_0003_src_channel_4_429_dataout <= ((((((((((NOT sink_data(40)) AND (NOT sink_data(41))) AND (NOT sink_data(42))) AND (NOT sink_data(43))) AND sink_data(44)) AND (NOT sink_data(45))) AND sink_data(46)) AND (NOT sink_data(47))) AND (NOT sink_data(48))) AND (NOT sink_data(49)));
+ s_wire_altera_merlin_router_0003_src_channel_5_462_dataout <= ((((((((((NOT sink_data(40)) AND (NOT sink_data(41))) AND (NOT sink_data(42))) AND (NOT sink_data(43))) AND (NOT sink_data(44))) AND (NOT sink_data(45))) AND (NOT sink_data(46))) AND sink_data(47)) AND (NOT sink_data(48))) AND (NOT sink_data(49)));
+ s_wire_altera_merlin_router_0003_src_channel_6_495_dataout <= (((((((NOT sink_data(43)) AND (NOT sink_data(44))) AND (NOT sink_data(45))) AND (NOT sink_data(46))) AND (NOT sink_data(47))) AND (NOT sink_data(48))) AND sink_data(49));
+ s_wire_altera_merlin_router_0003_src_channel_7_528_dataout <= ((((((NOT sink_data(44)) AND (NOT sink_data(45))) AND (NOT sink_data(46))) AND (NOT sink_data(47))) AND sink_data(48)) AND sink_data(49));
+ sink_ready <= src_ready;
+ src_channel <= ( wire_altera_merlin_router_0003_src_channel_87m_dataout & wire_altera_merlin_router_0003_src_channel_88m_dataout & wire_altera_merlin_router_0003_src_channel_89m_dataout & wire_altera_merlin_router_0003_src_channel_90m_dataout & wire_altera_merlin_router_0003_src_channel_91m_dataout & wire_altera_merlin_router_0003_src_channel_92m_dataout & wire_altera_merlin_router_0003_src_channel_93m_dataout & wire_altera_merlin_router_0003_src_channel_94m_dataout);
+ src_data <= ( sink_data(68) & wire_altera_merlin_router_0003_src_data_95m_dataout & wire_altera_merlin_router_0003_src_data_96m_dataout & wire_altera_merlin_router_0003_src_data_97m_dataout & sink_data(64 DOWNTO 0));
+ src_endofpacket <= sink_endofpacket;
+ src_startofpacket <= sink_startofpacket;
+ src_valid <= sink_valid;
+ wire_altera_merlin_router_0003_src_channel_15m_dataout <= wire_w1w(0) AND NOT(s_wire_altera_merlin_router_0003_src_channel_1_330_dataout);
+ wire_altera_merlin_router_0003_src_channel_22m_dataout <= s_wire_altera_merlin_router_0003_src_channel_0_297_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_1_330_dataout);
+ wire_altera_merlin_router_0003_src_channel_27m_dataout <= wire_altera_merlin_router_0003_src_channel_15m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_2_363_dataout);
+ wire_altera_merlin_router_0003_src_channel_33m_dataout <= s_wire_altera_merlin_router_0003_src_channel_1_330_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_2_363_dataout);
+ wire_altera_merlin_router_0003_src_channel_34m_dataout <= wire_altera_merlin_router_0003_src_channel_22m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_2_363_dataout);
+ wire_altera_merlin_router_0003_src_channel_39m_dataout <= wire_altera_merlin_router_0003_src_channel_27m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_3_396_dataout);
+ wire_altera_merlin_router_0003_src_channel_44m_dataout <= s_wire_altera_merlin_router_0003_src_channel_2_363_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_3_396_dataout);
+ wire_altera_merlin_router_0003_src_channel_45m_dataout <= wire_altera_merlin_router_0003_src_channel_33m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_3_396_dataout);
+ wire_altera_merlin_router_0003_src_channel_46m_dataout <= wire_altera_merlin_router_0003_src_channel_34m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_3_396_dataout);
+ wire_altera_merlin_router_0003_src_channel_51m_dataout <= wire_altera_merlin_router_0003_src_channel_39m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_4_429_dataout);
+ wire_altera_merlin_router_0003_src_channel_53m_dataout <= s_wire_altera_merlin_router_0003_src_channel_3_396_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_4_429_dataout);
+ wire_altera_merlin_router_0003_src_channel_56m_dataout <= wire_altera_merlin_router_0003_src_channel_44m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_4_429_dataout);
+ wire_altera_merlin_router_0003_src_channel_57m_dataout <= wire_altera_merlin_router_0003_src_channel_45m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_4_429_dataout);
+ wire_altera_merlin_router_0003_src_channel_58m_dataout <= wire_altera_merlin_router_0003_src_channel_46m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_4_429_dataout);
+ wire_altera_merlin_router_0003_src_channel_63m_dataout <= wire_altera_merlin_router_0003_src_channel_51m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_5_462_dataout);
+ wire_altera_merlin_router_0003_src_channel_65m_dataout <= wire_altera_merlin_router_0003_src_channel_53m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_5_462_dataout);
+ wire_altera_merlin_router_0003_src_channel_67m_dataout <= s_wire_altera_merlin_router_0003_src_channel_4_429_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_5_462_dataout);
+ wire_altera_merlin_router_0003_src_channel_68m_dataout <= wire_altera_merlin_router_0003_src_channel_56m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_5_462_dataout);
+ wire_altera_merlin_router_0003_src_channel_69m_dataout <= wire_altera_merlin_router_0003_src_channel_57m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_5_462_dataout);
+ wire_altera_merlin_router_0003_src_channel_70m_dataout <= wire_altera_merlin_router_0003_src_channel_58m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_5_462_dataout);
+ wire_altera_merlin_router_0003_src_channel_75m_dataout <= wire_altera_merlin_router_0003_src_channel_63m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_6_495_dataout);
+ wire_altera_merlin_router_0003_src_channel_77m_dataout <= wire_altera_merlin_router_0003_src_channel_65m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_6_495_dataout);
+ wire_altera_merlin_router_0003_src_channel_78m_dataout <= s_wire_altera_merlin_router_0003_src_channel_5_462_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_6_495_dataout);
+ wire_altera_merlin_router_0003_src_channel_79m_dataout <= wire_altera_merlin_router_0003_src_channel_67m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_6_495_dataout);
+ wire_altera_merlin_router_0003_src_channel_80m_dataout <= wire_altera_merlin_router_0003_src_channel_68m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_6_495_dataout);
+ wire_altera_merlin_router_0003_src_channel_81m_dataout <= wire_altera_merlin_router_0003_src_channel_69m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_6_495_dataout);
+ wire_altera_merlin_router_0003_src_channel_82m_dataout <= wire_altera_merlin_router_0003_src_channel_70m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_6_495_dataout);
+ wire_altera_merlin_router_0003_src_channel_87m_dataout <= wire_altera_merlin_router_0003_src_channel_75m_dataout OR s_wire_altera_merlin_router_0003_src_channel_7_528_dataout;
+ wire_altera_merlin_router_0003_src_channel_88m_dataout <= s_wire_altera_merlin_router_0003_src_channel_6_495_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_7_528_dataout);
+ wire_altera_merlin_router_0003_src_channel_89m_dataout <= wire_altera_merlin_router_0003_src_channel_77m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_7_528_dataout);
+ wire_altera_merlin_router_0003_src_channel_90m_dataout <= wire_altera_merlin_router_0003_src_channel_78m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_7_528_dataout);
+ wire_altera_merlin_router_0003_src_channel_91m_dataout <= wire_altera_merlin_router_0003_src_channel_79m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_7_528_dataout);
+ wire_altera_merlin_router_0003_src_channel_92m_dataout <= wire_altera_merlin_router_0003_src_channel_80m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_7_528_dataout);
+ wire_altera_merlin_router_0003_src_channel_93m_dataout <= wire_altera_merlin_router_0003_src_channel_81m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_7_528_dataout);
+ wire_altera_merlin_router_0003_src_channel_94m_dataout <= wire_altera_merlin_router_0003_src_channel_82m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_7_528_dataout);
+ wire_altera_merlin_router_0003_src_data_23m_dataout <= wire_w1w(0) AND NOT(s_wire_altera_merlin_router_0003_src_channel_1_330_dataout);
+ wire_altera_merlin_router_0003_src_data_24m_dataout <= wire_w1w(0) AND NOT(s_wire_altera_merlin_router_0003_src_channel_1_330_dataout);
+ wire_altera_merlin_router_0003_src_data_25m_dataout <= wire_w1w(0) OR s_wire_altera_merlin_router_0003_src_channel_1_330_dataout;
+ wire_altera_merlin_router_0003_src_data_35m_dataout <= wire_altera_merlin_router_0003_src_data_23m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_2_363_dataout);
+ wire_altera_merlin_router_0003_src_data_36m_dataout <= wire_altera_merlin_router_0003_src_data_24m_dataout OR s_wire_altera_merlin_router_0003_src_channel_2_363_dataout;
+ wire_altera_merlin_router_0003_src_data_37m_dataout <= wire_altera_merlin_router_0003_src_data_25m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_2_363_dataout);
+ wire_altera_merlin_router_0003_src_data_47m_dataout <= wire_altera_merlin_router_0003_src_data_35m_dataout OR s_wire_altera_merlin_router_0003_src_channel_3_396_dataout;
+ wire_altera_merlin_router_0003_src_data_48m_dataout <= wire_altera_merlin_router_0003_src_data_36m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_3_396_dataout);
+ wire_altera_merlin_router_0003_src_data_49m_dataout <= wire_altera_merlin_router_0003_src_data_37m_dataout OR s_wire_altera_merlin_router_0003_src_channel_3_396_dataout;
+ wire_altera_merlin_router_0003_src_data_59m_dataout <= wire_altera_merlin_router_0003_src_data_47m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_4_429_dataout);
+ wire_altera_merlin_router_0003_src_data_60m_dataout <= wire_altera_merlin_router_0003_src_data_48m_dataout OR s_wire_altera_merlin_router_0003_src_channel_4_429_dataout;
+ wire_altera_merlin_router_0003_src_data_61m_dataout <= wire_altera_merlin_router_0003_src_data_49m_dataout OR s_wire_altera_merlin_router_0003_src_channel_4_429_dataout;
+ wire_altera_merlin_router_0003_src_data_71m_dataout <= wire_altera_merlin_router_0003_src_data_59m_dataout OR s_wire_altera_merlin_router_0003_src_channel_5_462_dataout;
+ wire_altera_merlin_router_0003_src_data_72m_dataout <= wire_altera_merlin_router_0003_src_data_60m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_5_462_dataout);
+ wire_altera_merlin_router_0003_src_data_73m_dataout <= wire_altera_merlin_router_0003_src_data_61m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_5_462_dataout);
+ wire_altera_merlin_router_0003_src_data_83m_dataout <= wire_altera_merlin_router_0003_src_data_71m_dataout OR s_wire_altera_merlin_router_0003_src_channel_6_495_dataout;
+ wire_altera_merlin_router_0003_src_data_84m_dataout <= wire_altera_merlin_router_0003_src_data_72m_dataout OR s_wire_altera_merlin_router_0003_src_channel_6_495_dataout;
+ wire_altera_merlin_router_0003_src_data_85m_dataout <= wire_altera_merlin_router_0003_src_data_73m_dataout AND NOT(s_wire_altera_merlin_router_0003_src_channel_6_495_dataout);
+ wire_altera_merlin_router_0003_src_data_95m_dataout <= wire_altera_merlin_router_0003_src_data_83m_dataout OR s_wire_altera_merlin_router_0003_src_channel_7_528_dataout;
+ wire_altera_merlin_router_0003_src_data_96m_dataout <= wire_altera_merlin_router_0003_src_data_84m_dataout OR s_wire_altera_merlin_router_0003_src_channel_7_528_dataout;
+ wire_altera_merlin_router_0003_src_data_97m_dataout <= wire_altera_merlin_router_0003_src_data_85m_dataout OR s_wire_altera_merlin_router_0003_src_channel_7_528_dataout;
+
+ END RTL; --altera_merlin_router_0003
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_router/altera_merlin_router_0004.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_router/altera_merlin_router_0004.vho
new file mode 100644
index 0000000000000000000000000000000000000000..eb4c2dc7e87a7f520ad64f022068c7f4d80d3ef4
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_router/altera_merlin_router_0004.vho
@@ -0,0 +1,64 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_router_0004 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ reset : IN STD_LOGIC;
+ sink_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ sink_endofpacket : IN STD_LOGIC;
+ sink_ready : OUT STD_LOGIC;
+ sink_startofpacket : IN STD_LOGIC;
+ sink_valid : IN STD_LOGIC;
+ src_channel : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ src_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ src_endofpacket : OUT STD_LOGIC;
+ src_ready : IN STD_LOGIC;
+ src_startofpacket : OUT STD_LOGIC;
+ src_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_router_0004;
+
+ ARCHITECTURE RTL OF altera_merlin_router_0004 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ BEGIN
+
+ sink_ready <= src_ready;
+ src_channel <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1");
+ src_data <= ( sink_data(68 DOWNTO 0));
+ src_endofpacket <= sink_endofpacket;
+ src_startofpacket <= sink_startofpacket;
+ src_valid <= sink_valid;
+
+ END RTL; --altera_merlin_router_0004
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_router/altera_merlin_router_0005.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_router/altera_merlin_router_0005.vho
new file mode 100644
index 0000000000000000000000000000000000000000..f010e01fe9142187c22719017441709ee5075d28
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_router/altera_merlin_router_0005.vho
@@ -0,0 +1,166 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources = mux21 43
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_router_0005 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ reset : IN STD_LOGIC;
+ sink_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ sink_endofpacket : IN STD_LOGIC;
+ sink_ready : OUT STD_LOGIC;
+ sink_startofpacket : IN STD_LOGIC;
+ sink_valid : IN STD_LOGIC;
+ src_channel : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
+ src_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ src_endofpacket : OUT STD_LOGIC;
+ src_ready : IN STD_LOGIC;
+ src_startofpacket : OUT STD_LOGIC;
+ src_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_router_0005;
+
+ ARCHITECTURE RTL OF altera_merlin_router_0005 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL wire_altera_merlin_router_0005_src_channel_15m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_channel_20m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_channel_26m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_channel_30m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_channel_31m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_channel_37m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_channel_40m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_channel_41m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_channel_42m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_channel_48m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_channel_49m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_channel_51m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_channel_52m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_channel_53m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_channel_58m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_channel_59m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_channel_60m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_channel_62m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_channel_63m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_channel_64m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_channel_69m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_channel_70m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_channel_71m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_channel_72m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_channel_73m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_channel_74m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_channel_75m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_data_21m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_data_23m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_data_32m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_data_34m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_data_43m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_data_44m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_data_45m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_data_54m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_data_55m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_data_56m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_data_65m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_data_66m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_data_67m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_data_76m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_data_77m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_router_0005_src_data_78m_dataout : STD_LOGIC;
+ SIGNAL wire_w1w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_merlin_router_0005_src_channel_0_276_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_router_0005_src_channel_1_309_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_router_0005_src_channel_2_342_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_router_0005_src_channel_3_375_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_router_0005_src_channel_4_408_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_router_0005_src_channel_5_441_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_router_0005_src_channel_6_474_dataout : STD_LOGIC;
+ BEGIN
+
+ wire_w1w(0) <= NOT s_wire_altera_merlin_router_0005_src_channel_0_276_dataout;
+ s_wire_altera_merlin_router_0005_src_channel_0_276_dataout <= (((((((((((NOT sink_data(39)) AND (NOT sink_data(40))) AND (NOT sink_data(41))) AND (NOT sink_data(42))) AND (NOT sink_data(43))) AND (NOT sink_data(44))) AND (NOT sink_data(45))) AND (NOT sink_data(46))) AND (NOT sink_data(47))) AND (NOT sink_data(48))) AND (NOT sink_data(49)));
+ s_wire_altera_merlin_router_0005_src_channel_1_309_dataout <= ((((((((((NOT sink_data(40)) AND (NOT sink_data(41))) AND (NOT sink_data(42))) AND (NOT sink_data(43))) AND sink_data(44)) AND (NOT sink_data(45))) AND (NOT sink_data(46))) AND (NOT sink_data(47))) AND (NOT sink_data(48))) AND (NOT sink_data(49)));
+ s_wire_altera_merlin_router_0005_src_channel_2_342_dataout <= (((((((((((NOT sink_data(39)) AND (NOT sink_data(40))) AND (NOT sink_data(41))) AND (NOT sink_data(42))) AND (NOT sink_data(43))) AND (NOT sink_data(44))) AND sink_data(45)) AND (NOT sink_data(46))) AND (NOT sink_data(47))) AND (NOT sink_data(48))) AND (NOT sink_data(49)));
+ s_wire_altera_merlin_router_0005_src_channel_3_375_dataout <= ((((((((((NOT sink_data(40)) AND (NOT sink_data(41))) AND (NOT sink_data(42))) AND (NOT sink_data(43))) AND sink_data(44)) AND sink_data(45)) AND (NOT sink_data(46))) AND (NOT sink_data(47))) AND (NOT sink_data(48))) AND (NOT sink_data(49)));
+ s_wire_altera_merlin_router_0005_src_channel_4_408_dataout <= (((((((((((NOT sink_data(39)) AND (NOT sink_data(40))) AND (NOT sink_data(41))) AND (NOT sink_data(42))) AND (NOT sink_data(43))) AND sink_data(44)) AND (NOT sink_data(45))) AND sink_data(46)) AND (NOT sink_data(47))) AND (NOT sink_data(48))) AND (NOT sink_data(49)));
+ s_wire_altera_merlin_router_0005_src_channel_5_441_dataout <= (((((((NOT sink_data(43)) AND (NOT sink_data(44))) AND (NOT sink_data(45))) AND (NOT sink_data(46))) AND (NOT sink_data(47))) AND (NOT sink_data(48))) AND sink_data(49));
+ s_wire_altera_merlin_router_0005_src_channel_6_474_dataout <= ((((((NOT sink_data(44)) AND (NOT sink_data(45))) AND (NOT sink_data(46))) AND (NOT sink_data(47))) AND sink_data(48)) AND sink_data(49));
+ sink_ready <= src_ready;
+ src_channel <= ( wire_altera_merlin_router_0005_src_channel_69m_dataout & wire_altera_merlin_router_0005_src_channel_70m_dataout & wire_altera_merlin_router_0005_src_channel_71m_dataout & wire_altera_merlin_router_0005_src_channel_72m_dataout & wire_altera_merlin_router_0005_src_channel_73m_dataout & wire_altera_merlin_router_0005_src_channel_74m_dataout & wire_altera_merlin_router_0005_src_channel_75m_dataout);
+ src_data <= ( sink_data(68) & wire_altera_merlin_router_0005_src_data_76m_dataout & wire_altera_merlin_router_0005_src_data_77m_dataout & wire_altera_merlin_router_0005_src_data_78m_dataout & sink_data(64 DOWNTO 0));
+ src_endofpacket <= sink_endofpacket;
+ src_startofpacket <= sink_startofpacket;
+ src_valid <= sink_valid;
+ wire_altera_merlin_router_0005_src_channel_15m_dataout <= wire_w1w(0) AND NOT(s_wire_altera_merlin_router_0005_src_channel_1_309_dataout);
+ wire_altera_merlin_router_0005_src_channel_20m_dataout <= s_wire_altera_merlin_router_0005_src_channel_0_276_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_1_309_dataout);
+ wire_altera_merlin_router_0005_src_channel_26m_dataout <= wire_altera_merlin_router_0005_src_channel_15m_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_2_342_dataout);
+ wire_altera_merlin_router_0005_src_channel_30m_dataout <= s_wire_altera_merlin_router_0005_src_channel_1_309_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_2_342_dataout);
+ wire_altera_merlin_router_0005_src_channel_31m_dataout <= wire_altera_merlin_router_0005_src_channel_20m_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_2_342_dataout);
+ wire_altera_merlin_router_0005_src_channel_37m_dataout <= wire_altera_merlin_router_0005_src_channel_26m_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_3_375_dataout);
+ wire_altera_merlin_router_0005_src_channel_40m_dataout <= s_wire_altera_merlin_router_0005_src_channel_2_342_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_3_375_dataout);
+ wire_altera_merlin_router_0005_src_channel_41m_dataout <= wire_altera_merlin_router_0005_src_channel_30m_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_3_375_dataout);
+ wire_altera_merlin_router_0005_src_channel_42m_dataout <= wire_altera_merlin_router_0005_src_channel_31m_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_3_375_dataout);
+ wire_altera_merlin_router_0005_src_channel_48m_dataout <= wire_altera_merlin_router_0005_src_channel_37m_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_4_408_dataout);
+ wire_altera_merlin_router_0005_src_channel_49m_dataout <= s_wire_altera_merlin_router_0005_src_channel_3_375_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_4_408_dataout);
+ wire_altera_merlin_router_0005_src_channel_51m_dataout <= wire_altera_merlin_router_0005_src_channel_40m_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_4_408_dataout);
+ wire_altera_merlin_router_0005_src_channel_52m_dataout <= wire_altera_merlin_router_0005_src_channel_41m_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_4_408_dataout);
+ wire_altera_merlin_router_0005_src_channel_53m_dataout <= wire_altera_merlin_router_0005_src_channel_42m_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_4_408_dataout);
+ wire_altera_merlin_router_0005_src_channel_58m_dataout <= s_wire_altera_merlin_router_0005_src_channel_4_408_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_5_441_dataout);
+ wire_altera_merlin_router_0005_src_channel_59m_dataout <= wire_altera_merlin_router_0005_src_channel_48m_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_5_441_dataout);
+ wire_altera_merlin_router_0005_src_channel_60m_dataout <= wire_altera_merlin_router_0005_src_channel_49m_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_5_441_dataout);
+ wire_altera_merlin_router_0005_src_channel_62m_dataout <= wire_altera_merlin_router_0005_src_channel_51m_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_5_441_dataout);
+ wire_altera_merlin_router_0005_src_channel_63m_dataout <= wire_altera_merlin_router_0005_src_channel_52m_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_5_441_dataout);
+ wire_altera_merlin_router_0005_src_channel_64m_dataout <= wire_altera_merlin_router_0005_src_channel_53m_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_5_441_dataout);
+ wire_altera_merlin_router_0005_src_channel_69m_dataout <= wire_altera_merlin_router_0005_src_channel_58m_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_6_474_dataout);
+ wire_altera_merlin_router_0005_src_channel_70m_dataout <= wire_altera_merlin_router_0005_src_channel_59m_dataout OR s_wire_altera_merlin_router_0005_src_channel_6_474_dataout;
+ wire_altera_merlin_router_0005_src_channel_71m_dataout <= wire_altera_merlin_router_0005_src_channel_60m_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_6_474_dataout);
+ wire_altera_merlin_router_0005_src_channel_72m_dataout <= s_wire_altera_merlin_router_0005_src_channel_5_441_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_6_474_dataout);
+ wire_altera_merlin_router_0005_src_channel_73m_dataout <= wire_altera_merlin_router_0005_src_channel_62m_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_6_474_dataout);
+ wire_altera_merlin_router_0005_src_channel_74m_dataout <= wire_altera_merlin_router_0005_src_channel_63m_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_6_474_dataout);
+ wire_altera_merlin_router_0005_src_channel_75m_dataout <= wire_altera_merlin_router_0005_src_channel_64m_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_6_474_dataout);
+ wire_altera_merlin_router_0005_src_data_21m_dataout <= wire_w1w(0) AND NOT(s_wire_altera_merlin_router_0005_src_channel_1_309_dataout);
+ wire_altera_merlin_router_0005_src_data_23m_dataout <= wire_w1w(0) OR s_wire_altera_merlin_router_0005_src_channel_1_309_dataout;
+ wire_altera_merlin_router_0005_src_data_32m_dataout <= wire_altera_merlin_router_0005_src_data_21m_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_2_342_dataout);
+ wire_altera_merlin_router_0005_src_data_34m_dataout <= wire_altera_merlin_router_0005_src_data_23m_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_2_342_dataout);
+ wire_altera_merlin_router_0005_src_data_43m_dataout <= wire_altera_merlin_router_0005_src_data_32m_dataout OR s_wire_altera_merlin_router_0005_src_channel_3_375_dataout;
+ wire_altera_merlin_router_0005_src_data_44m_dataout <= s_wire_altera_merlin_router_0005_src_channel_2_342_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_3_375_dataout);
+ wire_altera_merlin_router_0005_src_data_45m_dataout <= wire_altera_merlin_router_0005_src_data_34m_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_3_375_dataout);
+ wire_altera_merlin_router_0005_src_data_54m_dataout <= wire_altera_merlin_router_0005_src_data_43m_dataout OR s_wire_altera_merlin_router_0005_src_channel_4_408_dataout;
+ wire_altera_merlin_router_0005_src_data_55m_dataout <= wire_altera_merlin_router_0005_src_data_44m_dataout OR s_wire_altera_merlin_router_0005_src_channel_4_408_dataout;
+ wire_altera_merlin_router_0005_src_data_56m_dataout <= wire_altera_merlin_router_0005_src_data_45m_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_4_408_dataout);
+ wire_altera_merlin_router_0005_src_data_65m_dataout <= wire_altera_merlin_router_0005_src_data_54m_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_5_441_dataout);
+ wire_altera_merlin_router_0005_src_data_66m_dataout <= wire_altera_merlin_router_0005_src_data_55m_dataout OR s_wire_altera_merlin_router_0005_src_channel_5_441_dataout;
+ wire_altera_merlin_router_0005_src_data_67m_dataout <= wire_altera_merlin_router_0005_src_data_56m_dataout OR s_wire_altera_merlin_router_0005_src_channel_5_441_dataout;
+ wire_altera_merlin_router_0005_src_data_76m_dataout <= wire_altera_merlin_router_0005_src_data_65m_dataout OR s_wire_altera_merlin_router_0005_src_channel_6_474_dataout;
+ wire_altera_merlin_router_0005_src_data_77m_dataout <= wire_altera_merlin_router_0005_src_data_66m_dataout AND NOT(s_wire_altera_merlin_router_0005_src_channel_6_474_dataout);
+ wire_altera_merlin_router_0005_src_data_78m_dataout <= wire_altera_merlin_router_0005_src_data_67m_dataout OR s_wire_altera_merlin_router_0005_src_channel_6_474_dataout;
+
+ END RTL; --altera_merlin_router_0005
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_router/altera_merlin_router_0006.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_router/altera_merlin_router_0006.vho
new file mode 100644
index 0000000000000000000000000000000000000000..8c265ed71206c98c5f44af63c05464e028c5b11a
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_router/altera_merlin_router_0006.vho
@@ -0,0 +1,64 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_router_0006 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ reset : IN STD_LOGIC;
+ sink_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ sink_endofpacket : IN STD_LOGIC;
+ sink_ready : OUT STD_LOGIC;
+ sink_startofpacket : IN STD_LOGIC;
+ sink_valid : IN STD_LOGIC;
+ src_channel : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
+ src_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ src_endofpacket : OUT STD_LOGIC;
+ src_ready : IN STD_LOGIC;
+ src_startofpacket : OUT STD_LOGIC;
+ src_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_router_0006;
+
+ ARCHITECTURE RTL OF altera_merlin_router_0006 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ BEGIN
+
+ sink_ready <= src_ready;
+ src_channel <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1");
+ src_data <= ( sink_data(68 DOWNTO 0));
+ src_endofpacket <= sink_endofpacket;
+ src_startofpacket <= sink_startofpacket;
+ src_valid <= sink_valid;
+
+ END RTL; --altera_merlin_router_0006
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0001.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0001.vho
new file mode 100644
index 0000000000000000000000000000000000000000..ad657c6ca4632a95828cfde3487e37e2a01cb0de
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0001.vho
@@ -0,0 +1,519 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+ LIBRARY sgate;
+ USE sgate.sgate_pack.all;
+
+--synthesis_resources = lut 34 mux21 46 oper_add 3
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_slave_agent_0001 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ cp_channel : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+ cp_data : IN STD_LOGIC_VECTOR (65 DOWNTO 0);
+ cp_endofpacket : IN STD_LOGIC;
+ cp_ready : OUT STD_LOGIC;
+ cp_startofpacket : IN STD_LOGIC;
+ cp_valid : IN STD_LOGIC;
+ m0_address : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
+ m0_burstcount : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ m0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+ m0_debugaccess : OUT STD_LOGIC;
+ m0_lock : OUT STD_LOGIC;
+ m0_read : OUT STD_LOGIC;
+ m0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ m0_readdatavalid : IN STD_LOGIC;
+ m0_waitrequest : IN STD_LOGIC;
+ m0_write : OUT STD_LOGIC;
+ m0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_ready : OUT STD_LOGIC;
+ rdata_fifo_sink_valid : IN STD_LOGIC;
+ rdata_fifo_src_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_src_ready : IN STD_LOGIC;
+ rdata_fifo_src_valid : OUT STD_LOGIC;
+ reset : IN STD_LOGIC;
+ rf_sink_data : IN STD_LOGIC_VECTOR (66 DOWNTO 0);
+ rf_sink_endofpacket : IN STD_LOGIC;
+ rf_sink_ready : OUT STD_LOGIC;
+ rf_sink_startofpacket : IN STD_LOGIC;
+ rf_sink_valid : IN STD_LOGIC;
+ rf_source_data : OUT STD_LOGIC_VECTOR (66 DOWNTO 0);
+ rf_source_endofpacket : OUT STD_LOGIC;
+ rf_source_ready : IN STD_LOGIC;
+ rf_source_startofpacket : OUT STD_LOGIC;
+ rf_source_valid : OUT STD_LOGIC;
+ rp_data : OUT STD_LOGIC_VECTOR (65 DOWNTO 0);
+ rp_endofpacket : OUT STD_LOGIC;
+ rp_ready : IN STD_LOGIC;
+ rp_startofpacket : OUT STD_LOGIC;
+ rp_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_slave_agent_0001;
+
+ ARCHITECTURE RTL OF altera_merlin_slave_agent_0001 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1111q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1055q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1054q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1053q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1052q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_14_1051q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1064q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1063q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1062q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1061q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1060q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1059q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1058q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1057q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1056q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1013q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1050q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1015q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1014q : STD_LOGIC := '0';
+ SIGNAL wire_nl_w602w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w321w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w603w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w601w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_989q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1116q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1115q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1114q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1113q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_14_1112q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1125q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1124q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1123q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1122q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1121q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1120q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1119q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1118q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1117q : STD_LOGIC := '0';
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1001m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1002m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1003m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1006m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1007m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1008m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_997m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_998m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_999m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1065m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1066m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1067m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1068m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1069m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1070m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1071m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1072m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1073m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1074m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1075m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1076m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1077m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1078m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1079m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_992m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1155m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1145m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1144m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1143m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1142m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_14_1141m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1154m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1153m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1152m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1151m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1150m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1149m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1148m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1147m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1146m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_985m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_984m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_983m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount_0_463m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount_1_462m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount_2_461m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_gnd : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_a : STD_LOGIC_VECTOR (14 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_b : STD_LOGIC_VECTOR (14 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o : STD_LOGIC_VECTOR (14 DOWNTO 0);
+ SIGNAL wire_w_lg_cp_valid64w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_rf_source_ready65w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range681w730w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range678w680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range676w677w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range674w675w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range672w673w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range670w671w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range668w669w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range666w667w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range664w665w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range662w663w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range660w661w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range658w659w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range656w657w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range654w655w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range651w653w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_m0_waitrequest580w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_reset595w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w649w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w584w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range304w729w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range306w679w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range309w652w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range295w297w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_994_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1016_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_993_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1159_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_995_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_comb_481_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_cp_ready_456_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_local_compressed_read_451_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_local_read_450_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_local_write_449_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount_460_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read_457_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read_458_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_write_464_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_454_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ SIGNAL wire_w_cp_data_range63w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range681w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range678w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range676w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range674w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range672w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range670w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range668w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range666w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range664w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range662w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range660w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range658w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range656w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range654w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range651w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range295w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range296w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range304w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range306w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range309w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+ wire_gnd <= '0';
+ wire_w_lg_cp_valid64w(0) <= cp_valid AND wire_w_cp_data_range63w(0);
+ wire_w_lg_rf_source_ready65w(0) <= rf_source_ready AND wire_w_lg_cp_valid64w(0);
+ wire_w_lg_w_rf_sink_data_range681w730w(0) <= wire_w_rf_sink_data_range681w(0) AND wire_w_lg_w_rf_sink_data_range304w729w(0);
+ wire_w_lg_w_rf_sink_data_range678w680w(0) <= wire_w_rf_sink_data_range678w(0) AND wire_w_lg_w_rf_sink_data_range306w679w(0);
+ wire_w_lg_w_rf_sink_data_range676w677w(0) <= wire_w_rf_sink_data_range676w(0) AND wire_w_lg_w_rf_sink_data_range309w652w(0);
+ wire_w_lg_w_rf_sink_data_range674w675w(0) <= wire_w_rf_sink_data_range674w(0) AND wire_w_lg_w_rf_sink_data_range309w652w(0);
+ wire_w_lg_w_rf_sink_data_range672w673w(0) <= wire_w_rf_sink_data_range672w(0) AND wire_w_lg_w_rf_sink_data_range309w652w(0);
+ wire_w_lg_w_rf_sink_data_range670w671w(0) <= wire_w_rf_sink_data_range670w(0) AND wire_w_lg_w_rf_sink_data_range309w652w(0);
+ wire_w_lg_w_rf_sink_data_range668w669w(0) <= wire_w_rf_sink_data_range668w(0) AND wire_w_lg_w_rf_sink_data_range309w652w(0);
+ wire_w_lg_w_rf_sink_data_range666w667w(0) <= wire_w_rf_sink_data_range666w(0) AND wire_w_lg_w_rf_sink_data_range309w652w(0);
+ wire_w_lg_w_rf_sink_data_range664w665w(0) <= wire_w_rf_sink_data_range664w(0) AND wire_w_lg_w_rf_sink_data_range309w652w(0);
+ wire_w_lg_w_rf_sink_data_range662w663w(0) <= wire_w_rf_sink_data_range662w(0) AND wire_w_lg_w_rf_sink_data_range309w652w(0);
+ wire_w_lg_w_rf_sink_data_range660w661w(0) <= wire_w_rf_sink_data_range660w(0) AND wire_w_lg_w_rf_sink_data_range309w652w(0);
+ wire_w_lg_w_rf_sink_data_range658w659w(0) <= wire_w_rf_sink_data_range658w(0) AND wire_w_lg_w_rf_sink_data_range309w652w(0);
+ wire_w_lg_w_rf_sink_data_range656w657w(0) <= wire_w_rf_sink_data_range656w(0) AND wire_w_lg_w_rf_sink_data_range309w652w(0);
+ wire_w_lg_w_rf_sink_data_range654w655w(0) <= wire_w_rf_sink_data_range654w(0) AND wire_w_lg_w_rf_sink_data_range309w652w(0);
+ wire_w_lg_w_rf_sink_data_range651w653w(0) <= wire_w_rf_sink_data_range651w(0) AND wire_w_lg_w_rf_sink_data_range309w652w(0);
+ wire_w_lg_m0_waitrequest580w(0) <= NOT m0_waitrequest;
+ wire_w_lg_reset595w(0) <= NOT reset;
+ wire_w649w(0) <= NOT s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_993_dataout;
+ wire_w584w(0) <= NOT s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_local_compressed_read_451_dataout;
+ wire_w_lg_w_rf_sink_data_range304w729w(0) <= NOT wire_w_rf_sink_data_range304w(0);
+ wire_w_lg_w_rf_sink_data_range306w679w(0) <= NOT wire_w_rf_sink_data_range306w(0);
+ wire_w_lg_w_rf_sink_data_range309w652w(0) <= NOT wire_w_rf_sink_data_range309w(0);
+ wire_w_lg_w_rf_sink_data_range295w297w(0) <= wire_w_rf_sink_data_range295w(0) OR wire_w_rf_sink_data_range296w(0);
+ cp_ready <= s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_cp_ready_456_dataout;
+ m0_address <= ( cp_data(50 DOWNTO 36));
+ m0_burstcount <= ( wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount_2_461m_dataout & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount_1_462m_dataout & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount_0_463m_dataout);
+ m0_byteenable <= ( cp_data(35 DOWNTO 32));
+ m0_debugaccess <= cp_data(65);
+ m0_lock <= (wire_w_lg_rf_source_ready65w(0) AND (s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read_458_dataout OR s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_write_464_dataout));
+ m0_read <= s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read_458_dataout;
+ m0_write <= s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_write_464_dataout;
+ m0_writedata <= ( cp_data(31 DOWNTO 0));
+ rdata_fifo_sink_ready <= ((rp_ready AND rdata_fifo_sink_valid) AND (NOT (rf_sink_valid AND rf_sink_data(66))));
+ rdata_fifo_src_data <= ( m0_readdata(31 DOWNTO 0));
+ rdata_fifo_src_valid <= m0_readdatavalid;
+ rf_sink_ready <= (s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_993_dataout AND s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1159_dataout);
+ rf_source_data <= ( s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_454_dataout & cp_data(65 DOWNTO 32) & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ rf_source_endofpacket <= cp_endofpacket;
+ rf_source_startofpacket <= cp_startofpacket;
+ rf_source_valid <= (s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_cp_ready_456_dataout AND (rf_source_ready AND (s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_454_dataout OR s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read_457_dataout)));
+ rp_data <= ( rf_sink_data(65) & rf_sink_data(63) & rf_sink_data(64) & rf_sink_data(62 DOWNTO 59) & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_983m_dataout & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_984m_dataout & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_985m_dataout & rf_sink_data(55) & wire_w_lg_w_rf_sink_data_range295w297w & rf_sink_data(53 DOWNTO 52) & "0" & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_14_1141m_dataout & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1142m_dataout & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1143m_dataout & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1144m_dataout & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1145m_dataout & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1146m_dataout & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1147m_dataout
+ & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1148m_dataout & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1149m_dataout & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1150m_dataout & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1151m_dataout & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1152m_dataout & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1153m_dataout & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1154m_dataout & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1155m_dataout & rf_sink_data(35 DOWNTO 32) & rdata_fifo_sink_data(31 DOWNTO 0));
+ rp_endofpacket <= (rf_sink_endofpacket AND s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_993_dataout);
+ rp_startofpacket <= (rf_sink_startofpacket AND wire_nl_w321w(0));
+ rp_valid <= (rdata_fifo_sink_valid OR s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_comb_481_dataout);
+ s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_994_dataout <= (s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_comb_481_dataout AND s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1159_dataout);
+ s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1016_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout);
+ s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout <= (s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_comb_481_dataout AND wire_nl_w321w(0));
+ s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_993_dataout <= ((NOT rf_sink_data(51)) OR wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_992m_dataout);
+ s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1159_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_comb_481_dataout);
+ s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_995_dataout <= ((altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1014q OR altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1015q) OR altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1050q);
+ s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_comb_481_dataout <= (rf_sink_valid AND (rf_sink_data(66) OR rdata_fifo_sink_valid));
+ s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_cp_ready_456_dataout <= (wire_w_lg_m0_waitrequest580w(0) AND rf_source_ready);
+ s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_local_compressed_read_451_dataout <= (cp_valid AND cp_data(51));
+ s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_local_read_450_dataout <= (cp_valid AND cp_data(54));
+ s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_local_write_449_dataout <= (cp_valid AND cp_data(53));
+ s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount_460_dataout <= (s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_local_read_450_dataout AND wire_w584w(0));
+ s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read_457_dataout <= (s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_local_read_450_dataout OR s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_local_compressed_read_451_dataout);
+ s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read_458_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read_457_dataout);
+ s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_write_464_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_local_write_449_dataout);
+ s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_454_dataout <= ((NOT cp_data(52)) AND (cp_endofpacket AND s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_local_write_449_dataout));
+ s_wire_vcc <= '1';
+ wire_w_cp_data_range63w(0) <= cp_data(55);
+ wire_w_rf_sink_data_range681w(0) <= rf_sink_data(36);
+ wire_w_rf_sink_data_range678w(0) <= rf_sink_data(37);
+ wire_w_rf_sink_data_range676w(0) <= rf_sink_data(38);
+ wire_w_rf_sink_data_range674w(0) <= rf_sink_data(39);
+ wire_w_rf_sink_data_range672w(0) <= rf_sink_data(40);
+ wire_w_rf_sink_data_range670w(0) <= rf_sink_data(41);
+ wire_w_rf_sink_data_range668w(0) <= rf_sink_data(42);
+ wire_w_rf_sink_data_range666w(0) <= rf_sink_data(43);
+ wire_w_rf_sink_data_range664w(0) <= rf_sink_data(44);
+ wire_w_rf_sink_data_range662w(0) <= rf_sink_data(45);
+ wire_w_rf_sink_data_range660w(0) <= rf_sink_data(46);
+ wire_w_rf_sink_data_range658w(0) <= rf_sink_data(47);
+ wire_w_rf_sink_data_range656w(0) <= rf_sink_data(48);
+ wire_w_rf_sink_data_range654w(0) <= rf_sink_data(49);
+ wire_w_rf_sink_data_range651w(0) <= rf_sink_data(50);
+ wire_w_rf_sink_data_range295w(0) <= rf_sink_data(51);
+ wire_w_rf_sink_data_range296w(0) <= rf_sink_data(54);
+ wire_w_rf_sink_data_range304w(0) <= rf_sink_data(59);
+ wire_w_rf_sink_data_range306w(0) <= rf_sink_data(60);
+ wire_w_rf_sink_data_range309w(0) <= rf_sink_data(61);
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1111q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1055q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1054q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1053q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1052q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_14_1051q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1064q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1063q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1062q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1061q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1060q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1059q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1058q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1057q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1056q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1016_dataout = '1') THEN
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1111q <= wire_w_lg_w_rf_sink_data_range681w730w(0);
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1055q <= wire_w_lg_w_rf_sink_data_range660w661w(0);
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1054q <= wire_w_lg_w_rf_sink_data_range658w659w(0);
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1053q <= wire_w_lg_w_rf_sink_data_range656w657w(0);
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1052q <= wire_w_lg_w_rf_sink_data_range654w655w(0);
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_14_1051q <= wire_w_lg_w_rf_sink_data_range651w653w(0);
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1064q <= wire_w_lg_w_rf_sink_data_range678w680w(0);
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1063q <= wire_w_lg_w_rf_sink_data_range676w677w(0);
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1062q <= wire_w_lg_w_rf_sink_data_range674w675w(0);
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1061q <= wire_w_lg_w_rf_sink_data_range672w673w(0);
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1060q <= wire_w_lg_w_rf_sink_data_range670w671w(0);
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1059q <= wire_w_lg_w_rf_sink_data_range668w669w(0);
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1058q <= wire_w_lg_w_rf_sink_data_range666w667w(0);
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1057q <= wire_w_lg_w_rf_sink_data_range664w665w(0);
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1056q <= wire_w_lg_w_rf_sink_data_range662w663w(0);
+ END IF;
+ END IF;
+ END PROCESS;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1013q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1050q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1015q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1014q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_994_dataout = '1') THEN
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1013q <= wire_w649w(0);
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1050q <= wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1008m_dataout;
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1015q <= wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1007m_dataout;
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1014q <= wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1006m_dataout;
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_nl_w602w(0) <= altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1014q AND wire_nl_w601w(0);
+ wire_nl_w321w(0) <= NOT altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1013q;
+ wire_nl_w603w(0) <= NOT altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1050q;
+ wire_nl_w601w(0) <= NOT altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1015q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_989q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1116q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1115q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1114q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1113q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_14_1112q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1125q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1124q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1123q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1122q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1121q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1120q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1119q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1118q <= '0';
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1117q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1159_dataout = '1') THEN
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_989q <= (rf_sink_data(59) AND wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o(0));
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1116q <= (rf_sink_data(61) AND wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o(10));
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1115q <= (rf_sink_data(61) AND wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o(11));
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1114q <= (rf_sink_data(61) AND wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o(12));
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1113q <= (rf_sink_data(61) AND wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o(13));
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_14_1112q <= (rf_sink_data(61) AND wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o(14));
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1125q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o(1));
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1124q <= (rf_sink_data(61) AND wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o(2));
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1123q <= (rf_sink_data(61) AND wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o(3));
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1122q <= (rf_sink_data(61) AND wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o(4));
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1121q <= (rf_sink_data(61) AND wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o(5));
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1120q <= (rf_sink_data(61) AND wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o(6));
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1119q <= (rf_sink_data(61) AND wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o(7));
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1118q <= (rf_sink_data(61) AND wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o(8));
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1117q <= (rf_sink_data(61) AND wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o(9));
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1001m_dataout <= wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_997m_dataout WHEN altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1013q = '1' ELSE wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000_o(3);
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1002m_dataout <= wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_998m_dataout WHEN altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1013q = '1' ELSE wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000_o(2);
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1003m_dataout <= wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_999m_dataout WHEN altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1013q = '1' ELSE wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000_o(1);
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1006m_dataout <= wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1001m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_993_dataout);
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1007m_dataout <= wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1002m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_993_dataout);
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1008m_dataout <= wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1003m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_993_dataout);
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_997m_dataout <= wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996_o(3) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_995_dataout = '1' ELSE wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000_o(3);
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_998m_dataout <= wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996_o(2) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_995_dataout = '1' ELSE wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000_o(2);
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_999m_dataout <= wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996_o(1) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_995_dataout = '1' ELSE wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000_o(1);
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1065m_dataout <= rf_sink_data(50) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_14_1112q;
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1066m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1113q;
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1067m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1114q;
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1068m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1115q;
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1069m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1116q;
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1070m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1117q;
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1071m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1118q;
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1072m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1119q;
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1073m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1120q;
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1074m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1121q;
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1075m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1122q;
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1076m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1123q;
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1077m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1124q;
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1078m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1125q;
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1079m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_989q;
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_992m_dataout <= (s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_comb_481_dataout AND (wire_nl_w602w(0) AND wire_nl_w603w(0))) WHEN altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1013q = '1' ELSE (s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_comb_481_dataout AND (((NOT rf_sink_data(56)) AND (NOT rf_sink_data(57))) AND rf_sink_data(58)));
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1155m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE (altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_989q OR altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1111q);
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1145m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE (altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1055q OR altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1116q);
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1144m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE (altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1054q OR altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1115q);
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1143m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE (altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1053q OR altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1114q);
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1142m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE (altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1052q OR altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1113q);
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_14_1141m_dataout <= rf_sink_data(50) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE (altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_14_1051q OR altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_14_1112q);
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1154m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE (altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1064q OR altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1125q);
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1153m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE (altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1063q OR altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1124q);
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1152m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE (altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1062q OR altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1123q);
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1151m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE (altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1061q OR altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1122q);
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1150m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE (altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1060q OR altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1121q);
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1149m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE (altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1059q OR altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1120q);
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1148m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE (altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1058q OR altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1119q);
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1147m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE (altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1057q OR altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1118q);
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1146m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE (altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1056q OR altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1117q);
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_985m_dataout <= rf_sink_data(56) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1050q;
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_984m_dataout <= rf_sink_data(57) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1015q;
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_983m_dataout <= rf_sink_data(58) WHEN s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1014q;
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount_0_463m_dataout <= cp_data(56) AND NOT(s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount_460_dataout);
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount_1_462m_dataout <= cp_data(57) AND NOT(s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount_460_dataout);
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount_2_461m_dataout <= cp_data(58) OR s_wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount_460_dataout;
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996_a <= ( altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1014q & altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1015q & altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1050q & "1");
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996_a,
+ b => wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996_o
+ );
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000_a <= ( rf_sink_data(58 DOWNTO 56) & "1");
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000_a,
+ b => wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000_o
+ );
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_a <= ( wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1065m_dataout & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1066m_dataout & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1067m_dataout & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1068m_dataout & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1069m_dataout & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1070m_dataout & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1071m_dataout & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1072m_dataout & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1073m_dataout & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1074m_dataout & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1075m_dataout
+ & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1076m_dataout & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1077m_dataout & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1078m_dataout & wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1079m_dataout);
+ wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0");
+ altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 15,
+ width_b => 15,
+ width_o => 15
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_a,
+ b => wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o
+ );
+
+ END RTL; --altera_merlin_slave_agent_0001
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0002.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0002.vho
new file mode 100644
index 0000000000000000000000000000000000000000..59d7018b89f823452b9dab798b9c30cd2d3cbd11
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0002.vho
@@ -0,0 +1,519 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+ LIBRARY sgate;
+ USE sgate.sgate_pack.all;
+
+--synthesis_resources = lut 34 mux21 46 oper_add 3
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_slave_agent_0002 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ cp_channel : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+ cp_data : IN STD_LOGIC_VECTOR (65 DOWNTO 0);
+ cp_endofpacket : IN STD_LOGIC;
+ cp_ready : OUT STD_LOGIC;
+ cp_startofpacket : IN STD_LOGIC;
+ cp_valid : IN STD_LOGIC;
+ m0_address : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
+ m0_burstcount : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ m0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+ m0_debugaccess : OUT STD_LOGIC;
+ m0_lock : OUT STD_LOGIC;
+ m0_read : OUT STD_LOGIC;
+ m0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ m0_readdatavalid : IN STD_LOGIC;
+ m0_waitrequest : IN STD_LOGIC;
+ m0_write : OUT STD_LOGIC;
+ m0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_ready : OUT STD_LOGIC;
+ rdata_fifo_sink_valid : IN STD_LOGIC;
+ rdata_fifo_src_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_src_ready : IN STD_LOGIC;
+ rdata_fifo_src_valid : OUT STD_LOGIC;
+ reset : IN STD_LOGIC;
+ rf_sink_data : IN STD_LOGIC_VECTOR (66 DOWNTO 0);
+ rf_sink_endofpacket : IN STD_LOGIC;
+ rf_sink_ready : OUT STD_LOGIC;
+ rf_sink_startofpacket : IN STD_LOGIC;
+ rf_sink_valid : IN STD_LOGIC;
+ rf_source_data : OUT STD_LOGIC_VECTOR (66 DOWNTO 0);
+ rf_source_endofpacket : OUT STD_LOGIC;
+ rf_source_ready : IN STD_LOGIC;
+ rf_source_startofpacket : OUT STD_LOGIC;
+ rf_source_valid : OUT STD_LOGIC;
+ rp_data : OUT STD_LOGIC_VECTOR (65 DOWNTO 0);
+ rp_endofpacket : OUT STD_LOGIC;
+ rp_ready : IN STD_LOGIC;
+ rp_startofpacket : OUT STD_LOGIC;
+ rp_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_slave_agent_0002;
+
+ ARCHITECTURE RTL OF altera_merlin_slave_agent_0002 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1111q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1055q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1054q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1053q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1052q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_14_1051q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1064q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1063q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1062q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1061q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1060q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1059q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1058q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1057q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1056q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1013q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1050q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1015q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1014q : STD_LOGIC := '0';
+ SIGNAL wire_nl_w602w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w321w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w603w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w601w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_989q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1116q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1115q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1114q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1113q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_14_1112q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1125q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1124q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1123q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1122q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1121q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1120q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1119q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1118q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1117q : STD_LOGIC := '0';
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1001m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1002m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1003m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1006m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1007m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1008m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_997m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_998m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_999m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1065m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1066m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1067m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1068m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1069m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1070m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1071m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1072m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1073m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1074m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1075m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1076m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1077m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1078m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1079m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_992m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1155m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1145m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1144m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1143m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1142m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_14_1141m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1154m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1153m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1152m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1151m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1150m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1149m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1148m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1147m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1146m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_985m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_984m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_983m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount_0_463m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount_1_462m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount_2_461m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_gnd : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_a : STD_LOGIC_VECTOR (14 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_b : STD_LOGIC_VECTOR (14 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o : STD_LOGIC_VECTOR (14 DOWNTO 0);
+ SIGNAL wire_w_lg_cp_valid64w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_rf_source_ready65w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range681w730w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range678w680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range676w677w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range674w675w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range672w673w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range670w671w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range668w669w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range666w667w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range664w665w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range662w663w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range660w661w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range658w659w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range656w657w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range654w655w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range651w653w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_m0_waitrequest580w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_reset595w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w649w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w584w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range304w729w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range306w679w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range309w652w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range295w297w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_994_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1016_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_993_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1159_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_995_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_comb_481_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_cp_ready_456_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_local_compressed_read_451_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_local_read_450_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_local_write_449_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount_460_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read_457_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read_458_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_write_464_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_454_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ SIGNAL wire_w_cp_data_range63w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range681w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range678w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range676w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range674w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range672w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range670w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range668w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range666w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range664w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range662w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range660w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range658w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range656w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range654w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range651w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range295w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range296w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range304w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range306w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range309w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+ wire_gnd <= '0';
+ wire_w_lg_cp_valid64w(0) <= cp_valid AND wire_w_cp_data_range63w(0);
+ wire_w_lg_rf_source_ready65w(0) <= rf_source_ready AND wire_w_lg_cp_valid64w(0);
+ wire_w_lg_w_rf_sink_data_range681w730w(0) <= wire_w_rf_sink_data_range681w(0) AND wire_w_lg_w_rf_sink_data_range304w729w(0);
+ wire_w_lg_w_rf_sink_data_range678w680w(0) <= wire_w_rf_sink_data_range678w(0) AND wire_w_lg_w_rf_sink_data_range306w679w(0);
+ wire_w_lg_w_rf_sink_data_range676w677w(0) <= wire_w_rf_sink_data_range676w(0) AND wire_w_lg_w_rf_sink_data_range309w652w(0);
+ wire_w_lg_w_rf_sink_data_range674w675w(0) <= wire_w_rf_sink_data_range674w(0) AND wire_w_lg_w_rf_sink_data_range309w652w(0);
+ wire_w_lg_w_rf_sink_data_range672w673w(0) <= wire_w_rf_sink_data_range672w(0) AND wire_w_lg_w_rf_sink_data_range309w652w(0);
+ wire_w_lg_w_rf_sink_data_range670w671w(0) <= wire_w_rf_sink_data_range670w(0) AND wire_w_lg_w_rf_sink_data_range309w652w(0);
+ wire_w_lg_w_rf_sink_data_range668w669w(0) <= wire_w_rf_sink_data_range668w(0) AND wire_w_lg_w_rf_sink_data_range309w652w(0);
+ wire_w_lg_w_rf_sink_data_range666w667w(0) <= wire_w_rf_sink_data_range666w(0) AND wire_w_lg_w_rf_sink_data_range309w652w(0);
+ wire_w_lg_w_rf_sink_data_range664w665w(0) <= wire_w_rf_sink_data_range664w(0) AND wire_w_lg_w_rf_sink_data_range309w652w(0);
+ wire_w_lg_w_rf_sink_data_range662w663w(0) <= wire_w_rf_sink_data_range662w(0) AND wire_w_lg_w_rf_sink_data_range309w652w(0);
+ wire_w_lg_w_rf_sink_data_range660w661w(0) <= wire_w_rf_sink_data_range660w(0) AND wire_w_lg_w_rf_sink_data_range309w652w(0);
+ wire_w_lg_w_rf_sink_data_range658w659w(0) <= wire_w_rf_sink_data_range658w(0) AND wire_w_lg_w_rf_sink_data_range309w652w(0);
+ wire_w_lg_w_rf_sink_data_range656w657w(0) <= wire_w_rf_sink_data_range656w(0) AND wire_w_lg_w_rf_sink_data_range309w652w(0);
+ wire_w_lg_w_rf_sink_data_range654w655w(0) <= wire_w_rf_sink_data_range654w(0) AND wire_w_lg_w_rf_sink_data_range309w652w(0);
+ wire_w_lg_w_rf_sink_data_range651w653w(0) <= wire_w_rf_sink_data_range651w(0) AND wire_w_lg_w_rf_sink_data_range309w652w(0);
+ wire_w_lg_m0_waitrequest580w(0) <= NOT m0_waitrequest;
+ wire_w_lg_reset595w(0) <= NOT reset;
+ wire_w649w(0) <= NOT s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_993_dataout;
+ wire_w584w(0) <= NOT s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_local_compressed_read_451_dataout;
+ wire_w_lg_w_rf_sink_data_range304w729w(0) <= NOT wire_w_rf_sink_data_range304w(0);
+ wire_w_lg_w_rf_sink_data_range306w679w(0) <= NOT wire_w_rf_sink_data_range306w(0);
+ wire_w_lg_w_rf_sink_data_range309w652w(0) <= NOT wire_w_rf_sink_data_range309w(0);
+ wire_w_lg_w_rf_sink_data_range295w297w(0) <= wire_w_rf_sink_data_range295w(0) OR wire_w_rf_sink_data_range296w(0);
+ cp_ready <= s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_cp_ready_456_dataout;
+ m0_address <= ( cp_data(50 DOWNTO 36));
+ m0_burstcount <= ( wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount_2_461m_dataout & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount_1_462m_dataout & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount_0_463m_dataout);
+ m0_byteenable <= ( cp_data(35 DOWNTO 32));
+ m0_debugaccess <= cp_data(65);
+ m0_lock <= (wire_w_lg_rf_source_ready65w(0) AND (s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read_458_dataout OR s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_write_464_dataout));
+ m0_read <= s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read_458_dataout;
+ m0_write <= s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_write_464_dataout;
+ m0_writedata <= ( cp_data(31 DOWNTO 0));
+ rdata_fifo_sink_ready <= ((rp_ready AND rdata_fifo_sink_valid) AND (NOT (rf_sink_valid AND rf_sink_data(66))));
+ rdata_fifo_src_data <= ( m0_readdata(31 DOWNTO 0));
+ rdata_fifo_src_valid <= m0_readdatavalid;
+ rf_sink_ready <= (s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_993_dataout AND s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1159_dataout);
+ rf_source_data <= ( s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_454_dataout & cp_data(65 DOWNTO 32) & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ rf_source_endofpacket <= cp_endofpacket;
+ rf_source_startofpacket <= cp_startofpacket;
+ rf_source_valid <= (s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_cp_ready_456_dataout AND (rf_source_ready AND (s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_454_dataout OR s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read_457_dataout)));
+ rp_data <= ( rf_sink_data(65) & rf_sink_data(63) & rf_sink_data(64) & rf_sink_data(62 DOWNTO 59) & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_983m_dataout & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_984m_dataout & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_985m_dataout & rf_sink_data(55) & wire_w_lg_w_rf_sink_data_range295w297w & rf_sink_data(53 DOWNTO 52) & "0" & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_14_1141m_dataout & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1142m_dataout & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1143m_dataout & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1144m_dataout & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1145m_dataout & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1146m_dataout & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1147m_dataout
+ & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1148m_dataout & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1149m_dataout & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1150m_dataout & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1151m_dataout & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1152m_dataout & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1153m_dataout & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1154m_dataout & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1155m_dataout & rf_sink_data(35 DOWNTO 32) & rdata_fifo_sink_data(31 DOWNTO 0));
+ rp_endofpacket <= (rf_sink_endofpacket AND s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_993_dataout);
+ rp_startofpacket <= (rf_sink_startofpacket AND wire_nl_w321w(0));
+ rp_valid <= (rdata_fifo_sink_valid OR s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_comb_481_dataout);
+ s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_994_dataout <= (s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_comb_481_dataout AND s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1159_dataout);
+ s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1016_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout);
+ s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout <= (s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_comb_481_dataout AND wire_nl_w321w(0));
+ s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_993_dataout <= ((NOT rf_sink_data(51)) OR wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_992m_dataout);
+ s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1159_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_comb_481_dataout);
+ s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_995_dataout <= ((altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1014q OR altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1015q) OR altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1050q);
+ s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_comb_481_dataout <= (rf_sink_valid AND (rf_sink_data(66) OR rdata_fifo_sink_valid));
+ s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_cp_ready_456_dataout <= (wire_w_lg_m0_waitrequest580w(0) AND rf_source_ready);
+ s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_local_compressed_read_451_dataout <= (cp_valid AND cp_data(51));
+ s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_local_read_450_dataout <= (cp_valid AND cp_data(54));
+ s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_local_write_449_dataout <= (cp_valid AND cp_data(53));
+ s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount_460_dataout <= (s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_local_read_450_dataout AND wire_w584w(0));
+ s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read_457_dataout <= (s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_local_read_450_dataout OR s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_local_compressed_read_451_dataout);
+ s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read_458_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read_457_dataout);
+ s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_write_464_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_local_write_449_dataout);
+ s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_454_dataout <= ((NOT cp_data(52)) AND (cp_endofpacket AND s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_local_write_449_dataout));
+ s_wire_vcc <= '1';
+ wire_w_cp_data_range63w(0) <= cp_data(55);
+ wire_w_rf_sink_data_range681w(0) <= rf_sink_data(36);
+ wire_w_rf_sink_data_range678w(0) <= rf_sink_data(37);
+ wire_w_rf_sink_data_range676w(0) <= rf_sink_data(38);
+ wire_w_rf_sink_data_range674w(0) <= rf_sink_data(39);
+ wire_w_rf_sink_data_range672w(0) <= rf_sink_data(40);
+ wire_w_rf_sink_data_range670w(0) <= rf_sink_data(41);
+ wire_w_rf_sink_data_range668w(0) <= rf_sink_data(42);
+ wire_w_rf_sink_data_range666w(0) <= rf_sink_data(43);
+ wire_w_rf_sink_data_range664w(0) <= rf_sink_data(44);
+ wire_w_rf_sink_data_range662w(0) <= rf_sink_data(45);
+ wire_w_rf_sink_data_range660w(0) <= rf_sink_data(46);
+ wire_w_rf_sink_data_range658w(0) <= rf_sink_data(47);
+ wire_w_rf_sink_data_range656w(0) <= rf_sink_data(48);
+ wire_w_rf_sink_data_range654w(0) <= rf_sink_data(49);
+ wire_w_rf_sink_data_range651w(0) <= rf_sink_data(50);
+ wire_w_rf_sink_data_range295w(0) <= rf_sink_data(51);
+ wire_w_rf_sink_data_range296w(0) <= rf_sink_data(54);
+ wire_w_rf_sink_data_range304w(0) <= rf_sink_data(59);
+ wire_w_rf_sink_data_range306w(0) <= rf_sink_data(60);
+ wire_w_rf_sink_data_range309w(0) <= rf_sink_data(61);
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1111q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1055q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1054q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1053q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1052q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_14_1051q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1064q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1063q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1062q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1061q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1060q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1059q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1058q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1057q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1056q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1016_dataout = '1') THEN
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1111q <= wire_w_lg_w_rf_sink_data_range681w730w(0);
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1055q <= wire_w_lg_w_rf_sink_data_range660w661w(0);
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1054q <= wire_w_lg_w_rf_sink_data_range658w659w(0);
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1053q <= wire_w_lg_w_rf_sink_data_range656w657w(0);
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1052q <= wire_w_lg_w_rf_sink_data_range654w655w(0);
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_14_1051q <= wire_w_lg_w_rf_sink_data_range651w653w(0);
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1064q <= wire_w_lg_w_rf_sink_data_range678w680w(0);
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1063q <= wire_w_lg_w_rf_sink_data_range676w677w(0);
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1062q <= wire_w_lg_w_rf_sink_data_range674w675w(0);
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1061q <= wire_w_lg_w_rf_sink_data_range672w673w(0);
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1060q <= wire_w_lg_w_rf_sink_data_range670w671w(0);
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1059q <= wire_w_lg_w_rf_sink_data_range668w669w(0);
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1058q <= wire_w_lg_w_rf_sink_data_range666w667w(0);
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1057q <= wire_w_lg_w_rf_sink_data_range664w665w(0);
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1056q <= wire_w_lg_w_rf_sink_data_range662w663w(0);
+ END IF;
+ END IF;
+ END PROCESS;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1013q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1050q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1015q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1014q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_994_dataout = '1') THEN
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1013q <= wire_w649w(0);
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1050q <= wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1008m_dataout;
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1015q <= wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1007m_dataout;
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1014q <= wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1006m_dataout;
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_nl_w602w(0) <= altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1014q AND wire_nl_w601w(0);
+ wire_nl_w321w(0) <= NOT altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1013q;
+ wire_nl_w603w(0) <= NOT altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1050q;
+ wire_nl_w601w(0) <= NOT altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1015q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_989q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1116q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1115q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1114q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1113q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_14_1112q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1125q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1124q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1123q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1122q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1121q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1120q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1119q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1118q <= '0';
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1117q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1159_dataout = '1') THEN
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_989q <= (rf_sink_data(59) AND wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o(0));
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1116q <= (rf_sink_data(61) AND wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o(10));
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1115q <= (rf_sink_data(61) AND wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o(11));
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1114q <= (rf_sink_data(61) AND wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o(12));
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1113q <= (rf_sink_data(61) AND wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o(13));
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_14_1112q <= (rf_sink_data(61) AND wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o(14));
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1125q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o(1));
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1124q <= (rf_sink_data(61) AND wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o(2));
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1123q <= (rf_sink_data(61) AND wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o(3));
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1122q <= (rf_sink_data(61) AND wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o(4));
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1121q <= (rf_sink_data(61) AND wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o(5));
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1120q <= (rf_sink_data(61) AND wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o(6));
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1119q <= (rf_sink_data(61) AND wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o(7));
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1118q <= (rf_sink_data(61) AND wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o(8));
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1117q <= (rf_sink_data(61) AND wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o(9));
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1001m_dataout <= wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_997m_dataout WHEN altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1013q = '1' ELSE wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000_o(3);
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1002m_dataout <= wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_998m_dataout WHEN altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1013q = '1' ELSE wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000_o(2);
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1003m_dataout <= wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_999m_dataout WHEN altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1013q = '1' ELSE wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000_o(1);
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1006m_dataout <= wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1001m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_993_dataout);
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1007m_dataout <= wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1002m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_993_dataout);
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1008m_dataout <= wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1003m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_993_dataout);
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_997m_dataout <= wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996_o(3) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_995_dataout = '1' ELSE wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000_o(3);
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_998m_dataout <= wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996_o(2) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_995_dataout = '1' ELSE wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000_o(2);
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_999m_dataout <= wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996_o(1) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_995_dataout = '1' ELSE wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000_o(1);
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1065m_dataout <= rf_sink_data(50) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_14_1112q;
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1066m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1113q;
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1067m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1114q;
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1068m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1115q;
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1069m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1116q;
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1070m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1117q;
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1071m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1118q;
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1072m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1119q;
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1073m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1120q;
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1074m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1121q;
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1075m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1122q;
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1076m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1123q;
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1077m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1124q;
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1078m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1125q;
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1079m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_989q;
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_992m_dataout <= (s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_comb_481_dataout AND (wire_nl_w602w(0) AND wire_nl_w603w(0))) WHEN altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1013q = '1' ELSE (s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_comb_481_dataout AND (((NOT rf_sink_data(56)) AND (NOT rf_sink_data(57))) AND rf_sink_data(58)));
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1155m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE (altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_989q OR altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1111q);
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1145m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE (altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1055q OR altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1116q);
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1144m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE (altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1054q OR altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1115q);
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1143m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE (altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1053q OR altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1114q);
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1142m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE (altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1052q OR altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1113q);
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_14_1141m_dataout <= rf_sink_data(50) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE (altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_14_1051q OR altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_14_1112q);
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1154m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE (altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1064q OR altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1125q);
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1153m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE (altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1063q OR altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1124q);
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1152m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE (altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1062q OR altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1123q);
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1151m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE (altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1061q OR altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1122q);
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1150m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE (altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1060q OR altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1121q);
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1149m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE (altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1059q OR altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1120q);
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1148m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE (altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1058q OR altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1119q);
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1147m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE (altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1057q OR altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1118q);
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1146m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE (altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1056q OR altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1117q);
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_985m_dataout <= rf_sink_data(56) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1050q;
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_984m_dataout <= rf_sink_data(57) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1015q;
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_983m_dataout <= rf_sink_data(58) WHEN s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_982_dataout = '1' ELSE altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1014q;
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount_0_463m_dataout <= cp_data(56) AND NOT(s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount_460_dataout);
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount_1_462m_dataout <= cp_data(57) AND NOT(s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount_460_dataout);
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount_2_461m_dataout <= cp_data(58) OR s_wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount_460_dataout;
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996_a <= ( altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1014q & altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1015q & altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1050q & "1");
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996_a,
+ b => wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996_o
+ );
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000_a <= ( rf_sink_data(58 DOWNTO 56) & "1");
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000_a,
+ b => wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000_o
+ );
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_a <= ( wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1065m_dataout & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1066m_dataout & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1067m_dataout & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1068m_dataout & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1069m_dataout & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1070m_dataout & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1071m_dataout & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1072m_dataout & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1073m_dataout & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1074m_dataout & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1075m_dataout
+ & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1076m_dataout & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1077m_dataout & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1078m_dataout & wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1079m_dataout);
+ wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0");
+ altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 15,
+ width_b => 15,
+ width_o => 15
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_a,
+ b => wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080_o
+ );
+
+ END RTL; --altera_merlin_slave_agent_0002
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0003.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0003.vho
new file mode 100644
index 0000000000000000000000000000000000000000..0077a2e5d0e1299b76283cba93a9cb2253051d1a
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0003.vho
@@ -0,0 +1,505 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+ LIBRARY sgate;
+ USE sgate.sgate_pack.all;
+
+--synthesis_resources = lut 32 mux21 44 oper_add 3
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_slave_agent_0003 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ cp_channel : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ cp_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ cp_endofpacket : IN STD_LOGIC;
+ cp_ready : OUT STD_LOGIC;
+ cp_startofpacket : IN STD_LOGIC;
+ cp_valid : IN STD_LOGIC;
+ m0_address : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
+ m0_burstcount : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ m0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+ m0_debugaccess : OUT STD_LOGIC;
+ m0_lock : OUT STD_LOGIC;
+ m0_read : OUT STD_LOGIC;
+ m0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ m0_readdatavalid : IN STD_LOGIC;
+ m0_waitrequest : IN STD_LOGIC;
+ m0_write : OUT STD_LOGIC;
+ m0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_ready : OUT STD_LOGIC;
+ rdata_fifo_sink_valid : IN STD_LOGIC;
+ rdata_fifo_src_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_src_ready : IN STD_LOGIC;
+ rdata_fifo_src_valid : OUT STD_LOGIC;
+ reset : IN STD_LOGIC;
+ rf_sink_data : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
+ rf_sink_endofpacket : IN STD_LOGIC;
+ rf_sink_ready : OUT STD_LOGIC;
+ rf_sink_startofpacket : IN STD_LOGIC;
+ rf_sink_valid : IN STD_LOGIC;
+ rf_source_data : OUT STD_LOGIC_VECTOR (69 DOWNTO 0);
+ rf_source_endofpacket : OUT STD_LOGIC;
+ rf_source_ready : IN STD_LOGIC;
+ rf_source_startofpacket : OUT STD_LOGIC;
+ rf_source_valid : OUT STD_LOGIC;
+ rp_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ rp_endofpacket : OUT STD_LOGIC;
+ rp_ready : IN STD_LOGIC;
+ rp_startofpacket : OUT STD_LOGIC;
+ rp_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_slave_agent_0003;
+
+ ARCHITECTURE RTL OF altera_merlin_slave_agent_0003 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q : STD_LOGIC := '0';
+ SIGNAL wire_nl_w620w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w329w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w619w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q : STD_LOGIC := '0';
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1030m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1034m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1035m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1039m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1040m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1106m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1107m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1024m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1178m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1168m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1167m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1166m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1165m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1177m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1176m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1175m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1174m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1173m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1172m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1171m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1170m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1169m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1017m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1016m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1015m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_480m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_479m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_478m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_gnd : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_a : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_b : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_w_lg_cp_valid61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_rf_source_ready62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range697w743w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range694w696w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range692w693w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range690w691w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range688w689w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range686w687w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range684w685w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range682w683w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range680w681w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range678w679w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range676w677w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range674w675w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range672w673w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range669w671w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_m0_waitrequest598w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_reset613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w667w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w602w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range300w742w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range302w695w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range305w670w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range291w293w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1026_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1048_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_local_read_467_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_local_write_466_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_read_475_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_write_481_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ SIGNAL wire_w_cp_data_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range697w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range694w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range692w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range690w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range688w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range686w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range684w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range682w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range678w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range676w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range674w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range672w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range669w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range292w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range300w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range302w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range305w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+ wire_gnd <= '0';
+ wire_w_lg_cp_valid61w(0) <= cp_valid AND wire_w_cp_data_range60w(0);
+ wire_w_lg_rf_source_ready62w(0) <= rf_source_ready AND wire_w_lg_cp_valid61w(0);
+ wire_w_lg_w_rf_sink_data_range697w743w(0) <= wire_w_rf_sink_data_range697w(0) AND wire_w_lg_w_rf_sink_data_range300w742w(0);
+ wire_w_lg_w_rf_sink_data_range694w696w(0) <= wire_w_rf_sink_data_range694w(0) AND wire_w_lg_w_rf_sink_data_range302w695w(0);
+ wire_w_lg_w_rf_sink_data_range692w693w(0) <= wire_w_rf_sink_data_range692w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range690w691w(0) <= wire_w_rf_sink_data_range690w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range688w689w(0) <= wire_w_rf_sink_data_range688w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range686w687w(0) <= wire_w_rf_sink_data_range686w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range684w685w(0) <= wire_w_rf_sink_data_range684w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range682w683w(0) <= wire_w_rf_sink_data_range682w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range680w681w(0) <= wire_w_rf_sink_data_range680w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range678w679w(0) <= wire_w_rf_sink_data_range678w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range676w677w(0) <= wire_w_rf_sink_data_range676w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range674w675w(0) <= wire_w_rf_sink_data_range674w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range672w673w(0) <= wire_w_rf_sink_data_range672w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range669w671w(0) <= wire_w_rf_sink_data_range669w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_m0_waitrequest598w(0) <= NOT m0_waitrequest;
+ wire_w_lg_reset613w(0) <= NOT reset;
+ wire_w667w(0) <= NOT s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout;
+ wire_w602w(0) <= NOT s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout;
+ wire_w_lg_w_rf_sink_data_range300w742w(0) <= NOT wire_w_rf_sink_data_range300w(0);
+ wire_w_lg_w_rf_sink_data_range302w695w(0) <= NOT wire_w_rf_sink_data_range302w(0);
+ wire_w_lg_w_rf_sink_data_range305w670w(0) <= NOT wire_w_rf_sink_data_range305w(0);
+ wire_w_lg_w_rf_sink_data_range291w293w(0) <= wire_w_rf_sink_data_range291w(0) OR wire_w_rf_sink_data_range292w(0);
+ cp_ready <= s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout;
+ m0_address <= ( cp_data(49 DOWNTO 36));
+ m0_burstcount <= ( wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_478m_dataout & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_479m_dataout & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_480m_dataout);
+ m0_byteenable <= ( cp_data(35 DOWNTO 32));
+ m0_debugaccess <= cp_data(68);
+ m0_lock <= (wire_w_lg_rf_source_ready62w(0) AND (s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_read_475_dataout OR s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_write_481_dataout));
+ m0_read <= s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_read_475_dataout;
+ m0_write <= s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_write_481_dataout;
+ m0_writedata <= ( cp_data(31 DOWNTO 0));
+ rdata_fifo_sink_ready <= ((rp_ready AND rdata_fifo_sink_valid) AND (NOT (rf_sink_valid AND rf_sink_data(69))));
+ rdata_fifo_src_data <= ( m0_readdata(31 DOWNTO 0));
+ rdata_fifo_src_valid <= m0_readdatavalid;
+ rf_sink_ready <= (s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout AND s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout);
+ rf_source_data <= ( s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout & cp_data(68 DOWNTO 32) & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ rf_source_endofpacket <= cp_endofpacket;
+ rf_source_startofpacket <= cp_startofpacket;
+ rf_source_valid <= (s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout AND (rf_source_ready AND (s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout OR s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout)));
+ rp_data <= ( rf_sink_data(68) & rf_sink_data(64 DOWNTO 62) & rf_sink_data(67 DOWNTO 65) & rf_sink_data(61 DOWNTO 58) & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1015m_dataout & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1016m_dataout & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1017m_dataout & rf_sink_data(54) & wire_w_lg_w_rf_sink_data_range291w293w & rf_sink_data(52 DOWNTO 51) & "0" & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1165m_dataout & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1166m_dataout & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1167m_dataout & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1168m_dataout & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1169m_dataout & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1170m_dataout
+ & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1171m_dataout & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1172m_dataout & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1173m_dataout & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1174m_dataout & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1175m_dataout & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1176m_dataout & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1177m_dataout & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1178m_dataout & rf_sink_data(35 DOWNTO 32) & rdata_fifo_sink_data(31 DOWNTO 0));
+ rp_endofpacket <= (rf_sink_endofpacket AND s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ rp_startofpacket <= (rf_sink_startofpacket AND wire_nl_w329w(0));
+ rp_valid <= (rdata_fifo_sink_valid OR s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout);
+ s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1026_dataout <= (s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout AND s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout);
+ s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1048_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout);
+ s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout <= (s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout AND wire_nl_w329w(0));
+ s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout <= ((NOT rf_sink_data(50)) OR wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1024m_dataout);
+ s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout);
+ s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout <= ((altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q OR altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q) OR altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q);
+ s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout <= (rf_sink_valid AND (rf_sink_data(69) OR rdata_fifo_sink_valid));
+ s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout <= (wire_w_lg_m0_waitrequest598w(0) AND rf_source_ready);
+ s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout <= (cp_valid AND cp_data(50));
+ s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_local_read_467_dataout <= (cp_valid AND cp_data(53));
+ s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_local_write_466_dataout <= (cp_valid AND cp_data(52));
+ s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout <= (s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_local_read_467_dataout AND wire_w602w(0));
+ s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout <= (s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_local_read_467_dataout OR s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout);
+ s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_read_475_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout);
+ s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_write_481_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_local_write_466_dataout);
+ s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout <= ((NOT cp_data(51)) AND (cp_endofpacket AND s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_local_write_466_dataout));
+ s_wire_vcc <= '1';
+ wire_w_cp_data_range60w(0) <= cp_data(54);
+ wire_w_rf_sink_data_range697w(0) <= rf_sink_data(36);
+ wire_w_rf_sink_data_range694w(0) <= rf_sink_data(37);
+ wire_w_rf_sink_data_range692w(0) <= rf_sink_data(38);
+ wire_w_rf_sink_data_range690w(0) <= rf_sink_data(39);
+ wire_w_rf_sink_data_range688w(0) <= rf_sink_data(40);
+ wire_w_rf_sink_data_range686w(0) <= rf_sink_data(41);
+ wire_w_rf_sink_data_range684w(0) <= rf_sink_data(42);
+ wire_w_rf_sink_data_range682w(0) <= rf_sink_data(43);
+ wire_w_rf_sink_data_range680w(0) <= rf_sink_data(44);
+ wire_w_rf_sink_data_range678w(0) <= rf_sink_data(45);
+ wire_w_rf_sink_data_range676w(0) <= rf_sink_data(46);
+ wire_w_rf_sink_data_range674w(0) <= rf_sink_data(47);
+ wire_w_rf_sink_data_range672w(0) <= rf_sink_data(48);
+ wire_w_rf_sink_data_range669w(0) <= rf_sink_data(49);
+ wire_w_rf_sink_data_range291w(0) <= rf_sink_data(50);
+ wire_w_rf_sink_data_range292w(0) <= rf_sink_data(53);
+ wire_w_rf_sink_data_range300w(0) <= rf_sink_data(58);
+ wire_w_rf_sink_data_range302w(0) <= rf_sink_data(59);
+ wire_w_rf_sink_data_range305w(0) <= rf_sink_data(60);
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q <= '0';
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q <= '0';
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q <= '0';
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q <= '0';
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q <= '0';
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q <= '0';
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q <= '0';
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q <= '0';
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q <= '0';
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q <= '0';
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q <= '0';
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q <= '0';
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q <= '0';
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1048_dataout = '1') THEN
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q <= wire_w_lg_w_rf_sink_data_range697w743w(0);
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q <= wire_w_lg_w_rf_sink_data_range676w677w(0);
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q <= wire_w_lg_w_rf_sink_data_range674w675w(0);
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q <= wire_w_lg_w_rf_sink_data_range672w673w(0);
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q <= wire_w_lg_w_rf_sink_data_range669w671w(0);
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q <= wire_w_lg_w_rf_sink_data_range694w696w(0);
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q <= wire_w_lg_w_rf_sink_data_range692w693w(0);
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q <= wire_w_lg_w_rf_sink_data_range690w691w(0);
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q <= wire_w_lg_w_rf_sink_data_range688w689w(0);
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q <= wire_w_lg_w_rf_sink_data_range686w687w(0);
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q <= wire_w_lg_w_rf_sink_data_range684w685w(0);
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q <= wire_w_lg_w_rf_sink_data_range682w683w(0);
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q <= wire_w_lg_w_rf_sink_data_range680w681w(0);
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q <= wire_w_lg_w_rf_sink_data_range678w679w(0);
+ END IF;
+ END IF;
+ END PROCESS;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q <= '0';
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q <= '0';
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q <= '0';
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1026_dataout = '1') THEN
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q <= wire_w667w(0);
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q <= wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1040m_dataout;
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q <= wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1039m_dataout;
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q <= wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout;
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_nl_w620w(0) <= altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q AND wire_nl_w619w(0);
+ wire_nl_w329w(0) <= NOT altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q;
+ wire_nl_w621w(0) <= NOT altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q;
+ wire_nl_w619w(0) <= NOT altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q <= '0';
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q <= '0';
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q <= '0';
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q <= '0';
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q <= '0';
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q <= '0';
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q <= '0';
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q <= '0';
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q <= '0';
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q <= '0';
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q <= '0';
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q <= '0';
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q <= '0';
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout = '1') THEN
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q <= (rf_sink_data(58) AND wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(0));
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(10));
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(11));
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(12));
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(13));
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q <= (rf_sink_data(59) AND wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(1));
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(2));
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(3));
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(4));
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(5));
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(6));
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(7));
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(8));
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(9));
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout <= wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o(3) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout = '1' ELSE wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(3);
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1030m_dataout <= wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o(2) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout = '1' ELSE wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(2);
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout <= wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o(1) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout = '1' ELSE wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(1);
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout <= wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout WHEN altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(3);
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1034m_dataout <= wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1030m_dataout WHEN altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(2);
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1035m_dataout <= wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout WHEN altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(1);
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout <= wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1039m_dataout <= wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1034m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1040m_dataout <= wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1035m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q;
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q;
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q;
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q;
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q;
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q;
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q;
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q;
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q;
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q;
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q;
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q;
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1106m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q;
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1107m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q;
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1024m_dataout <= (s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout AND (wire_nl_w620w(0) AND wire_nl_w621w(0))) WHEN altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE (s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout AND (((NOT rf_sink_data(55)) AND (NOT rf_sink_data(56))) AND rf_sink_data(57)));
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1178m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q OR altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q);
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1168m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q OR altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q);
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1167m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q OR altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q);
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1166m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q OR altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q);
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1165m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q OR altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q);
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1177m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q OR altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q);
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1176m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q OR altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q);
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1175m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q OR altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q);
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1174m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q OR altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q);
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1173m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q OR altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q);
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1172m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q OR altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q);
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1171m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q OR altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q);
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1170m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q OR altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q);
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1169m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q OR altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q);
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1017m_dataout <= rf_sink_data(55) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q;
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1016m_dataout <= rf_sink_data(56) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q;
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1015m_dataout <= rf_sink_data(57) WHEN s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q;
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_480m_dataout <= cp_data(55) AND NOT(s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout);
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_479m_dataout <= cp_data(56) AND NOT(s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout);
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_478m_dataout <= cp_data(57) OR s_wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout;
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_a <= ( altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q & altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q & altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q & "1");
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_a,
+ b => wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o
+ );
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_a <= ( rf_sink_data(57 DOWNTO 55) & "1");
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_a,
+ b => wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o
+ );
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_a <= ( wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout
+ & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1106m_dataout & wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1107m_dataout);
+ wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0");
+ altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 14,
+ width_b => 14,
+ width_o => 14
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_a,
+ b => wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o
+ );
+
+ END RTL; --altera_merlin_slave_agent_0003
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0004.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0004.vho
new file mode 100644
index 0000000000000000000000000000000000000000..04e3536ff274d6585036e3ff5b2cb7c897fc1645
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0004.vho
@@ -0,0 +1,505 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+ LIBRARY sgate;
+ USE sgate.sgate_pack.all;
+
+--synthesis_resources = lut 32 mux21 44 oper_add 3
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_slave_agent_0004 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ cp_channel : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ cp_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ cp_endofpacket : IN STD_LOGIC;
+ cp_ready : OUT STD_LOGIC;
+ cp_startofpacket : IN STD_LOGIC;
+ cp_valid : IN STD_LOGIC;
+ m0_address : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
+ m0_burstcount : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ m0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+ m0_debugaccess : OUT STD_LOGIC;
+ m0_lock : OUT STD_LOGIC;
+ m0_read : OUT STD_LOGIC;
+ m0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ m0_readdatavalid : IN STD_LOGIC;
+ m0_waitrequest : IN STD_LOGIC;
+ m0_write : OUT STD_LOGIC;
+ m0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_ready : OUT STD_LOGIC;
+ rdata_fifo_sink_valid : IN STD_LOGIC;
+ rdata_fifo_src_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_src_ready : IN STD_LOGIC;
+ rdata_fifo_src_valid : OUT STD_LOGIC;
+ reset : IN STD_LOGIC;
+ rf_sink_data : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
+ rf_sink_endofpacket : IN STD_LOGIC;
+ rf_sink_ready : OUT STD_LOGIC;
+ rf_sink_startofpacket : IN STD_LOGIC;
+ rf_sink_valid : IN STD_LOGIC;
+ rf_source_data : OUT STD_LOGIC_VECTOR (69 DOWNTO 0);
+ rf_source_endofpacket : OUT STD_LOGIC;
+ rf_source_ready : IN STD_LOGIC;
+ rf_source_startofpacket : OUT STD_LOGIC;
+ rf_source_valid : OUT STD_LOGIC;
+ rp_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ rp_endofpacket : OUT STD_LOGIC;
+ rp_ready : IN STD_LOGIC;
+ rp_startofpacket : OUT STD_LOGIC;
+ rp_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_slave_agent_0004;
+
+ ARCHITECTURE RTL OF altera_merlin_slave_agent_0004 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q : STD_LOGIC := '0';
+ SIGNAL wire_nl_w620w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w329w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w619w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q : STD_LOGIC := '0';
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1030m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1034m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1035m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1039m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1040m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1106m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1107m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1024m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1178m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1168m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1167m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1166m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1165m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1177m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1176m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1175m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1174m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1173m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1172m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1171m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1170m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1169m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1017m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1016m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1015m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_480m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_479m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_478m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_gnd : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_a : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_b : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_w_lg_cp_valid61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_rf_source_ready62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range697w743w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range694w696w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range692w693w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range690w691w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range688w689w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range686w687w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range684w685w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range682w683w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range680w681w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range678w679w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range676w677w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range674w675w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range672w673w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range669w671w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_m0_waitrequest598w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_reset613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w667w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w602w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range300w742w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range302w695w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range305w670w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range291w293w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1026_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1048_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_local_read_467_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_local_write_466_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read_475_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_write_481_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ SIGNAL wire_w_cp_data_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range697w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range694w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range692w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range690w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range688w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range686w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range684w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range682w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range678w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range676w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range674w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range672w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range669w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range292w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range300w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range302w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range305w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+ wire_gnd <= '0';
+ wire_w_lg_cp_valid61w(0) <= cp_valid AND wire_w_cp_data_range60w(0);
+ wire_w_lg_rf_source_ready62w(0) <= rf_source_ready AND wire_w_lg_cp_valid61w(0);
+ wire_w_lg_w_rf_sink_data_range697w743w(0) <= wire_w_rf_sink_data_range697w(0) AND wire_w_lg_w_rf_sink_data_range300w742w(0);
+ wire_w_lg_w_rf_sink_data_range694w696w(0) <= wire_w_rf_sink_data_range694w(0) AND wire_w_lg_w_rf_sink_data_range302w695w(0);
+ wire_w_lg_w_rf_sink_data_range692w693w(0) <= wire_w_rf_sink_data_range692w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range690w691w(0) <= wire_w_rf_sink_data_range690w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range688w689w(0) <= wire_w_rf_sink_data_range688w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range686w687w(0) <= wire_w_rf_sink_data_range686w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range684w685w(0) <= wire_w_rf_sink_data_range684w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range682w683w(0) <= wire_w_rf_sink_data_range682w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range680w681w(0) <= wire_w_rf_sink_data_range680w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range678w679w(0) <= wire_w_rf_sink_data_range678w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range676w677w(0) <= wire_w_rf_sink_data_range676w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range674w675w(0) <= wire_w_rf_sink_data_range674w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range672w673w(0) <= wire_w_rf_sink_data_range672w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range669w671w(0) <= wire_w_rf_sink_data_range669w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_m0_waitrequest598w(0) <= NOT m0_waitrequest;
+ wire_w_lg_reset613w(0) <= NOT reset;
+ wire_w667w(0) <= NOT s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout;
+ wire_w602w(0) <= NOT s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout;
+ wire_w_lg_w_rf_sink_data_range300w742w(0) <= NOT wire_w_rf_sink_data_range300w(0);
+ wire_w_lg_w_rf_sink_data_range302w695w(0) <= NOT wire_w_rf_sink_data_range302w(0);
+ wire_w_lg_w_rf_sink_data_range305w670w(0) <= NOT wire_w_rf_sink_data_range305w(0);
+ wire_w_lg_w_rf_sink_data_range291w293w(0) <= wire_w_rf_sink_data_range291w(0) OR wire_w_rf_sink_data_range292w(0);
+ cp_ready <= s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout;
+ m0_address <= ( cp_data(49 DOWNTO 36));
+ m0_burstcount <= ( wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_478m_dataout & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_479m_dataout & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_480m_dataout);
+ m0_byteenable <= ( cp_data(35 DOWNTO 32));
+ m0_debugaccess <= cp_data(68);
+ m0_lock <= (wire_w_lg_rf_source_ready62w(0) AND (s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read_475_dataout OR s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_write_481_dataout));
+ m0_read <= s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read_475_dataout;
+ m0_write <= s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_write_481_dataout;
+ m0_writedata <= ( cp_data(31 DOWNTO 0));
+ rdata_fifo_sink_ready <= ((rp_ready AND rdata_fifo_sink_valid) AND (NOT (rf_sink_valid AND rf_sink_data(69))));
+ rdata_fifo_src_data <= ( m0_readdata(31 DOWNTO 0));
+ rdata_fifo_src_valid <= m0_readdatavalid;
+ rf_sink_ready <= (s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout AND s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout);
+ rf_source_data <= ( s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout & cp_data(68 DOWNTO 32) & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ rf_source_endofpacket <= cp_endofpacket;
+ rf_source_startofpacket <= cp_startofpacket;
+ rf_source_valid <= (s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout AND (rf_source_ready AND (s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout OR s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout)));
+ rp_data <= ( rf_sink_data(68) & rf_sink_data(64 DOWNTO 62) & rf_sink_data(67 DOWNTO 65) & rf_sink_data(61 DOWNTO 58) & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1015m_dataout & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1016m_dataout & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1017m_dataout & rf_sink_data(54) & wire_w_lg_w_rf_sink_data_range291w293w & rf_sink_data(52 DOWNTO 51) & "0" & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1165m_dataout & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1166m_dataout & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1167m_dataout & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1168m_dataout & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1169m_dataout & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1170m_dataout
+ & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1171m_dataout & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1172m_dataout & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1173m_dataout & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1174m_dataout & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1175m_dataout & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1176m_dataout & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1177m_dataout & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1178m_dataout & rf_sink_data(35 DOWNTO 32) & rdata_fifo_sink_data(31 DOWNTO 0));
+ rp_endofpacket <= (rf_sink_endofpacket AND s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ rp_startofpacket <= (rf_sink_startofpacket AND wire_nl_w329w(0));
+ rp_valid <= (rdata_fifo_sink_valid OR s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout);
+ s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1026_dataout <= (s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout AND s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout);
+ s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1048_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout);
+ s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout <= (s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout AND wire_nl_w329w(0));
+ s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout <= ((NOT rf_sink_data(50)) OR wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1024m_dataout);
+ s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout);
+ s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout <= ((altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q OR altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q) OR altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q);
+ s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout <= (rf_sink_valid AND (rf_sink_data(69) OR rdata_fifo_sink_valid));
+ s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout <= (wire_w_lg_m0_waitrequest598w(0) AND rf_source_ready);
+ s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout <= (cp_valid AND cp_data(50));
+ s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_local_read_467_dataout <= (cp_valid AND cp_data(53));
+ s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_local_write_466_dataout <= (cp_valid AND cp_data(52));
+ s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout <= (s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_local_read_467_dataout AND wire_w602w(0));
+ s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout <= (s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_local_read_467_dataout OR s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout);
+ s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read_475_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout);
+ s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_write_481_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_local_write_466_dataout);
+ s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout <= ((NOT cp_data(51)) AND (cp_endofpacket AND s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_local_write_466_dataout));
+ s_wire_vcc <= '1';
+ wire_w_cp_data_range60w(0) <= cp_data(54);
+ wire_w_rf_sink_data_range697w(0) <= rf_sink_data(36);
+ wire_w_rf_sink_data_range694w(0) <= rf_sink_data(37);
+ wire_w_rf_sink_data_range692w(0) <= rf_sink_data(38);
+ wire_w_rf_sink_data_range690w(0) <= rf_sink_data(39);
+ wire_w_rf_sink_data_range688w(0) <= rf_sink_data(40);
+ wire_w_rf_sink_data_range686w(0) <= rf_sink_data(41);
+ wire_w_rf_sink_data_range684w(0) <= rf_sink_data(42);
+ wire_w_rf_sink_data_range682w(0) <= rf_sink_data(43);
+ wire_w_rf_sink_data_range680w(0) <= rf_sink_data(44);
+ wire_w_rf_sink_data_range678w(0) <= rf_sink_data(45);
+ wire_w_rf_sink_data_range676w(0) <= rf_sink_data(46);
+ wire_w_rf_sink_data_range674w(0) <= rf_sink_data(47);
+ wire_w_rf_sink_data_range672w(0) <= rf_sink_data(48);
+ wire_w_rf_sink_data_range669w(0) <= rf_sink_data(49);
+ wire_w_rf_sink_data_range291w(0) <= rf_sink_data(50);
+ wire_w_rf_sink_data_range292w(0) <= rf_sink_data(53);
+ wire_w_rf_sink_data_range300w(0) <= rf_sink_data(58);
+ wire_w_rf_sink_data_range302w(0) <= rf_sink_data(59);
+ wire_w_rf_sink_data_range305w(0) <= rf_sink_data(60);
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q <= '0';
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q <= '0';
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q <= '0';
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q <= '0';
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q <= '0';
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q <= '0';
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q <= '0';
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q <= '0';
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q <= '0';
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q <= '0';
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q <= '0';
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q <= '0';
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q <= '0';
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1048_dataout = '1') THEN
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q <= wire_w_lg_w_rf_sink_data_range697w743w(0);
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q <= wire_w_lg_w_rf_sink_data_range676w677w(0);
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q <= wire_w_lg_w_rf_sink_data_range674w675w(0);
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q <= wire_w_lg_w_rf_sink_data_range672w673w(0);
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q <= wire_w_lg_w_rf_sink_data_range669w671w(0);
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q <= wire_w_lg_w_rf_sink_data_range694w696w(0);
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q <= wire_w_lg_w_rf_sink_data_range692w693w(0);
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q <= wire_w_lg_w_rf_sink_data_range690w691w(0);
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q <= wire_w_lg_w_rf_sink_data_range688w689w(0);
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q <= wire_w_lg_w_rf_sink_data_range686w687w(0);
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q <= wire_w_lg_w_rf_sink_data_range684w685w(0);
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q <= wire_w_lg_w_rf_sink_data_range682w683w(0);
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q <= wire_w_lg_w_rf_sink_data_range680w681w(0);
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q <= wire_w_lg_w_rf_sink_data_range678w679w(0);
+ END IF;
+ END IF;
+ END PROCESS;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q <= '0';
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q <= '0';
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q <= '0';
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1026_dataout = '1') THEN
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q <= wire_w667w(0);
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q <= wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1040m_dataout;
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q <= wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1039m_dataout;
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q <= wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout;
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_nl_w620w(0) <= altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q AND wire_nl_w619w(0);
+ wire_nl_w329w(0) <= NOT altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q;
+ wire_nl_w621w(0) <= NOT altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q;
+ wire_nl_w619w(0) <= NOT altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q <= '0';
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q <= '0';
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q <= '0';
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q <= '0';
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q <= '0';
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q <= '0';
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q <= '0';
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q <= '0';
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q <= '0';
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q <= '0';
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q <= '0';
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q <= '0';
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q <= '0';
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout = '1') THEN
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q <= (rf_sink_data(58) AND wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(0));
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(10));
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(11));
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(12));
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(13));
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q <= (rf_sink_data(59) AND wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(1));
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(2));
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(3));
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(4));
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(5));
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(6));
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(7));
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(8));
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(9));
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout <= wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o(3) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout = '1' ELSE wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(3);
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1030m_dataout <= wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o(2) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout = '1' ELSE wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(2);
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout <= wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o(1) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout = '1' ELSE wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(1);
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout <= wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout WHEN altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(3);
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1034m_dataout <= wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1030m_dataout WHEN altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(2);
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1035m_dataout <= wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout WHEN altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(1);
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout <= wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1039m_dataout <= wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1034m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1040m_dataout <= wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1035m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q;
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q;
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q;
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q;
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q;
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q;
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q;
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q;
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q;
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q;
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q;
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q;
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1106m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q;
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1107m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q;
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1024m_dataout <= (s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout AND (wire_nl_w620w(0) AND wire_nl_w621w(0))) WHEN altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE (s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout AND (((NOT rf_sink_data(55)) AND (NOT rf_sink_data(56))) AND rf_sink_data(57)));
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1178m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q OR altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q);
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1168m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q OR altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q);
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1167m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q OR altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q);
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1166m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q OR altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q);
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1165m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q OR altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q);
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1177m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q OR altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q);
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1176m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q OR altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q);
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1175m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q OR altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q);
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1174m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q OR altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q);
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1173m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q OR altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q);
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1172m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q OR altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q);
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1171m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q OR altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q);
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1170m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q OR altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q);
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1169m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q OR altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q);
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1017m_dataout <= rf_sink_data(55) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q;
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1016m_dataout <= rf_sink_data(56) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q;
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1015m_dataout <= rf_sink_data(57) WHEN s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q;
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_480m_dataout <= cp_data(55) AND NOT(s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout);
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_479m_dataout <= cp_data(56) AND NOT(s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout);
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_478m_dataout <= cp_data(57) OR s_wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout;
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_a <= ( altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q & altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q & altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q & "1");
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_a,
+ b => wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o
+ );
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_a <= ( rf_sink_data(57 DOWNTO 55) & "1");
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_a,
+ b => wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o
+ );
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_a <= ( wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout
+ & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1106m_dataout & wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1107m_dataout);
+ wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0");
+ altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 14,
+ width_b => 14,
+ width_o => 14
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_a,
+ b => wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o
+ );
+
+ END RTL; --altera_merlin_slave_agent_0004
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0005.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0005.vho
new file mode 100644
index 0000000000000000000000000000000000000000..ea7be1dac99058edc48ee5c2b6351a210f1e4e3e
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0005.vho
@@ -0,0 +1,505 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+ LIBRARY sgate;
+ USE sgate.sgate_pack.all;
+
+--synthesis_resources = lut 32 mux21 44 oper_add 3
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_slave_agent_0005 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ cp_channel : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ cp_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ cp_endofpacket : IN STD_LOGIC;
+ cp_ready : OUT STD_LOGIC;
+ cp_startofpacket : IN STD_LOGIC;
+ cp_valid : IN STD_LOGIC;
+ m0_address : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
+ m0_burstcount : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ m0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+ m0_debugaccess : OUT STD_LOGIC;
+ m0_lock : OUT STD_LOGIC;
+ m0_read : OUT STD_LOGIC;
+ m0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ m0_readdatavalid : IN STD_LOGIC;
+ m0_waitrequest : IN STD_LOGIC;
+ m0_write : OUT STD_LOGIC;
+ m0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_ready : OUT STD_LOGIC;
+ rdata_fifo_sink_valid : IN STD_LOGIC;
+ rdata_fifo_src_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_src_ready : IN STD_LOGIC;
+ rdata_fifo_src_valid : OUT STD_LOGIC;
+ reset : IN STD_LOGIC;
+ rf_sink_data : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
+ rf_sink_endofpacket : IN STD_LOGIC;
+ rf_sink_ready : OUT STD_LOGIC;
+ rf_sink_startofpacket : IN STD_LOGIC;
+ rf_sink_valid : IN STD_LOGIC;
+ rf_source_data : OUT STD_LOGIC_VECTOR (69 DOWNTO 0);
+ rf_source_endofpacket : OUT STD_LOGIC;
+ rf_source_ready : IN STD_LOGIC;
+ rf_source_startofpacket : OUT STD_LOGIC;
+ rf_source_valid : OUT STD_LOGIC;
+ rp_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ rp_endofpacket : OUT STD_LOGIC;
+ rp_ready : IN STD_LOGIC;
+ rp_startofpacket : OUT STD_LOGIC;
+ rp_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_slave_agent_0005;
+
+ ARCHITECTURE RTL OF altera_merlin_slave_agent_0005 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q : STD_LOGIC := '0';
+ SIGNAL wire_nl_w620w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w329w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w619w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q : STD_LOGIC := '0';
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1030m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1034m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1035m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1039m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1040m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1106m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1107m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1024m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1178m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1168m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1167m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1166m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1165m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1177m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1176m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1175m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1174m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1173m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1172m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1171m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1170m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1169m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1017m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1016m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1015m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_480m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_479m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_478m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_gnd : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_a : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_b : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_w_lg_cp_valid61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_rf_source_ready62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range697w743w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range694w696w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range692w693w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range690w691w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range688w689w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range686w687w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range684w685w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range682w683w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range680w681w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range678w679w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range676w677w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range674w675w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range672w673w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range669w671w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_m0_waitrequest598w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_reset613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w667w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w602w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range300w742w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range302w695w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range305w670w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range291w293w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1026_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1048_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_local_read_467_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_local_write_466_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read_475_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_write_481_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ SIGNAL wire_w_cp_data_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range697w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range694w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range692w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range690w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range688w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range686w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range684w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range682w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range678w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range676w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range674w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range672w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range669w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range292w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range300w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range302w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range305w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+ wire_gnd <= '0';
+ wire_w_lg_cp_valid61w(0) <= cp_valid AND wire_w_cp_data_range60w(0);
+ wire_w_lg_rf_source_ready62w(0) <= rf_source_ready AND wire_w_lg_cp_valid61w(0);
+ wire_w_lg_w_rf_sink_data_range697w743w(0) <= wire_w_rf_sink_data_range697w(0) AND wire_w_lg_w_rf_sink_data_range300w742w(0);
+ wire_w_lg_w_rf_sink_data_range694w696w(0) <= wire_w_rf_sink_data_range694w(0) AND wire_w_lg_w_rf_sink_data_range302w695w(0);
+ wire_w_lg_w_rf_sink_data_range692w693w(0) <= wire_w_rf_sink_data_range692w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range690w691w(0) <= wire_w_rf_sink_data_range690w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range688w689w(0) <= wire_w_rf_sink_data_range688w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range686w687w(0) <= wire_w_rf_sink_data_range686w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range684w685w(0) <= wire_w_rf_sink_data_range684w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range682w683w(0) <= wire_w_rf_sink_data_range682w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range680w681w(0) <= wire_w_rf_sink_data_range680w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range678w679w(0) <= wire_w_rf_sink_data_range678w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range676w677w(0) <= wire_w_rf_sink_data_range676w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range674w675w(0) <= wire_w_rf_sink_data_range674w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range672w673w(0) <= wire_w_rf_sink_data_range672w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range669w671w(0) <= wire_w_rf_sink_data_range669w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_m0_waitrequest598w(0) <= NOT m0_waitrequest;
+ wire_w_lg_reset613w(0) <= NOT reset;
+ wire_w667w(0) <= NOT s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout;
+ wire_w602w(0) <= NOT s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout;
+ wire_w_lg_w_rf_sink_data_range300w742w(0) <= NOT wire_w_rf_sink_data_range300w(0);
+ wire_w_lg_w_rf_sink_data_range302w695w(0) <= NOT wire_w_rf_sink_data_range302w(0);
+ wire_w_lg_w_rf_sink_data_range305w670w(0) <= NOT wire_w_rf_sink_data_range305w(0);
+ wire_w_lg_w_rf_sink_data_range291w293w(0) <= wire_w_rf_sink_data_range291w(0) OR wire_w_rf_sink_data_range292w(0);
+ cp_ready <= s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout;
+ m0_address <= ( cp_data(49 DOWNTO 36));
+ m0_burstcount <= ( wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_478m_dataout & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_479m_dataout & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_480m_dataout);
+ m0_byteenable <= ( cp_data(35 DOWNTO 32));
+ m0_debugaccess <= cp_data(68);
+ m0_lock <= (wire_w_lg_rf_source_ready62w(0) AND (s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read_475_dataout OR s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_write_481_dataout));
+ m0_read <= s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read_475_dataout;
+ m0_write <= s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_write_481_dataout;
+ m0_writedata <= ( cp_data(31 DOWNTO 0));
+ rdata_fifo_sink_ready <= ((rp_ready AND rdata_fifo_sink_valid) AND (NOT (rf_sink_valid AND rf_sink_data(69))));
+ rdata_fifo_src_data <= ( m0_readdata(31 DOWNTO 0));
+ rdata_fifo_src_valid <= m0_readdatavalid;
+ rf_sink_ready <= (s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout AND s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout);
+ rf_source_data <= ( s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout & cp_data(68 DOWNTO 32) & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ rf_source_endofpacket <= cp_endofpacket;
+ rf_source_startofpacket <= cp_startofpacket;
+ rf_source_valid <= (s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout AND (rf_source_ready AND (s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout OR s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout)));
+ rp_data <= ( rf_sink_data(68) & rf_sink_data(64 DOWNTO 62) & rf_sink_data(67 DOWNTO 65) & rf_sink_data(61 DOWNTO 58) & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1015m_dataout & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1016m_dataout & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1017m_dataout & rf_sink_data(54) & wire_w_lg_w_rf_sink_data_range291w293w & rf_sink_data(52 DOWNTO 51) & "0" & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1165m_dataout & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1166m_dataout & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1167m_dataout & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1168m_dataout & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1169m_dataout & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1170m_dataout
+ & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1171m_dataout & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1172m_dataout & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1173m_dataout & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1174m_dataout & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1175m_dataout & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1176m_dataout & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1177m_dataout & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1178m_dataout & rf_sink_data(35 DOWNTO 32) & rdata_fifo_sink_data(31 DOWNTO 0));
+ rp_endofpacket <= (rf_sink_endofpacket AND s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ rp_startofpacket <= (rf_sink_startofpacket AND wire_nl_w329w(0));
+ rp_valid <= (rdata_fifo_sink_valid OR s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout);
+ s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1026_dataout <= (s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout AND s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout);
+ s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1048_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout);
+ s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout <= (s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout AND wire_nl_w329w(0));
+ s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout <= ((NOT rf_sink_data(50)) OR wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1024m_dataout);
+ s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout);
+ s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout <= ((altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q OR altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q) OR altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q);
+ s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout <= (rf_sink_valid AND (rf_sink_data(69) OR rdata_fifo_sink_valid));
+ s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout <= (wire_w_lg_m0_waitrequest598w(0) AND rf_source_ready);
+ s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout <= (cp_valid AND cp_data(50));
+ s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_local_read_467_dataout <= (cp_valid AND cp_data(53));
+ s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_local_write_466_dataout <= (cp_valid AND cp_data(52));
+ s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout <= (s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_local_read_467_dataout AND wire_w602w(0));
+ s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout <= (s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_local_read_467_dataout OR s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout);
+ s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read_475_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout);
+ s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_write_481_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_local_write_466_dataout);
+ s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout <= ((NOT cp_data(51)) AND (cp_endofpacket AND s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_local_write_466_dataout));
+ s_wire_vcc <= '1';
+ wire_w_cp_data_range60w(0) <= cp_data(54);
+ wire_w_rf_sink_data_range697w(0) <= rf_sink_data(36);
+ wire_w_rf_sink_data_range694w(0) <= rf_sink_data(37);
+ wire_w_rf_sink_data_range692w(0) <= rf_sink_data(38);
+ wire_w_rf_sink_data_range690w(0) <= rf_sink_data(39);
+ wire_w_rf_sink_data_range688w(0) <= rf_sink_data(40);
+ wire_w_rf_sink_data_range686w(0) <= rf_sink_data(41);
+ wire_w_rf_sink_data_range684w(0) <= rf_sink_data(42);
+ wire_w_rf_sink_data_range682w(0) <= rf_sink_data(43);
+ wire_w_rf_sink_data_range680w(0) <= rf_sink_data(44);
+ wire_w_rf_sink_data_range678w(0) <= rf_sink_data(45);
+ wire_w_rf_sink_data_range676w(0) <= rf_sink_data(46);
+ wire_w_rf_sink_data_range674w(0) <= rf_sink_data(47);
+ wire_w_rf_sink_data_range672w(0) <= rf_sink_data(48);
+ wire_w_rf_sink_data_range669w(0) <= rf_sink_data(49);
+ wire_w_rf_sink_data_range291w(0) <= rf_sink_data(50);
+ wire_w_rf_sink_data_range292w(0) <= rf_sink_data(53);
+ wire_w_rf_sink_data_range300w(0) <= rf_sink_data(58);
+ wire_w_rf_sink_data_range302w(0) <= rf_sink_data(59);
+ wire_w_rf_sink_data_range305w(0) <= rf_sink_data(60);
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q <= '0';
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q <= '0';
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q <= '0';
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q <= '0';
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q <= '0';
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q <= '0';
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q <= '0';
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q <= '0';
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q <= '0';
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q <= '0';
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q <= '0';
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q <= '0';
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q <= '0';
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1048_dataout = '1') THEN
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q <= wire_w_lg_w_rf_sink_data_range697w743w(0);
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q <= wire_w_lg_w_rf_sink_data_range676w677w(0);
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q <= wire_w_lg_w_rf_sink_data_range674w675w(0);
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q <= wire_w_lg_w_rf_sink_data_range672w673w(0);
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q <= wire_w_lg_w_rf_sink_data_range669w671w(0);
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q <= wire_w_lg_w_rf_sink_data_range694w696w(0);
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q <= wire_w_lg_w_rf_sink_data_range692w693w(0);
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q <= wire_w_lg_w_rf_sink_data_range690w691w(0);
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q <= wire_w_lg_w_rf_sink_data_range688w689w(0);
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q <= wire_w_lg_w_rf_sink_data_range686w687w(0);
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q <= wire_w_lg_w_rf_sink_data_range684w685w(0);
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q <= wire_w_lg_w_rf_sink_data_range682w683w(0);
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q <= wire_w_lg_w_rf_sink_data_range680w681w(0);
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q <= wire_w_lg_w_rf_sink_data_range678w679w(0);
+ END IF;
+ END IF;
+ END PROCESS;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q <= '0';
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q <= '0';
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q <= '0';
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1026_dataout = '1') THEN
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q <= wire_w667w(0);
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q <= wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1040m_dataout;
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q <= wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1039m_dataout;
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q <= wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout;
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_nl_w620w(0) <= altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q AND wire_nl_w619w(0);
+ wire_nl_w329w(0) <= NOT altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q;
+ wire_nl_w621w(0) <= NOT altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q;
+ wire_nl_w619w(0) <= NOT altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q <= '0';
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q <= '0';
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q <= '0';
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q <= '0';
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q <= '0';
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q <= '0';
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q <= '0';
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q <= '0';
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q <= '0';
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q <= '0';
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q <= '0';
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q <= '0';
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q <= '0';
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout = '1') THEN
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q <= (rf_sink_data(58) AND wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(0));
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(10));
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(11));
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(12));
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(13));
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q <= (rf_sink_data(59) AND wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(1));
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(2));
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(3));
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(4));
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(5));
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(6));
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(7));
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(8));
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(9));
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout <= wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o(3) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout = '1' ELSE wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(3);
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1030m_dataout <= wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o(2) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout = '1' ELSE wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(2);
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout <= wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o(1) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout = '1' ELSE wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(1);
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout <= wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout WHEN altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(3);
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1034m_dataout <= wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1030m_dataout WHEN altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(2);
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1035m_dataout <= wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout WHEN altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(1);
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout <= wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1039m_dataout <= wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1034m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1040m_dataout <= wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1035m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q;
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q;
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q;
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q;
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q;
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q;
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q;
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q;
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q;
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q;
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q;
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q;
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1106m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q;
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1107m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q;
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1024m_dataout <= (s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout AND (wire_nl_w620w(0) AND wire_nl_w621w(0))) WHEN altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE (s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout AND (((NOT rf_sink_data(55)) AND (NOT rf_sink_data(56))) AND rf_sink_data(57)));
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1178m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q OR altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q);
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1168m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q OR altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q);
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1167m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q OR altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q);
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1166m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q OR altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q);
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1165m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q OR altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q);
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1177m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q OR altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q);
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1176m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q OR altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q);
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1175m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q OR altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q);
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1174m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q OR altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q);
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1173m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q OR altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q);
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1172m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q OR altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q);
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1171m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q OR altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q);
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1170m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q OR altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q);
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1169m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q OR altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q);
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1017m_dataout <= rf_sink_data(55) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q;
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1016m_dataout <= rf_sink_data(56) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q;
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1015m_dataout <= rf_sink_data(57) WHEN s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q;
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_480m_dataout <= cp_data(55) AND NOT(s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout);
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_479m_dataout <= cp_data(56) AND NOT(s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout);
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_478m_dataout <= cp_data(57) OR s_wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout;
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_a <= ( altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q & altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q & altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q & "1");
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_a,
+ b => wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o
+ );
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_a <= ( rf_sink_data(57 DOWNTO 55) & "1");
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_a,
+ b => wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o
+ );
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_a <= ( wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout
+ & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1106m_dataout & wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1107m_dataout);
+ wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0");
+ altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 14,
+ width_b => 14,
+ width_o => 14
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_a,
+ b => wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o
+ );
+
+ END RTL; --altera_merlin_slave_agent_0005
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0006.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0006.vho
new file mode 100644
index 0000000000000000000000000000000000000000..8e6f67ab87431de290989eff09ae445793dfc7b0
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0006.vho
@@ -0,0 +1,505 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+ LIBRARY sgate;
+ USE sgate.sgate_pack.all;
+
+--synthesis_resources = lut 32 mux21 44 oper_add 3
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_slave_agent_0006 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ cp_channel : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ cp_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ cp_endofpacket : IN STD_LOGIC;
+ cp_ready : OUT STD_LOGIC;
+ cp_startofpacket : IN STD_LOGIC;
+ cp_valid : IN STD_LOGIC;
+ m0_address : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
+ m0_burstcount : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ m0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+ m0_debugaccess : OUT STD_LOGIC;
+ m0_lock : OUT STD_LOGIC;
+ m0_read : OUT STD_LOGIC;
+ m0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ m0_readdatavalid : IN STD_LOGIC;
+ m0_waitrequest : IN STD_LOGIC;
+ m0_write : OUT STD_LOGIC;
+ m0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_ready : OUT STD_LOGIC;
+ rdata_fifo_sink_valid : IN STD_LOGIC;
+ rdata_fifo_src_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_src_ready : IN STD_LOGIC;
+ rdata_fifo_src_valid : OUT STD_LOGIC;
+ reset : IN STD_LOGIC;
+ rf_sink_data : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
+ rf_sink_endofpacket : IN STD_LOGIC;
+ rf_sink_ready : OUT STD_LOGIC;
+ rf_sink_startofpacket : IN STD_LOGIC;
+ rf_sink_valid : IN STD_LOGIC;
+ rf_source_data : OUT STD_LOGIC_VECTOR (69 DOWNTO 0);
+ rf_source_endofpacket : OUT STD_LOGIC;
+ rf_source_ready : IN STD_LOGIC;
+ rf_source_startofpacket : OUT STD_LOGIC;
+ rf_source_valid : OUT STD_LOGIC;
+ rp_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ rp_endofpacket : OUT STD_LOGIC;
+ rp_ready : IN STD_LOGIC;
+ rp_startofpacket : OUT STD_LOGIC;
+ rp_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_slave_agent_0006;
+
+ ARCHITECTURE RTL OF altera_merlin_slave_agent_0006 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q : STD_LOGIC := '0';
+ SIGNAL wire_nl_w620w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w329w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w619w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q : STD_LOGIC := '0';
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1030m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1034m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1035m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1039m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1040m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1106m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1107m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1024m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1178m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1168m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1167m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1166m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1165m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1177m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1176m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1175m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1174m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1173m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1172m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1171m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1170m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1169m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1017m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1016m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1015m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_480m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_479m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_478m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_gnd : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_a : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_b : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_w_lg_cp_valid61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_rf_source_ready62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range697w743w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range694w696w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range692w693w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range690w691w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range688w689w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range686w687w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range684w685w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range682w683w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range680w681w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range678w679w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range676w677w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range674w675w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range672w673w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range669w671w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_m0_waitrequest598w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_reset613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w667w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w602w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range300w742w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range302w695w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range305w670w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range291w293w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1026_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1048_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_local_read_467_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_local_write_466_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read_475_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_write_481_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ SIGNAL wire_w_cp_data_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range697w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range694w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range692w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range690w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range688w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range686w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range684w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range682w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range678w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range676w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range674w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range672w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range669w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range292w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range300w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range302w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range305w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+ wire_gnd <= '0';
+ wire_w_lg_cp_valid61w(0) <= cp_valid AND wire_w_cp_data_range60w(0);
+ wire_w_lg_rf_source_ready62w(0) <= rf_source_ready AND wire_w_lg_cp_valid61w(0);
+ wire_w_lg_w_rf_sink_data_range697w743w(0) <= wire_w_rf_sink_data_range697w(0) AND wire_w_lg_w_rf_sink_data_range300w742w(0);
+ wire_w_lg_w_rf_sink_data_range694w696w(0) <= wire_w_rf_sink_data_range694w(0) AND wire_w_lg_w_rf_sink_data_range302w695w(0);
+ wire_w_lg_w_rf_sink_data_range692w693w(0) <= wire_w_rf_sink_data_range692w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range690w691w(0) <= wire_w_rf_sink_data_range690w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range688w689w(0) <= wire_w_rf_sink_data_range688w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range686w687w(0) <= wire_w_rf_sink_data_range686w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range684w685w(0) <= wire_w_rf_sink_data_range684w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range682w683w(0) <= wire_w_rf_sink_data_range682w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range680w681w(0) <= wire_w_rf_sink_data_range680w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range678w679w(0) <= wire_w_rf_sink_data_range678w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range676w677w(0) <= wire_w_rf_sink_data_range676w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range674w675w(0) <= wire_w_rf_sink_data_range674w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range672w673w(0) <= wire_w_rf_sink_data_range672w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range669w671w(0) <= wire_w_rf_sink_data_range669w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_m0_waitrequest598w(0) <= NOT m0_waitrequest;
+ wire_w_lg_reset613w(0) <= NOT reset;
+ wire_w667w(0) <= NOT s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout;
+ wire_w602w(0) <= NOT s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout;
+ wire_w_lg_w_rf_sink_data_range300w742w(0) <= NOT wire_w_rf_sink_data_range300w(0);
+ wire_w_lg_w_rf_sink_data_range302w695w(0) <= NOT wire_w_rf_sink_data_range302w(0);
+ wire_w_lg_w_rf_sink_data_range305w670w(0) <= NOT wire_w_rf_sink_data_range305w(0);
+ wire_w_lg_w_rf_sink_data_range291w293w(0) <= wire_w_rf_sink_data_range291w(0) OR wire_w_rf_sink_data_range292w(0);
+ cp_ready <= s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout;
+ m0_address <= ( cp_data(49 DOWNTO 36));
+ m0_burstcount <= ( wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_478m_dataout & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_479m_dataout & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_480m_dataout);
+ m0_byteenable <= ( cp_data(35 DOWNTO 32));
+ m0_debugaccess <= cp_data(68);
+ m0_lock <= (wire_w_lg_rf_source_ready62w(0) AND (s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read_475_dataout OR s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_write_481_dataout));
+ m0_read <= s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read_475_dataout;
+ m0_write <= s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_write_481_dataout;
+ m0_writedata <= ( cp_data(31 DOWNTO 0));
+ rdata_fifo_sink_ready <= ((rp_ready AND rdata_fifo_sink_valid) AND (NOT (rf_sink_valid AND rf_sink_data(69))));
+ rdata_fifo_src_data <= ( m0_readdata(31 DOWNTO 0));
+ rdata_fifo_src_valid <= m0_readdatavalid;
+ rf_sink_ready <= (s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout AND s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout);
+ rf_source_data <= ( s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout & cp_data(68 DOWNTO 32) & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ rf_source_endofpacket <= cp_endofpacket;
+ rf_source_startofpacket <= cp_startofpacket;
+ rf_source_valid <= (s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout AND (rf_source_ready AND (s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout OR s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout)));
+ rp_data <= ( rf_sink_data(68) & rf_sink_data(64 DOWNTO 62) & rf_sink_data(67 DOWNTO 65) & rf_sink_data(61 DOWNTO 58) & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1015m_dataout & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1016m_dataout & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1017m_dataout & rf_sink_data(54) & wire_w_lg_w_rf_sink_data_range291w293w & rf_sink_data(52 DOWNTO 51) & "0" & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1165m_dataout & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1166m_dataout & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1167m_dataout & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1168m_dataout & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1169m_dataout & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1170m_dataout
+ & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1171m_dataout & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1172m_dataout & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1173m_dataout & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1174m_dataout & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1175m_dataout & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1176m_dataout & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1177m_dataout & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1178m_dataout & rf_sink_data(35 DOWNTO 32) & rdata_fifo_sink_data(31 DOWNTO 0));
+ rp_endofpacket <= (rf_sink_endofpacket AND s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ rp_startofpacket <= (rf_sink_startofpacket AND wire_nl_w329w(0));
+ rp_valid <= (rdata_fifo_sink_valid OR s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout);
+ s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1026_dataout <= (s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout AND s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout);
+ s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1048_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout);
+ s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout <= (s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout AND wire_nl_w329w(0));
+ s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout <= ((NOT rf_sink_data(50)) OR wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1024m_dataout);
+ s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout);
+ s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout <= ((altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q OR altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q) OR altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q);
+ s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout <= (rf_sink_valid AND (rf_sink_data(69) OR rdata_fifo_sink_valid));
+ s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout <= (wire_w_lg_m0_waitrequest598w(0) AND rf_source_ready);
+ s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout <= (cp_valid AND cp_data(50));
+ s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_local_read_467_dataout <= (cp_valid AND cp_data(53));
+ s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_local_write_466_dataout <= (cp_valid AND cp_data(52));
+ s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout <= (s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_local_read_467_dataout AND wire_w602w(0));
+ s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout <= (s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_local_read_467_dataout OR s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout);
+ s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read_475_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout);
+ s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_write_481_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_local_write_466_dataout);
+ s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout <= ((NOT cp_data(51)) AND (cp_endofpacket AND s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_local_write_466_dataout));
+ s_wire_vcc <= '1';
+ wire_w_cp_data_range60w(0) <= cp_data(54);
+ wire_w_rf_sink_data_range697w(0) <= rf_sink_data(36);
+ wire_w_rf_sink_data_range694w(0) <= rf_sink_data(37);
+ wire_w_rf_sink_data_range692w(0) <= rf_sink_data(38);
+ wire_w_rf_sink_data_range690w(0) <= rf_sink_data(39);
+ wire_w_rf_sink_data_range688w(0) <= rf_sink_data(40);
+ wire_w_rf_sink_data_range686w(0) <= rf_sink_data(41);
+ wire_w_rf_sink_data_range684w(0) <= rf_sink_data(42);
+ wire_w_rf_sink_data_range682w(0) <= rf_sink_data(43);
+ wire_w_rf_sink_data_range680w(0) <= rf_sink_data(44);
+ wire_w_rf_sink_data_range678w(0) <= rf_sink_data(45);
+ wire_w_rf_sink_data_range676w(0) <= rf_sink_data(46);
+ wire_w_rf_sink_data_range674w(0) <= rf_sink_data(47);
+ wire_w_rf_sink_data_range672w(0) <= rf_sink_data(48);
+ wire_w_rf_sink_data_range669w(0) <= rf_sink_data(49);
+ wire_w_rf_sink_data_range291w(0) <= rf_sink_data(50);
+ wire_w_rf_sink_data_range292w(0) <= rf_sink_data(53);
+ wire_w_rf_sink_data_range300w(0) <= rf_sink_data(58);
+ wire_w_rf_sink_data_range302w(0) <= rf_sink_data(59);
+ wire_w_rf_sink_data_range305w(0) <= rf_sink_data(60);
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q <= '0';
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q <= '0';
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q <= '0';
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q <= '0';
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q <= '0';
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q <= '0';
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q <= '0';
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q <= '0';
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q <= '0';
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q <= '0';
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q <= '0';
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q <= '0';
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q <= '0';
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1048_dataout = '1') THEN
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q <= wire_w_lg_w_rf_sink_data_range697w743w(0);
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q <= wire_w_lg_w_rf_sink_data_range676w677w(0);
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q <= wire_w_lg_w_rf_sink_data_range674w675w(0);
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q <= wire_w_lg_w_rf_sink_data_range672w673w(0);
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q <= wire_w_lg_w_rf_sink_data_range669w671w(0);
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q <= wire_w_lg_w_rf_sink_data_range694w696w(0);
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q <= wire_w_lg_w_rf_sink_data_range692w693w(0);
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q <= wire_w_lg_w_rf_sink_data_range690w691w(0);
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q <= wire_w_lg_w_rf_sink_data_range688w689w(0);
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q <= wire_w_lg_w_rf_sink_data_range686w687w(0);
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q <= wire_w_lg_w_rf_sink_data_range684w685w(0);
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q <= wire_w_lg_w_rf_sink_data_range682w683w(0);
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q <= wire_w_lg_w_rf_sink_data_range680w681w(0);
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q <= wire_w_lg_w_rf_sink_data_range678w679w(0);
+ END IF;
+ END IF;
+ END PROCESS;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q <= '0';
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q <= '0';
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q <= '0';
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1026_dataout = '1') THEN
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q <= wire_w667w(0);
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q <= wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1040m_dataout;
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q <= wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1039m_dataout;
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q <= wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout;
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_nl_w620w(0) <= altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q AND wire_nl_w619w(0);
+ wire_nl_w329w(0) <= NOT altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q;
+ wire_nl_w621w(0) <= NOT altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q;
+ wire_nl_w619w(0) <= NOT altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q <= '0';
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q <= '0';
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q <= '0';
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q <= '0';
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q <= '0';
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q <= '0';
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q <= '0';
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q <= '0';
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q <= '0';
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q <= '0';
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q <= '0';
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q <= '0';
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q <= '0';
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout = '1') THEN
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q <= (rf_sink_data(58) AND wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(0));
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(10));
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(11));
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(12));
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(13));
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q <= (rf_sink_data(59) AND wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(1));
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(2));
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(3));
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(4));
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(5));
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(6));
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(7));
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(8));
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(9));
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout <= wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o(3) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout = '1' ELSE wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(3);
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1030m_dataout <= wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o(2) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout = '1' ELSE wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(2);
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout <= wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o(1) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout = '1' ELSE wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(1);
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout <= wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout WHEN altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(3);
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1034m_dataout <= wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1030m_dataout WHEN altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(2);
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1035m_dataout <= wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout WHEN altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(1);
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout <= wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1039m_dataout <= wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1034m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1040m_dataout <= wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1035m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q;
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q;
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q;
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q;
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q;
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q;
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q;
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q;
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q;
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q;
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q;
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q;
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1106m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q;
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1107m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q;
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1024m_dataout <= (s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout AND (wire_nl_w620w(0) AND wire_nl_w621w(0))) WHEN altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE (s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout AND (((NOT rf_sink_data(55)) AND (NOT rf_sink_data(56))) AND rf_sink_data(57)));
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1178m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q OR altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q);
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1168m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q OR altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q);
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1167m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q OR altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q);
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1166m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q OR altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q);
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1165m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q OR altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q);
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1177m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q OR altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q);
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1176m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q OR altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q);
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1175m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q OR altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q);
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1174m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q OR altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q);
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1173m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q OR altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q);
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1172m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q OR altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q);
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1171m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q OR altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q);
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1170m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q OR altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q);
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1169m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q OR altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q);
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1017m_dataout <= rf_sink_data(55) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q;
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1016m_dataout <= rf_sink_data(56) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q;
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1015m_dataout <= rf_sink_data(57) WHEN s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q;
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_480m_dataout <= cp_data(55) AND NOT(s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout);
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_479m_dataout <= cp_data(56) AND NOT(s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout);
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_478m_dataout <= cp_data(57) OR s_wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout;
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_a <= ( altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q & altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q & altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q & "1");
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_a,
+ b => wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o
+ );
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_a <= ( rf_sink_data(57 DOWNTO 55) & "1");
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_a,
+ b => wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o
+ );
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_a <= ( wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout
+ & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1106m_dataout & wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1107m_dataout);
+ wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0");
+ altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 14,
+ width_b => 14,
+ width_o => 14
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_a,
+ b => wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o
+ );
+
+ END RTL; --altera_merlin_slave_agent_0006
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0007.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0007.vho
new file mode 100644
index 0000000000000000000000000000000000000000..e567923edcc397fdc6febd38575cfadfd1b88494
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0007.vho
@@ -0,0 +1,505 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+ LIBRARY sgate;
+ USE sgate.sgate_pack.all;
+
+--synthesis_resources = lut 32 mux21 44 oper_add 3
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_slave_agent_0007 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ cp_channel : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ cp_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ cp_endofpacket : IN STD_LOGIC;
+ cp_ready : OUT STD_LOGIC;
+ cp_startofpacket : IN STD_LOGIC;
+ cp_valid : IN STD_LOGIC;
+ m0_address : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
+ m0_burstcount : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ m0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+ m0_debugaccess : OUT STD_LOGIC;
+ m0_lock : OUT STD_LOGIC;
+ m0_read : OUT STD_LOGIC;
+ m0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ m0_readdatavalid : IN STD_LOGIC;
+ m0_waitrequest : IN STD_LOGIC;
+ m0_write : OUT STD_LOGIC;
+ m0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_ready : OUT STD_LOGIC;
+ rdata_fifo_sink_valid : IN STD_LOGIC;
+ rdata_fifo_src_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_src_ready : IN STD_LOGIC;
+ rdata_fifo_src_valid : OUT STD_LOGIC;
+ reset : IN STD_LOGIC;
+ rf_sink_data : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
+ rf_sink_endofpacket : IN STD_LOGIC;
+ rf_sink_ready : OUT STD_LOGIC;
+ rf_sink_startofpacket : IN STD_LOGIC;
+ rf_sink_valid : IN STD_LOGIC;
+ rf_source_data : OUT STD_LOGIC_VECTOR (69 DOWNTO 0);
+ rf_source_endofpacket : OUT STD_LOGIC;
+ rf_source_ready : IN STD_LOGIC;
+ rf_source_startofpacket : OUT STD_LOGIC;
+ rf_source_valid : OUT STD_LOGIC;
+ rp_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ rp_endofpacket : OUT STD_LOGIC;
+ rp_ready : IN STD_LOGIC;
+ rp_startofpacket : OUT STD_LOGIC;
+ rp_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_slave_agent_0007;
+
+ ARCHITECTURE RTL OF altera_merlin_slave_agent_0007 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q : STD_LOGIC := '0';
+ SIGNAL wire_nl_w620w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w329w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w619w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q : STD_LOGIC := '0';
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1030m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1034m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1035m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1039m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1040m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1106m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1107m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1024m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1178m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1168m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1167m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1166m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1165m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1177m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1176m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1175m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1174m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1173m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1172m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1171m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1170m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1169m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1017m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1016m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1015m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_480m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_479m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_478m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_gnd : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_a : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_b : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_w_lg_cp_valid61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_rf_source_ready62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range697w743w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range694w696w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range692w693w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range690w691w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range688w689w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range686w687w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range684w685w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range682w683w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range680w681w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range678w679w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range676w677w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range674w675w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range672w673w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range669w671w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_m0_waitrequest598w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_reset613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w667w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w602w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range300w742w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range302w695w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range305w670w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range291w293w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1026_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1048_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_local_read_467_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_local_write_466_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_read_475_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_write_481_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ SIGNAL wire_w_cp_data_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range697w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range694w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range692w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range690w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range688w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range686w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range684w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range682w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range678w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range676w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range674w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range672w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range669w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range292w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range300w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range302w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range305w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+ wire_gnd <= '0';
+ wire_w_lg_cp_valid61w(0) <= cp_valid AND wire_w_cp_data_range60w(0);
+ wire_w_lg_rf_source_ready62w(0) <= rf_source_ready AND wire_w_lg_cp_valid61w(0);
+ wire_w_lg_w_rf_sink_data_range697w743w(0) <= wire_w_rf_sink_data_range697w(0) AND wire_w_lg_w_rf_sink_data_range300w742w(0);
+ wire_w_lg_w_rf_sink_data_range694w696w(0) <= wire_w_rf_sink_data_range694w(0) AND wire_w_lg_w_rf_sink_data_range302w695w(0);
+ wire_w_lg_w_rf_sink_data_range692w693w(0) <= wire_w_rf_sink_data_range692w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range690w691w(0) <= wire_w_rf_sink_data_range690w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range688w689w(0) <= wire_w_rf_sink_data_range688w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range686w687w(0) <= wire_w_rf_sink_data_range686w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range684w685w(0) <= wire_w_rf_sink_data_range684w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range682w683w(0) <= wire_w_rf_sink_data_range682w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range680w681w(0) <= wire_w_rf_sink_data_range680w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range678w679w(0) <= wire_w_rf_sink_data_range678w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range676w677w(0) <= wire_w_rf_sink_data_range676w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range674w675w(0) <= wire_w_rf_sink_data_range674w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range672w673w(0) <= wire_w_rf_sink_data_range672w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range669w671w(0) <= wire_w_rf_sink_data_range669w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_m0_waitrequest598w(0) <= NOT m0_waitrequest;
+ wire_w_lg_reset613w(0) <= NOT reset;
+ wire_w667w(0) <= NOT s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout;
+ wire_w602w(0) <= NOT s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout;
+ wire_w_lg_w_rf_sink_data_range300w742w(0) <= NOT wire_w_rf_sink_data_range300w(0);
+ wire_w_lg_w_rf_sink_data_range302w695w(0) <= NOT wire_w_rf_sink_data_range302w(0);
+ wire_w_lg_w_rf_sink_data_range305w670w(0) <= NOT wire_w_rf_sink_data_range305w(0);
+ wire_w_lg_w_rf_sink_data_range291w293w(0) <= wire_w_rf_sink_data_range291w(0) OR wire_w_rf_sink_data_range292w(0);
+ cp_ready <= s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout;
+ m0_address <= ( cp_data(49 DOWNTO 36));
+ m0_burstcount <= ( wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_478m_dataout & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_479m_dataout & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_480m_dataout);
+ m0_byteenable <= ( cp_data(35 DOWNTO 32));
+ m0_debugaccess <= cp_data(68);
+ m0_lock <= (wire_w_lg_rf_source_ready62w(0) AND (s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_read_475_dataout OR s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_write_481_dataout));
+ m0_read <= s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_read_475_dataout;
+ m0_write <= s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_write_481_dataout;
+ m0_writedata <= ( cp_data(31 DOWNTO 0));
+ rdata_fifo_sink_ready <= ((rp_ready AND rdata_fifo_sink_valid) AND (NOT (rf_sink_valid AND rf_sink_data(69))));
+ rdata_fifo_src_data <= ( m0_readdata(31 DOWNTO 0));
+ rdata_fifo_src_valid <= m0_readdatavalid;
+ rf_sink_ready <= (s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout AND s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout);
+ rf_source_data <= ( s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout & cp_data(68 DOWNTO 32) & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ rf_source_endofpacket <= cp_endofpacket;
+ rf_source_startofpacket <= cp_startofpacket;
+ rf_source_valid <= (s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout AND (rf_source_ready AND (s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout OR s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout)));
+ rp_data <= ( rf_sink_data(68) & rf_sink_data(64 DOWNTO 62) & rf_sink_data(67 DOWNTO 65) & rf_sink_data(61 DOWNTO 58) & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1015m_dataout & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1016m_dataout & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1017m_dataout & rf_sink_data(54) & wire_w_lg_w_rf_sink_data_range291w293w & rf_sink_data(52 DOWNTO 51) & "0" & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1165m_dataout & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1166m_dataout & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1167m_dataout & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1168m_dataout & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1169m_dataout & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1170m_dataout
+ & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1171m_dataout & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1172m_dataout & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1173m_dataout & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1174m_dataout & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1175m_dataout & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1176m_dataout & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1177m_dataout & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1178m_dataout & rf_sink_data(35 DOWNTO 32) & rdata_fifo_sink_data(31 DOWNTO 0));
+ rp_endofpacket <= (rf_sink_endofpacket AND s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ rp_startofpacket <= (rf_sink_startofpacket AND wire_nl_w329w(0));
+ rp_valid <= (rdata_fifo_sink_valid OR s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout);
+ s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1026_dataout <= (s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout AND s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout);
+ s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1048_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout);
+ s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout <= (s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout AND wire_nl_w329w(0));
+ s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout <= ((NOT rf_sink_data(50)) OR wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1024m_dataout);
+ s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout);
+ s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout <= ((altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q OR altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q) OR altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q);
+ s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout <= (rf_sink_valid AND (rf_sink_data(69) OR rdata_fifo_sink_valid));
+ s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout <= (wire_w_lg_m0_waitrequest598w(0) AND rf_source_ready);
+ s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout <= (cp_valid AND cp_data(50));
+ s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_local_read_467_dataout <= (cp_valid AND cp_data(53));
+ s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_local_write_466_dataout <= (cp_valid AND cp_data(52));
+ s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout <= (s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_local_read_467_dataout AND wire_w602w(0));
+ s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout <= (s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_local_read_467_dataout OR s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout);
+ s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_read_475_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout);
+ s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_write_481_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_local_write_466_dataout);
+ s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout <= ((NOT cp_data(51)) AND (cp_endofpacket AND s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_local_write_466_dataout));
+ s_wire_vcc <= '1';
+ wire_w_cp_data_range60w(0) <= cp_data(54);
+ wire_w_rf_sink_data_range697w(0) <= rf_sink_data(36);
+ wire_w_rf_sink_data_range694w(0) <= rf_sink_data(37);
+ wire_w_rf_sink_data_range692w(0) <= rf_sink_data(38);
+ wire_w_rf_sink_data_range690w(0) <= rf_sink_data(39);
+ wire_w_rf_sink_data_range688w(0) <= rf_sink_data(40);
+ wire_w_rf_sink_data_range686w(0) <= rf_sink_data(41);
+ wire_w_rf_sink_data_range684w(0) <= rf_sink_data(42);
+ wire_w_rf_sink_data_range682w(0) <= rf_sink_data(43);
+ wire_w_rf_sink_data_range680w(0) <= rf_sink_data(44);
+ wire_w_rf_sink_data_range678w(0) <= rf_sink_data(45);
+ wire_w_rf_sink_data_range676w(0) <= rf_sink_data(46);
+ wire_w_rf_sink_data_range674w(0) <= rf_sink_data(47);
+ wire_w_rf_sink_data_range672w(0) <= rf_sink_data(48);
+ wire_w_rf_sink_data_range669w(0) <= rf_sink_data(49);
+ wire_w_rf_sink_data_range291w(0) <= rf_sink_data(50);
+ wire_w_rf_sink_data_range292w(0) <= rf_sink_data(53);
+ wire_w_rf_sink_data_range300w(0) <= rf_sink_data(58);
+ wire_w_rf_sink_data_range302w(0) <= rf_sink_data(59);
+ wire_w_rf_sink_data_range305w(0) <= rf_sink_data(60);
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q <= '0';
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q <= '0';
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q <= '0';
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q <= '0';
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q <= '0';
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q <= '0';
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q <= '0';
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q <= '0';
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q <= '0';
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q <= '0';
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q <= '0';
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q <= '0';
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q <= '0';
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1048_dataout = '1') THEN
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q <= wire_w_lg_w_rf_sink_data_range697w743w(0);
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q <= wire_w_lg_w_rf_sink_data_range676w677w(0);
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q <= wire_w_lg_w_rf_sink_data_range674w675w(0);
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q <= wire_w_lg_w_rf_sink_data_range672w673w(0);
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q <= wire_w_lg_w_rf_sink_data_range669w671w(0);
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q <= wire_w_lg_w_rf_sink_data_range694w696w(0);
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q <= wire_w_lg_w_rf_sink_data_range692w693w(0);
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q <= wire_w_lg_w_rf_sink_data_range690w691w(0);
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q <= wire_w_lg_w_rf_sink_data_range688w689w(0);
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q <= wire_w_lg_w_rf_sink_data_range686w687w(0);
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q <= wire_w_lg_w_rf_sink_data_range684w685w(0);
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q <= wire_w_lg_w_rf_sink_data_range682w683w(0);
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q <= wire_w_lg_w_rf_sink_data_range680w681w(0);
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q <= wire_w_lg_w_rf_sink_data_range678w679w(0);
+ END IF;
+ END IF;
+ END PROCESS;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q <= '0';
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q <= '0';
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q <= '0';
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1026_dataout = '1') THEN
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q <= wire_w667w(0);
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q <= wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1040m_dataout;
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q <= wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1039m_dataout;
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q <= wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout;
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_nl_w620w(0) <= altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q AND wire_nl_w619w(0);
+ wire_nl_w329w(0) <= NOT altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q;
+ wire_nl_w621w(0) <= NOT altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q;
+ wire_nl_w619w(0) <= NOT altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q <= '0';
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q <= '0';
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q <= '0';
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q <= '0';
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q <= '0';
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q <= '0';
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q <= '0';
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q <= '0';
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q <= '0';
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q <= '0';
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q <= '0';
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q <= '0';
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q <= '0';
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout = '1') THEN
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q <= (rf_sink_data(58) AND wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(0));
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(10));
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(11));
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(12));
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(13));
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q <= (rf_sink_data(59) AND wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(1));
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(2));
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(3));
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(4));
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(5));
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(6));
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(7));
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(8));
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(9));
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout <= wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o(3) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout = '1' ELSE wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(3);
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1030m_dataout <= wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o(2) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout = '1' ELSE wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(2);
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout <= wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o(1) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout = '1' ELSE wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(1);
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout <= wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout WHEN altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(3);
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1034m_dataout <= wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1030m_dataout WHEN altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(2);
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1035m_dataout <= wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout WHEN altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(1);
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout <= wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1039m_dataout <= wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1034m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1040m_dataout <= wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1035m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q;
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q;
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q;
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q;
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q;
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q;
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q;
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q;
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q;
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q;
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q;
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q;
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1106m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q;
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1107m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q;
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1024m_dataout <= (s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout AND (wire_nl_w620w(0) AND wire_nl_w621w(0))) WHEN altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE (s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout AND (((NOT rf_sink_data(55)) AND (NOT rf_sink_data(56))) AND rf_sink_data(57)));
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1178m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q OR altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q);
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1168m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q OR altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q);
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1167m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q OR altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q);
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1166m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q OR altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q);
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1165m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q OR altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q);
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1177m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q OR altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q);
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1176m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q OR altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q);
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1175m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q OR altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q);
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1174m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q OR altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q);
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1173m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q OR altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q);
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1172m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q OR altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q);
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1171m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q OR altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q);
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1170m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q OR altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q);
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1169m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q OR altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q);
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1017m_dataout <= rf_sink_data(55) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q;
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1016m_dataout <= rf_sink_data(56) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q;
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1015m_dataout <= rf_sink_data(57) WHEN s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q;
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_480m_dataout <= cp_data(55) AND NOT(s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout);
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_479m_dataout <= cp_data(56) AND NOT(s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout);
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_478m_dataout <= cp_data(57) OR s_wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout;
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_a <= ( altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q & altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q & altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q & "1");
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_a,
+ b => wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o
+ );
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_a <= ( rf_sink_data(57 DOWNTO 55) & "1");
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_a,
+ b => wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o
+ );
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_a <= ( wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout
+ & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1106m_dataout & wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1107m_dataout);
+ wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0");
+ altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 14,
+ width_b => 14,
+ width_o => 14
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_a,
+ b => wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o
+ );
+
+ END RTL; --altera_merlin_slave_agent_0007
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0008.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0008.vho
new file mode 100644
index 0000000000000000000000000000000000000000..1660031ec68a1f5e447c8ff84f527fc63c9ee113
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0008.vho
@@ -0,0 +1,505 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+ LIBRARY sgate;
+ USE sgate.sgate_pack.all;
+
+--synthesis_resources = lut 32 mux21 44 oper_add 3
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_slave_agent_0008 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ cp_channel : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ cp_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ cp_endofpacket : IN STD_LOGIC;
+ cp_ready : OUT STD_LOGIC;
+ cp_startofpacket : IN STD_LOGIC;
+ cp_valid : IN STD_LOGIC;
+ m0_address : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
+ m0_burstcount : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ m0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+ m0_debugaccess : OUT STD_LOGIC;
+ m0_lock : OUT STD_LOGIC;
+ m0_read : OUT STD_LOGIC;
+ m0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ m0_readdatavalid : IN STD_LOGIC;
+ m0_waitrequest : IN STD_LOGIC;
+ m0_write : OUT STD_LOGIC;
+ m0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_ready : OUT STD_LOGIC;
+ rdata_fifo_sink_valid : IN STD_LOGIC;
+ rdata_fifo_src_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_src_ready : IN STD_LOGIC;
+ rdata_fifo_src_valid : OUT STD_LOGIC;
+ reset : IN STD_LOGIC;
+ rf_sink_data : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
+ rf_sink_endofpacket : IN STD_LOGIC;
+ rf_sink_ready : OUT STD_LOGIC;
+ rf_sink_startofpacket : IN STD_LOGIC;
+ rf_sink_valid : IN STD_LOGIC;
+ rf_source_data : OUT STD_LOGIC_VECTOR (69 DOWNTO 0);
+ rf_source_endofpacket : OUT STD_LOGIC;
+ rf_source_ready : IN STD_LOGIC;
+ rf_source_startofpacket : OUT STD_LOGIC;
+ rf_source_valid : OUT STD_LOGIC;
+ rp_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ rp_endofpacket : OUT STD_LOGIC;
+ rp_ready : IN STD_LOGIC;
+ rp_startofpacket : OUT STD_LOGIC;
+ rp_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_slave_agent_0008;
+
+ ARCHITECTURE RTL OF altera_merlin_slave_agent_0008 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q : STD_LOGIC := '0';
+ SIGNAL wire_nl_w620w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w329w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w619w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q : STD_LOGIC := '0';
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1030m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1034m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1035m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1039m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1040m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1106m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1107m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1024m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1178m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1168m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1167m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1166m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1165m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1177m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1176m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1175m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1174m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1173m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1172m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1171m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1170m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1169m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1017m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1016m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1015m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_480m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_479m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_478m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_gnd : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_a : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_b : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_w_lg_cp_valid61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_rf_source_ready62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range697w743w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range694w696w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range692w693w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range690w691w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range688w689w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range686w687w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range684w685w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range682w683w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range680w681w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range678w679w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range676w677w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range674w675w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range672w673w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range669w671w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_m0_waitrequest598w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_reset613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w667w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w602w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range300w742w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range302w695w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range305w670w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range291w293w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1026_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1048_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_local_read_467_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_local_write_466_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_read_475_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_write_481_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ SIGNAL wire_w_cp_data_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range697w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range694w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range692w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range690w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range688w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range686w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range684w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range682w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range678w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range676w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range674w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range672w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range669w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range292w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range300w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range302w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range305w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+ wire_gnd <= '0';
+ wire_w_lg_cp_valid61w(0) <= cp_valid AND wire_w_cp_data_range60w(0);
+ wire_w_lg_rf_source_ready62w(0) <= rf_source_ready AND wire_w_lg_cp_valid61w(0);
+ wire_w_lg_w_rf_sink_data_range697w743w(0) <= wire_w_rf_sink_data_range697w(0) AND wire_w_lg_w_rf_sink_data_range300w742w(0);
+ wire_w_lg_w_rf_sink_data_range694w696w(0) <= wire_w_rf_sink_data_range694w(0) AND wire_w_lg_w_rf_sink_data_range302w695w(0);
+ wire_w_lg_w_rf_sink_data_range692w693w(0) <= wire_w_rf_sink_data_range692w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range690w691w(0) <= wire_w_rf_sink_data_range690w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range688w689w(0) <= wire_w_rf_sink_data_range688w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range686w687w(0) <= wire_w_rf_sink_data_range686w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range684w685w(0) <= wire_w_rf_sink_data_range684w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range682w683w(0) <= wire_w_rf_sink_data_range682w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range680w681w(0) <= wire_w_rf_sink_data_range680w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range678w679w(0) <= wire_w_rf_sink_data_range678w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range676w677w(0) <= wire_w_rf_sink_data_range676w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range674w675w(0) <= wire_w_rf_sink_data_range674w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range672w673w(0) <= wire_w_rf_sink_data_range672w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range669w671w(0) <= wire_w_rf_sink_data_range669w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_m0_waitrequest598w(0) <= NOT m0_waitrequest;
+ wire_w_lg_reset613w(0) <= NOT reset;
+ wire_w667w(0) <= NOT s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout;
+ wire_w602w(0) <= NOT s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout;
+ wire_w_lg_w_rf_sink_data_range300w742w(0) <= NOT wire_w_rf_sink_data_range300w(0);
+ wire_w_lg_w_rf_sink_data_range302w695w(0) <= NOT wire_w_rf_sink_data_range302w(0);
+ wire_w_lg_w_rf_sink_data_range305w670w(0) <= NOT wire_w_rf_sink_data_range305w(0);
+ wire_w_lg_w_rf_sink_data_range291w293w(0) <= wire_w_rf_sink_data_range291w(0) OR wire_w_rf_sink_data_range292w(0);
+ cp_ready <= s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout;
+ m0_address <= ( cp_data(49 DOWNTO 36));
+ m0_burstcount <= ( wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_478m_dataout & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_479m_dataout & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_480m_dataout);
+ m0_byteenable <= ( cp_data(35 DOWNTO 32));
+ m0_debugaccess <= cp_data(68);
+ m0_lock <= (wire_w_lg_rf_source_ready62w(0) AND (s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_read_475_dataout OR s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_write_481_dataout));
+ m0_read <= s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_read_475_dataout;
+ m0_write <= s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_write_481_dataout;
+ m0_writedata <= ( cp_data(31 DOWNTO 0));
+ rdata_fifo_sink_ready <= ((rp_ready AND rdata_fifo_sink_valid) AND (NOT (rf_sink_valid AND rf_sink_data(69))));
+ rdata_fifo_src_data <= ( m0_readdata(31 DOWNTO 0));
+ rdata_fifo_src_valid <= m0_readdatavalid;
+ rf_sink_ready <= (s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout AND s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout);
+ rf_source_data <= ( s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout & cp_data(68 DOWNTO 32) & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ rf_source_endofpacket <= cp_endofpacket;
+ rf_source_startofpacket <= cp_startofpacket;
+ rf_source_valid <= (s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout AND (rf_source_ready AND (s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout OR s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout)));
+ rp_data <= ( rf_sink_data(68) & rf_sink_data(64 DOWNTO 62) & rf_sink_data(67 DOWNTO 65) & rf_sink_data(61 DOWNTO 58) & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1015m_dataout & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1016m_dataout & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1017m_dataout & rf_sink_data(54) & wire_w_lg_w_rf_sink_data_range291w293w & rf_sink_data(52 DOWNTO 51) & "0" & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1165m_dataout & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1166m_dataout & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1167m_dataout & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1168m_dataout & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1169m_dataout & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1170m_dataout
+ & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1171m_dataout & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1172m_dataout & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1173m_dataout & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1174m_dataout & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1175m_dataout & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1176m_dataout & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1177m_dataout & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1178m_dataout & rf_sink_data(35 DOWNTO 32) & rdata_fifo_sink_data(31 DOWNTO 0));
+ rp_endofpacket <= (rf_sink_endofpacket AND s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ rp_startofpacket <= (rf_sink_startofpacket AND wire_nl_w329w(0));
+ rp_valid <= (rdata_fifo_sink_valid OR s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout);
+ s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1026_dataout <= (s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout AND s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout);
+ s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1048_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout);
+ s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout <= (s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout AND wire_nl_w329w(0));
+ s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout <= ((NOT rf_sink_data(50)) OR wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1024m_dataout);
+ s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout);
+ s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout <= ((altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q OR altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q) OR altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q);
+ s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout <= (rf_sink_valid AND (rf_sink_data(69) OR rdata_fifo_sink_valid));
+ s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout <= (wire_w_lg_m0_waitrequest598w(0) AND rf_source_ready);
+ s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout <= (cp_valid AND cp_data(50));
+ s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_local_read_467_dataout <= (cp_valid AND cp_data(53));
+ s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_local_write_466_dataout <= (cp_valid AND cp_data(52));
+ s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout <= (s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_local_read_467_dataout AND wire_w602w(0));
+ s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout <= (s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_local_read_467_dataout OR s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout);
+ s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_read_475_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout);
+ s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_write_481_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_local_write_466_dataout);
+ s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout <= ((NOT cp_data(51)) AND (cp_endofpacket AND s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_local_write_466_dataout));
+ s_wire_vcc <= '1';
+ wire_w_cp_data_range60w(0) <= cp_data(54);
+ wire_w_rf_sink_data_range697w(0) <= rf_sink_data(36);
+ wire_w_rf_sink_data_range694w(0) <= rf_sink_data(37);
+ wire_w_rf_sink_data_range692w(0) <= rf_sink_data(38);
+ wire_w_rf_sink_data_range690w(0) <= rf_sink_data(39);
+ wire_w_rf_sink_data_range688w(0) <= rf_sink_data(40);
+ wire_w_rf_sink_data_range686w(0) <= rf_sink_data(41);
+ wire_w_rf_sink_data_range684w(0) <= rf_sink_data(42);
+ wire_w_rf_sink_data_range682w(0) <= rf_sink_data(43);
+ wire_w_rf_sink_data_range680w(0) <= rf_sink_data(44);
+ wire_w_rf_sink_data_range678w(0) <= rf_sink_data(45);
+ wire_w_rf_sink_data_range676w(0) <= rf_sink_data(46);
+ wire_w_rf_sink_data_range674w(0) <= rf_sink_data(47);
+ wire_w_rf_sink_data_range672w(0) <= rf_sink_data(48);
+ wire_w_rf_sink_data_range669w(0) <= rf_sink_data(49);
+ wire_w_rf_sink_data_range291w(0) <= rf_sink_data(50);
+ wire_w_rf_sink_data_range292w(0) <= rf_sink_data(53);
+ wire_w_rf_sink_data_range300w(0) <= rf_sink_data(58);
+ wire_w_rf_sink_data_range302w(0) <= rf_sink_data(59);
+ wire_w_rf_sink_data_range305w(0) <= rf_sink_data(60);
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q <= '0';
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q <= '0';
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q <= '0';
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q <= '0';
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q <= '0';
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q <= '0';
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q <= '0';
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q <= '0';
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q <= '0';
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q <= '0';
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q <= '0';
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q <= '0';
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q <= '0';
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1048_dataout = '1') THEN
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q <= wire_w_lg_w_rf_sink_data_range697w743w(0);
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q <= wire_w_lg_w_rf_sink_data_range676w677w(0);
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q <= wire_w_lg_w_rf_sink_data_range674w675w(0);
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q <= wire_w_lg_w_rf_sink_data_range672w673w(0);
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q <= wire_w_lg_w_rf_sink_data_range669w671w(0);
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q <= wire_w_lg_w_rf_sink_data_range694w696w(0);
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q <= wire_w_lg_w_rf_sink_data_range692w693w(0);
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q <= wire_w_lg_w_rf_sink_data_range690w691w(0);
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q <= wire_w_lg_w_rf_sink_data_range688w689w(0);
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q <= wire_w_lg_w_rf_sink_data_range686w687w(0);
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q <= wire_w_lg_w_rf_sink_data_range684w685w(0);
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q <= wire_w_lg_w_rf_sink_data_range682w683w(0);
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q <= wire_w_lg_w_rf_sink_data_range680w681w(0);
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q <= wire_w_lg_w_rf_sink_data_range678w679w(0);
+ END IF;
+ END IF;
+ END PROCESS;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q <= '0';
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q <= '0';
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q <= '0';
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1026_dataout = '1') THEN
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q <= wire_w667w(0);
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q <= wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1040m_dataout;
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q <= wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1039m_dataout;
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q <= wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout;
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_nl_w620w(0) <= altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q AND wire_nl_w619w(0);
+ wire_nl_w329w(0) <= NOT altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q;
+ wire_nl_w621w(0) <= NOT altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q;
+ wire_nl_w619w(0) <= NOT altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q <= '0';
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q <= '0';
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q <= '0';
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q <= '0';
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q <= '0';
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q <= '0';
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q <= '0';
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q <= '0';
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q <= '0';
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q <= '0';
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q <= '0';
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q <= '0';
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q <= '0';
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout = '1') THEN
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q <= (rf_sink_data(58) AND wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(0));
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(10));
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(11));
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(12));
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(13));
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q <= (rf_sink_data(59) AND wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(1));
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(2));
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(3));
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(4));
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(5));
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(6));
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(7));
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(8));
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(9));
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout <= wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o(3) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout = '1' ELSE wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(3);
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1030m_dataout <= wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o(2) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout = '1' ELSE wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(2);
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout <= wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o(1) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout = '1' ELSE wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(1);
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout <= wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout WHEN altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(3);
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1034m_dataout <= wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1030m_dataout WHEN altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(2);
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1035m_dataout <= wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout WHEN altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(1);
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout <= wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1039m_dataout <= wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1034m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1040m_dataout <= wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1035m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q;
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q;
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q;
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q;
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q;
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q;
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q;
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q;
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q;
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q;
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q;
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q;
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1106m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q;
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1107m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q;
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1024m_dataout <= (s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout AND (wire_nl_w620w(0) AND wire_nl_w621w(0))) WHEN altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE (s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout AND (((NOT rf_sink_data(55)) AND (NOT rf_sink_data(56))) AND rf_sink_data(57)));
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1178m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q OR altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q);
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1168m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q OR altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q);
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1167m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q OR altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q);
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1166m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q OR altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q);
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1165m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q OR altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q);
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1177m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q OR altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q);
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1176m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q OR altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q);
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1175m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q OR altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q);
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1174m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q OR altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q);
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1173m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q OR altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q);
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1172m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q OR altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q);
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1171m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q OR altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q);
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1170m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q OR altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q);
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1169m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q OR altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q);
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1017m_dataout <= rf_sink_data(55) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q;
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1016m_dataout <= rf_sink_data(56) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q;
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1015m_dataout <= rf_sink_data(57) WHEN s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q;
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_480m_dataout <= cp_data(55) AND NOT(s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout);
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_479m_dataout <= cp_data(56) AND NOT(s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout);
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_478m_dataout <= cp_data(57) OR s_wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout;
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_a <= ( altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q & altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q & altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q & "1");
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_a,
+ b => wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o
+ );
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_a <= ( rf_sink_data(57 DOWNTO 55) & "1");
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_a,
+ b => wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o
+ );
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_a <= ( wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout
+ & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1106m_dataout & wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1107m_dataout);
+ wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0");
+ altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 14,
+ width_b => 14,
+ width_o => 14
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_a,
+ b => wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o
+ );
+
+ END RTL; --altera_merlin_slave_agent_0008
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0009.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0009.vho
new file mode 100644
index 0000000000000000000000000000000000000000..c4e54157942fcacb3e71fd53e4e263d256bd65dc
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0009.vho
@@ -0,0 +1,505 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+ LIBRARY sgate;
+ USE sgate.sgate_pack.all;
+
+--synthesis_resources = lut 32 mux21 44 oper_add 3
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_slave_agent_0009 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ cp_channel : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ cp_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ cp_endofpacket : IN STD_LOGIC;
+ cp_ready : OUT STD_LOGIC;
+ cp_startofpacket : IN STD_LOGIC;
+ cp_valid : IN STD_LOGIC;
+ m0_address : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
+ m0_burstcount : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ m0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+ m0_debugaccess : OUT STD_LOGIC;
+ m0_lock : OUT STD_LOGIC;
+ m0_read : OUT STD_LOGIC;
+ m0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ m0_readdatavalid : IN STD_LOGIC;
+ m0_waitrequest : IN STD_LOGIC;
+ m0_write : OUT STD_LOGIC;
+ m0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_ready : OUT STD_LOGIC;
+ rdata_fifo_sink_valid : IN STD_LOGIC;
+ rdata_fifo_src_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_src_ready : IN STD_LOGIC;
+ rdata_fifo_src_valid : OUT STD_LOGIC;
+ reset : IN STD_LOGIC;
+ rf_sink_data : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
+ rf_sink_endofpacket : IN STD_LOGIC;
+ rf_sink_ready : OUT STD_LOGIC;
+ rf_sink_startofpacket : IN STD_LOGIC;
+ rf_sink_valid : IN STD_LOGIC;
+ rf_source_data : OUT STD_LOGIC_VECTOR (69 DOWNTO 0);
+ rf_source_endofpacket : OUT STD_LOGIC;
+ rf_source_ready : IN STD_LOGIC;
+ rf_source_startofpacket : OUT STD_LOGIC;
+ rf_source_valid : OUT STD_LOGIC;
+ rp_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ rp_endofpacket : OUT STD_LOGIC;
+ rp_ready : IN STD_LOGIC;
+ rp_startofpacket : OUT STD_LOGIC;
+ rp_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_slave_agent_0009;
+
+ ARCHITECTURE RTL OF altera_merlin_slave_agent_0009 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q : STD_LOGIC := '0';
+ SIGNAL wire_nl_w620w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w329w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w619w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q : STD_LOGIC := '0';
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1030m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1034m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1035m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1039m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1040m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1106m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1107m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1024m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1178m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1168m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1167m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1166m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1165m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1177m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1176m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1175m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1174m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1173m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1172m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1171m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1170m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1169m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1017m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1016m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1015m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount_0_480m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount_1_479m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount_2_478m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_gnd : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_a : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_b : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_w_lg_cp_valid61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_rf_source_ready62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range697w743w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range694w696w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range692w693w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range690w691w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range688w689w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range686w687w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range684w685w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range682w683w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range680w681w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range678w679w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range676w677w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range674w675w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range672w673w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range669w671w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_m0_waitrequest598w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_reset613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w667w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w602w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range300w742w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range302w695w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range305w670w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range291w293w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1026_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1048_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_comb_498_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_local_read_467_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_local_write_466_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read_474_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read_475_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write_481_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ SIGNAL wire_w_cp_data_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range697w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range694w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range692w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range690w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range688w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range686w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range684w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range682w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range678w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range676w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range674w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range672w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range669w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range292w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range300w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range302w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range305w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+ wire_gnd <= '0';
+ wire_w_lg_cp_valid61w(0) <= cp_valid AND wire_w_cp_data_range60w(0);
+ wire_w_lg_rf_source_ready62w(0) <= rf_source_ready AND wire_w_lg_cp_valid61w(0);
+ wire_w_lg_w_rf_sink_data_range697w743w(0) <= wire_w_rf_sink_data_range697w(0) AND wire_w_lg_w_rf_sink_data_range300w742w(0);
+ wire_w_lg_w_rf_sink_data_range694w696w(0) <= wire_w_rf_sink_data_range694w(0) AND wire_w_lg_w_rf_sink_data_range302w695w(0);
+ wire_w_lg_w_rf_sink_data_range692w693w(0) <= wire_w_rf_sink_data_range692w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range690w691w(0) <= wire_w_rf_sink_data_range690w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range688w689w(0) <= wire_w_rf_sink_data_range688w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range686w687w(0) <= wire_w_rf_sink_data_range686w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range684w685w(0) <= wire_w_rf_sink_data_range684w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range682w683w(0) <= wire_w_rf_sink_data_range682w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range680w681w(0) <= wire_w_rf_sink_data_range680w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range678w679w(0) <= wire_w_rf_sink_data_range678w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range676w677w(0) <= wire_w_rf_sink_data_range676w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range674w675w(0) <= wire_w_rf_sink_data_range674w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range672w673w(0) <= wire_w_rf_sink_data_range672w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range669w671w(0) <= wire_w_rf_sink_data_range669w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_m0_waitrequest598w(0) <= NOT m0_waitrequest;
+ wire_w_lg_reset613w(0) <= NOT reset;
+ wire_w667w(0) <= NOT s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout;
+ wire_w602w(0) <= NOT s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout;
+ wire_w_lg_w_rf_sink_data_range300w742w(0) <= NOT wire_w_rf_sink_data_range300w(0);
+ wire_w_lg_w_rf_sink_data_range302w695w(0) <= NOT wire_w_rf_sink_data_range302w(0);
+ wire_w_lg_w_rf_sink_data_range305w670w(0) <= NOT wire_w_rf_sink_data_range305w(0);
+ wire_w_lg_w_rf_sink_data_range291w293w(0) <= wire_w_rf_sink_data_range291w(0) OR wire_w_rf_sink_data_range292w(0);
+ cp_ready <= s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout;
+ m0_address <= ( cp_data(49 DOWNTO 36));
+ m0_burstcount <= ( wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount_2_478m_dataout & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount_1_479m_dataout & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount_0_480m_dataout);
+ m0_byteenable <= ( cp_data(35 DOWNTO 32));
+ m0_debugaccess <= cp_data(68);
+ m0_lock <= (wire_w_lg_rf_source_ready62w(0) AND (s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read_475_dataout OR s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write_481_dataout));
+ m0_read <= s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read_475_dataout;
+ m0_write <= s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write_481_dataout;
+ m0_writedata <= ( cp_data(31 DOWNTO 0));
+ rdata_fifo_sink_ready <= ((rp_ready AND rdata_fifo_sink_valid) AND (NOT (rf_sink_valid AND rf_sink_data(69))));
+ rdata_fifo_src_data <= ( m0_readdata(31 DOWNTO 0));
+ rdata_fifo_src_valid <= m0_readdatavalid;
+ rf_sink_ready <= (s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout AND s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout);
+ rf_source_data <= ( s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout & cp_data(68 DOWNTO 32) & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ rf_source_endofpacket <= cp_endofpacket;
+ rf_source_startofpacket <= cp_startofpacket;
+ rf_source_valid <= (s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout AND (rf_source_ready AND (s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout OR s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read_474_dataout)));
+ rp_data <= ( rf_sink_data(68) & rf_sink_data(64 DOWNTO 62) & rf_sink_data(67 DOWNTO 65) & rf_sink_data(61 DOWNTO 58) & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1015m_dataout & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1016m_dataout & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1017m_dataout & rf_sink_data(54) & wire_w_lg_w_rf_sink_data_range291w293w & rf_sink_data(52 DOWNTO 51) & "0" & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1165m_dataout & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1166m_dataout & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1167m_dataout & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1168m_dataout & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1169m_dataout & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1170m_dataout
+ & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1171m_dataout & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1172m_dataout & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1173m_dataout & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1174m_dataout & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1175m_dataout & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1176m_dataout & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1177m_dataout & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1178m_dataout & rf_sink_data(35 DOWNTO 32) & rdata_fifo_sink_data(31 DOWNTO 0));
+ rp_endofpacket <= (rf_sink_endofpacket AND s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ rp_startofpacket <= (rf_sink_startofpacket AND wire_nl_w329w(0));
+ rp_valid <= (rdata_fifo_sink_valid OR s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_comb_498_dataout);
+ s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1026_dataout <= (s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_comb_498_dataout AND s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout);
+ s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1048_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout);
+ s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout <= (s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_comb_498_dataout AND wire_nl_w329w(0));
+ s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout <= ((NOT rf_sink_data(50)) OR wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1024m_dataout);
+ s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_comb_498_dataout);
+ s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout <= ((altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q OR altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q) OR altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q);
+ s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_comb_498_dataout <= (rf_sink_valid AND (rf_sink_data(69) OR rdata_fifo_sink_valid));
+ s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout <= (wire_w_lg_m0_waitrequest598w(0) AND rf_source_ready);
+ s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout <= (cp_valid AND cp_data(50));
+ s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_local_read_467_dataout <= (cp_valid AND cp_data(53));
+ s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_local_write_466_dataout <= (cp_valid AND cp_data(52));
+ s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout <= (s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_local_read_467_dataout AND wire_w602w(0));
+ s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read_474_dataout <= (s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_local_read_467_dataout OR s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout);
+ s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read_475_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read_474_dataout);
+ s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write_481_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_local_write_466_dataout);
+ s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout <= ((NOT cp_data(51)) AND (cp_endofpacket AND s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_local_write_466_dataout));
+ s_wire_vcc <= '1';
+ wire_w_cp_data_range60w(0) <= cp_data(54);
+ wire_w_rf_sink_data_range697w(0) <= rf_sink_data(36);
+ wire_w_rf_sink_data_range694w(0) <= rf_sink_data(37);
+ wire_w_rf_sink_data_range692w(0) <= rf_sink_data(38);
+ wire_w_rf_sink_data_range690w(0) <= rf_sink_data(39);
+ wire_w_rf_sink_data_range688w(0) <= rf_sink_data(40);
+ wire_w_rf_sink_data_range686w(0) <= rf_sink_data(41);
+ wire_w_rf_sink_data_range684w(0) <= rf_sink_data(42);
+ wire_w_rf_sink_data_range682w(0) <= rf_sink_data(43);
+ wire_w_rf_sink_data_range680w(0) <= rf_sink_data(44);
+ wire_w_rf_sink_data_range678w(0) <= rf_sink_data(45);
+ wire_w_rf_sink_data_range676w(0) <= rf_sink_data(46);
+ wire_w_rf_sink_data_range674w(0) <= rf_sink_data(47);
+ wire_w_rf_sink_data_range672w(0) <= rf_sink_data(48);
+ wire_w_rf_sink_data_range669w(0) <= rf_sink_data(49);
+ wire_w_rf_sink_data_range291w(0) <= rf_sink_data(50);
+ wire_w_rf_sink_data_range292w(0) <= rf_sink_data(53);
+ wire_w_rf_sink_data_range300w(0) <= rf_sink_data(58);
+ wire_w_rf_sink_data_range302w(0) <= rf_sink_data(59);
+ wire_w_rf_sink_data_range305w(0) <= rf_sink_data(60);
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q <= '0';
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q <= '0';
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q <= '0';
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q <= '0';
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q <= '0';
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q <= '0';
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q <= '0';
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q <= '0';
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q <= '0';
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q <= '0';
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q <= '0';
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q <= '0';
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q <= '0';
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1048_dataout = '1') THEN
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q <= wire_w_lg_w_rf_sink_data_range697w743w(0);
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q <= wire_w_lg_w_rf_sink_data_range676w677w(0);
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q <= wire_w_lg_w_rf_sink_data_range674w675w(0);
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q <= wire_w_lg_w_rf_sink_data_range672w673w(0);
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q <= wire_w_lg_w_rf_sink_data_range669w671w(0);
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q <= wire_w_lg_w_rf_sink_data_range694w696w(0);
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q <= wire_w_lg_w_rf_sink_data_range692w693w(0);
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q <= wire_w_lg_w_rf_sink_data_range690w691w(0);
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q <= wire_w_lg_w_rf_sink_data_range688w689w(0);
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q <= wire_w_lg_w_rf_sink_data_range686w687w(0);
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q <= wire_w_lg_w_rf_sink_data_range684w685w(0);
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q <= wire_w_lg_w_rf_sink_data_range682w683w(0);
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q <= wire_w_lg_w_rf_sink_data_range680w681w(0);
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q <= wire_w_lg_w_rf_sink_data_range678w679w(0);
+ END IF;
+ END IF;
+ END PROCESS;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q <= '0';
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q <= '0';
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q <= '0';
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1026_dataout = '1') THEN
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q <= wire_w667w(0);
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q <= wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1040m_dataout;
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q <= wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1039m_dataout;
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q <= wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout;
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_nl_w620w(0) <= altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q AND wire_nl_w619w(0);
+ wire_nl_w329w(0) <= NOT altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q;
+ wire_nl_w621w(0) <= NOT altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q;
+ wire_nl_w619w(0) <= NOT altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q <= '0';
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q <= '0';
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q <= '0';
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q <= '0';
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q <= '0';
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q <= '0';
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q <= '0';
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q <= '0';
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q <= '0';
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q <= '0';
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q <= '0';
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q <= '0';
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q <= '0';
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout = '1') THEN
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q <= (rf_sink_data(58) AND wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(0));
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(10));
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(11));
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(12));
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(13));
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q <= (rf_sink_data(59) AND wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(1));
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(2));
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(3));
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(4));
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(5));
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(6));
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(7));
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(8));
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(9));
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout <= wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o(3) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout = '1' ELSE wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(3);
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1030m_dataout <= wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o(2) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout = '1' ELSE wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(2);
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout <= wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o(1) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout = '1' ELSE wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(1);
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout <= wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout WHEN altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(3);
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1034m_dataout <= wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1030m_dataout WHEN altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(2);
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1035m_dataout <= wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout WHEN altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(1);
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout <= wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1039m_dataout <= wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1034m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1040m_dataout <= wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1035m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q;
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q;
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q;
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q;
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q;
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q;
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q;
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q;
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q;
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q;
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q;
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q;
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1106m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q;
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1107m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q;
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1024m_dataout <= (s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_comb_498_dataout AND (wire_nl_w620w(0) AND wire_nl_w621w(0))) WHEN altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE (s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_comb_498_dataout AND (((NOT rf_sink_data(55)) AND (NOT rf_sink_data(56))) AND rf_sink_data(57)));
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1178m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q OR altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q);
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1168m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q OR altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q);
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1167m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q OR altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q);
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1166m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q OR altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q);
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1165m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q OR altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q);
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1177m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q OR altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q);
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1176m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q OR altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q);
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1175m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q OR altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q);
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1174m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q OR altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q);
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1173m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q OR altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q);
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1172m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q OR altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q);
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1171m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q OR altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q);
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1170m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q OR altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q);
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1169m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q OR altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q);
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1017m_dataout <= rf_sink_data(55) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q;
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1016m_dataout <= rf_sink_data(56) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q;
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1015m_dataout <= rf_sink_data(57) WHEN s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q;
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount_0_480m_dataout <= cp_data(55) AND NOT(s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout);
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount_1_479m_dataout <= cp_data(56) AND NOT(s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout);
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount_2_478m_dataout <= cp_data(57) OR s_wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout;
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_a <= ( altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q & altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q & altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q & "1");
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_a,
+ b => wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o
+ );
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_a <= ( rf_sink_data(57 DOWNTO 55) & "1");
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_a,
+ b => wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o
+ );
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_a <= ( wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout
+ & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1106m_dataout & wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1107m_dataout);
+ wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0");
+ altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 14,
+ width_b => 14,
+ width_o => 14
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_a,
+ b => wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o
+ );
+
+ END RTL; --altera_merlin_slave_agent_0009
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0010.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0010.vho
new file mode 100644
index 0000000000000000000000000000000000000000..6a92ec8186e5437146aeabaf15b95f23cb513919
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0010.vho
@@ -0,0 +1,505 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+ LIBRARY sgate;
+ USE sgate.sgate_pack.all;
+
+--synthesis_resources = lut 32 mux21 44 oper_add 3
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_slave_agent_0010 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ cp_channel : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ cp_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ cp_endofpacket : IN STD_LOGIC;
+ cp_ready : OUT STD_LOGIC;
+ cp_startofpacket : IN STD_LOGIC;
+ cp_valid : IN STD_LOGIC;
+ m0_address : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
+ m0_burstcount : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ m0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+ m0_debugaccess : OUT STD_LOGIC;
+ m0_lock : OUT STD_LOGIC;
+ m0_read : OUT STD_LOGIC;
+ m0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ m0_readdatavalid : IN STD_LOGIC;
+ m0_waitrequest : IN STD_LOGIC;
+ m0_write : OUT STD_LOGIC;
+ m0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_ready : OUT STD_LOGIC;
+ rdata_fifo_sink_valid : IN STD_LOGIC;
+ rdata_fifo_src_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_src_ready : IN STD_LOGIC;
+ rdata_fifo_src_valid : OUT STD_LOGIC;
+ reset : IN STD_LOGIC;
+ rf_sink_data : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
+ rf_sink_endofpacket : IN STD_LOGIC;
+ rf_sink_ready : OUT STD_LOGIC;
+ rf_sink_startofpacket : IN STD_LOGIC;
+ rf_sink_valid : IN STD_LOGIC;
+ rf_source_data : OUT STD_LOGIC_VECTOR (69 DOWNTO 0);
+ rf_source_endofpacket : OUT STD_LOGIC;
+ rf_source_ready : IN STD_LOGIC;
+ rf_source_startofpacket : OUT STD_LOGIC;
+ rf_source_valid : OUT STD_LOGIC;
+ rp_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ rp_endofpacket : OUT STD_LOGIC;
+ rp_ready : IN STD_LOGIC;
+ rp_startofpacket : OUT STD_LOGIC;
+ rp_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_slave_agent_0010;
+
+ ARCHITECTURE RTL OF altera_merlin_slave_agent_0010 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q : STD_LOGIC := '0';
+ SIGNAL wire_nl_w620w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w329w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w619w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q : STD_LOGIC := '0';
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1030m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1034m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1035m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1039m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1040m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1106m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1107m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1024m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1178m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1168m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1167m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1166m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1165m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1177m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1176m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1175m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1174m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1173m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1172m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1171m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1170m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1169m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1017m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1016m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1015m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_480m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_479m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_478m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_gnd : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_a : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_b : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_w_lg_cp_valid61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_rf_source_ready62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range697w743w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range694w696w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range692w693w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range690w691w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range688w689w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range686w687w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range684w685w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range682w683w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range680w681w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range678w679w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range676w677w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range674w675w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range672w673w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range669w671w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_m0_waitrequest598w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_reset613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w667w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w602w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range300w742w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range302w695w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range305w670w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range291w293w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1026_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1048_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_local_read_467_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_local_write_466_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_read_475_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_write_481_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ SIGNAL wire_w_cp_data_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range697w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range694w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range692w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range690w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range688w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range686w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range684w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range682w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range678w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range676w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range674w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range672w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range669w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range292w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range300w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range302w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range305w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+ wire_gnd <= '0';
+ wire_w_lg_cp_valid61w(0) <= cp_valid AND wire_w_cp_data_range60w(0);
+ wire_w_lg_rf_source_ready62w(0) <= rf_source_ready AND wire_w_lg_cp_valid61w(0);
+ wire_w_lg_w_rf_sink_data_range697w743w(0) <= wire_w_rf_sink_data_range697w(0) AND wire_w_lg_w_rf_sink_data_range300w742w(0);
+ wire_w_lg_w_rf_sink_data_range694w696w(0) <= wire_w_rf_sink_data_range694w(0) AND wire_w_lg_w_rf_sink_data_range302w695w(0);
+ wire_w_lg_w_rf_sink_data_range692w693w(0) <= wire_w_rf_sink_data_range692w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range690w691w(0) <= wire_w_rf_sink_data_range690w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range688w689w(0) <= wire_w_rf_sink_data_range688w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range686w687w(0) <= wire_w_rf_sink_data_range686w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range684w685w(0) <= wire_w_rf_sink_data_range684w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range682w683w(0) <= wire_w_rf_sink_data_range682w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range680w681w(0) <= wire_w_rf_sink_data_range680w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range678w679w(0) <= wire_w_rf_sink_data_range678w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range676w677w(0) <= wire_w_rf_sink_data_range676w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range674w675w(0) <= wire_w_rf_sink_data_range674w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range672w673w(0) <= wire_w_rf_sink_data_range672w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range669w671w(0) <= wire_w_rf_sink_data_range669w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_m0_waitrequest598w(0) <= NOT m0_waitrequest;
+ wire_w_lg_reset613w(0) <= NOT reset;
+ wire_w667w(0) <= NOT s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout;
+ wire_w602w(0) <= NOT s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout;
+ wire_w_lg_w_rf_sink_data_range300w742w(0) <= NOT wire_w_rf_sink_data_range300w(0);
+ wire_w_lg_w_rf_sink_data_range302w695w(0) <= NOT wire_w_rf_sink_data_range302w(0);
+ wire_w_lg_w_rf_sink_data_range305w670w(0) <= NOT wire_w_rf_sink_data_range305w(0);
+ wire_w_lg_w_rf_sink_data_range291w293w(0) <= wire_w_rf_sink_data_range291w(0) OR wire_w_rf_sink_data_range292w(0);
+ cp_ready <= s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout;
+ m0_address <= ( cp_data(49 DOWNTO 36));
+ m0_burstcount <= ( wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_478m_dataout & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_479m_dataout & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_480m_dataout);
+ m0_byteenable <= ( cp_data(35 DOWNTO 32));
+ m0_debugaccess <= cp_data(68);
+ m0_lock <= (wire_w_lg_rf_source_ready62w(0) AND (s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_read_475_dataout OR s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_write_481_dataout));
+ m0_read <= s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_read_475_dataout;
+ m0_write <= s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_write_481_dataout;
+ m0_writedata <= ( cp_data(31 DOWNTO 0));
+ rdata_fifo_sink_ready <= ((rp_ready AND rdata_fifo_sink_valid) AND (NOT (rf_sink_valid AND rf_sink_data(69))));
+ rdata_fifo_src_data <= ( m0_readdata(31 DOWNTO 0));
+ rdata_fifo_src_valid <= m0_readdatavalid;
+ rf_sink_ready <= (s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout AND s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout);
+ rf_source_data <= ( s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout & cp_data(68 DOWNTO 32) & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ rf_source_endofpacket <= cp_endofpacket;
+ rf_source_startofpacket <= cp_startofpacket;
+ rf_source_valid <= (s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout AND (rf_source_ready AND (s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout OR s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout)));
+ rp_data <= ( rf_sink_data(68) & rf_sink_data(64 DOWNTO 62) & rf_sink_data(67 DOWNTO 65) & rf_sink_data(61 DOWNTO 58) & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1015m_dataout & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1016m_dataout & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1017m_dataout & rf_sink_data(54) & wire_w_lg_w_rf_sink_data_range291w293w & rf_sink_data(52 DOWNTO 51) & "0" & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1165m_dataout & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1166m_dataout & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1167m_dataout & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1168m_dataout & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1169m_dataout & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1170m_dataout
+ & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1171m_dataout & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1172m_dataout & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1173m_dataout & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1174m_dataout & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1175m_dataout & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1176m_dataout & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1177m_dataout & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1178m_dataout & rf_sink_data(35 DOWNTO 32) & rdata_fifo_sink_data(31 DOWNTO 0));
+ rp_endofpacket <= (rf_sink_endofpacket AND s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ rp_startofpacket <= (rf_sink_startofpacket AND wire_nl_w329w(0));
+ rp_valid <= (rdata_fifo_sink_valid OR s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout);
+ s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1026_dataout <= (s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout AND s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout);
+ s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1048_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout);
+ s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout <= (s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout AND wire_nl_w329w(0));
+ s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout <= ((NOT rf_sink_data(50)) OR wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1024m_dataout);
+ s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout);
+ s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout <= ((altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q OR altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q) OR altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q);
+ s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout <= (rf_sink_valid AND (rf_sink_data(69) OR rdata_fifo_sink_valid));
+ s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_cp_ready_473_dataout <= (wire_w_lg_m0_waitrequest598w(0) AND rf_source_ready);
+ s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout <= (cp_valid AND cp_data(50));
+ s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_local_read_467_dataout <= (cp_valid AND cp_data(53));
+ s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_local_write_466_dataout <= (cp_valid AND cp_data(52));
+ s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout <= (s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_local_read_467_dataout AND wire_w602w(0));
+ s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout <= (s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_local_read_467_dataout OR s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_468_dataout);
+ s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_read_475_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout);
+ s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_write_481_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_local_write_466_dataout);
+ s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_471_dataout <= ((NOT cp_data(51)) AND (cp_endofpacket AND s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_local_write_466_dataout));
+ s_wire_vcc <= '1';
+ wire_w_cp_data_range60w(0) <= cp_data(54);
+ wire_w_rf_sink_data_range697w(0) <= rf_sink_data(36);
+ wire_w_rf_sink_data_range694w(0) <= rf_sink_data(37);
+ wire_w_rf_sink_data_range692w(0) <= rf_sink_data(38);
+ wire_w_rf_sink_data_range690w(0) <= rf_sink_data(39);
+ wire_w_rf_sink_data_range688w(0) <= rf_sink_data(40);
+ wire_w_rf_sink_data_range686w(0) <= rf_sink_data(41);
+ wire_w_rf_sink_data_range684w(0) <= rf_sink_data(42);
+ wire_w_rf_sink_data_range682w(0) <= rf_sink_data(43);
+ wire_w_rf_sink_data_range680w(0) <= rf_sink_data(44);
+ wire_w_rf_sink_data_range678w(0) <= rf_sink_data(45);
+ wire_w_rf_sink_data_range676w(0) <= rf_sink_data(46);
+ wire_w_rf_sink_data_range674w(0) <= rf_sink_data(47);
+ wire_w_rf_sink_data_range672w(0) <= rf_sink_data(48);
+ wire_w_rf_sink_data_range669w(0) <= rf_sink_data(49);
+ wire_w_rf_sink_data_range291w(0) <= rf_sink_data(50);
+ wire_w_rf_sink_data_range292w(0) <= rf_sink_data(53);
+ wire_w_rf_sink_data_range300w(0) <= rf_sink_data(58);
+ wire_w_rf_sink_data_range302w(0) <= rf_sink_data(59);
+ wire_w_rf_sink_data_range305w(0) <= rf_sink_data(60);
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q <= '0';
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q <= '0';
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q <= '0';
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q <= '0';
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q <= '0';
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q <= '0';
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q <= '0';
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q <= '0';
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q <= '0';
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q <= '0';
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q <= '0';
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q <= '0';
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q <= '0';
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1048_dataout = '1') THEN
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q <= wire_w_lg_w_rf_sink_data_range697w743w(0);
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q <= wire_w_lg_w_rf_sink_data_range676w677w(0);
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q <= wire_w_lg_w_rf_sink_data_range674w675w(0);
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q <= wire_w_lg_w_rf_sink_data_range672w673w(0);
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q <= wire_w_lg_w_rf_sink_data_range669w671w(0);
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q <= wire_w_lg_w_rf_sink_data_range694w696w(0);
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q <= wire_w_lg_w_rf_sink_data_range692w693w(0);
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q <= wire_w_lg_w_rf_sink_data_range690w691w(0);
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q <= wire_w_lg_w_rf_sink_data_range688w689w(0);
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q <= wire_w_lg_w_rf_sink_data_range686w687w(0);
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q <= wire_w_lg_w_rf_sink_data_range684w685w(0);
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q <= wire_w_lg_w_rf_sink_data_range682w683w(0);
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q <= wire_w_lg_w_rf_sink_data_range680w681w(0);
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q <= wire_w_lg_w_rf_sink_data_range678w679w(0);
+ END IF;
+ END IF;
+ END PROCESS;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q <= '0';
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q <= '0';
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q <= '0';
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1026_dataout = '1') THEN
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q <= wire_w667w(0);
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q <= wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1040m_dataout;
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q <= wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1039m_dataout;
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q <= wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout;
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_nl_w620w(0) <= altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q AND wire_nl_w619w(0);
+ wire_nl_w329w(0) <= NOT altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q;
+ wire_nl_w621w(0) <= NOT altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q;
+ wire_nl_w619w(0) <= NOT altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q <= '0';
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q <= '0';
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q <= '0';
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q <= '0';
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q <= '0';
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q <= '0';
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q <= '0';
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q <= '0';
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q <= '0';
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q <= '0';
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q <= '0';
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q <= '0';
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q <= '0';
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1182_dataout = '1') THEN
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q <= (rf_sink_data(58) AND wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(0));
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(10));
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(11));
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(12));
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(13));
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q <= (rf_sink_data(59) AND wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(1));
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(2));
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(3));
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(4));
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(5));
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(6));
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(7));
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(8));
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o(9));
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout <= wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o(3) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout = '1' ELSE wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(3);
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1030m_dataout <= wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o(2) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout = '1' ELSE wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(2);
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout <= wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o(1) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1027_dataout = '1' ELSE wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(1);
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout <= wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout WHEN altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(3);
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1034m_dataout <= wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1030m_dataout WHEN altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(2);
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1035m_dataout <= wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout WHEN altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o(1);
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout <= wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1039m_dataout <= wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1034m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1040m_dataout <= wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1035m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1025_dataout);
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q;
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q;
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q;
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q;
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q;
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q;
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q;
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q;
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q;
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q;
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q;
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q;
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1106m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q;
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1107m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q;
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1024m_dataout <= (s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout AND (wire_nl_w620w(0) AND wire_nl_w621w(0))) WHEN altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1045q = '1' ELSE (s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_comb_498_dataout AND (((NOT rf_sink_data(55)) AND (NOT rf_sink_data(56))) AND rf_sink_data(57)));
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1178m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1021q OR altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1137q);
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1168m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1084q OR altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1141q);
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1167m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1083q OR altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1140q);
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1166m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1082q OR altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1139q);
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1165m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1081q OR altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1138q);
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1177m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1093q OR altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1150q);
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1176m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1092q OR altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1149q);
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1175m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1091q OR altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1148q);
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1174m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1090q OR altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1147q);
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1173m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1089q OR altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1146q);
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1172m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1088q OR altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1145q);
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1171m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1087q OR altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1144q);
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1170m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1086q OR altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1143q);
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1169m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE (altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1085q OR altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1142q);
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1017m_dataout <= rf_sink_data(55) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q;
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1016m_dataout <= rf_sink_data(56) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q;
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1015m_dataout <= rf_sink_data(57) WHEN s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1014_dataout = '1' ELSE altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q;
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_480m_dataout <= cp_data(55) AND NOT(s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout);
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_479m_dataout <= cp_data(56) AND NOT(s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout);
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_478m_dataout <= cp_data(57) OR s_wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_477_dataout;
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_a <= ( altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1046q & altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1047q & altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1080q & "1");
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_a,
+ b => wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028_o
+ );
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_a <= ( rf_sink_data(57 DOWNTO 55) & "1");
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_a,
+ b => wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032_o
+ );
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_a <= ( wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout
+ & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1106m_dataout & wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1107m_dataout);
+ wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0");
+ altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 14,
+ width_b => 14,
+ width_o => 14
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_a,
+ b => wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108_o
+ );
+
+ END RTL; --altera_merlin_slave_agent_0010
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0011.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0011.vho
new file mode 100644
index 0000000000000000000000000000000000000000..b7f53bf5ca4f50983016466f7df40c314fd348ec
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0011.vho
@@ -0,0 +1,505 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+ LIBRARY sgate;
+ USE sgate.sgate_pack.all;
+
+--synthesis_resources = lut 32 mux21 44 oper_add 3
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_slave_agent_0011 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ cp_channel : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+ cp_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ cp_endofpacket : IN STD_LOGIC;
+ cp_ready : OUT STD_LOGIC;
+ cp_startofpacket : IN STD_LOGIC;
+ cp_valid : IN STD_LOGIC;
+ m0_address : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
+ m0_burstcount : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ m0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+ m0_debugaccess : OUT STD_LOGIC;
+ m0_lock : OUT STD_LOGIC;
+ m0_read : OUT STD_LOGIC;
+ m0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ m0_readdatavalid : IN STD_LOGIC;
+ m0_waitrequest : IN STD_LOGIC;
+ m0_write : OUT STD_LOGIC;
+ m0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_ready : OUT STD_LOGIC;
+ rdata_fifo_sink_valid : IN STD_LOGIC;
+ rdata_fifo_src_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_src_ready : IN STD_LOGIC;
+ rdata_fifo_src_valid : OUT STD_LOGIC;
+ reset : IN STD_LOGIC;
+ rf_sink_data : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
+ rf_sink_endofpacket : IN STD_LOGIC;
+ rf_sink_ready : OUT STD_LOGIC;
+ rf_sink_startofpacket : IN STD_LOGIC;
+ rf_sink_valid : IN STD_LOGIC;
+ rf_source_data : OUT STD_LOGIC_VECTOR (69 DOWNTO 0);
+ rf_source_endofpacket : OUT STD_LOGIC;
+ rf_source_ready : IN STD_LOGIC;
+ rf_source_startofpacket : OUT STD_LOGIC;
+ rf_source_valid : OUT STD_LOGIC;
+ rp_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ rp_endofpacket : OUT STD_LOGIC;
+ rp_ready : IN STD_LOGIC;
+ rp_startofpacket : OUT STD_LOGIC;
+ rp_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_slave_agent_0011;
+
+ ARCHITECTURE RTL OF altera_merlin_slave_agent_0011 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1135q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1082q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1081q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1080q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1079q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1091q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1090q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1089q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1088q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1087q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1086q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1085q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1084q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1083q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q : STD_LOGIC := '0';
+ SIGNAL wire_nl_w620w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w329w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w619w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q : STD_LOGIC := '0';
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1027m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1028m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1032m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1036m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1037m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1092m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1093m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1022m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1176m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1166m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1165m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1164m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1163m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1175m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1174m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1173m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1172m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1171m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1170m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1169m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1168m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1167m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1015m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1014m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1013m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_479m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_478m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_477m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_gnd : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_a : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_b : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_w_lg_cp_valid61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_rf_source_ready62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range697w743w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range694w696w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range692w693w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range690w691w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range688w689w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range686w687w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range684w685w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range682w683w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range680w681w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range678w679w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range676w677w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range674w675w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range672w673w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range669w671w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_m0_waitrequest598w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_reset613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w667w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w602w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range300w742w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range302w695w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range305w670w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range291w293w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1024_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1046_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_cp_ready_472_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_467_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_local_read_466_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_local_write_465_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_read_473_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_write_480_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_470_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ SIGNAL wire_w_cp_data_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range697w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range694w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range692w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range690w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range688w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range686w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range684w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range682w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range678w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range676w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range674w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range672w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range669w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range292w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range300w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range302w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range305w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+ wire_gnd <= '0';
+ wire_w_lg_cp_valid61w(0) <= cp_valid AND wire_w_cp_data_range60w(0);
+ wire_w_lg_rf_source_ready62w(0) <= rf_source_ready AND wire_w_lg_cp_valid61w(0);
+ wire_w_lg_w_rf_sink_data_range697w743w(0) <= wire_w_rf_sink_data_range697w(0) AND wire_w_lg_w_rf_sink_data_range300w742w(0);
+ wire_w_lg_w_rf_sink_data_range694w696w(0) <= wire_w_rf_sink_data_range694w(0) AND wire_w_lg_w_rf_sink_data_range302w695w(0);
+ wire_w_lg_w_rf_sink_data_range692w693w(0) <= wire_w_rf_sink_data_range692w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range690w691w(0) <= wire_w_rf_sink_data_range690w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range688w689w(0) <= wire_w_rf_sink_data_range688w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range686w687w(0) <= wire_w_rf_sink_data_range686w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range684w685w(0) <= wire_w_rf_sink_data_range684w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range682w683w(0) <= wire_w_rf_sink_data_range682w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range680w681w(0) <= wire_w_rf_sink_data_range680w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range678w679w(0) <= wire_w_rf_sink_data_range678w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range676w677w(0) <= wire_w_rf_sink_data_range676w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range674w675w(0) <= wire_w_rf_sink_data_range674w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range672w673w(0) <= wire_w_rf_sink_data_range672w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range669w671w(0) <= wire_w_rf_sink_data_range669w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_m0_waitrequest598w(0) <= NOT m0_waitrequest;
+ wire_w_lg_reset613w(0) <= NOT reset;
+ wire_w667w(0) <= NOT s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout;
+ wire_w602w(0) <= NOT s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_467_dataout;
+ wire_w_lg_w_rf_sink_data_range300w742w(0) <= NOT wire_w_rf_sink_data_range300w(0);
+ wire_w_lg_w_rf_sink_data_range302w695w(0) <= NOT wire_w_rf_sink_data_range302w(0);
+ wire_w_lg_w_rf_sink_data_range305w670w(0) <= NOT wire_w_rf_sink_data_range305w(0);
+ wire_w_lg_w_rf_sink_data_range291w293w(0) <= wire_w_rf_sink_data_range291w(0) OR wire_w_rf_sink_data_range292w(0);
+ cp_ready <= s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_cp_ready_472_dataout;
+ m0_address <= ( cp_data(49 DOWNTO 36));
+ m0_burstcount <= ( wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_477m_dataout & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_478m_dataout & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_479m_dataout);
+ m0_byteenable <= ( cp_data(35 DOWNTO 32));
+ m0_debugaccess <= cp_data(68);
+ m0_lock <= (wire_w_lg_rf_source_ready62w(0) AND (s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout OR s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_write_480_dataout));
+ m0_read <= s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout;
+ m0_write <= s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_write_480_dataout;
+ m0_writedata <= ( cp_data(31 DOWNTO 0));
+ rdata_fifo_sink_ready <= ((rp_ready AND rdata_fifo_sink_valid) AND (NOT (rf_sink_valid AND rf_sink_data(69))));
+ rdata_fifo_src_data <= ( m0_readdata(31 DOWNTO 0));
+ rdata_fifo_src_valid <= m0_readdatavalid;
+ rf_sink_ready <= (s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout AND s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout);
+ rf_source_data <= ( s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_470_dataout & cp_data(68 DOWNTO 32) & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ rf_source_endofpacket <= cp_endofpacket;
+ rf_source_startofpacket <= cp_startofpacket;
+ rf_source_valid <= (s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_cp_ready_472_dataout AND (rf_source_ready AND (s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_470_dataout OR s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_read_473_dataout)));
+ rp_data <= ( rf_sink_data(68) & rf_sink_data(64 DOWNTO 62) & rf_sink_data(67 DOWNTO 65) & rf_sink_data(61 DOWNTO 58) & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1013m_dataout & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1014m_dataout & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1015m_dataout & rf_sink_data(54) & wire_w_lg_w_rf_sink_data_range291w293w & rf_sink_data(52 DOWNTO 51) & "0" & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1163m_dataout & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1164m_dataout & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1165m_dataout & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1166m_dataout & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1167m_dataout & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1168m_dataout
+ & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1169m_dataout & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1170m_dataout & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1171m_dataout & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1172m_dataout & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1173m_dataout & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1174m_dataout & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1175m_dataout & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1176m_dataout & rf_sink_data(35 DOWNTO 32) & rdata_fifo_sink_data(31 DOWNTO 0));
+ rp_endofpacket <= (rf_sink_endofpacket AND s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout);
+ rp_startofpacket <= (rf_sink_startofpacket AND wire_nl_w329w(0));
+ rp_valid <= (rdata_fifo_sink_valid OR s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout);
+ s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1024_dataout <= (s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout AND s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout);
+ s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1046_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout);
+ s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout <= (s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout AND wire_nl_w329w(0));
+ s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout <= ((NOT rf_sink_data(50)) OR wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1022m_dataout);
+ s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout);
+ s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout <= ((altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q OR altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q) OR altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q);
+ s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout <= (rf_sink_valid AND (rf_sink_data(69) OR rdata_fifo_sink_valid));
+ s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_cp_ready_472_dataout <= (wire_w_lg_m0_waitrequest598w(0) AND rf_source_ready);
+ s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_467_dataout <= (cp_valid AND cp_data(50));
+ s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_local_read_466_dataout <= (cp_valid AND cp_data(53));
+ s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_local_write_465_dataout <= (cp_valid AND cp_data(52));
+ s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout <= (s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_local_read_466_dataout AND wire_w602w(0));
+ s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_read_473_dataout <= (s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_local_read_466_dataout OR s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_467_dataout);
+ s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_read_473_dataout);
+ s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_write_480_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_local_write_465_dataout);
+ s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_470_dataout <= ((NOT cp_data(51)) AND (cp_endofpacket AND s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_local_write_465_dataout));
+ s_wire_vcc <= '1';
+ wire_w_cp_data_range60w(0) <= cp_data(54);
+ wire_w_rf_sink_data_range697w(0) <= rf_sink_data(36);
+ wire_w_rf_sink_data_range694w(0) <= rf_sink_data(37);
+ wire_w_rf_sink_data_range692w(0) <= rf_sink_data(38);
+ wire_w_rf_sink_data_range690w(0) <= rf_sink_data(39);
+ wire_w_rf_sink_data_range688w(0) <= rf_sink_data(40);
+ wire_w_rf_sink_data_range686w(0) <= rf_sink_data(41);
+ wire_w_rf_sink_data_range684w(0) <= rf_sink_data(42);
+ wire_w_rf_sink_data_range682w(0) <= rf_sink_data(43);
+ wire_w_rf_sink_data_range680w(0) <= rf_sink_data(44);
+ wire_w_rf_sink_data_range678w(0) <= rf_sink_data(45);
+ wire_w_rf_sink_data_range676w(0) <= rf_sink_data(46);
+ wire_w_rf_sink_data_range674w(0) <= rf_sink_data(47);
+ wire_w_rf_sink_data_range672w(0) <= rf_sink_data(48);
+ wire_w_rf_sink_data_range669w(0) <= rf_sink_data(49);
+ wire_w_rf_sink_data_range291w(0) <= rf_sink_data(50);
+ wire_w_rf_sink_data_range292w(0) <= rf_sink_data(53);
+ wire_w_rf_sink_data_range300w(0) <= rf_sink_data(58);
+ wire_w_rf_sink_data_range302w(0) <= rf_sink_data(59);
+ wire_w_rf_sink_data_range305w(0) <= rf_sink_data(60);
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1135q <= '0';
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1082q <= '0';
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1081q <= '0';
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1080q <= '0';
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1079q <= '0';
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1091q <= '0';
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1090q <= '0';
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1089q <= '0';
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1088q <= '0';
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1087q <= '0';
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1086q <= '0';
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1085q <= '0';
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1084q <= '0';
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1083q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1046_dataout = '1') THEN
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1135q <= wire_w_lg_w_rf_sink_data_range697w743w(0);
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1082q <= wire_w_lg_w_rf_sink_data_range676w677w(0);
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1081q <= wire_w_lg_w_rf_sink_data_range674w675w(0);
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1080q <= wire_w_lg_w_rf_sink_data_range672w673w(0);
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1079q <= wire_w_lg_w_rf_sink_data_range669w671w(0);
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1091q <= wire_w_lg_w_rf_sink_data_range694w696w(0);
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1090q <= wire_w_lg_w_rf_sink_data_range692w693w(0);
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1089q <= wire_w_lg_w_rf_sink_data_range690w691w(0);
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1088q <= wire_w_lg_w_rf_sink_data_range688w689w(0);
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1087q <= wire_w_lg_w_rf_sink_data_range686w687w(0);
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1086q <= wire_w_lg_w_rf_sink_data_range684w685w(0);
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1085q <= wire_w_lg_w_rf_sink_data_range682w683w(0);
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1084q <= wire_w_lg_w_rf_sink_data_range680w681w(0);
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1083q <= wire_w_lg_w_rf_sink_data_range678w679w(0);
+ END IF;
+ END IF;
+ END PROCESS;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q <= '0';
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q <= '0';
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q <= '0';
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1024_dataout = '1') THEN
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q <= wire_w667w(0);
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q <= wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout;
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q <= wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1037m_dataout;
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q <= wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1036m_dataout;
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_nl_w620w(0) <= altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q AND wire_nl_w619w(0);
+ wire_nl_w329w(0) <= NOT altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q;
+ wire_nl_w621w(0) <= NOT altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q;
+ wire_nl_w619w(0) <= NOT altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q <= '0';
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q <= '0';
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q <= '0';
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q <= '0';
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q <= '0';
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q <= '0';
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q <= '0';
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q <= '0';
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q <= '0';
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q <= '0';
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q <= '0';
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q <= '0';
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q <= '0';
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout = '1') THEN
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q <= (rf_sink_data(58) AND wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(0));
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(10));
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(11));
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(12));
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(13));
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q <= (rf_sink_data(59) AND wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(1));
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(2));
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(3));
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(4));
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(5));
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(6));
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(7));
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(8));
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(9));
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1027m_dataout <= wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o(3) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout = '1' ELSE wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(3);
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1028m_dataout <= wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o(2) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout = '1' ELSE wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(2);
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout <= wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o(1) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout = '1' ELSE wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(1);
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout <= wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1027m_dataout WHEN altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q = '1' ELSE wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(3);
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1032m_dataout <= wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1028m_dataout WHEN altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q = '1' ELSE wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(2);
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout <= wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout WHEN altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q = '1' ELSE wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(1);
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1036m_dataout <= wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout);
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1037m_dataout <= wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1032m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout);
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout <= wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout);
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1092m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q;
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1093m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q;
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q;
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q;
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q;
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q;
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q;
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q;
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q;
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q;
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q;
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q;
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q;
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q;
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1022m_dataout <= (s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout AND (wire_nl_w620w(0) AND wire_nl_w621w(0))) WHEN altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q = '1' ELSE (s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout AND (((NOT rf_sink_data(55)) AND (NOT rf_sink_data(56))) AND rf_sink_data(57)));
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1176m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q OR altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1135q);
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1166m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1082q OR altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q);
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1165m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1081q OR altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q);
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1164m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1080q OR altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q);
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1163m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1079q OR altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q);
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1175m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1091q OR altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q);
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1174m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1090q OR altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q);
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1173m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1089q OR altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q);
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1172m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1088q OR altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q);
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1171m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1087q OR altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q);
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1170m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1086q OR altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q);
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1169m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1085q OR altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q);
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1168m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1084q OR altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q);
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1167m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1083q OR altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q);
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1015m_dataout <= rf_sink_data(55) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q;
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1014m_dataout <= rf_sink_data(56) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q;
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1013m_dataout <= rf_sink_data(57) WHEN s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q;
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_479m_dataout <= cp_data(55) AND NOT(s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout);
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_478m_dataout <= cp_data(56) AND NOT(s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout);
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_477m_dataout <= cp_data(57) OR s_wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout;
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_a <= ( altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q & altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q & altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q & "1");
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_a,
+ b => wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o
+ );
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_a <= ( rf_sink_data(57 DOWNTO 55) & "1");
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_a,
+ b => wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o
+ );
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_a <= ( wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1092m_dataout & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1093m_dataout & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout
+ & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout & wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout);
+ wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0");
+ altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 14,
+ width_b => 14,
+ width_o => 14
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_a,
+ b => wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o
+ );
+
+ END RTL; --altera_merlin_slave_agent_0011
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0012.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0012.vho
new file mode 100644
index 0000000000000000000000000000000000000000..ac21b0ba45d395638f2ebddf52baae2cbf84cac4
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0012.vho
@@ -0,0 +1,505 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+ LIBRARY sgate;
+ USE sgate.sgate_pack.all;
+
+--synthesis_resources = lut 32 mux21 44 oper_add 3
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_slave_agent_0012 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ cp_channel : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+ cp_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ cp_endofpacket : IN STD_LOGIC;
+ cp_ready : OUT STD_LOGIC;
+ cp_startofpacket : IN STD_LOGIC;
+ cp_valid : IN STD_LOGIC;
+ m0_address : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
+ m0_burstcount : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ m0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+ m0_debugaccess : OUT STD_LOGIC;
+ m0_lock : OUT STD_LOGIC;
+ m0_read : OUT STD_LOGIC;
+ m0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ m0_readdatavalid : IN STD_LOGIC;
+ m0_waitrequest : IN STD_LOGIC;
+ m0_write : OUT STD_LOGIC;
+ m0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_ready : OUT STD_LOGIC;
+ rdata_fifo_sink_valid : IN STD_LOGIC;
+ rdata_fifo_src_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_src_ready : IN STD_LOGIC;
+ rdata_fifo_src_valid : OUT STD_LOGIC;
+ reset : IN STD_LOGIC;
+ rf_sink_data : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
+ rf_sink_endofpacket : IN STD_LOGIC;
+ rf_sink_ready : OUT STD_LOGIC;
+ rf_sink_startofpacket : IN STD_LOGIC;
+ rf_sink_valid : IN STD_LOGIC;
+ rf_source_data : OUT STD_LOGIC_VECTOR (69 DOWNTO 0);
+ rf_source_endofpacket : OUT STD_LOGIC;
+ rf_source_ready : IN STD_LOGIC;
+ rf_source_startofpacket : OUT STD_LOGIC;
+ rf_source_valid : OUT STD_LOGIC;
+ rp_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ rp_endofpacket : OUT STD_LOGIC;
+ rp_ready : IN STD_LOGIC;
+ rp_startofpacket : OUT STD_LOGIC;
+ rp_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_slave_agent_0012;
+
+ ARCHITECTURE RTL OF altera_merlin_slave_agent_0012 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1135q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1082q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1081q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1080q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1079q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1091q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1090q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1089q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1088q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1087q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1086q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1085q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1084q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1083q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q : STD_LOGIC := '0';
+ SIGNAL wire_nl_w620w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w329w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w619w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q : STD_LOGIC := '0';
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1027m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1028m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1032m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1036m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1037m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1092m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1093m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1022m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1176m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1166m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1165m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1164m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1163m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1175m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1174m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1173m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1172m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1171m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1170m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1169m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1168m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1167m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1015m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1014m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1013m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_479m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_478m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_477m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_gnd : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_a : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_b : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_w_lg_cp_valid61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_rf_source_ready62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range697w743w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range694w696w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range692w693w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range690w691w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range688w689w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range686w687w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range684w685w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range682w683w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range680w681w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range678w679w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range676w677w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range674w675w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range672w673w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range669w671w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_m0_waitrequest598w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_reset613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w667w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w602w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range300w742w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range302w695w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range305w670w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range291w293w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1024_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1046_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_cp_ready_472_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_467_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_local_read_466_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_local_write_465_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_read_473_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_write_480_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_470_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ SIGNAL wire_w_cp_data_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range697w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range694w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range692w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range690w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range688w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range686w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range684w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range682w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range678w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range676w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range674w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range672w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range669w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range292w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range300w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range302w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range305w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+ wire_gnd <= '0';
+ wire_w_lg_cp_valid61w(0) <= cp_valid AND wire_w_cp_data_range60w(0);
+ wire_w_lg_rf_source_ready62w(0) <= rf_source_ready AND wire_w_lg_cp_valid61w(0);
+ wire_w_lg_w_rf_sink_data_range697w743w(0) <= wire_w_rf_sink_data_range697w(0) AND wire_w_lg_w_rf_sink_data_range300w742w(0);
+ wire_w_lg_w_rf_sink_data_range694w696w(0) <= wire_w_rf_sink_data_range694w(0) AND wire_w_lg_w_rf_sink_data_range302w695w(0);
+ wire_w_lg_w_rf_sink_data_range692w693w(0) <= wire_w_rf_sink_data_range692w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range690w691w(0) <= wire_w_rf_sink_data_range690w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range688w689w(0) <= wire_w_rf_sink_data_range688w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range686w687w(0) <= wire_w_rf_sink_data_range686w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range684w685w(0) <= wire_w_rf_sink_data_range684w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range682w683w(0) <= wire_w_rf_sink_data_range682w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range680w681w(0) <= wire_w_rf_sink_data_range680w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range678w679w(0) <= wire_w_rf_sink_data_range678w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range676w677w(0) <= wire_w_rf_sink_data_range676w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range674w675w(0) <= wire_w_rf_sink_data_range674w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range672w673w(0) <= wire_w_rf_sink_data_range672w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range669w671w(0) <= wire_w_rf_sink_data_range669w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_m0_waitrequest598w(0) <= NOT m0_waitrequest;
+ wire_w_lg_reset613w(0) <= NOT reset;
+ wire_w667w(0) <= NOT s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout;
+ wire_w602w(0) <= NOT s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_467_dataout;
+ wire_w_lg_w_rf_sink_data_range300w742w(0) <= NOT wire_w_rf_sink_data_range300w(0);
+ wire_w_lg_w_rf_sink_data_range302w695w(0) <= NOT wire_w_rf_sink_data_range302w(0);
+ wire_w_lg_w_rf_sink_data_range305w670w(0) <= NOT wire_w_rf_sink_data_range305w(0);
+ wire_w_lg_w_rf_sink_data_range291w293w(0) <= wire_w_rf_sink_data_range291w(0) OR wire_w_rf_sink_data_range292w(0);
+ cp_ready <= s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_cp_ready_472_dataout;
+ m0_address <= ( cp_data(49 DOWNTO 36));
+ m0_burstcount <= ( wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_477m_dataout & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_478m_dataout & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_479m_dataout);
+ m0_byteenable <= ( cp_data(35 DOWNTO 32));
+ m0_debugaccess <= cp_data(68);
+ m0_lock <= (wire_w_lg_rf_source_ready62w(0) AND (s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout OR s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_write_480_dataout));
+ m0_read <= s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout;
+ m0_write <= s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_write_480_dataout;
+ m0_writedata <= ( cp_data(31 DOWNTO 0));
+ rdata_fifo_sink_ready <= ((rp_ready AND rdata_fifo_sink_valid) AND (NOT (rf_sink_valid AND rf_sink_data(69))));
+ rdata_fifo_src_data <= ( m0_readdata(31 DOWNTO 0));
+ rdata_fifo_src_valid <= m0_readdatavalid;
+ rf_sink_ready <= (s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout AND s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout);
+ rf_source_data <= ( s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_470_dataout & cp_data(68 DOWNTO 32) & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ rf_source_endofpacket <= cp_endofpacket;
+ rf_source_startofpacket <= cp_startofpacket;
+ rf_source_valid <= (s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_cp_ready_472_dataout AND (rf_source_ready AND (s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_470_dataout OR s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_read_473_dataout)));
+ rp_data <= ( rf_sink_data(68) & rf_sink_data(64 DOWNTO 62) & rf_sink_data(67 DOWNTO 65) & rf_sink_data(61 DOWNTO 58) & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1013m_dataout & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1014m_dataout & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1015m_dataout & rf_sink_data(54) & wire_w_lg_w_rf_sink_data_range291w293w & rf_sink_data(52 DOWNTO 51) & "0" & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1163m_dataout & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1164m_dataout & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1165m_dataout & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1166m_dataout & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1167m_dataout & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1168m_dataout
+ & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1169m_dataout & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1170m_dataout & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1171m_dataout & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1172m_dataout & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1173m_dataout & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1174m_dataout & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1175m_dataout & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1176m_dataout & rf_sink_data(35 DOWNTO 32) & rdata_fifo_sink_data(31 DOWNTO 0));
+ rp_endofpacket <= (rf_sink_endofpacket AND s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout);
+ rp_startofpacket <= (rf_sink_startofpacket AND wire_nl_w329w(0));
+ rp_valid <= (rdata_fifo_sink_valid OR s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout);
+ s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1024_dataout <= (s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout AND s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout);
+ s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1046_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout);
+ s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout <= (s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout AND wire_nl_w329w(0));
+ s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout <= ((NOT rf_sink_data(50)) OR wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1022m_dataout);
+ s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout);
+ s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout <= ((altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q OR altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q) OR altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q);
+ s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout <= (rf_sink_valid AND (rf_sink_data(69) OR rdata_fifo_sink_valid));
+ s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_cp_ready_472_dataout <= (wire_w_lg_m0_waitrequest598w(0) AND rf_source_ready);
+ s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_467_dataout <= (cp_valid AND cp_data(50));
+ s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_local_read_466_dataout <= (cp_valid AND cp_data(53));
+ s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_local_write_465_dataout <= (cp_valid AND cp_data(52));
+ s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout <= (s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_local_read_466_dataout AND wire_w602w(0));
+ s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_read_473_dataout <= (s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_local_read_466_dataout OR s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_467_dataout);
+ s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_read_473_dataout);
+ s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_write_480_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_local_write_465_dataout);
+ s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_470_dataout <= ((NOT cp_data(51)) AND (cp_endofpacket AND s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_local_write_465_dataout));
+ s_wire_vcc <= '1';
+ wire_w_cp_data_range60w(0) <= cp_data(54);
+ wire_w_rf_sink_data_range697w(0) <= rf_sink_data(36);
+ wire_w_rf_sink_data_range694w(0) <= rf_sink_data(37);
+ wire_w_rf_sink_data_range692w(0) <= rf_sink_data(38);
+ wire_w_rf_sink_data_range690w(0) <= rf_sink_data(39);
+ wire_w_rf_sink_data_range688w(0) <= rf_sink_data(40);
+ wire_w_rf_sink_data_range686w(0) <= rf_sink_data(41);
+ wire_w_rf_sink_data_range684w(0) <= rf_sink_data(42);
+ wire_w_rf_sink_data_range682w(0) <= rf_sink_data(43);
+ wire_w_rf_sink_data_range680w(0) <= rf_sink_data(44);
+ wire_w_rf_sink_data_range678w(0) <= rf_sink_data(45);
+ wire_w_rf_sink_data_range676w(0) <= rf_sink_data(46);
+ wire_w_rf_sink_data_range674w(0) <= rf_sink_data(47);
+ wire_w_rf_sink_data_range672w(0) <= rf_sink_data(48);
+ wire_w_rf_sink_data_range669w(0) <= rf_sink_data(49);
+ wire_w_rf_sink_data_range291w(0) <= rf_sink_data(50);
+ wire_w_rf_sink_data_range292w(0) <= rf_sink_data(53);
+ wire_w_rf_sink_data_range300w(0) <= rf_sink_data(58);
+ wire_w_rf_sink_data_range302w(0) <= rf_sink_data(59);
+ wire_w_rf_sink_data_range305w(0) <= rf_sink_data(60);
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1135q <= '0';
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1082q <= '0';
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1081q <= '0';
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1080q <= '0';
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1079q <= '0';
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1091q <= '0';
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1090q <= '0';
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1089q <= '0';
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1088q <= '0';
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1087q <= '0';
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1086q <= '0';
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1085q <= '0';
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1084q <= '0';
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1083q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1046_dataout = '1') THEN
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1135q <= wire_w_lg_w_rf_sink_data_range697w743w(0);
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1082q <= wire_w_lg_w_rf_sink_data_range676w677w(0);
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1081q <= wire_w_lg_w_rf_sink_data_range674w675w(0);
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1080q <= wire_w_lg_w_rf_sink_data_range672w673w(0);
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1079q <= wire_w_lg_w_rf_sink_data_range669w671w(0);
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1091q <= wire_w_lg_w_rf_sink_data_range694w696w(0);
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1090q <= wire_w_lg_w_rf_sink_data_range692w693w(0);
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1089q <= wire_w_lg_w_rf_sink_data_range690w691w(0);
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1088q <= wire_w_lg_w_rf_sink_data_range688w689w(0);
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1087q <= wire_w_lg_w_rf_sink_data_range686w687w(0);
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1086q <= wire_w_lg_w_rf_sink_data_range684w685w(0);
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1085q <= wire_w_lg_w_rf_sink_data_range682w683w(0);
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1084q <= wire_w_lg_w_rf_sink_data_range680w681w(0);
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1083q <= wire_w_lg_w_rf_sink_data_range678w679w(0);
+ END IF;
+ END IF;
+ END PROCESS;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q <= '0';
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q <= '0';
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q <= '0';
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1024_dataout = '1') THEN
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q <= wire_w667w(0);
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q <= wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout;
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q <= wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1037m_dataout;
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q <= wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1036m_dataout;
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_nl_w620w(0) <= altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q AND wire_nl_w619w(0);
+ wire_nl_w329w(0) <= NOT altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q;
+ wire_nl_w621w(0) <= NOT altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q;
+ wire_nl_w619w(0) <= NOT altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q <= '0';
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q <= '0';
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q <= '0';
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q <= '0';
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q <= '0';
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q <= '0';
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q <= '0';
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q <= '0';
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q <= '0';
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q <= '0';
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q <= '0';
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q <= '0';
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q <= '0';
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout = '1') THEN
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q <= (rf_sink_data(58) AND wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(0));
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(10));
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(11));
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(12));
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(13));
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q <= (rf_sink_data(59) AND wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(1));
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(2));
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(3));
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(4));
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(5));
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(6));
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(7));
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(8));
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(9));
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1027m_dataout <= wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o(3) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout = '1' ELSE wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(3);
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1028m_dataout <= wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o(2) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout = '1' ELSE wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(2);
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout <= wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o(1) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout = '1' ELSE wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(1);
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout <= wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1027m_dataout WHEN altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q = '1' ELSE wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(3);
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1032m_dataout <= wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1028m_dataout WHEN altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q = '1' ELSE wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(2);
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout <= wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout WHEN altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q = '1' ELSE wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(1);
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1036m_dataout <= wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout);
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1037m_dataout <= wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1032m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout);
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout <= wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout);
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1092m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q;
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1093m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q;
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q;
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q;
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q;
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q;
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q;
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q;
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q;
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q;
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q;
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q;
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q;
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q;
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1022m_dataout <= (s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout AND (wire_nl_w620w(0) AND wire_nl_w621w(0))) WHEN altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q = '1' ELSE (s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout AND (((NOT rf_sink_data(55)) AND (NOT rf_sink_data(56))) AND rf_sink_data(57)));
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1176m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q OR altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1135q);
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1166m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1082q OR altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q);
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1165m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1081q OR altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q);
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1164m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1080q OR altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q);
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1163m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1079q OR altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q);
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1175m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1091q OR altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q);
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1174m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1090q OR altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q);
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1173m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1089q OR altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q);
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1172m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1088q OR altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q);
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1171m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1087q OR altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q);
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1170m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1086q OR altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q);
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1169m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1085q OR altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q);
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1168m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1084q OR altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q);
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1167m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1083q OR altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q);
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1015m_dataout <= rf_sink_data(55) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q;
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1014m_dataout <= rf_sink_data(56) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q;
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1013m_dataout <= rf_sink_data(57) WHEN s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q;
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_479m_dataout <= cp_data(55) AND NOT(s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout);
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_478m_dataout <= cp_data(56) AND NOT(s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout);
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_477m_dataout <= cp_data(57) OR s_wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout;
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_a <= ( altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q & altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q & altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q & "1");
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_a,
+ b => wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o
+ );
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_a <= ( rf_sink_data(57 DOWNTO 55) & "1");
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_a,
+ b => wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o
+ );
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_a <= ( wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1092m_dataout & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1093m_dataout & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout
+ & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout & wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout);
+ wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0");
+ altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 14,
+ width_b => 14,
+ width_o => 14
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_a,
+ b => wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o
+ );
+
+ END RTL; --altera_merlin_slave_agent_0012
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0013.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0013.vho
new file mode 100644
index 0000000000000000000000000000000000000000..7e2e076e94cc94b0b507538deba606bab74feb2b
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0013.vho
@@ -0,0 +1,505 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+ LIBRARY sgate;
+ USE sgate.sgate_pack.all;
+
+--synthesis_resources = lut 32 mux21 44 oper_add 3
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_slave_agent_0013 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ cp_channel : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+ cp_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ cp_endofpacket : IN STD_LOGIC;
+ cp_ready : OUT STD_LOGIC;
+ cp_startofpacket : IN STD_LOGIC;
+ cp_valid : IN STD_LOGIC;
+ m0_address : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
+ m0_burstcount : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ m0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+ m0_debugaccess : OUT STD_LOGIC;
+ m0_lock : OUT STD_LOGIC;
+ m0_read : OUT STD_LOGIC;
+ m0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ m0_readdatavalid : IN STD_LOGIC;
+ m0_waitrequest : IN STD_LOGIC;
+ m0_write : OUT STD_LOGIC;
+ m0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_ready : OUT STD_LOGIC;
+ rdata_fifo_sink_valid : IN STD_LOGIC;
+ rdata_fifo_src_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_src_ready : IN STD_LOGIC;
+ rdata_fifo_src_valid : OUT STD_LOGIC;
+ reset : IN STD_LOGIC;
+ rf_sink_data : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
+ rf_sink_endofpacket : IN STD_LOGIC;
+ rf_sink_ready : OUT STD_LOGIC;
+ rf_sink_startofpacket : IN STD_LOGIC;
+ rf_sink_valid : IN STD_LOGIC;
+ rf_source_data : OUT STD_LOGIC_VECTOR (69 DOWNTO 0);
+ rf_source_endofpacket : OUT STD_LOGIC;
+ rf_source_ready : IN STD_LOGIC;
+ rf_source_startofpacket : OUT STD_LOGIC;
+ rf_source_valid : OUT STD_LOGIC;
+ rp_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ rp_endofpacket : OUT STD_LOGIC;
+ rp_ready : IN STD_LOGIC;
+ rp_startofpacket : OUT STD_LOGIC;
+ rp_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_slave_agent_0013;
+
+ ARCHITECTURE RTL OF altera_merlin_slave_agent_0013 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1135q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1082q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1081q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1080q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1079q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1091q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1090q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1089q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1088q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1087q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1086q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1085q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1084q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1083q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q : STD_LOGIC := '0';
+ SIGNAL wire_nl_w620w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w329w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w619w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q : STD_LOGIC := '0';
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1027m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1028m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1032m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1036m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1037m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1092m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1093m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1022m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1176m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1166m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1165m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1164m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1163m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1175m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1174m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1173m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1172m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1171m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1170m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1169m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1168m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1167m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1015m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1014m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1013m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_479m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_478m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_477m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_gnd : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_a : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_b : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_w_lg_cp_valid61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_rf_source_ready62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range697w743w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range694w696w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range692w693w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range690w691w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range688w689w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range686w687w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range684w685w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range682w683w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range680w681w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range678w679w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range676w677w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range674w675w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range672w673w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range669w671w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_m0_waitrequest598w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_reset613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w667w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w602w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range300w742w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range302w695w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range305w670w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range291w293w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1024_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1046_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_cp_ready_472_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_467_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_local_read_466_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_local_write_465_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_read_473_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_write_480_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_470_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ SIGNAL wire_w_cp_data_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range697w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range694w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range692w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range690w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range688w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range686w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range684w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range682w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range678w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range676w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range674w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range672w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range669w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range292w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range300w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range302w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range305w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+ wire_gnd <= '0';
+ wire_w_lg_cp_valid61w(0) <= cp_valid AND wire_w_cp_data_range60w(0);
+ wire_w_lg_rf_source_ready62w(0) <= rf_source_ready AND wire_w_lg_cp_valid61w(0);
+ wire_w_lg_w_rf_sink_data_range697w743w(0) <= wire_w_rf_sink_data_range697w(0) AND wire_w_lg_w_rf_sink_data_range300w742w(0);
+ wire_w_lg_w_rf_sink_data_range694w696w(0) <= wire_w_rf_sink_data_range694w(0) AND wire_w_lg_w_rf_sink_data_range302w695w(0);
+ wire_w_lg_w_rf_sink_data_range692w693w(0) <= wire_w_rf_sink_data_range692w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range690w691w(0) <= wire_w_rf_sink_data_range690w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range688w689w(0) <= wire_w_rf_sink_data_range688w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range686w687w(0) <= wire_w_rf_sink_data_range686w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range684w685w(0) <= wire_w_rf_sink_data_range684w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range682w683w(0) <= wire_w_rf_sink_data_range682w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range680w681w(0) <= wire_w_rf_sink_data_range680w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range678w679w(0) <= wire_w_rf_sink_data_range678w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range676w677w(0) <= wire_w_rf_sink_data_range676w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range674w675w(0) <= wire_w_rf_sink_data_range674w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range672w673w(0) <= wire_w_rf_sink_data_range672w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range669w671w(0) <= wire_w_rf_sink_data_range669w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_m0_waitrequest598w(0) <= NOT m0_waitrequest;
+ wire_w_lg_reset613w(0) <= NOT reset;
+ wire_w667w(0) <= NOT s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout;
+ wire_w602w(0) <= NOT s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_467_dataout;
+ wire_w_lg_w_rf_sink_data_range300w742w(0) <= NOT wire_w_rf_sink_data_range300w(0);
+ wire_w_lg_w_rf_sink_data_range302w695w(0) <= NOT wire_w_rf_sink_data_range302w(0);
+ wire_w_lg_w_rf_sink_data_range305w670w(0) <= NOT wire_w_rf_sink_data_range305w(0);
+ wire_w_lg_w_rf_sink_data_range291w293w(0) <= wire_w_rf_sink_data_range291w(0) OR wire_w_rf_sink_data_range292w(0);
+ cp_ready <= s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_cp_ready_472_dataout;
+ m0_address <= ( cp_data(49 DOWNTO 36));
+ m0_burstcount <= ( wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_477m_dataout & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_478m_dataout & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_479m_dataout);
+ m0_byteenable <= ( cp_data(35 DOWNTO 32));
+ m0_debugaccess <= cp_data(68);
+ m0_lock <= (wire_w_lg_rf_source_ready62w(0) AND (s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout OR s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_write_480_dataout));
+ m0_read <= s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout;
+ m0_write <= s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_write_480_dataout;
+ m0_writedata <= ( cp_data(31 DOWNTO 0));
+ rdata_fifo_sink_ready <= ((rp_ready AND rdata_fifo_sink_valid) AND (NOT (rf_sink_valid AND rf_sink_data(69))));
+ rdata_fifo_src_data <= ( m0_readdata(31 DOWNTO 0));
+ rdata_fifo_src_valid <= m0_readdatavalid;
+ rf_sink_ready <= (s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout AND s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout);
+ rf_source_data <= ( s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_470_dataout & cp_data(68 DOWNTO 32) & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ rf_source_endofpacket <= cp_endofpacket;
+ rf_source_startofpacket <= cp_startofpacket;
+ rf_source_valid <= (s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_cp_ready_472_dataout AND (rf_source_ready AND (s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_470_dataout OR s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_read_473_dataout)));
+ rp_data <= ( rf_sink_data(68) & rf_sink_data(64 DOWNTO 62) & rf_sink_data(67 DOWNTO 65) & rf_sink_data(61 DOWNTO 58) & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1013m_dataout & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1014m_dataout & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1015m_dataout & rf_sink_data(54) & wire_w_lg_w_rf_sink_data_range291w293w & rf_sink_data(52 DOWNTO 51) & "0" & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1163m_dataout & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1164m_dataout & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1165m_dataout & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1166m_dataout & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1167m_dataout & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1168m_dataout
+ & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1169m_dataout & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1170m_dataout & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1171m_dataout & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1172m_dataout & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1173m_dataout & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1174m_dataout & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1175m_dataout & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1176m_dataout & rf_sink_data(35 DOWNTO 32) & rdata_fifo_sink_data(31 DOWNTO 0));
+ rp_endofpacket <= (rf_sink_endofpacket AND s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout);
+ rp_startofpacket <= (rf_sink_startofpacket AND wire_nl_w329w(0));
+ rp_valid <= (rdata_fifo_sink_valid OR s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout);
+ s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1024_dataout <= (s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout AND s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout);
+ s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1046_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout);
+ s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout <= (s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout AND wire_nl_w329w(0));
+ s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout <= ((NOT rf_sink_data(50)) OR wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1022m_dataout);
+ s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout);
+ s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout <= ((altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q OR altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q) OR altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q);
+ s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout <= (rf_sink_valid AND (rf_sink_data(69) OR rdata_fifo_sink_valid));
+ s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_cp_ready_472_dataout <= (wire_w_lg_m0_waitrequest598w(0) AND rf_source_ready);
+ s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_467_dataout <= (cp_valid AND cp_data(50));
+ s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_local_read_466_dataout <= (cp_valid AND cp_data(53));
+ s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_local_write_465_dataout <= (cp_valid AND cp_data(52));
+ s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout <= (s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_local_read_466_dataout AND wire_w602w(0));
+ s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_read_473_dataout <= (s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_local_read_466_dataout OR s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_467_dataout);
+ s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_read_473_dataout);
+ s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_write_480_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_local_write_465_dataout);
+ s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_470_dataout <= ((NOT cp_data(51)) AND (cp_endofpacket AND s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_local_write_465_dataout));
+ s_wire_vcc <= '1';
+ wire_w_cp_data_range60w(0) <= cp_data(54);
+ wire_w_rf_sink_data_range697w(0) <= rf_sink_data(36);
+ wire_w_rf_sink_data_range694w(0) <= rf_sink_data(37);
+ wire_w_rf_sink_data_range692w(0) <= rf_sink_data(38);
+ wire_w_rf_sink_data_range690w(0) <= rf_sink_data(39);
+ wire_w_rf_sink_data_range688w(0) <= rf_sink_data(40);
+ wire_w_rf_sink_data_range686w(0) <= rf_sink_data(41);
+ wire_w_rf_sink_data_range684w(0) <= rf_sink_data(42);
+ wire_w_rf_sink_data_range682w(0) <= rf_sink_data(43);
+ wire_w_rf_sink_data_range680w(0) <= rf_sink_data(44);
+ wire_w_rf_sink_data_range678w(0) <= rf_sink_data(45);
+ wire_w_rf_sink_data_range676w(0) <= rf_sink_data(46);
+ wire_w_rf_sink_data_range674w(0) <= rf_sink_data(47);
+ wire_w_rf_sink_data_range672w(0) <= rf_sink_data(48);
+ wire_w_rf_sink_data_range669w(0) <= rf_sink_data(49);
+ wire_w_rf_sink_data_range291w(0) <= rf_sink_data(50);
+ wire_w_rf_sink_data_range292w(0) <= rf_sink_data(53);
+ wire_w_rf_sink_data_range300w(0) <= rf_sink_data(58);
+ wire_w_rf_sink_data_range302w(0) <= rf_sink_data(59);
+ wire_w_rf_sink_data_range305w(0) <= rf_sink_data(60);
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1135q <= '0';
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1082q <= '0';
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1081q <= '0';
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1080q <= '0';
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1079q <= '0';
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1091q <= '0';
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1090q <= '0';
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1089q <= '0';
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1088q <= '0';
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1087q <= '0';
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1086q <= '0';
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1085q <= '0';
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1084q <= '0';
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1083q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1046_dataout = '1') THEN
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1135q <= wire_w_lg_w_rf_sink_data_range697w743w(0);
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1082q <= wire_w_lg_w_rf_sink_data_range676w677w(0);
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1081q <= wire_w_lg_w_rf_sink_data_range674w675w(0);
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1080q <= wire_w_lg_w_rf_sink_data_range672w673w(0);
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1079q <= wire_w_lg_w_rf_sink_data_range669w671w(0);
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1091q <= wire_w_lg_w_rf_sink_data_range694w696w(0);
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1090q <= wire_w_lg_w_rf_sink_data_range692w693w(0);
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1089q <= wire_w_lg_w_rf_sink_data_range690w691w(0);
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1088q <= wire_w_lg_w_rf_sink_data_range688w689w(0);
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1087q <= wire_w_lg_w_rf_sink_data_range686w687w(0);
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1086q <= wire_w_lg_w_rf_sink_data_range684w685w(0);
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1085q <= wire_w_lg_w_rf_sink_data_range682w683w(0);
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1084q <= wire_w_lg_w_rf_sink_data_range680w681w(0);
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1083q <= wire_w_lg_w_rf_sink_data_range678w679w(0);
+ END IF;
+ END IF;
+ END PROCESS;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q <= '0';
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q <= '0';
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q <= '0';
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1024_dataout = '1') THEN
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q <= wire_w667w(0);
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q <= wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout;
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q <= wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1037m_dataout;
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q <= wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1036m_dataout;
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_nl_w620w(0) <= altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q AND wire_nl_w619w(0);
+ wire_nl_w329w(0) <= NOT altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q;
+ wire_nl_w621w(0) <= NOT altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q;
+ wire_nl_w619w(0) <= NOT altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q <= '0';
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q <= '0';
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q <= '0';
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q <= '0';
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q <= '0';
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q <= '0';
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q <= '0';
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q <= '0';
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q <= '0';
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q <= '0';
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q <= '0';
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q <= '0';
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q <= '0';
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout = '1') THEN
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q <= (rf_sink_data(58) AND wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(0));
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(10));
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(11));
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(12));
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(13));
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q <= (rf_sink_data(59) AND wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(1));
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(2));
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(3));
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(4));
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(5));
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(6));
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(7));
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(8));
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(9));
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1027m_dataout <= wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o(3) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout = '1' ELSE wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(3);
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1028m_dataout <= wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o(2) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout = '1' ELSE wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(2);
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout <= wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o(1) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout = '1' ELSE wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(1);
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout <= wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1027m_dataout WHEN altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q = '1' ELSE wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(3);
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1032m_dataout <= wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1028m_dataout WHEN altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q = '1' ELSE wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(2);
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout <= wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout WHEN altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q = '1' ELSE wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(1);
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1036m_dataout <= wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout);
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1037m_dataout <= wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1032m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout);
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout <= wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout);
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1092m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q;
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1093m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q;
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q;
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q;
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q;
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q;
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q;
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q;
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q;
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q;
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q;
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q;
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q;
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q;
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1022m_dataout <= (s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout AND (wire_nl_w620w(0) AND wire_nl_w621w(0))) WHEN altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q = '1' ELSE (s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout AND (((NOT rf_sink_data(55)) AND (NOT rf_sink_data(56))) AND rf_sink_data(57)));
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1176m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q OR altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1135q);
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1166m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1082q OR altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q);
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1165m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1081q OR altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q);
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1164m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1080q OR altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q);
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1163m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1079q OR altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q);
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1175m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1091q OR altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q);
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1174m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1090q OR altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q);
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1173m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1089q OR altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q);
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1172m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1088q OR altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q);
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1171m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1087q OR altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q);
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1170m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1086q OR altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q);
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1169m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1085q OR altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q);
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1168m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1084q OR altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q);
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1167m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1083q OR altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q);
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1015m_dataout <= rf_sink_data(55) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q;
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1014m_dataout <= rf_sink_data(56) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q;
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1013m_dataout <= rf_sink_data(57) WHEN s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q;
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_479m_dataout <= cp_data(55) AND NOT(s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout);
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_478m_dataout <= cp_data(56) AND NOT(s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout);
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_477m_dataout <= cp_data(57) OR s_wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout;
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_a <= ( altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q & altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q & altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q & "1");
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_a,
+ b => wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o
+ );
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_a <= ( rf_sink_data(57 DOWNTO 55) & "1");
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_a,
+ b => wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o
+ );
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_a <= ( wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1092m_dataout & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1093m_dataout & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout
+ & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout & wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout);
+ wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0");
+ altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 14,
+ width_b => 14,
+ width_o => 14
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_a,
+ b => wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o
+ );
+
+ END RTL; --altera_merlin_slave_agent_0013
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0014.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0014.vho
new file mode 100644
index 0000000000000000000000000000000000000000..cc4ceca6642c126f9875ecc954067a553e74416a
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0014.vho
@@ -0,0 +1,505 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+ LIBRARY sgate;
+ USE sgate.sgate_pack.all;
+
+--synthesis_resources = lut 32 mux21 44 oper_add 3
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_slave_agent_0014 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ cp_channel : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+ cp_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ cp_endofpacket : IN STD_LOGIC;
+ cp_ready : OUT STD_LOGIC;
+ cp_startofpacket : IN STD_LOGIC;
+ cp_valid : IN STD_LOGIC;
+ m0_address : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
+ m0_burstcount : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ m0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+ m0_debugaccess : OUT STD_LOGIC;
+ m0_lock : OUT STD_LOGIC;
+ m0_read : OUT STD_LOGIC;
+ m0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ m0_readdatavalid : IN STD_LOGIC;
+ m0_waitrequest : IN STD_LOGIC;
+ m0_write : OUT STD_LOGIC;
+ m0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_ready : OUT STD_LOGIC;
+ rdata_fifo_sink_valid : IN STD_LOGIC;
+ rdata_fifo_src_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_src_ready : IN STD_LOGIC;
+ rdata_fifo_src_valid : OUT STD_LOGIC;
+ reset : IN STD_LOGIC;
+ rf_sink_data : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
+ rf_sink_endofpacket : IN STD_LOGIC;
+ rf_sink_ready : OUT STD_LOGIC;
+ rf_sink_startofpacket : IN STD_LOGIC;
+ rf_sink_valid : IN STD_LOGIC;
+ rf_source_data : OUT STD_LOGIC_VECTOR (69 DOWNTO 0);
+ rf_source_endofpacket : OUT STD_LOGIC;
+ rf_source_ready : IN STD_LOGIC;
+ rf_source_startofpacket : OUT STD_LOGIC;
+ rf_source_valid : OUT STD_LOGIC;
+ rp_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ rp_endofpacket : OUT STD_LOGIC;
+ rp_ready : IN STD_LOGIC;
+ rp_startofpacket : OUT STD_LOGIC;
+ rp_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_slave_agent_0014;
+
+ ARCHITECTURE RTL OF altera_merlin_slave_agent_0014 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1135q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1082q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1081q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1080q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1079q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1091q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1090q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1089q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1088q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1087q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1086q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1085q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1084q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1083q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q : STD_LOGIC := '0';
+ SIGNAL wire_nl_w620w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w329w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w619w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q : STD_LOGIC := '0';
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1027m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1028m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1032m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1036m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1037m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1092m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1093m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1022m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1176m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1166m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1165m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1164m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1163m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1175m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1174m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1173m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1172m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1171m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1170m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1169m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1168m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1167m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1015m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1014m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1013m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_479m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_478m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_477m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_gnd : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_a : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_b : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_w_lg_cp_valid61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_rf_source_ready62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range697w743w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range694w696w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range692w693w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range690w691w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range688w689w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range686w687w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range684w685w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range682w683w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range680w681w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range678w679w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range676w677w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range674w675w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range672w673w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range669w671w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_m0_waitrequest598w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_reset613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w667w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w602w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range300w742w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range302w695w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range305w670w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range291w293w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1024_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1046_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_cp_ready_472_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_467_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_local_read_466_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_local_write_465_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_read_473_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_write_480_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_470_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ SIGNAL wire_w_cp_data_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range697w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range694w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range692w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range690w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range688w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range686w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range684w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range682w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range678w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range676w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range674w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range672w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range669w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range292w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range300w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range302w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range305w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+ wire_gnd <= '0';
+ wire_w_lg_cp_valid61w(0) <= cp_valid AND wire_w_cp_data_range60w(0);
+ wire_w_lg_rf_source_ready62w(0) <= rf_source_ready AND wire_w_lg_cp_valid61w(0);
+ wire_w_lg_w_rf_sink_data_range697w743w(0) <= wire_w_rf_sink_data_range697w(0) AND wire_w_lg_w_rf_sink_data_range300w742w(0);
+ wire_w_lg_w_rf_sink_data_range694w696w(0) <= wire_w_rf_sink_data_range694w(0) AND wire_w_lg_w_rf_sink_data_range302w695w(0);
+ wire_w_lg_w_rf_sink_data_range692w693w(0) <= wire_w_rf_sink_data_range692w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range690w691w(0) <= wire_w_rf_sink_data_range690w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range688w689w(0) <= wire_w_rf_sink_data_range688w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range686w687w(0) <= wire_w_rf_sink_data_range686w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range684w685w(0) <= wire_w_rf_sink_data_range684w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range682w683w(0) <= wire_w_rf_sink_data_range682w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range680w681w(0) <= wire_w_rf_sink_data_range680w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range678w679w(0) <= wire_w_rf_sink_data_range678w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range676w677w(0) <= wire_w_rf_sink_data_range676w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range674w675w(0) <= wire_w_rf_sink_data_range674w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range672w673w(0) <= wire_w_rf_sink_data_range672w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range669w671w(0) <= wire_w_rf_sink_data_range669w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_m0_waitrequest598w(0) <= NOT m0_waitrequest;
+ wire_w_lg_reset613w(0) <= NOT reset;
+ wire_w667w(0) <= NOT s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout;
+ wire_w602w(0) <= NOT s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_467_dataout;
+ wire_w_lg_w_rf_sink_data_range300w742w(0) <= NOT wire_w_rf_sink_data_range300w(0);
+ wire_w_lg_w_rf_sink_data_range302w695w(0) <= NOT wire_w_rf_sink_data_range302w(0);
+ wire_w_lg_w_rf_sink_data_range305w670w(0) <= NOT wire_w_rf_sink_data_range305w(0);
+ wire_w_lg_w_rf_sink_data_range291w293w(0) <= wire_w_rf_sink_data_range291w(0) OR wire_w_rf_sink_data_range292w(0);
+ cp_ready <= s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_cp_ready_472_dataout;
+ m0_address <= ( cp_data(49 DOWNTO 36));
+ m0_burstcount <= ( wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_477m_dataout & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_478m_dataout & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_479m_dataout);
+ m0_byteenable <= ( cp_data(35 DOWNTO 32));
+ m0_debugaccess <= cp_data(68);
+ m0_lock <= (wire_w_lg_rf_source_ready62w(0) AND (s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout OR s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_write_480_dataout));
+ m0_read <= s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout;
+ m0_write <= s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_write_480_dataout;
+ m0_writedata <= ( cp_data(31 DOWNTO 0));
+ rdata_fifo_sink_ready <= ((rp_ready AND rdata_fifo_sink_valid) AND (NOT (rf_sink_valid AND rf_sink_data(69))));
+ rdata_fifo_src_data <= ( m0_readdata(31 DOWNTO 0));
+ rdata_fifo_src_valid <= m0_readdatavalid;
+ rf_sink_ready <= (s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout AND s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout);
+ rf_source_data <= ( s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_470_dataout & cp_data(68 DOWNTO 32) & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ rf_source_endofpacket <= cp_endofpacket;
+ rf_source_startofpacket <= cp_startofpacket;
+ rf_source_valid <= (s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_cp_ready_472_dataout AND (rf_source_ready AND (s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_470_dataout OR s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_read_473_dataout)));
+ rp_data <= ( rf_sink_data(68) & rf_sink_data(64 DOWNTO 62) & rf_sink_data(67 DOWNTO 65) & rf_sink_data(61 DOWNTO 58) & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1013m_dataout & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1014m_dataout & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1015m_dataout & rf_sink_data(54) & wire_w_lg_w_rf_sink_data_range291w293w & rf_sink_data(52 DOWNTO 51) & "0" & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1163m_dataout & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1164m_dataout & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1165m_dataout & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1166m_dataout & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1167m_dataout & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1168m_dataout
+ & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1169m_dataout & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1170m_dataout & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1171m_dataout & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1172m_dataout & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1173m_dataout & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1174m_dataout & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1175m_dataout & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1176m_dataout & rf_sink_data(35 DOWNTO 32) & rdata_fifo_sink_data(31 DOWNTO 0));
+ rp_endofpacket <= (rf_sink_endofpacket AND s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout);
+ rp_startofpacket <= (rf_sink_startofpacket AND wire_nl_w329w(0));
+ rp_valid <= (rdata_fifo_sink_valid OR s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout);
+ s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1024_dataout <= (s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout AND s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout);
+ s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1046_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout);
+ s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout <= (s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout AND wire_nl_w329w(0));
+ s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout <= ((NOT rf_sink_data(50)) OR wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1022m_dataout);
+ s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout);
+ s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout <= ((altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q OR altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q) OR altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q);
+ s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout <= (rf_sink_valid AND (rf_sink_data(69) OR rdata_fifo_sink_valid));
+ s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_cp_ready_472_dataout <= (wire_w_lg_m0_waitrequest598w(0) AND rf_source_ready);
+ s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_467_dataout <= (cp_valid AND cp_data(50));
+ s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_local_read_466_dataout <= (cp_valid AND cp_data(53));
+ s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_local_write_465_dataout <= (cp_valid AND cp_data(52));
+ s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout <= (s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_local_read_466_dataout AND wire_w602w(0));
+ s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_read_473_dataout <= (s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_local_read_466_dataout OR s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_467_dataout);
+ s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_read_473_dataout);
+ s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_write_480_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_local_write_465_dataout);
+ s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_470_dataout <= ((NOT cp_data(51)) AND (cp_endofpacket AND s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_local_write_465_dataout));
+ s_wire_vcc <= '1';
+ wire_w_cp_data_range60w(0) <= cp_data(54);
+ wire_w_rf_sink_data_range697w(0) <= rf_sink_data(36);
+ wire_w_rf_sink_data_range694w(0) <= rf_sink_data(37);
+ wire_w_rf_sink_data_range692w(0) <= rf_sink_data(38);
+ wire_w_rf_sink_data_range690w(0) <= rf_sink_data(39);
+ wire_w_rf_sink_data_range688w(0) <= rf_sink_data(40);
+ wire_w_rf_sink_data_range686w(0) <= rf_sink_data(41);
+ wire_w_rf_sink_data_range684w(0) <= rf_sink_data(42);
+ wire_w_rf_sink_data_range682w(0) <= rf_sink_data(43);
+ wire_w_rf_sink_data_range680w(0) <= rf_sink_data(44);
+ wire_w_rf_sink_data_range678w(0) <= rf_sink_data(45);
+ wire_w_rf_sink_data_range676w(0) <= rf_sink_data(46);
+ wire_w_rf_sink_data_range674w(0) <= rf_sink_data(47);
+ wire_w_rf_sink_data_range672w(0) <= rf_sink_data(48);
+ wire_w_rf_sink_data_range669w(0) <= rf_sink_data(49);
+ wire_w_rf_sink_data_range291w(0) <= rf_sink_data(50);
+ wire_w_rf_sink_data_range292w(0) <= rf_sink_data(53);
+ wire_w_rf_sink_data_range300w(0) <= rf_sink_data(58);
+ wire_w_rf_sink_data_range302w(0) <= rf_sink_data(59);
+ wire_w_rf_sink_data_range305w(0) <= rf_sink_data(60);
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1135q <= '0';
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1082q <= '0';
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1081q <= '0';
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1080q <= '0';
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1079q <= '0';
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1091q <= '0';
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1090q <= '0';
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1089q <= '0';
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1088q <= '0';
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1087q <= '0';
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1086q <= '0';
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1085q <= '0';
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1084q <= '0';
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1083q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1046_dataout = '1') THEN
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1135q <= wire_w_lg_w_rf_sink_data_range697w743w(0);
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1082q <= wire_w_lg_w_rf_sink_data_range676w677w(0);
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1081q <= wire_w_lg_w_rf_sink_data_range674w675w(0);
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1080q <= wire_w_lg_w_rf_sink_data_range672w673w(0);
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1079q <= wire_w_lg_w_rf_sink_data_range669w671w(0);
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1091q <= wire_w_lg_w_rf_sink_data_range694w696w(0);
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1090q <= wire_w_lg_w_rf_sink_data_range692w693w(0);
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1089q <= wire_w_lg_w_rf_sink_data_range690w691w(0);
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1088q <= wire_w_lg_w_rf_sink_data_range688w689w(0);
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1087q <= wire_w_lg_w_rf_sink_data_range686w687w(0);
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1086q <= wire_w_lg_w_rf_sink_data_range684w685w(0);
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1085q <= wire_w_lg_w_rf_sink_data_range682w683w(0);
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1084q <= wire_w_lg_w_rf_sink_data_range680w681w(0);
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1083q <= wire_w_lg_w_rf_sink_data_range678w679w(0);
+ END IF;
+ END IF;
+ END PROCESS;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q <= '0';
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q <= '0';
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q <= '0';
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1024_dataout = '1') THEN
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q <= wire_w667w(0);
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q <= wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout;
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q <= wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1037m_dataout;
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q <= wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1036m_dataout;
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_nl_w620w(0) <= altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q AND wire_nl_w619w(0);
+ wire_nl_w329w(0) <= NOT altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q;
+ wire_nl_w621w(0) <= NOT altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q;
+ wire_nl_w619w(0) <= NOT altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q <= '0';
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q <= '0';
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q <= '0';
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q <= '0';
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q <= '0';
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q <= '0';
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q <= '0';
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q <= '0';
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q <= '0';
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q <= '0';
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q <= '0';
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q <= '0';
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q <= '0';
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout = '1') THEN
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q <= (rf_sink_data(58) AND wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(0));
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(10));
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(11));
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(12));
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(13));
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q <= (rf_sink_data(59) AND wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(1));
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(2));
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(3));
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(4));
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(5));
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(6));
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(7));
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(8));
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(9));
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1027m_dataout <= wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o(3) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout = '1' ELSE wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(3);
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1028m_dataout <= wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o(2) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout = '1' ELSE wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(2);
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout <= wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o(1) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout = '1' ELSE wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(1);
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout <= wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1027m_dataout WHEN altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q = '1' ELSE wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(3);
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1032m_dataout <= wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1028m_dataout WHEN altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q = '1' ELSE wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(2);
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout <= wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout WHEN altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q = '1' ELSE wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(1);
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1036m_dataout <= wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout);
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1037m_dataout <= wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1032m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout);
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout <= wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout);
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1092m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q;
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1093m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q;
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q;
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q;
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q;
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q;
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q;
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q;
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q;
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q;
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q;
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q;
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q;
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q;
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1022m_dataout <= (s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout AND (wire_nl_w620w(0) AND wire_nl_w621w(0))) WHEN altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q = '1' ELSE (s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout AND (((NOT rf_sink_data(55)) AND (NOT rf_sink_data(56))) AND rf_sink_data(57)));
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1176m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q OR altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1135q);
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1166m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1082q OR altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q);
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1165m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1081q OR altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q);
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1164m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1080q OR altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q);
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1163m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1079q OR altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q);
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1175m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1091q OR altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q);
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1174m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1090q OR altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q);
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1173m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1089q OR altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q);
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1172m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1088q OR altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q);
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1171m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1087q OR altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q);
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1170m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1086q OR altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q);
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1169m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1085q OR altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q);
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1168m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1084q OR altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q);
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1167m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1083q OR altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q);
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1015m_dataout <= rf_sink_data(55) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q;
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1014m_dataout <= rf_sink_data(56) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q;
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1013m_dataout <= rf_sink_data(57) WHEN s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q;
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_479m_dataout <= cp_data(55) AND NOT(s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout);
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_478m_dataout <= cp_data(56) AND NOT(s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout);
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_477m_dataout <= cp_data(57) OR s_wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout;
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_a <= ( altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q & altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q & altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q & "1");
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_a,
+ b => wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o
+ );
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_a <= ( rf_sink_data(57 DOWNTO 55) & "1");
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_a,
+ b => wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o
+ );
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_a <= ( wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1092m_dataout & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1093m_dataout & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout
+ & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout & wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout);
+ wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0");
+ altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 14,
+ width_b => 14,
+ width_o => 14
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_a,
+ b => wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o
+ );
+
+ END RTL; --altera_merlin_slave_agent_0014
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0015.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0015.vho
new file mode 100644
index 0000000000000000000000000000000000000000..0b678880c2784ffa35ee2a7ec40ff498cbd7e342
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0015.vho
@@ -0,0 +1,505 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+ LIBRARY sgate;
+ USE sgate.sgate_pack.all;
+
+--synthesis_resources = lut 32 mux21 44 oper_add 3
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_slave_agent_0015 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ cp_channel : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+ cp_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ cp_endofpacket : IN STD_LOGIC;
+ cp_ready : OUT STD_LOGIC;
+ cp_startofpacket : IN STD_LOGIC;
+ cp_valid : IN STD_LOGIC;
+ m0_address : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
+ m0_burstcount : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ m0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+ m0_debugaccess : OUT STD_LOGIC;
+ m0_lock : OUT STD_LOGIC;
+ m0_read : OUT STD_LOGIC;
+ m0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ m0_readdatavalid : IN STD_LOGIC;
+ m0_waitrequest : IN STD_LOGIC;
+ m0_write : OUT STD_LOGIC;
+ m0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_ready : OUT STD_LOGIC;
+ rdata_fifo_sink_valid : IN STD_LOGIC;
+ rdata_fifo_src_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_src_ready : IN STD_LOGIC;
+ rdata_fifo_src_valid : OUT STD_LOGIC;
+ reset : IN STD_LOGIC;
+ rf_sink_data : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
+ rf_sink_endofpacket : IN STD_LOGIC;
+ rf_sink_ready : OUT STD_LOGIC;
+ rf_sink_startofpacket : IN STD_LOGIC;
+ rf_sink_valid : IN STD_LOGIC;
+ rf_source_data : OUT STD_LOGIC_VECTOR (69 DOWNTO 0);
+ rf_source_endofpacket : OUT STD_LOGIC;
+ rf_source_ready : IN STD_LOGIC;
+ rf_source_startofpacket : OUT STD_LOGIC;
+ rf_source_valid : OUT STD_LOGIC;
+ rp_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ rp_endofpacket : OUT STD_LOGIC;
+ rp_ready : IN STD_LOGIC;
+ rp_startofpacket : OUT STD_LOGIC;
+ rp_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_slave_agent_0015;
+
+ ARCHITECTURE RTL OF altera_merlin_slave_agent_0015 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1135q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1082q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1081q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1080q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1079q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1091q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1090q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1089q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1088q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1087q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1086q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1085q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1084q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1083q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q : STD_LOGIC := '0';
+ SIGNAL wire_nl_w620w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w329w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w619w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q : STD_LOGIC := '0';
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1027m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1028m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1032m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1036m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1037m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1092m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1093m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1022m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1176m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1166m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1165m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1164m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1163m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1175m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1174m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1173m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1172m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1171m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1170m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1169m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1168m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1167m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1015m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1014m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1013m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_479m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_478m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_477m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_gnd : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_a : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_b : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_w_lg_cp_valid61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_rf_source_ready62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range697w743w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range694w696w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range692w693w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range690w691w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range688w689w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range686w687w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range684w685w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range682w683w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range680w681w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range678w679w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range676w677w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range674w675w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range672w673w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range669w671w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_m0_waitrequest598w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_reset613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w667w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w602w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range300w742w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range302w695w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range305w670w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range291w293w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1024_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1046_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_cp_ready_472_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_467_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_local_read_466_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_local_write_465_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_read_473_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_write_480_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_470_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ SIGNAL wire_w_cp_data_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range697w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range694w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range692w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range690w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range688w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range686w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range684w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range682w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range678w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range676w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range674w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range672w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range669w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range292w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range300w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range302w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range305w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+ wire_gnd <= '0';
+ wire_w_lg_cp_valid61w(0) <= cp_valid AND wire_w_cp_data_range60w(0);
+ wire_w_lg_rf_source_ready62w(0) <= rf_source_ready AND wire_w_lg_cp_valid61w(0);
+ wire_w_lg_w_rf_sink_data_range697w743w(0) <= wire_w_rf_sink_data_range697w(0) AND wire_w_lg_w_rf_sink_data_range300w742w(0);
+ wire_w_lg_w_rf_sink_data_range694w696w(0) <= wire_w_rf_sink_data_range694w(0) AND wire_w_lg_w_rf_sink_data_range302w695w(0);
+ wire_w_lg_w_rf_sink_data_range692w693w(0) <= wire_w_rf_sink_data_range692w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range690w691w(0) <= wire_w_rf_sink_data_range690w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range688w689w(0) <= wire_w_rf_sink_data_range688w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range686w687w(0) <= wire_w_rf_sink_data_range686w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range684w685w(0) <= wire_w_rf_sink_data_range684w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range682w683w(0) <= wire_w_rf_sink_data_range682w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range680w681w(0) <= wire_w_rf_sink_data_range680w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range678w679w(0) <= wire_w_rf_sink_data_range678w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range676w677w(0) <= wire_w_rf_sink_data_range676w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range674w675w(0) <= wire_w_rf_sink_data_range674w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range672w673w(0) <= wire_w_rf_sink_data_range672w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range669w671w(0) <= wire_w_rf_sink_data_range669w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_m0_waitrequest598w(0) <= NOT m0_waitrequest;
+ wire_w_lg_reset613w(0) <= NOT reset;
+ wire_w667w(0) <= NOT s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout;
+ wire_w602w(0) <= NOT s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_467_dataout;
+ wire_w_lg_w_rf_sink_data_range300w742w(0) <= NOT wire_w_rf_sink_data_range300w(0);
+ wire_w_lg_w_rf_sink_data_range302w695w(0) <= NOT wire_w_rf_sink_data_range302w(0);
+ wire_w_lg_w_rf_sink_data_range305w670w(0) <= NOT wire_w_rf_sink_data_range305w(0);
+ wire_w_lg_w_rf_sink_data_range291w293w(0) <= wire_w_rf_sink_data_range291w(0) OR wire_w_rf_sink_data_range292w(0);
+ cp_ready <= s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_cp_ready_472_dataout;
+ m0_address <= ( cp_data(49 DOWNTO 36));
+ m0_burstcount <= ( wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_477m_dataout & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_478m_dataout & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_479m_dataout);
+ m0_byteenable <= ( cp_data(35 DOWNTO 32));
+ m0_debugaccess <= cp_data(68);
+ m0_lock <= (wire_w_lg_rf_source_ready62w(0) AND (s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout OR s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_write_480_dataout));
+ m0_read <= s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout;
+ m0_write <= s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_write_480_dataout;
+ m0_writedata <= ( cp_data(31 DOWNTO 0));
+ rdata_fifo_sink_ready <= ((rp_ready AND rdata_fifo_sink_valid) AND (NOT (rf_sink_valid AND rf_sink_data(69))));
+ rdata_fifo_src_data <= ( m0_readdata(31 DOWNTO 0));
+ rdata_fifo_src_valid <= m0_readdatavalid;
+ rf_sink_ready <= (s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout AND s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout);
+ rf_source_data <= ( s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_470_dataout & cp_data(68 DOWNTO 32) & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ rf_source_endofpacket <= cp_endofpacket;
+ rf_source_startofpacket <= cp_startofpacket;
+ rf_source_valid <= (s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_cp_ready_472_dataout AND (rf_source_ready AND (s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_470_dataout OR s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_read_473_dataout)));
+ rp_data <= ( rf_sink_data(68) & rf_sink_data(64 DOWNTO 62) & rf_sink_data(67 DOWNTO 65) & rf_sink_data(61 DOWNTO 58) & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1013m_dataout & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1014m_dataout & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1015m_dataout & rf_sink_data(54) & wire_w_lg_w_rf_sink_data_range291w293w & rf_sink_data(52 DOWNTO 51) & "0" & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1163m_dataout & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1164m_dataout & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1165m_dataout & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1166m_dataout & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1167m_dataout & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1168m_dataout
+ & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1169m_dataout & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1170m_dataout & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1171m_dataout & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1172m_dataout & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1173m_dataout & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1174m_dataout & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1175m_dataout & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1176m_dataout & rf_sink_data(35 DOWNTO 32) & rdata_fifo_sink_data(31 DOWNTO 0));
+ rp_endofpacket <= (rf_sink_endofpacket AND s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout);
+ rp_startofpacket <= (rf_sink_startofpacket AND wire_nl_w329w(0));
+ rp_valid <= (rdata_fifo_sink_valid OR s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout);
+ s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1024_dataout <= (s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout AND s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout);
+ s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1046_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout);
+ s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout <= (s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout AND wire_nl_w329w(0));
+ s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout <= ((NOT rf_sink_data(50)) OR wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1022m_dataout);
+ s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout);
+ s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout <= ((altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q OR altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q) OR altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q);
+ s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout <= (rf_sink_valid AND (rf_sink_data(69) OR rdata_fifo_sink_valid));
+ s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_cp_ready_472_dataout <= (wire_w_lg_m0_waitrequest598w(0) AND rf_source_ready);
+ s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_467_dataout <= (cp_valid AND cp_data(50));
+ s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_local_read_466_dataout <= (cp_valid AND cp_data(53));
+ s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_local_write_465_dataout <= (cp_valid AND cp_data(52));
+ s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout <= (s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_local_read_466_dataout AND wire_w602w(0));
+ s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_read_473_dataout <= (s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_local_read_466_dataout OR s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_467_dataout);
+ s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_read_473_dataout);
+ s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_write_480_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_local_write_465_dataout);
+ s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_470_dataout <= ((NOT cp_data(51)) AND (cp_endofpacket AND s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_local_write_465_dataout));
+ s_wire_vcc <= '1';
+ wire_w_cp_data_range60w(0) <= cp_data(54);
+ wire_w_rf_sink_data_range697w(0) <= rf_sink_data(36);
+ wire_w_rf_sink_data_range694w(0) <= rf_sink_data(37);
+ wire_w_rf_sink_data_range692w(0) <= rf_sink_data(38);
+ wire_w_rf_sink_data_range690w(0) <= rf_sink_data(39);
+ wire_w_rf_sink_data_range688w(0) <= rf_sink_data(40);
+ wire_w_rf_sink_data_range686w(0) <= rf_sink_data(41);
+ wire_w_rf_sink_data_range684w(0) <= rf_sink_data(42);
+ wire_w_rf_sink_data_range682w(0) <= rf_sink_data(43);
+ wire_w_rf_sink_data_range680w(0) <= rf_sink_data(44);
+ wire_w_rf_sink_data_range678w(0) <= rf_sink_data(45);
+ wire_w_rf_sink_data_range676w(0) <= rf_sink_data(46);
+ wire_w_rf_sink_data_range674w(0) <= rf_sink_data(47);
+ wire_w_rf_sink_data_range672w(0) <= rf_sink_data(48);
+ wire_w_rf_sink_data_range669w(0) <= rf_sink_data(49);
+ wire_w_rf_sink_data_range291w(0) <= rf_sink_data(50);
+ wire_w_rf_sink_data_range292w(0) <= rf_sink_data(53);
+ wire_w_rf_sink_data_range300w(0) <= rf_sink_data(58);
+ wire_w_rf_sink_data_range302w(0) <= rf_sink_data(59);
+ wire_w_rf_sink_data_range305w(0) <= rf_sink_data(60);
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1135q <= '0';
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1082q <= '0';
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1081q <= '0';
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1080q <= '0';
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1079q <= '0';
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1091q <= '0';
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1090q <= '0';
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1089q <= '0';
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1088q <= '0';
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1087q <= '0';
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1086q <= '0';
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1085q <= '0';
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1084q <= '0';
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1083q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1046_dataout = '1') THEN
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1135q <= wire_w_lg_w_rf_sink_data_range697w743w(0);
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1082q <= wire_w_lg_w_rf_sink_data_range676w677w(0);
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1081q <= wire_w_lg_w_rf_sink_data_range674w675w(0);
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1080q <= wire_w_lg_w_rf_sink_data_range672w673w(0);
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1079q <= wire_w_lg_w_rf_sink_data_range669w671w(0);
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1091q <= wire_w_lg_w_rf_sink_data_range694w696w(0);
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1090q <= wire_w_lg_w_rf_sink_data_range692w693w(0);
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1089q <= wire_w_lg_w_rf_sink_data_range690w691w(0);
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1088q <= wire_w_lg_w_rf_sink_data_range688w689w(0);
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1087q <= wire_w_lg_w_rf_sink_data_range686w687w(0);
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1086q <= wire_w_lg_w_rf_sink_data_range684w685w(0);
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1085q <= wire_w_lg_w_rf_sink_data_range682w683w(0);
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1084q <= wire_w_lg_w_rf_sink_data_range680w681w(0);
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1083q <= wire_w_lg_w_rf_sink_data_range678w679w(0);
+ END IF;
+ END IF;
+ END PROCESS;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q <= '0';
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q <= '0';
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q <= '0';
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1024_dataout = '1') THEN
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q <= wire_w667w(0);
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q <= wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout;
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q <= wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1037m_dataout;
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q <= wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1036m_dataout;
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_nl_w620w(0) <= altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q AND wire_nl_w619w(0);
+ wire_nl_w329w(0) <= NOT altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q;
+ wire_nl_w621w(0) <= NOT altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q;
+ wire_nl_w619w(0) <= NOT altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q <= '0';
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q <= '0';
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q <= '0';
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q <= '0';
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q <= '0';
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q <= '0';
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q <= '0';
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q <= '0';
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q <= '0';
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q <= '0';
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q <= '0';
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q <= '0';
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q <= '0';
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout = '1') THEN
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q <= (rf_sink_data(58) AND wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(0));
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(10));
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(11));
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(12));
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(13));
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q <= (rf_sink_data(59) AND wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(1));
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(2));
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(3));
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(4));
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(5));
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(6));
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(7));
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(8));
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(9));
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1027m_dataout <= wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o(3) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout = '1' ELSE wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(3);
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1028m_dataout <= wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o(2) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout = '1' ELSE wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(2);
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout <= wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o(1) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout = '1' ELSE wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(1);
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout <= wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1027m_dataout WHEN altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q = '1' ELSE wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(3);
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1032m_dataout <= wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1028m_dataout WHEN altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q = '1' ELSE wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(2);
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout <= wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout WHEN altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q = '1' ELSE wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(1);
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1036m_dataout <= wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout);
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1037m_dataout <= wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1032m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout);
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout <= wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout);
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1092m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q;
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1093m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q;
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q;
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q;
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q;
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q;
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q;
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q;
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q;
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q;
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q;
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q;
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q;
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q;
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1022m_dataout <= (s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout AND (wire_nl_w620w(0) AND wire_nl_w621w(0))) WHEN altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q = '1' ELSE (s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout AND (((NOT rf_sink_data(55)) AND (NOT rf_sink_data(56))) AND rf_sink_data(57)));
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1176m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q OR altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1135q);
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1166m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1082q OR altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q);
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1165m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1081q OR altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q);
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1164m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1080q OR altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q);
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1163m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1079q OR altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q);
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1175m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1091q OR altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q);
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1174m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1090q OR altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q);
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1173m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1089q OR altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q);
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1172m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1088q OR altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q);
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1171m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1087q OR altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q);
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1170m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1086q OR altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q);
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1169m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1085q OR altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q);
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1168m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1084q OR altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q);
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1167m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1083q OR altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q);
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1015m_dataout <= rf_sink_data(55) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q;
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1014m_dataout <= rf_sink_data(56) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q;
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1013m_dataout <= rf_sink_data(57) WHEN s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q;
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_479m_dataout <= cp_data(55) AND NOT(s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout);
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_478m_dataout <= cp_data(56) AND NOT(s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout);
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_477m_dataout <= cp_data(57) OR s_wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout;
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_a <= ( altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q & altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q & altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q & "1");
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_a,
+ b => wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o
+ );
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_a <= ( rf_sink_data(57 DOWNTO 55) & "1");
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_a,
+ b => wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o
+ );
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_a <= ( wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1092m_dataout & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1093m_dataout & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout
+ & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout & wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout);
+ wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0");
+ altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 14,
+ width_b => 14,
+ width_o => 14
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_a,
+ b => wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o
+ );
+
+ END RTL; --altera_merlin_slave_agent_0015
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0016.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0016.vho
new file mode 100644
index 0000000000000000000000000000000000000000..645680adabbe6113dde486fa7d5c2a533246ce66
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0016.vho
@@ -0,0 +1,505 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+ LIBRARY sgate;
+ USE sgate.sgate_pack.all;
+
+--synthesis_resources = lut 32 mux21 44 oper_add 3
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_slave_agent_0016 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ cp_channel : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+ cp_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ cp_endofpacket : IN STD_LOGIC;
+ cp_ready : OUT STD_LOGIC;
+ cp_startofpacket : IN STD_LOGIC;
+ cp_valid : IN STD_LOGIC;
+ m0_address : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
+ m0_burstcount : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ m0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+ m0_debugaccess : OUT STD_LOGIC;
+ m0_lock : OUT STD_LOGIC;
+ m0_read : OUT STD_LOGIC;
+ m0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ m0_readdatavalid : IN STD_LOGIC;
+ m0_waitrequest : IN STD_LOGIC;
+ m0_write : OUT STD_LOGIC;
+ m0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_ready : OUT STD_LOGIC;
+ rdata_fifo_sink_valid : IN STD_LOGIC;
+ rdata_fifo_src_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_src_ready : IN STD_LOGIC;
+ rdata_fifo_src_valid : OUT STD_LOGIC;
+ reset : IN STD_LOGIC;
+ rf_sink_data : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
+ rf_sink_endofpacket : IN STD_LOGIC;
+ rf_sink_ready : OUT STD_LOGIC;
+ rf_sink_startofpacket : IN STD_LOGIC;
+ rf_sink_valid : IN STD_LOGIC;
+ rf_source_data : OUT STD_LOGIC_VECTOR (69 DOWNTO 0);
+ rf_source_endofpacket : OUT STD_LOGIC;
+ rf_source_ready : IN STD_LOGIC;
+ rf_source_startofpacket : OUT STD_LOGIC;
+ rf_source_valid : OUT STD_LOGIC;
+ rp_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ rp_endofpacket : OUT STD_LOGIC;
+ rp_ready : IN STD_LOGIC;
+ rp_startofpacket : OUT STD_LOGIC;
+ rp_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_slave_agent_0016;
+
+ ARCHITECTURE RTL OF altera_merlin_slave_agent_0016 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1135q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1082q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1081q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1080q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1079q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1091q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1090q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1089q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1088q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1087q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1086q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1085q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1084q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1083q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q : STD_LOGIC := '0';
+ SIGNAL wire_nl_w620w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w329w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w619w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q : STD_LOGIC := '0';
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1027m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1028m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1032m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1036m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1037m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1092m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1093m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1022m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1176m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1166m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1165m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1164m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1163m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1175m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1174m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1173m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1172m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1171m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1170m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1169m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1168m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1167m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1015m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1014m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1013m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_479m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_478m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_477m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_gnd : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_a : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_b : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_w_lg_cp_valid61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_rf_source_ready62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range697w743w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range694w696w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range692w693w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range690w691w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range688w689w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range686w687w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range684w685w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range682w683w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range680w681w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range678w679w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range676w677w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range674w675w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range672w673w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range669w671w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_m0_waitrequest598w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_reset613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w667w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w602w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range300w742w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range302w695w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range305w670w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range291w293w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1024_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1046_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_cp_ready_472_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_467_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_local_read_466_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_local_write_465_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_read_473_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_write_480_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_470_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ SIGNAL wire_w_cp_data_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range697w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range694w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range692w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range690w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range688w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range686w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range684w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range682w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range678w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range676w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range674w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range672w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range669w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range292w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range300w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range302w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range305w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+ wire_gnd <= '0';
+ wire_w_lg_cp_valid61w(0) <= cp_valid AND wire_w_cp_data_range60w(0);
+ wire_w_lg_rf_source_ready62w(0) <= rf_source_ready AND wire_w_lg_cp_valid61w(0);
+ wire_w_lg_w_rf_sink_data_range697w743w(0) <= wire_w_rf_sink_data_range697w(0) AND wire_w_lg_w_rf_sink_data_range300w742w(0);
+ wire_w_lg_w_rf_sink_data_range694w696w(0) <= wire_w_rf_sink_data_range694w(0) AND wire_w_lg_w_rf_sink_data_range302w695w(0);
+ wire_w_lg_w_rf_sink_data_range692w693w(0) <= wire_w_rf_sink_data_range692w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range690w691w(0) <= wire_w_rf_sink_data_range690w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range688w689w(0) <= wire_w_rf_sink_data_range688w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range686w687w(0) <= wire_w_rf_sink_data_range686w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range684w685w(0) <= wire_w_rf_sink_data_range684w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range682w683w(0) <= wire_w_rf_sink_data_range682w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range680w681w(0) <= wire_w_rf_sink_data_range680w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range678w679w(0) <= wire_w_rf_sink_data_range678w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range676w677w(0) <= wire_w_rf_sink_data_range676w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range674w675w(0) <= wire_w_rf_sink_data_range674w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range672w673w(0) <= wire_w_rf_sink_data_range672w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range669w671w(0) <= wire_w_rf_sink_data_range669w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_m0_waitrequest598w(0) <= NOT m0_waitrequest;
+ wire_w_lg_reset613w(0) <= NOT reset;
+ wire_w667w(0) <= NOT s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout;
+ wire_w602w(0) <= NOT s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_467_dataout;
+ wire_w_lg_w_rf_sink_data_range300w742w(0) <= NOT wire_w_rf_sink_data_range300w(0);
+ wire_w_lg_w_rf_sink_data_range302w695w(0) <= NOT wire_w_rf_sink_data_range302w(0);
+ wire_w_lg_w_rf_sink_data_range305w670w(0) <= NOT wire_w_rf_sink_data_range305w(0);
+ wire_w_lg_w_rf_sink_data_range291w293w(0) <= wire_w_rf_sink_data_range291w(0) OR wire_w_rf_sink_data_range292w(0);
+ cp_ready <= s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_cp_ready_472_dataout;
+ m0_address <= ( cp_data(49 DOWNTO 36));
+ m0_burstcount <= ( wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_477m_dataout & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_478m_dataout & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_479m_dataout);
+ m0_byteenable <= ( cp_data(35 DOWNTO 32));
+ m0_debugaccess <= cp_data(68);
+ m0_lock <= (wire_w_lg_rf_source_ready62w(0) AND (s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout OR s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_write_480_dataout));
+ m0_read <= s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout;
+ m0_write <= s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_write_480_dataout;
+ m0_writedata <= ( cp_data(31 DOWNTO 0));
+ rdata_fifo_sink_ready <= ((rp_ready AND rdata_fifo_sink_valid) AND (NOT (rf_sink_valid AND rf_sink_data(69))));
+ rdata_fifo_src_data <= ( m0_readdata(31 DOWNTO 0));
+ rdata_fifo_src_valid <= m0_readdatavalid;
+ rf_sink_ready <= (s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout AND s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout);
+ rf_source_data <= ( s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_470_dataout & cp_data(68 DOWNTO 32) & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ rf_source_endofpacket <= cp_endofpacket;
+ rf_source_startofpacket <= cp_startofpacket;
+ rf_source_valid <= (s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_cp_ready_472_dataout AND (rf_source_ready AND (s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_470_dataout OR s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_read_473_dataout)));
+ rp_data <= ( rf_sink_data(68) & rf_sink_data(64 DOWNTO 62) & rf_sink_data(67 DOWNTO 65) & rf_sink_data(61 DOWNTO 58) & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1013m_dataout & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1014m_dataout & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1015m_dataout & rf_sink_data(54) & wire_w_lg_w_rf_sink_data_range291w293w & rf_sink_data(52 DOWNTO 51) & "0" & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1163m_dataout & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1164m_dataout & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1165m_dataout & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1166m_dataout & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1167m_dataout & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1168m_dataout
+ & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1169m_dataout & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1170m_dataout & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1171m_dataout & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1172m_dataout & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1173m_dataout & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1174m_dataout & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1175m_dataout & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1176m_dataout & rf_sink_data(35 DOWNTO 32) & rdata_fifo_sink_data(31 DOWNTO 0));
+ rp_endofpacket <= (rf_sink_endofpacket AND s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout);
+ rp_startofpacket <= (rf_sink_startofpacket AND wire_nl_w329w(0));
+ rp_valid <= (rdata_fifo_sink_valid OR s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout);
+ s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1024_dataout <= (s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout AND s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout);
+ s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1046_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout);
+ s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout <= (s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout AND wire_nl_w329w(0));
+ s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout <= ((NOT rf_sink_data(50)) OR wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1022m_dataout);
+ s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout);
+ s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout <= ((altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q OR altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q) OR altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q);
+ s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout <= (rf_sink_valid AND (rf_sink_data(69) OR rdata_fifo_sink_valid));
+ s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_cp_ready_472_dataout <= (wire_w_lg_m0_waitrequest598w(0) AND rf_source_ready);
+ s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_467_dataout <= (cp_valid AND cp_data(50));
+ s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_local_read_466_dataout <= (cp_valid AND cp_data(53));
+ s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_local_write_465_dataout <= (cp_valid AND cp_data(52));
+ s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout <= (s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_local_read_466_dataout AND wire_w602w(0));
+ s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_read_473_dataout <= (s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_local_read_466_dataout OR s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_467_dataout);
+ s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_read_473_dataout);
+ s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_write_480_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_local_write_465_dataout);
+ s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_470_dataout <= ((NOT cp_data(51)) AND (cp_endofpacket AND s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_local_write_465_dataout));
+ s_wire_vcc <= '1';
+ wire_w_cp_data_range60w(0) <= cp_data(54);
+ wire_w_rf_sink_data_range697w(0) <= rf_sink_data(36);
+ wire_w_rf_sink_data_range694w(0) <= rf_sink_data(37);
+ wire_w_rf_sink_data_range692w(0) <= rf_sink_data(38);
+ wire_w_rf_sink_data_range690w(0) <= rf_sink_data(39);
+ wire_w_rf_sink_data_range688w(0) <= rf_sink_data(40);
+ wire_w_rf_sink_data_range686w(0) <= rf_sink_data(41);
+ wire_w_rf_sink_data_range684w(0) <= rf_sink_data(42);
+ wire_w_rf_sink_data_range682w(0) <= rf_sink_data(43);
+ wire_w_rf_sink_data_range680w(0) <= rf_sink_data(44);
+ wire_w_rf_sink_data_range678w(0) <= rf_sink_data(45);
+ wire_w_rf_sink_data_range676w(0) <= rf_sink_data(46);
+ wire_w_rf_sink_data_range674w(0) <= rf_sink_data(47);
+ wire_w_rf_sink_data_range672w(0) <= rf_sink_data(48);
+ wire_w_rf_sink_data_range669w(0) <= rf_sink_data(49);
+ wire_w_rf_sink_data_range291w(0) <= rf_sink_data(50);
+ wire_w_rf_sink_data_range292w(0) <= rf_sink_data(53);
+ wire_w_rf_sink_data_range300w(0) <= rf_sink_data(58);
+ wire_w_rf_sink_data_range302w(0) <= rf_sink_data(59);
+ wire_w_rf_sink_data_range305w(0) <= rf_sink_data(60);
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1135q <= '0';
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1082q <= '0';
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1081q <= '0';
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1080q <= '0';
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1079q <= '0';
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1091q <= '0';
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1090q <= '0';
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1089q <= '0';
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1088q <= '0';
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1087q <= '0';
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1086q <= '0';
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1085q <= '0';
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1084q <= '0';
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1083q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1046_dataout = '1') THEN
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1135q <= wire_w_lg_w_rf_sink_data_range697w743w(0);
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1082q <= wire_w_lg_w_rf_sink_data_range676w677w(0);
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1081q <= wire_w_lg_w_rf_sink_data_range674w675w(0);
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1080q <= wire_w_lg_w_rf_sink_data_range672w673w(0);
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1079q <= wire_w_lg_w_rf_sink_data_range669w671w(0);
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1091q <= wire_w_lg_w_rf_sink_data_range694w696w(0);
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1090q <= wire_w_lg_w_rf_sink_data_range692w693w(0);
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1089q <= wire_w_lg_w_rf_sink_data_range690w691w(0);
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1088q <= wire_w_lg_w_rf_sink_data_range688w689w(0);
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1087q <= wire_w_lg_w_rf_sink_data_range686w687w(0);
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1086q <= wire_w_lg_w_rf_sink_data_range684w685w(0);
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1085q <= wire_w_lg_w_rf_sink_data_range682w683w(0);
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1084q <= wire_w_lg_w_rf_sink_data_range680w681w(0);
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1083q <= wire_w_lg_w_rf_sink_data_range678w679w(0);
+ END IF;
+ END IF;
+ END PROCESS;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q <= '0';
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q <= '0';
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q <= '0';
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1024_dataout = '1') THEN
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q <= wire_w667w(0);
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q <= wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout;
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q <= wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1037m_dataout;
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q <= wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1036m_dataout;
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_nl_w620w(0) <= altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q AND wire_nl_w619w(0);
+ wire_nl_w329w(0) <= NOT altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q;
+ wire_nl_w621w(0) <= NOT altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q;
+ wire_nl_w619w(0) <= NOT altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q <= '0';
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q <= '0';
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q <= '0';
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q <= '0';
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q <= '0';
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q <= '0';
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q <= '0';
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q <= '0';
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q <= '0';
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q <= '0';
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q <= '0';
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q <= '0';
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q <= '0';
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout = '1') THEN
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q <= (rf_sink_data(58) AND wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(0));
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(10));
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(11));
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(12));
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(13));
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q <= (rf_sink_data(59) AND wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(1));
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(2));
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(3));
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(4));
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(5));
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(6));
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(7));
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(8));
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(9));
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1027m_dataout <= wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o(3) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout = '1' ELSE wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(3);
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1028m_dataout <= wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o(2) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout = '1' ELSE wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(2);
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout <= wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o(1) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout = '1' ELSE wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(1);
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout <= wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1027m_dataout WHEN altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q = '1' ELSE wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(3);
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1032m_dataout <= wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1028m_dataout WHEN altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q = '1' ELSE wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(2);
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout <= wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout WHEN altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q = '1' ELSE wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(1);
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1036m_dataout <= wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout);
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1037m_dataout <= wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1032m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout);
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout <= wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout);
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1092m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q;
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1093m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q;
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q;
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q;
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q;
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q;
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q;
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q;
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q;
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q;
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q;
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q;
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q;
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q;
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1022m_dataout <= (s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout AND (wire_nl_w620w(0) AND wire_nl_w621w(0))) WHEN altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q = '1' ELSE (s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout AND (((NOT rf_sink_data(55)) AND (NOT rf_sink_data(56))) AND rf_sink_data(57)));
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1176m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q OR altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1135q);
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1166m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1082q OR altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q);
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1165m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1081q OR altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q);
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1164m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1080q OR altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q);
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1163m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1079q OR altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q);
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1175m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1091q OR altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q);
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1174m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1090q OR altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q);
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1173m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1089q OR altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q);
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1172m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1088q OR altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q);
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1171m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1087q OR altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q);
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1170m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1086q OR altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q);
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1169m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1085q OR altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q);
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1168m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1084q OR altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q);
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1167m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1083q OR altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q);
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1015m_dataout <= rf_sink_data(55) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q;
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1014m_dataout <= rf_sink_data(56) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q;
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1013m_dataout <= rf_sink_data(57) WHEN s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q;
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_479m_dataout <= cp_data(55) AND NOT(s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout);
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_478m_dataout <= cp_data(56) AND NOT(s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout);
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_477m_dataout <= cp_data(57) OR s_wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout;
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_a <= ( altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q & altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q & altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q & "1");
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_a,
+ b => wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o
+ );
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_a <= ( rf_sink_data(57 DOWNTO 55) & "1");
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_a,
+ b => wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o
+ );
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_a <= ( wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1092m_dataout & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1093m_dataout & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout
+ & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout & wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout);
+ wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0");
+ altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 14,
+ width_b => 14,
+ width_o => 14
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_a,
+ b => wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o
+ );
+
+ END RTL; --altera_merlin_slave_agent_0016
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0017.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0017.vho
new file mode 100644
index 0000000000000000000000000000000000000000..cff20c326a21da50dbb7a7d26365c1741d668cbc
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_agent/altera_merlin_slave_agent_0017.vho
@@ -0,0 +1,505 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+ LIBRARY sgate;
+ USE sgate.sgate_pack.all;
+
+--synthesis_resources = lut 32 mux21 44 oper_add 3
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_slave_agent_0017 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ cp_channel : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+ cp_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ cp_endofpacket : IN STD_LOGIC;
+ cp_ready : OUT STD_LOGIC;
+ cp_startofpacket : IN STD_LOGIC;
+ cp_valid : IN STD_LOGIC;
+ m0_address : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
+ m0_burstcount : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ m0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+ m0_debugaccess : OUT STD_LOGIC;
+ m0_lock : OUT STD_LOGIC;
+ m0_read : OUT STD_LOGIC;
+ m0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ m0_readdatavalid : IN STD_LOGIC;
+ m0_waitrequest : IN STD_LOGIC;
+ m0_write : OUT STD_LOGIC;
+ m0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_sink_ready : OUT STD_LOGIC;
+ rdata_fifo_sink_valid : IN STD_LOGIC;
+ rdata_fifo_src_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdata_fifo_src_ready : IN STD_LOGIC;
+ rdata_fifo_src_valid : OUT STD_LOGIC;
+ reset : IN STD_LOGIC;
+ rf_sink_data : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
+ rf_sink_endofpacket : IN STD_LOGIC;
+ rf_sink_ready : OUT STD_LOGIC;
+ rf_sink_startofpacket : IN STD_LOGIC;
+ rf_sink_valid : IN STD_LOGIC;
+ rf_source_data : OUT STD_LOGIC_VECTOR (69 DOWNTO 0);
+ rf_source_endofpacket : OUT STD_LOGIC;
+ rf_source_ready : IN STD_LOGIC;
+ rf_source_startofpacket : OUT STD_LOGIC;
+ rf_source_valid : OUT STD_LOGIC;
+ rp_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ rp_endofpacket : OUT STD_LOGIC;
+ rp_ready : IN STD_LOGIC;
+ rp_startofpacket : OUT STD_LOGIC;
+ rp_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_slave_agent_0017;
+
+ ARCHITECTURE RTL OF altera_merlin_slave_agent_0017 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1135q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1082q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1081q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1080q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1079q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1091q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1090q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1089q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1088q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1087q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1086q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1085q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1084q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1083q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q : STD_LOGIC := '0';
+ SIGNAL wire_nl_w620w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w329w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nl_w619w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q : STD_LOGIC := '0';
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1027m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1028m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1032m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1036m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1037m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1092m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1093m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1022m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1176m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1166m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1165m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1164m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1163m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1175m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1174m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1173m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1172m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1171m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1170m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1169m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1168m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1167m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1015m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1014m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1013m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_479m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_478m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_477m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_gnd : STD_LOGIC;
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_a : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_b : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ SIGNAL wire_w_lg_cp_valid61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_rf_source_ready62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range697w743w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range694w696w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range692w693w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range690w691w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range688w689w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range686w687w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range684w685w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range682w683w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range680w681w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range678w679w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range676w677w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range674w675w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range672w673w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range669w671w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_m0_waitrequest598w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_reset613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w667w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w602w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range300w742w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range302w695w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range305w670w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_rf_sink_data_range291w293w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1024_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1046_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_cp_ready_472_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_467_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_local_read_466_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_local_write_465_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_read_473_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_write_480_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_470_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ SIGNAL wire_w_cp_data_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range697w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range694w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range692w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range690w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range688w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range686w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range684w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range682w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range678w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range676w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range674w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range672w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range669w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range292w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range300w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range302w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_rf_sink_data_range305w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+ wire_gnd <= '0';
+ wire_w_lg_cp_valid61w(0) <= cp_valid AND wire_w_cp_data_range60w(0);
+ wire_w_lg_rf_source_ready62w(0) <= rf_source_ready AND wire_w_lg_cp_valid61w(0);
+ wire_w_lg_w_rf_sink_data_range697w743w(0) <= wire_w_rf_sink_data_range697w(0) AND wire_w_lg_w_rf_sink_data_range300w742w(0);
+ wire_w_lg_w_rf_sink_data_range694w696w(0) <= wire_w_rf_sink_data_range694w(0) AND wire_w_lg_w_rf_sink_data_range302w695w(0);
+ wire_w_lg_w_rf_sink_data_range692w693w(0) <= wire_w_rf_sink_data_range692w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range690w691w(0) <= wire_w_rf_sink_data_range690w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range688w689w(0) <= wire_w_rf_sink_data_range688w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range686w687w(0) <= wire_w_rf_sink_data_range686w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range684w685w(0) <= wire_w_rf_sink_data_range684w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range682w683w(0) <= wire_w_rf_sink_data_range682w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range680w681w(0) <= wire_w_rf_sink_data_range680w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range678w679w(0) <= wire_w_rf_sink_data_range678w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range676w677w(0) <= wire_w_rf_sink_data_range676w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range674w675w(0) <= wire_w_rf_sink_data_range674w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range672w673w(0) <= wire_w_rf_sink_data_range672w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_w_rf_sink_data_range669w671w(0) <= wire_w_rf_sink_data_range669w(0) AND wire_w_lg_w_rf_sink_data_range305w670w(0);
+ wire_w_lg_m0_waitrequest598w(0) <= NOT m0_waitrequest;
+ wire_w_lg_reset613w(0) <= NOT reset;
+ wire_w667w(0) <= NOT s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout;
+ wire_w602w(0) <= NOT s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_467_dataout;
+ wire_w_lg_w_rf_sink_data_range300w742w(0) <= NOT wire_w_rf_sink_data_range300w(0);
+ wire_w_lg_w_rf_sink_data_range302w695w(0) <= NOT wire_w_rf_sink_data_range302w(0);
+ wire_w_lg_w_rf_sink_data_range305w670w(0) <= NOT wire_w_rf_sink_data_range305w(0);
+ wire_w_lg_w_rf_sink_data_range291w293w(0) <= wire_w_rf_sink_data_range291w(0) OR wire_w_rf_sink_data_range292w(0);
+ cp_ready <= s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_cp_ready_472_dataout;
+ m0_address <= ( cp_data(49 DOWNTO 36));
+ m0_burstcount <= ( wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_477m_dataout & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_478m_dataout & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_479m_dataout);
+ m0_byteenable <= ( cp_data(35 DOWNTO 32));
+ m0_debugaccess <= cp_data(68);
+ m0_lock <= (wire_w_lg_rf_source_ready62w(0) AND (s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout OR s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_write_480_dataout));
+ m0_read <= s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout;
+ m0_write <= s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_write_480_dataout;
+ m0_writedata <= ( cp_data(31 DOWNTO 0));
+ rdata_fifo_sink_ready <= ((rp_ready AND rdata_fifo_sink_valid) AND (NOT (rf_sink_valid AND rf_sink_data(69))));
+ rdata_fifo_src_data <= ( m0_readdata(31 DOWNTO 0));
+ rdata_fifo_src_valid <= m0_readdatavalid;
+ rf_sink_ready <= (s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout AND s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout);
+ rf_source_data <= ( s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_470_dataout & cp_data(68 DOWNTO 32) & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0");
+ rf_source_endofpacket <= cp_endofpacket;
+ rf_source_startofpacket <= cp_startofpacket;
+ rf_source_valid <= (s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_cp_ready_472_dataout AND (rf_source_ready AND (s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_470_dataout OR s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_read_473_dataout)));
+ rp_data <= ( rf_sink_data(68) & rf_sink_data(64 DOWNTO 62) & rf_sink_data(67 DOWNTO 65) & rf_sink_data(61 DOWNTO 58) & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1013m_dataout & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1014m_dataout & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1015m_dataout & rf_sink_data(54) & wire_w_lg_w_rf_sink_data_range291w293w & rf_sink_data(52 DOWNTO 51) & "0" & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1163m_dataout & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1164m_dataout & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1165m_dataout & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1166m_dataout & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1167m_dataout & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1168m_dataout
+ & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1169m_dataout & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1170m_dataout & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1171m_dataout & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1172m_dataout & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1173m_dataout & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1174m_dataout & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1175m_dataout & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1176m_dataout & rf_sink_data(35 DOWNTO 32) & rdata_fifo_sink_data(31 DOWNTO 0));
+ rp_endofpacket <= (rf_sink_endofpacket AND s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout);
+ rp_startofpacket <= (rf_sink_startofpacket AND wire_nl_w329w(0));
+ rp_valid <= (rdata_fifo_sink_valid OR s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout);
+ s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1024_dataout <= (s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout AND s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout);
+ s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1046_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout);
+ s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout <= (s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout AND wire_nl_w329w(0));
+ s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout <= ((NOT rf_sink_data(50)) OR wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1022m_dataout);
+ s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout <= (rp_ready AND s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout);
+ s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout <= ((altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q OR altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q) OR altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q);
+ s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout <= (rf_sink_valid AND (rf_sink_data(69) OR rdata_fifo_sink_valid));
+ s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_cp_ready_472_dataout <= (wire_w_lg_m0_waitrequest598w(0) AND rf_source_ready);
+ s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_467_dataout <= (cp_valid AND cp_data(50));
+ s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_local_read_466_dataout <= (cp_valid AND cp_data(53));
+ s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_local_write_465_dataout <= (cp_valid AND cp_data(52));
+ s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout <= (s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_local_read_466_dataout AND wire_w602w(0));
+ s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_read_473_dataout <= (s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_local_read_466_dataout OR s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_local_compressed_read_467_dataout);
+ s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_read_474_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_read_473_dataout);
+ s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_write_480_dataout <= (rf_source_ready AND s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_local_write_465_dataout);
+ s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_nonposted_write_endofpacket_470_dataout <= ((NOT cp_data(51)) AND (cp_endofpacket AND s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_local_write_465_dataout));
+ s_wire_vcc <= '1';
+ wire_w_cp_data_range60w(0) <= cp_data(54);
+ wire_w_rf_sink_data_range697w(0) <= rf_sink_data(36);
+ wire_w_rf_sink_data_range694w(0) <= rf_sink_data(37);
+ wire_w_rf_sink_data_range692w(0) <= rf_sink_data(38);
+ wire_w_rf_sink_data_range690w(0) <= rf_sink_data(39);
+ wire_w_rf_sink_data_range688w(0) <= rf_sink_data(40);
+ wire_w_rf_sink_data_range686w(0) <= rf_sink_data(41);
+ wire_w_rf_sink_data_range684w(0) <= rf_sink_data(42);
+ wire_w_rf_sink_data_range682w(0) <= rf_sink_data(43);
+ wire_w_rf_sink_data_range680w(0) <= rf_sink_data(44);
+ wire_w_rf_sink_data_range678w(0) <= rf_sink_data(45);
+ wire_w_rf_sink_data_range676w(0) <= rf_sink_data(46);
+ wire_w_rf_sink_data_range674w(0) <= rf_sink_data(47);
+ wire_w_rf_sink_data_range672w(0) <= rf_sink_data(48);
+ wire_w_rf_sink_data_range669w(0) <= rf_sink_data(49);
+ wire_w_rf_sink_data_range291w(0) <= rf_sink_data(50);
+ wire_w_rf_sink_data_range292w(0) <= rf_sink_data(53);
+ wire_w_rf_sink_data_range300w(0) <= rf_sink_data(58);
+ wire_w_rf_sink_data_range302w(0) <= rf_sink_data(59);
+ wire_w_rf_sink_data_range305w(0) <= rf_sink_data(60);
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1135q <= '0';
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1082q <= '0';
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1081q <= '0';
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1080q <= '0';
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1079q <= '0';
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1091q <= '0';
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1090q <= '0';
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1089q <= '0';
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1088q <= '0';
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1087q <= '0';
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1086q <= '0';
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1085q <= '0';
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1084q <= '0';
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1083q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always1_1046_dataout = '1') THEN
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1135q <= wire_w_lg_w_rf_sink_data_range697w743w(0);
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1082q <= wire_w_lg_w_rf_sink_data_range676w677w(0);
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1081q <= wire_w_lg_w_rf_sink_data_range674w675w(0);
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1080q <= wire_w_lg_w_rf_sink_data_range672w673w(0);
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1079q <= wire_w_lg_w_rf_sink_data_range669w671w(0);
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1091q <= wire_w_lg_w_rf_sink_data_range694w696w(0);
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1090q <= wire_w_lg_w_rf_sink_data_range692w693w(0);
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1089q <= wire_w_lg_w_rf_sink_data_range690w691w(0);
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1088q <= wire_w_lg_w_rf_sink_data_range688w689w(0);
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1087q <= wire_w_lg_w_rf_sink_data_range686w687w(0);
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1086q <= wire_w_lg_w_rf_sink_data_range684w685w(0);
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1085q <= wire_w_lg_w_rf_sink_data_range682w683w(0);
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1084q <= wire_w_lg_w_rf_sink_data_range680w681w(0);
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1083q <= wire_w_lg_w_rf_sink_data_range678w679w(0);
+ END IF;
+ END IF;
+ END PROCESS;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q <= '0';
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q <= '0';
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q <= '0';
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_always0_1024_dataout = '1') THEN
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q <= wire_w667w(0);
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q <= wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout;
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q <= wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1037m_dataout;
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q <= wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1036m_dataout;
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_nl_w620w(0) <= altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q AND wire_nl_w619w(0);
+ wire_nl_w329w(0) <= NOT altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q;
+ wire_nl_w621w(0) <= NOT altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q;
+ wire_nl_w619w(0) <= NOT altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q <= '0';
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q <= '0';
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q <= '0';
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q <= '0';
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q <= '0';
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q <= '0';
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q <= '0';
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q <= '0';
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q <= '0';
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q <= '0';
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q <= '0';
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q <= '0';
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q <= '0';
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_sink_ready_1180_dataout = '1') THEN
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q <= (rf_sink_data(58) AND wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(0));
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(10));
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(11));
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(12));
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(13));
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q <= (rf_sink_data(59) AND wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(1));
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(2));
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(3));
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(4));
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(5));
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(6));
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(7));
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(8));
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q <= (rf_sink_data(60) AND wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o(9));
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1027m_dataout <= wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o(3) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout = '1' ELSE wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(3);
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1028m_dataout <= wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o(2) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout = '1' ELSE wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(2);
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout <= wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o(1) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_wideor0_1025_dataout = '1' ELSE wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(1);
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout <= wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1027m_dataout WHEN altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q = '1' ELSE wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(3);
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1032m_dataout <= wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1028m_dataout WHEN altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q = '1' ELSE wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(2);
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout <= wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1029m_dataout WHEN altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q = '1' ELSE wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o(1);
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1036m_dataout <= wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1031m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout);
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1037m_dataout <= wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1032m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout);
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1038m_dataout <= wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1033m_dataout AND NOT(s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1023_dataout);
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1092m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q;
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1093m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q;
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q;
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q;
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q;
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q;
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q;
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q;
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q;
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q;
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q;
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q;
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q;
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q;
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_last_packet_beat_1022m_dataout <= (s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout AND (wire_nl_w620w(0) AND wire_nl_w621w(0))) WHEN altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_busy_1043q = '1' ELSE (s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_comb_497_dataout AND (((NOT rf_sink_data(55)) AND (NOT rf_sink_data(56))) AND rf_sink_data(57)));
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_0_1176m_dataout <= rf_sink_data(36) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_0_1019q OR altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_0_1135q);
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_10_1166m_dataout <= rf_sink_data(46) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_10_1082q OR altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_10_1139q);
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_11_1165m_dataout <= rf_sink_data(47) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_11_1081q OR altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_11_1138q);
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_12_1164m_dataout <= rf_sink_data(48) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_12_1080q OR altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_12_1137q);
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_13_1163m_dataout <= rf_sink_data(49) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_13_1079q OR altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_13_1136q);
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_1_1175m_dataout <= rf_sink_data(37) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_1_1091q OR altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_1_1148q);
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_2_1174m_dataout <= rf_sink_data(38) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_2_1090q OR altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_2_1147q);
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_3_1173m_dataout <= rf_sink_data(39) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_3_1089q OR altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_3_1146q);
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_4_1172m_dataout <= rf_sink_data(40) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_4_1088q OR altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_4_1145q);
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_5_1171m_dataout <= rf_sink_data(41) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_5_1087q OR altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_5_1144q);
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_6_1170m_dataout <= rf_sink_data(42) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_6_1086q OR altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_6_1143q);
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_7_1169m_dataout <= rf_sink_data(43) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_7_1085q OR altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_7_1142q);
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_8_1168m_dataout <= rf_sink_data(44) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_8_1084q OR altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_8_1141q);
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_addr_9_1167m_dataout <= rf_sink_data(45) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE (altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_base_9_1083q OR altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_address_offset_9_1140q);
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_0_1015m_dataout <= rf_sink_data(55) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q;
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_1_1014m_dataout <= rf_sink_data(56) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q;
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_source_byte_cnt_2_1013m_dataout <= rf_sink_data(57) WHEN s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_first_packet_beat_1012_dataout = '1' ELSE altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q;
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_0_479m_dataout <= cp_data(55) AND NOT(s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout);
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_1_478m_dataout <= cp_data(56) AND NOT(s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout);
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_2_477m_dataout <= cp_data(57) OR s_wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount_476_dataout;
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_a <= ( altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_2_1044q & altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_1_1045q & altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_burst_uncompress_byte_counter_0_1078q & "1");
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_a,
+ b => wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026_o
+ );
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_a <= ( rf_sink_data(57 DOWNTO 55) & "1");
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_b <= ( "0" & "1" & "1" & "1");
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_a,
+ b => wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030_o
+ );
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_a <= ( wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1092m_dataout & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1093m_dataout & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1094m_dataout & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1095m_dataout & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1096m_dataout & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1097m_dataout & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1098m_dataout & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1099m_dataout & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1100m_dataout & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1101m_dataout
+ & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1102m_dataout & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1103m_dataout & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1104m_dataout & wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_comb_1105m_dataout);
+ wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0");
+ altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 14,
+ width_b => 14,
+ width_o => 14
+ )
+ PORT MAP (
+ a => wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_a,
+ b => wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106_o
+ );
+
+ END RTL; --altera_merlin_slave_agent_0017
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_translator/altera_merlin_slave_translator_0001.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_translator/altera_merlin_slave_translator_0001.vho
new file mode 100644
index 0000000000000000000000000000000000000000..203a381df01f2f13ecaa8221c3c796ab9d17e21e
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_translator/altera_merlin_slave_translator_0001.vho
@@ -0,0 +1,78 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_slave_translator_0001 IS
+ PORT
+ (
+ av_address : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
+ av_burstcount : OUT STD_LOGIC;
+ av_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+ av_debugaccess : OUT STD_LOGIC;
+ av_read : OUT STD_LOGIC;
+ av_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ av_readdatavalid : IN STD_LOGIC;
+ av_waitrequest : IN STD_LOGIC;
+ av_write : OUT STD_LOGIC;
+ av_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ clk : IN STD_LOGIC;
+ reset : IN STD_LOGIC;
+ uav_address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
+ uav_burstcount : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+ uav_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+ uav_debugaccess : IN STD_LOGIC;
+ uav_lock : IN STD_LOGIC;
+ uav_read : IN STD_LOGIC;
+ uav_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ uav_readdatavalid : OUT STD_LOGIC;
+ uav_waitrequest : OUT STD_LOGIC;
+ uav_write : IN STD_LOGIC;
+ uav_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
+ );
+ END altera_merlin_slave_translator_0001;
+
+ ARCHITECTURE RTL OF altera_merlin_slave_translator_0001 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ BEGIN
+
+ av_address <= ( uav_address(13 DOWNTO 0));
+ av_burstcount <= uav_burstcount(2);
+ av_byteenable <= ( uav_byteenable(3 DOWNTO 0));
+ av_debugaccess <= uav_debugaccess;
+ av_read <= uav_read;
+ av_write <= uav_write;
+ av_writedata <= ( uav_writedata(31 DOWNTO 0));
+ uav_readdata <= ( av_readdata(31 DOWNTO 0));
+ uav_readdatavalid <= av_readdatavalid;
+ uav_waitrequest <= av_waitrequest;
+
+ END RTL; --altera_merlin_slave_translator_0001
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_translator/altera_merlin_slave_translator_0002.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_translator/altera_merlin_slave_translator_0002.vho
new file mode 100644
index 0000000000000000000000000000000000000000..1dbe9da538bec1853f6bfca34afae042eb3d5ef0
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_translator/altera_merlin_slave_translator_0002.vho
@@ -0,0 +1,99 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources = lut 2
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_slave_translator_0002 IS
+ PORT
+ (
+ av_address : OUT STD_LOGIC;
+ av_read : OUT STD_LOGIC;
+ av_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ av_write : OUT STD_LOGIC;
+ av_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ clk : IN STD_LOGIC;
+ reset : IN STD_LOGIC;
+ uav_address : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
+ uav_burstcount : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+ uav_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+ uav_debugaccess : IN STD_LOGIC;
+ uav_lock : IN STD_LOGIC;
+ uav_read : IN STD_LOGIC;
+ uav_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ uav_readdatavalid : OUT STD_LOGIC;
+ uav_waitrequest : OUT STD_LOGIC;
+ uav_write : IN STD_LOGIC;
+ uav_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
+ );
+ END altera_merlin_slave_translator_0002;
+
+ ARCHITECTURE RTL OF altera_merlin_slave_translator_0002 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_merlin_slave_translator_0002_altera_merlin_slave_translator_tx_eth_pkt_backpressure_control_csr_translator_read_latency_shift_reg_0_175q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_translator_0002_altera_merlin_slave_translator_tx_eth_pkt_backpressure_control_csr_translator_waitrequest_reset_override_168q : STD_LOGIC := '0';
+ SIGNAL wire_nO_w195w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_reset194w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_gnd : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ BEGIN
+
+ wire_w_lg_reset194w(0) <= NOT reset;
+ av_address <= uav_address(2);
+ av_read <= uav_read;
+ av_write <= uav_write;
+ av_writedata <= ( uav_writedata(31 DOWNTO 0));
+ s_wire_gnd <= '0';
+ s_wire_vcc <= '1';
+ uav_readdata <= ( av_readdata(31 DOWNTO 0));
+ uav_readdatavalid <= altera_merlin_slave_translator_0002_altera_merlin_slave_translator_tx_eth_pkt_backpressure_control_csr_translator_read_latency_shift_reg_0_175q;
+ uav_waitrequest <= altera_merlin_slave_translator_0002_altera_merlin_slave_translator_tx_eth_pkt_backpressure_control_csr_translator_waitrequest_reset_override_168q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_translator_0002_altera_merlin_slave_translator_tx_eth_pkt_backpressure_control_csr_translator_read_latency_shift_reg_0_175q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ altera_merlin_slave_translator_0002_altera_merlin_slave_translator_tx_eth_pkt_backpressure_control_csr_translator_read_latency_shift_reg_0_175q <= (uav_read AND wire_nO_w195w(0));
+ END IF;
+ END PROCESS;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_translator_0002_altera_merlin_slave_translator_tx_eth_pkt_backpressure_control_csr_translator_waitrequest_reset_override_168q <= '1';
+ ELSIF (clk = '1' AND clk'event) THEN
+ altera_merlin_slave_translator_0002_altera_merlin_slave_translator_tx_eth_pkt_backpressure_control_csr_translator_waitrequest_reset_override_168q <= s_wire_gnd;
+ END IF;
+ if (now = 0 ns) then
+ altera_merlin_slave_translator_0002_altera_merlin_slave_translator_tx_eth_pkt_backpressure_control_csr_translator_waitrequest_reset_override_168q <= '1' after 1 ps;
+ end if;
+ END PROCESS;
+ wire_nO_w195w(0) <= NOT altera_merlin_slave_translator_0002_altera_merlin_slave_translator_tx_eth_pkt_backpressure_control_csr_translator_waitrequest_reset_override_168q;
+
+ END RTL; --altera_merlin_slave_translator_0002
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_translator/altera_merlin_slave_translator_0003.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_translator/altera_merlin_slave_translator_0003.vho
new file mode 100644
index 0000000000000000000000000000000000000000..80a0f0b0954250b94d60eeb4fb0233c44463af7b
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_translator/altera_merlin_slave_translator_0003.vho
@@ -0,0 +1,99 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources = lut 2
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_slave_translator_0003 IS
+ PORT
+ (
+ av_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+ av_read : OUT STD_LOGIC;
+ av_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ av_write : OUT STD_LOGIC;
+ av_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ clk : IN STD_LOGIC;
+ reset : IN STD_LOGIC;
+ uav_address : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
+ uav_burstcount : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+ uav_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+ uav_debugaccess : IN STD_LOGIC;
+ uav_lock : IN STD_LOGIC;
+ uav_read : IN STD_LOGIC;
+ uav_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ uav_readdatavalid : OUT STD_LOGIC;
+ uav_waitrequest : OUT STD_LOGIC;
+ uav_write : IN STD_LOGIC;
+ uav_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
+ );
+ END altera_merlin_slave_translator_0003;
+
+ ARCHITECTURE RTL OF altera_merlin_slave_translator_0003 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_merlin_slave_translator_0003_altera_merlin_slave_translator_tx_eth_pause_ctrl_gen_csr_translator_read_latency_shift_reg_0_176q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_translator_0003_altera_merlin_slave_translator_tx_eth_pause_ctrl_gen_csr_translator_waitrequest_reset_override_169q : STD_LOGIC := '0';
+ SIGNAL wire_nO_w200w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_reset199w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_gnd : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ BEGIN
+
+ wire_w_lg_reset199w(0) <= NOT reset;
+ av_address <= ( uav_address(3 DOWNTO 2));
+ av_read <= uav_read;
+ av_write <= uav_write;
+ av_writedata <= ( uav_writedata(31 DOWNTO 0));
+ s_wire_gnd <= '0';
+ s_wire_vcc <= '1';
+ uav_readdata <= ( av_readdata(31 DOWNTO 0));
+ uav_readdatavalid <= altera_merlin_slave_translator_0003_altera_merlin_slave_translator_tx_eth_pause_ctrl_gen_csr_translator_read_latency_shift_reg_0_176q;
+ uav_waitrequest <= altera_merlin_slave_translator_0003_altera_merlin_slave_translator_tx_eth_pause_ctrl_gen_csr_translator_waitrequest_reset_override_169q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_translator_0003_altera_merlin_slave_translator_tx_eth_pause_ctrl_gen_csr_translator_read_latency_shift_reg_0_176q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ altera_merlin_slave_translator_0003_altera_merlin_slave_translator_tx_eth_pause_ctrl_gen_csr_translator_read_latency_shift_reg_0_176q <= (uav_read AND wire_nO_w200w(0));
+ END IF;
+ END PROCESS;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_translator_0003_altera_merlin_slave_translator_tx_eth_pause_ctrl_gen_csr_translator_waitrequest_reset_override_169q <= '1';
+ ELSIF (clk = '1' AND clk'event) THEN
+ altera_merlin_slave_translator_0003_altera_merlin_slave_translator_tx_eth_pause_ctrl_gen_csr_translator_waitrequest_reset_override_169q <= s_wire_gnd;
+ END IF;
+ if (now = 0 ns) then
+ altera_merlin_slave_translator_0003_altera_merlin_slave_translator_tx_eth_pause_ctrl_gen_csr_translator_waitrequest_reset_override_169q <= '1' after 1 ps;
+ end if;
+ END PROCESS;
+ wire_nO_w200w(0) <= NOT altera_merlin_slave_translator_0003_altera_merlin_slave_translator_tx_eth_pause_ctrl_gen_csr_translator_waitrequest_reset_override_169q;
+
+ END RTL; --altera_merlin_slave_translator_0003
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_translator/altera_merlin_slave_translator_0004.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_translator/altera_merlin_slave_translator_0004.vho
new file mode 100644
index 0000000000000000000000000000000000000000..fafe5e285f1c60054b877b9bfb63d1fd7fae3e1f
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_translator/altera_merlin_slave_translator_0004.vho
@@ -0,0 +1,95 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources = lut 2
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_slave_translator_0004 IS
+ PORT
+ (
+ av_address : OUT STD_LOGIC;
+ av_read : OUT STD_LOGIC;
+ av_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ clk : IN STD_LOGIC;
+ reset : IN STD_LOGIC;
+ uav_address : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
+ uav_burstcount : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+ uav_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+ uav_debugaccess : IN STD_LOGIC;
+ uav_lock : IN STD_LOGIC;
+ uav_read : IN STD_LOGIC;
+ uav_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ uav_readdatavalid : OUT STD_LOGIC;
+ uav_waitrequest : OUT STD_LOGIC;
+ uav_write : IN STD_LOGIC;
+ uav_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
+ );
+ END altera_merlin_slave_translator_0004;
+
+ ARCHITECTURE RTL OF altera_merlin_slave_translator_0004 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_merlin_slave_translator_0004_altera_merlin_slave_translator_tx_eth_packet_underflow_control_avalon_slave_0_translator_read_latency_shift_reg_0_142q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_translator_0004_altera_merlin_slave_translator_tx_eth_packet_underflow_control_avalon_slave_0_translator_waitrequest_reset_override_135q : STD_LOGIC := '0';
+ SIGNAL wire_nO_w99w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_reset98w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_gnd : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ BEGIN
+
+ wire_w_lg_reset98w(0) <= NOT reset;
+ av_address <= uav_address(2);
+ av_read <= uav_read;
+ s_wire_gnd <= '0';
+ s_wire_vcc <= '1';
+ uav_readdata <= ( av_readdata(31 DOWNTO 0));
+ uav_readdatavalid <= altera_merlin_slave_translator_0004_altera_merlin_slave_translator_tx_eth_packet_underflow_control_avalon_slave_0_translator_read_latency_shift_reg_0_142q;
+ uav_waitrequest <= altera_merlin_slave_translator_0004_altera_merlin_slave_translator_tx_eth_packet_underflow_control_avalon_slave_0_translator_waitrequest_reset_override_135q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_translator_0004_altera_merlin_slave_translator_tx_eth_packet_underflow_control_avalon_slave_0_translator_read_latency_shift_reg_0_142q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ altera_merlin_slave_translator_0004_altera_merlin_slave_translator_tx_eth_packet_underflow_control_avalon_slave_0_translator_read_latency_shift_reg_0_142q <= (uav_read AND wire_nO_w99w(0));
+ END IF;
+ END PROCESS;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_translator_0004_altera_merlin_slave_translator_tx_eth_packet_underflow_control_avalon_slave_0_translator_waitrequest_reset_override_135q <= '1';
+ ELSIF (clk = '1' AND clk'event) THEN
+ altera_merlin_slave_translator_0004_altera_merlin_slave_translator_tx_eth_packet_underflow_control_avalon_slave_0_translator_waitrequest_reset_override_135q <= s_wire_gnd;
+ END IF;
+ if (now = 0 ns) then
+ altera_merlin_slave_translator_0004_altera_merlin_slave_translator_tx_eth_packet_underflow_control_avalon_slave_0_translator_waitrequest_reset_override_135q <= '1' after 1 ps;
+ end if;
+ END PROCESS;
+ wire_nO_w99w(0) <= NOT altera_merlin_slave_translator_0004_altera_merlin_slave_translator_tx_eth_packet_underflow_control_avalon_slave_0_translator_waitrequest_reset_override_135q;
+
+ END RTL; --altera_merlin_slave_translator_0004
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_translator/altera_merlin_slave_translator_0005.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_translator/altera_merlin_slave_translator_0005.vho
new file mode 100644
index 0000000000000000000000000000000000000000..d0a3bc8c7dc3afac40574b49eaf92e949ba5a9de
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_translator/altera_merlin_slave_translator_0005.vho
@@ -0,0 +1,99 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources = lut 2
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_slave_translator_0005 IS
+ PORT
+ (
+ av_address : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+ av_read : OUT STD_LOGIC;
+ av_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ av_write : OUT STD_LOGIC;
+ av_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ clk : IN STD_LOGIC;
+ reset : IN STD_LOGIC;
+ uav_address : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
+ uav_burstcount : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+ uav_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+ uav_debugaccess : IN STD_LOGIC;
+ uav_lock : IN STD_LOGIC;
+ uav_read : IN STD_LOGIC;
+ uav_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ uav_readdatavalid : OUT STD_LOGIC;
+ uav_waitrequest : OUT STD_LOGIC;
+ uav_write : IN STD_LOGIC;
+ uav_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
+ );
+ END altera_merlin_slave_translator_0005;
+
+ ARCHITECTURE RTL OF altera_merlin_slave_translator_0005 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_merlin_slave_translator_0005_altera_merlin_slave_translator_tx_eth_frame_decoder_avalom_mm_csr_translator_read_latency_shift_reg_0_179q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_translator_0005_altera_merlin_slave_translator_tx_eth_frame_decoder_avalom_mm_csr_translator_waitrequest_reset_override_172q : STD_LOGIC := '0';
+ SIGNAL wire_nO_w209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_reset208w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_gnd : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ BEGIN
+
+ wire_w_lg_reset208w(0) <= NOT reset;
+ av_address <= ( uav_address(6 DOWNTO 2));
+ av_read <= uav_read;
+ av_write <= uav_write;
+ av_writedata <= ( uav_writedata(31 DOWNTO 0));
+ s_wire_gnd <= '0';
+ s_wire_vcc <= '1';
+ uav_readdata <= ( av_readdata(31 DOWNTO 0));
+ uav_readdatavalid <= altera_merlin_slave_translator_0005_altera_merlin_slave_translator_tx_eth_frame_decoder_avalom_mm_csr_translator_read_latency_shift_reg_0_179q;
+ uav_waitrequest <= altera_merlin_slave_translator_0005_altera_merlin_slave_translator_tx_eth_frame_decoder_avalom_mm_csr_translator_waitrequest_reset_override_172q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_translator_0005_altera_merlin_slave_translator_tx_eth_frame_decoder_avalom_mm_csr_translator_read_latency_shift_reg_0_179q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ altera_merlin_slave_translator_0005_altera_merlin_slave_translator_tx_eth_frame_decoder_avalom_mm_csr_translator_read_latency_shift_reg_0_179q <= (uav_read AND wire_nO_w209w(0));
+ END IF;
+ END PROCESS;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_translator_0005_altera_merlin_slave_translator_tx_eth_frame_decoder_avalom_mm_csr_translator_waitrequest_reset_override_172q <= '1';
+ ELSIF (clk = '1' AND clk'event) THEN
+ altera_merlin_slave_translator_0005_altera_merlin_slave_translator_tx_eth_frame_decoder_avalom_mm_csr_translator_waitrequest_reset_override_172q <= s_wire_gnd;
+ END IF;
+ if (now = 0 ns) then
+ altera_merlin_slave_translator_0005_altera_merlin_slave_translator_tx_eth_frame_decoder_avalom_mm_csr_translator_waitrequest_reset_override_172q <= '1' after 1 ps;
+ end if;
+ END PROCESS;
+ wire_nO_w209w(0) <= NOT altera_merlin_slave_translator_0005_altera_merlin_slave_translator_tx_eth_frame_decoder_avalom_mm_csr_translator_waitrequest_reset_override_172q;
+
+ END RTL; --altera_merlin_slave_translator_0005
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_translator/altera_merlin_slave_translator_0006.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_translator/altera_merlin_slave_translator_0006.vho
new file mode 100644
index 0000000000000000000000000000000000000000..e6d5d8118e5cc0b8192b82243a52e676df1a8ecc
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_translator/altera_merlin_slave_translator_0006.vho
@@ -0,0 +1,102 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources = lut 3
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_slave_translator_0006 IS
+ PORT
+ (
+ av_address : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+ av_read : OUT STD_LOGIC;
+ av_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ av_write : OUT STD_LOGIC;
+ av_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ clk : IN STD_LOGIC;
+ reset : IN STD_LOGIC;
+ uav_address : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
+ uav_burstcount : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+ uav_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+ uav_debugaccess : IN STD_LOGIC;
+ uav_lock : IN STD_LOGIC;
+ uav_read : IN STD_LOGIC;
+ uav_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ uav_readdatavalid : OUT STD_LOGIC;
+ uav_waitrequest : OUT STD_LOGIC;
+ uav_write : IN STD_LOGIC;
+ uav_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
+ );
+ END altera_merlin_slave_translator_0006;
+
+ ARCHITECTURE RTL OF altera_merlin_slave_translator_0006 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_merlin_slave_translator_0006_altera_merlin_slave_translator_tx_eth_statistics_collector_csr_translator_read_latency_shift_reg_0_185q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_translator_0006_altera_merlin_slave_translator_tx_eth_statistics_collector_csr_translator_read_latency_shift_reg_1_174q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_translator_0006_altera_merlin_slave_translator_tx_eth_statistics_collector_csr_translator_waitrequest_reset_override_173q : STD_LOGIC := '0';
+ SIGNAL wire_nO_w212w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_reset211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_gnd : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ BEGIN
+
+ wire_w_lg_reset211w(0) <= NOT reset;
+ av_address <= ( uav_address(7 DOWNTO 2));
+ av_read <= uav_read;
+ av_write <= uav_write;
+ av_writedata <= ( uav_writedata(31 DOWNTO 0));
+ s_wire_gnd <= '0';
+ s_wire_vcc <= '1';
+ uav_readdata <= ( av_readdata(31 DOWNTO 0));
+ uav_readdatavalid <= altera_merlin_slave_translator_0006_altera_merlin_slave_translator_tx_eth_statistics_collector_csr_translator_read_latency_shift_reg_1_174q;
+ uav_waitrequest <= altera_merlin_slave_translator_0006_altera_merlin_slave_translator_tx_eth_statistics_collector_csr_translator_waitrequest_reset_override_173q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_translator_0006_altera_merlin_slave_translator_tx_eth_statistics_collector_csr_translator_read_latency_shift_reg_0_185q <= '0';
+ altera_merlin_slave_translator_0006_altera_merlin_slave_translator_tx_eth_statistics_collector_csr_translator_read_latency_shift_reg_1_174q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ altera_merlin_slave_translator_0006_altera_merlin_slave_translator_tx_eth_statistics_collector_csr_translator_read_latency_shift_reg_0_185q <= (uav_read AND wire_nO_w212w(0));
+ altera_merlin_slave_translator_0006_altera_merlin_slave_translator_tx_eth_statistics_collector_csr_translator_read_latency_shift_reg_1_174q <= altera_merlin_slave_translator_0006_altera_merlin_slave_translator_tx_eth_statistics_collector_csr_translator_read_latency_shift_reg_0_185q;
+ END IF;
+ END PROCESS;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_translator_0006_altera_merlin_slave_translator_tx_eth_statistics_collector_csr_translator_waitrequest_reset_override_173q <= '1';
+ ELSIF (clk = '1' AND clk'event) THEN
+ altera_merlin_slave_translator_0006_altera_merlin_slave_translator_tx_eth_statistics_collector_csr_translator_waitrequest_reset_override_173q <= s_wire_gnd;
+ END IF;
+ if (now = 0 ns) then
+ altera_merlin_slave_translator_0006_altera_merlin_slave_translator_tx_eth_statistics_collector_csr_translator_waitrequest_reset_override_173q <= '1' after 1 ps;
+ end if;
+ END PROCESS;
+ wire_nO_w212w(0) <= NOT altera_merlin_slave_translator_0006_altera_merlin_slave_translator_tx_eth_statistics_collector_csr_translator_waitrequest_reset_override_173q;
+
+ END RTL; --altera_merlin_slave_translator_0006
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_translator/altera_merlin_slave_translator_0007.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_translator/altera_merlin_slave_translator_0007.vho
new file mode 100644
index 0000000000000000000000000000000000000000..9e13d8f240fdf959c6f96d4b2a902e9db38b7404
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_slave_translator/altera_merlin_slave_translator_0007.vho
@@ -0,0 +1,95 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources = lut 2
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_slave_translator_0007 IS
+ PORT
+ (
+ av_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+ av_read : OUT STD_LOGIC;
+ av_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ clk : IN STD_LOGIC;
+ reset : IN STD_LOGIC;
+ uav_address : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
+ uav_burstcount : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+ uav_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+ uav_debugaccess : IN STD_LOGIC;
+ uav_lock : IN STD_LOGIC;
+ uav_read : IN STD_LOGIC;
+ uav_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ uav_readdatavalid : OUT STD_LOGIC;
+ uav_waitrequest : OUT STD_LOGIC;
+ uav_write : IN STD_LOGIC;
+ uav_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
+ );
+ END altera_merlin_slave_translator_0007;
+
+ ARCHITECTURE RTL OF altera_merlin_slave_translator_0007 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_merlin_slave_translator_0007_altera_merlin_slave_translator_rx_eth_packet_overflow_control_csr_translator_read_latency_shift_reg_0_143q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_slave_translator_0007_altera_merlin_slave_translator_rx_eth_packet_overflow_control_csr_translator_waitrequest_reset_override_136q : STD_LOGIC := '0';
+ SIGNAL wire_nO_w104w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_reset103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_gnd : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ BEGIN
+
+ wire_w_lg_reset103w(0) <= NOT reset;
+ av_address <= ( uav_address(3 DOWNTO 2));
+ av_read <= uav_read;
+ s_wire_gnd <= '0';
+ s_wire_vcc <= '1';
+ uav_readdata <= ( av_readdata(31 DOWNTO 0));
+ uav_readdatavalid <= altera_merlin_slave_translator_0007_altera_merlin_slave_translator_rx_eth_packet_overflow_control_csr_translator_read_latency_shift_reg_0_143q;
+ uav_waitrequest <= altera_merlin_slave_translator_0007_altera_merlin_slave_translator_rx_eth_packet_overflow_control_csr_translator_waitrequest_reset_override_136q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_translator_0007_altera_merlin_slave_translator_rx_eth_packet_overflow_control_csr_translator_read_latency_shift_reg_0_143q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ altera_merlin_slave_translator_0007_altera_merlin_slave_translator_rx_eth_packet_overflow_control_csr_translator_read_latency_shift_reg_0_143q <= (uav_read AND wire_nO_w104w(0));
+ END IF;
+ END PROCESS;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_slave_translator_0007_altera_merlin_slave_translator_rx_eth_packet_overflow_control_csr_translator_waitrequest_reset_override_136q <= '1';
+ ELSIF (clk = '1' AND clk'event) THEN
+ altera_merlin_slave_translator_0007_altera_merlin_slave_translator_rx_eth_packet_overflow_control_csr_translator_waitrequest_reset_override_136q <= s_wire_gnd;
+ END IF;
+ if (now = 0 ns) then
+ altera_merlin_slave_translator_0007_altera_merlin_slave_translator_rx_eth_packet_overflow_control_csr_translator_waitrequest_reset_override_136q <= '1' after 1 ps;
+ end if;
+ END PROCESS;
+ wire_nO_w104w(0) <= NOT altera_merlin_slave_translator_0007_altera_merlin_slave_translator_rx_eth_packet_overflow_control_csr_translator_waitrequest_reset_override_136q;
+
+ END RTL; --altera_merlin_slave_translator_0007
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_traffic_limiter/altera_merlin_traffic_limiter_0001.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_traffic_limiter/altera_merlin_traffic_limiter_0001.vho
new file mode 100644
index 0000000000000000000000000000000000000000..694f8bc56bef9665675277fd7c8557f501f25cfa
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_traffic_limiter/altera_merlin_traffic_limiter_0001.vho
@@ -0,0 +1,245 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+ LIBRARY sgate;
+ USE sgate.sgate_pack.all;
+
+--synthesis_resources = lut 7 mux21 10 oper_add 2
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_traffic_limiter_0001 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ cmd_sink_channel : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+ cmd_sink_data : IN STD_LOGIC_VECTOR (65 DOWNTO 0);
+ cmd_sink_endofpacket : IN STD_LOGIC;
+ cmd_sink_ready : OUT STD_LOGIC;
+ cmd_sink_startofpacket : IN STD_LOGIC;
+ cmd_sink_valid : IN STD_LOGIC;
+ cmd_src_channel : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+ cmd_src_data : OUT STD_LOGIC_VECTOR (65 DOWNTO 0);
+ cmd_src_endofpacket : OUT STD_LOGIC;
+ cmd_src_ready : IN STD_LOGIC;
+ cmd_src_startofpacket : OUT STD_LOGIC;
+ cmd_src_valid : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+ reset : IN STD_LOGIC;
+ rsp_sink_channel : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+ rsp_sink_data : IN STD_LOGIC_VECTOR (65 DOWNTO 0);
+ rsp_sink_endofpacket : IN STD_LOGIC;
+ rsp_sink_ready : OUT STD_LOGIC;
+ rsp_sink_startofpacket : IN STD_LOGIC;
+ rsp_sink_valid : IN STD_LOGIC;
+ rsp_src_channel : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+ rsp_src_data : OUT STD_LOGIC_VECTOR (65 DOWNTO 0);
+ rsp_src_endofpacket : OUT STD_LOGIC;
+ rsp_src_ready : IN STD_LOGIC;
+ rsp_src_startofpacket : OUT STD_LOGIC;
+ rsp_src_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_traffic_limiter_0001;
+
+ ARCHITECTURE RTL OF altera_merlin_traffic_limiter_0001 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_pending_response_count_0_343q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_pending_response_count_1_342q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_pending_response_count_2_341q : STD_LOGIC := '0';
+ SIGNAL wire_ni_w_lg_w_lg_w413w415w423w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_ni_w_lg_w_lg_w413w415w416w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_ni_w_lg_w413w415w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_ni_w422w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_ni_w414w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_ni_w413w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_last_channel_0_337q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_last_channel_1_305q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_last_dest_id_0_304q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_has_pending_responses_293q : STD_LOGIC := '0';
+ SIGNAL wire_nO_w420w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_cmd_sink_ready_346m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_cmd_src_valid_0_353m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_cmd_src_valid_1_352m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_internal_valid_347m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_next_pending_response_count_314m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_next_pending_response_count_315m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_next_pending_response_count_316m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_next_pending_response_count_318m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_next_pending_response_count_319m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_next_pending_response_count_320m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add0_313_a : STD_LOGIC_VECTOR (2 DOWNTO 0);
+ SIGNAL wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add0_313_b : STD_LOGIC_VECTOR (2 DOWNTO 0);
+ SIGNAL wire_gnd : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add0_313_o : STD_LOGIC_VECTOR (2 DOWNTO 0);
+ SIGNAL wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add1_317_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add1_317_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add1_317_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL wire_w_lg_w412w418w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_cmd_sink_data_range157w428w432w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_cmd_sink_valid430w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w424w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w417w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w412w418w419w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_reset427w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w470w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w412w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w421w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w429w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_cmd_sink_data_range157w428w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_always1_321_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_cmd_src_valid_348_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_cmd_src_valid_349_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_nonposted_cmd_accepted_310_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_response_accepted_312_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_save_dest_id_298_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_suppress_344_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_suppress_345_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ SIGNAL wire_w_cmd_sink_data_range157w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+ wire_gnd <= '0';
+ wire_w_lg_w412w418w(0) <= wire_w412w(0) AND wire_w417w(0);
+ wire_w_lg_w_lg_w_cmd_sink_data_range157w428w432w(0) <= wire_w_lg_w_cmd_sink_data_range157w428w(0) AND wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_internal_valid_347m_dataout;
+ wire_w_lg_cmd_sink_valid430w(0) <= cmd_sink_valid AND wire_w429w(0);
+ wire_w424w(0) <= s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_nonposted_cmd_accepted_310_dataout AND wire_ni_w_lg_w_lg_w413w415w423w(0);
+ wire_w417w(0) <= s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_response_accepted_312_dataout AND wire_ni_w_lg_w_lg_w413w415w416w(0);
+ wire_w_lg_w_lg_w412w418w419w(0) <= NOT wire_w_lg_w412w418w(0);
+ wire_w_lg_reset427w(0) <= NOT reset;
+ wire_w470w(0) <= NOT s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_always1_321_dataout;
+ wire_w412w(0) <= NOT s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_nonposted_cmd_accepted_310_dataout;
+ wire_w421w(0) <= NOT s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_response_accepted_312_dataout;
+ wire_w429w(0) <= NOT s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_suppress_345_dataout;
+ wire_w_lg_w_cmd_sink_data_range157w428w(0) <= NOT wire_w_cmd_sink_data_range157w(0);
+ cmd_sink_ready <= wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_cmd_sink_ready_346m_dataout;
+ cmd_src_channel <= ( cmd_sink_channel(1 DOWNTO 0));
+ cmd_src_data <= ( cmd_sink_data(65 DOWNTO 0));
+ cmd_src_endofpacket <= cmd_sink_endofpacket;
+ cmd_src_startofpacket <= cmd_sink_startofpacket;
+ cmd_src_valid <= ( wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_cmd_src_valid_1_352m_dataout & wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_cmd_src_valid_0_353m_dataout);
+ rsp_sink_ready <= rsp_src_ready;
+ rsp_src_channel <= ( rsp_sink_channel(1 DOWNTO 0));
+ rsp_src_data <= ( rsp_sink_data(65 DOWNTO 0));
+ rsp_src_endofpacket <= rsp_sink_endofpacket;
+ rsp_src_startofpacket <= rsp_sink_startofpacket;
+ rsp_src_valid <= rsp_sink_valid;
+ s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_always1_321_dataout <= (s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_nonposted_cmd_accepted_310_dataout AND s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_response_accepted_312_dataout);
+ s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_cmd_src_valid_348_dataout <= (cmd_sink_valid AND cmd_sink_channel(0));
+ s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_cmd_src_valid_349_dataout <= (cmd_sink_valid AND cmd_sink_channel(1));
+ s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_nonposted_cmd_accepted_310_dataout <= (wire_w_lg_w_lg_w_cmd_sink_data_range157w428w432w(0) AND (cmd_sink_endofpacket AND cmd_src_ready));
+ s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_response_accepted_312_dataout <= (rsp_sink_endofpacket AND (rsp_sink_valid AND rsp_src_ready));
+ s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_save_dest_id_298_dataout <= (wire_w_lg_w_cmd_sink_data_range157w428w(0) AND wire_w_lg_cmd_sink_valid430w(0));
+ s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_suppress_344_dataout <= (wire_w_lg_w_cmd_sink_data_range157w428w(0) AND altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_has_pending_responses_293q);
+ s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_suppress_345_dataout <= ((cmd_sink_data(64) XOR altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_last_dest_id_0_304q) AND s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_suppress_344_dataout);
+ s_wire_vcc <= '1';
+ wire_w_cmd_sink_data_range157w(0) <= cmd_sink_data(52);
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_pending_response_count_0_343q <= '0';
+ altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_pending_response_count_1_342q <= '0';
+ altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_pending_response_count_2_341q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_always1_321_dataout = '0') THEN
+ altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_pending_response_count_0_343q <= wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_next_pending_response_count_320m_dataout;
+ altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_pending_response_count_1_342q <= wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_next_pending_response_count_319m_dataout;
+ altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_pending_response_count_2_341q <= wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_next_pending_response_count_318m_dataout;
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_ni_w_lg_w_lg_w413w415w423w(0) <= wire_ni_w_lg_w413w415w(0) AND wire_ni_w422w(0);
+ wire_ni_w_lg_w_lg_w413w415w416w(0) <= wire_ni_w_lg_w413w415w(0) AND altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_pending_response_count_0_343q;
+ wire_ni_w_lg_w413w415w(0) <= wire_ni_w413w(0) AND wire_ni_w414w(0);
+ wire_ni_w422w(0) <= NOT altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_pending_response_count_0_343q;
+ wire_ni_w414w(0) <= NOT altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_pending_response_count_1_342q;
+ wire_ni_w413w(0) <= NOT altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_pending_response_count_2_341q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_last_channel_0_337q <= '0';
+ altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_last_channel_1_305q <= '0';
+ altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_last_dest_id_0_304q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_save_dest_id_298_dataout = '1') THEN
+ altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_last_channel_0_337q <= cmd_sink_channel(0);
+ altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_last_channel_1_305q <= cmd_sink_channel(1);
+ altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_last_dest_id_0_304q <= cmd_sink_data(64);
+ END IF;
+ END IF;
+ END PROCESS;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_has_pending_responses_293q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_has_pending_responses_293q <= (wire_nO_w420w(0) OR (wire_w421w(0) AND wire_w424w(0)));
+ END IF;
+ END PROCESS;
+ wire_nO_w420w(0) <= altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_has_pending_responses_293q AND wire_w_lg_w_lg_w412w418w419w(0);
+ wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_cmd_sink_ready_346m_dataout <= cmd_src_ready AND NOT(s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_suppress_345_dataout);
+ wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_cmd_src_valid_0_353m_dataout <= (altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_last_channel_0_337q AND s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_cmd_src_valid_348_dataout) WHEN s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_suppress_344_dataout = '1' ELSE s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_cmd_src_valid_348_dataout;
+ wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_cmd_src_valid_1_352m_dataout <= (altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_last_channel_1_305q AND s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_cmd_src_valid_349_dataout) WHEN s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_suppress_344_dataout = '1' ELSE s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_cmd_src_valid_349_dataout;
+ wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_internal_valid_347m_dataout <= cmd_sink_valid AND NOT(s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_suppress_345_dataout);
+ wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_next_pending_response_count_314m_dataout <= wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add0_313_o(2) WHEN s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_nonposted_cmd_accepted_310_dataout = '1' ELSE altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_pending_response_count_2_341q;
+ wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_next_pending_response_count_315m_dataout <= wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add0_313_o(1) WHEN s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_nonposted_cmd_accepted_310_dataout = '1' ELSE altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_pending_response_count_1_342q;
+ wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_next_pending_response_count_316m_dataout <= wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add0_313_o(0) WHEN s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_nonposted_cmd_accepted_310_dataout = '1' ELSE altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_pending_response_count_0_343q;
+ wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_next_pending_response_count_318m_dataout <= wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add1_317_o(3) WHEN s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_response_accepted_312_dataout = '1' ELSE wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_next_pending_response_count_314m_dataout;
+ wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_next_pending_response_count_319m_dataout <= wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add1_317_o(2) WHEN s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_response_accepted_312_dataout = '1' ELSE wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_next_pending_response_count_315m_dataout;
+ wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_next_pending_response_count_320m_dataout <= wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add1_317_o(1) WHEN s_wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_response_accepted_312_dataout = '1' ELSE wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_next_pending_response_count_316m_dataout;
+ wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add0_313_a <= ( altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_pending_response_count_2_341q & altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_pending_response_count_1_342q & altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_pending_response_count_0_343q);
+ wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add0_313_b <= ( "0" & "0" & "1");
+ altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add0_313 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 3,
+ width_b => 3,
+ width_o => 3
+ )
+ PORT MAP (
+ a => wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add0_313_a,
+ b => wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add0_313_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add0_313_o
+ );
+ wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add1_317_a <= ( altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_pending_response_count_2_341q & altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_pending_response_count_1_342q & altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_pending_response_count_0_343q & "1");
+ wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add1_317_b <= ( "1" & "1" & "0" & "1");
+ altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add1_317 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 4,
+ width_b => 4,
+ width_o => 4
+ )
+ PORT MAP (
+ a => wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add1_317_a,
+ b => wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add1_317_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add1_317_o
+ );
+
+ END RTL; --altera_merlin_traffic_limiter_0001
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_traffic_limiter/altera_merlin_traffic_limiter_0002.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_traffic_limiter/altera_merlin_traffic_limiter_0002.vho
new file mode 100644
index 0000000000000000000000000000000000000000..9f9ee4eb8aef8892fa40710f8869cb355892cc4b
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_traffic_limiter/altera_merlin_traffic_limiter_0002.vho
@@ -0,0 +1,282 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+ LIBRARY sgate;
+ USE sgate.sgate_pack.all;
+
+--synthesis_resources = lut 14 mux21 14 oper_add 2
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_traffic_limiter_0002 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ cmd_sink_channel : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ cmd_sink_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ cmd_sink_endofpacket : IN STD_LOGIC;
+ cmd_sink_ready : OUT STD_LOGIC;
+ cmd_sink_startofpacket : IN STD_LOGIC;
+ cmd_sink_valid : IN STD_LOGIC;
+ cmd_src_channel : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ cmd_src_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ cmd_src_endofpacket : OUT STD_LOGIC;
+ cmd_src_ready : IN STD_LOGIC;
+ cmd_src_startofpacket : OUT STD_LOGIC;
+ cmd_src_valid : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ reset : IN STD_LOGIC;
+ rsp_sink_channel : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ rsp_sink_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ rsp_sink_endofpacket : IN STD_LOGIC;
+ rsp_sink_ready : OUT STD_LOGIC;
+ rsp_sink_startofpacket : IN STD_LOGIC;
+ rsp_sink_valid : IN STD_LOGIC;
+ rsp_src_channel : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ rsp_src_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ rsp_src_endofpacket : OUT STD_LOGIC;
+ rsp_src_ready : IN STD_LOGIC;
+ rsp_src_startofpacket : OUT STD_LOGIC;
+ rsp_src_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_traffic_limiter_0002;
+
+ ARCHITECTURE RTL OF altera_merlin_traffic_limiter_0002 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_pending_response_count_0_405q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_pending_response_count_1_404q : STD_LOGIC := '0';
+ SIGNAL wire_ni_w_lg_w478w486w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_ni_w_lg_w478w479w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_ni_w485w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_ni_w478w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_has_pending_responses_370q : STD_LOGIC := '0';
+ SIGNAL wire_nl_w483w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_0_401q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_1_369q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_2_368q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_3_367q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_4_366q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_5_365q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_6_364q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_7_363q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_dest_id_0_362q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_dest_id_1_361q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_dest_id_2_360q : STD_LOGIC := '0';
+ SIGNAL wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_sink_ready_408m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_0_433m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_1_432m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_2_431m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_3_430m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_4_429m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_5_428m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_6_427m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_7_426m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_internal_valid_409m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_next_pending_response_count_381m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_next_pending_response_count_382m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_next_pending_response_count_384m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_next_pending_response_count_385m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add0_380_a : STD_LOGIC_VECTOR (1 DOWNTO 0);
+ SIGNAL wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add0_380_b : STD_LOGIC_VECTOR (1 DOWNTO 0);
+ SIGNAL wire_gnd : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add0_380_o : STD_LOGIC_VECTOR (1 DOWNTO 0);
+ SIGNAL wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add1_383_a : STD_LOGIC_VECTOR (2 DOWNTO 0);
+ SIGNAL wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add1_383_b : STD_LOGIC_VECTOR (2 DOWNTO 0);
+ SIGNAL wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add1_383_o : STD_LOGIC_VECTOR (2 DOWNTO 0);
+ SIGNAL wire_w_lg_w477w481w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_cmd_sink_data_range154w472w490w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_cmd_sink_valid474w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w487w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w480w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w477w481w482w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_reset476w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w520w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w477w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w484w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w473w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_cmd_sink_data_range154w472w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_always1_386_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_410_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_411_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_412_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_413_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_414_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_415_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_416_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_417_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_nonposted_cmd_accepted_377_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_response_accepted_379_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_save_dest_id_338_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_suppress_406_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_suppress_407_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ SIGNAL wire_w_cmd_sink_data_range154w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+ wire_gnd <= '0';
+ wire_w_lg_w477w481w(0) <= wire_w477w(0) AND wire_w480w(0);
+ wire_w_lg_w_lg_w_cmd_sink_data_range154w472w490w(0) <= wire_w_lg_w_cmd_sink_data_range154w472w(0) AND wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_internal_valid_409m_dataout;
+ wire_w_lg_cmd_sink_valid474w(0) <= cmd_sink_valid AND wire_w473w(0);
+ wire_w487w(0) <= s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_nonposted_cmd_accepted_377_dataout AND wire_ni_w_lg_w478w486w(0);
+ wire_w480w(0) <= s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_response_accepted_379_dataout AND wire_ni_w_lg_w478w479w(0);
+ wire_w_lg_w_lg_w477w481w482w(0) <= NOT wire_w_lg_w477w481w(0);
+ wire_w_lg_reset476w(0) <= NOT reset;
+ wire_w520w(0) <= NOT s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_always1_386_dataout;
+ wire_w477w(0) <= NOT s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_nonposted_cmd_accepted_377_dataout;
+ wire_w484w(0) <= NOT s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_response_accepted_379_dataout;
+ wire_w473w(0) <= NOT s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_suppress_407_dataout;
+ wire_w_lg_w_cmd_sink_data_range154w472w(0) <= NOT wire_w_cmd_sink_data_range154w(0);
+ cmd_sink_ready <= wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_sink_ready_408m_dataout;
+ cmd_src_channel <= ( cmd_sink_channel(7 DOWNTO 0));
+ cmd_src_data <= ( cmd_sink_data(68 DOWNTO 0));
+ cmd_src_endofpacket <= cmd_sink_endofpacket;
+ cmd_src_startofpacket <= cmd_sink_startofpacket;
+ cmd_src_valid <= ( wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_7_426m_dataout & wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_6_427m_dataout & wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_5_428m_dataout & wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_4_429m_dataout & wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_3_430m_dataout & wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_2_431m_dataout & wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_1_432m_dataout & wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_0_433m_dataout);
+ rsp_sink_ready <= rsp_src_ready;
+ rsp_src_channel <= ( rsp_sink_channel(7 DOWNTO 0));
+ rsp_src_data <= ( rsp_sink_data(68 DOWNTO 0));
+ rsp_src_endofpacket <= rsp_sink_endofpacket;
+ rsp_src_startofpacket <= rsp_sink_startofpacket;
+ rsp_src_valid <= rsp_sink_valid;
+ s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_always1_386_dataout <= (s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_nonposted_cmd_accepted_377_dataout AND s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_response_accepted_379_dataout);
+ s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_410_dataout <= (cmd_sink_valid AND cmd_sink_channel(0));
+ s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_411_dataout <= (cmd_sink_valid AND cmd_sink_channel(1));
+ s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_412_dataout <= (cmd_sink_valid AND cmd_sink_channel(2));
+ s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_413_dataout <= (cmd_sink_valid AND cmd_sink_channel(3));
+ s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_414_dataout <= (cmd_sink_valid AND cmd_sink_channel(4));
+ s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_415_dataout <= (cmd_sink_valid AND cmd_sink_channel(5));
+ s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_416_dataout <= (cmd_sink_valid AND cmd_sink_channel(6));
+ s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_417_dataout <= (cmd_sink_valid AND cmd_sink_channel(7));
+ s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_nonposted_cmd_accepted_377_dataout <= (wire_w_lg_w_lg_w_cmd_sink_data_range154w472w490w(0) AND (cmd_sink_endofpacket AND cmd_src_ready));
+ s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_response_accepted_379_dataout <= (rsp_sink_endofpacket AND (rsp_sink_valid AND rsp_src_ready));
+ s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_save_dest_id_338_dataout <= (wire_w_lg_w_cmd_sink_data_range154w472w(0) AND wire_w_lg_cmd_sink_valid474w(0));
+ s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_suppress_406_dataout <= (wire_w_lg_w_cmd_sink_data_range154w472w(0) AND altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_has_pending_responses_370q);
+ s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_suppress_407_dataout <= (s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_suppress_406_dataout AND (NOT (((NOT (cmd_sink_data(65) XOR altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_dest_id_0_362q)) AND (NOT (cmd_sink_data(66) XOR altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_dest_id_1_361q))) AND (NOT (cmd_sink_data(67) XOR altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_dest_id_2_360q)))));
+ s_wire_vcc <= '1';
+ wire_w_cmd_sink_data_range154w(0) <= cmd_sink_data(51);
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_pending_response_count_0_405q <= '0';
+ altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_pending_response_count_1_404q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_always1_386_dataout = '0') THEN
+ altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_pending_response_count_0_405q <= wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_next_pending_response_count_385m_dataout;
+ altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_pending_response_count_1_404q <= wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_next_pending_response_count_384m_dataout;
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_ni_w_lg_w478w486w(0) <= wire_ni_w478w(0) AND wire_ni_w485w(0);
+ wire_ni_w_lg_w478w479w(0) <= wire_ni_w478w(0) AND altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_pending_response_count_0_405q;
+ wire_ni_w485w(0) <= NOT altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_pending_response_count_0_405q;
+ wire_ni_w478w(0) <= NOT altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_pending_response_count_1_404q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_has_pending_responses_370q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_has_pending_responses_370q <= (wire_nl_w483w(0) OR (wire_w484w(0) AND wire_w487w(0)));
+ END IF;
+ END PROCESS;
+ wire_nl_w483w(0) <= altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_has_pending_responses_370q AND wire_w_lg_w_lg_w477w481w482w(0);
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_0_401q <= '0';
+ altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_1_369q <= '0';
+ altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_2_368q <= '0';
+ altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_3_367q <= '0';
+ altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_4_366q <= '0';
+ altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_5_365q <= '0';
+ altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_6_364q <= '0';
+ altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_7_363q <= '0';
+ altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_dest_id_0_362q <= '0';
+ altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_dest_id_1_361q <= '0';
+ altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_dest_id_2_360q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_save_dest_id_338_dataout = '1') THEN
+ altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_0_401q <= cmd_sink_channel(0);
+ altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_1_369q <= cmd_sink_channel(1);
+ altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_2_368q <= cmd_sink_channel(2);
+ altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_3_367q <= cmd_sink_channel(3);
+ altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_4_366q <= cmd_sink_channel(4);
+ altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_5_365q <= cmd_sink_channel(5);
+ altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_6_364q <= cmd_sink_channel(6);
+ altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_7_363q <= cmd_sink_channel(7);
+ altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_dest_id_0_362q <= cmd_sink_data(65);
+ altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_dest_id_1_361q <= cmd_sink_data(66);
+ altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_dest_id_2_360q <= cmd_sink_data(67);
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_sink_ready_408m_dataout <= cmd_src_ready AND NOT(s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_suppress_407_dataout);
+ wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_0_433m_dataout <= (altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_0_401q AND s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_410_dataout) WHEN s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_suppress_406_dataout = '1' ELSE s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_410_dataout;
+ wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_1_432m_dataout <= (altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_1_369q AND s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_411_dataout) WHEN s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_suppress_406_dataout = '1' ELSE s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_411_dataout;
+ wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_2_431m_dataout <= (altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_2_368q AND s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_412_dataout) WHEN s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_suppress_406_dataout = '1' ELSE s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_412_dataout;
+ wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_3_430m_dataout <= (altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_3_367q AND s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_413_dataout) WHEN s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_suppress_406_dataout = '1' ELSE s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_413_dataout;
+ wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_4_429m_dataout <= (altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_4_366q AND s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_414_dataout) WHEN s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_suppress_406_dataout = '1' ELSE s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_414_dataout;
+ wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_5_428m_dataout <= (altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_5_365q AND s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_415_dataout) WHEN s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_suppress_406_dataout = '1' ELSE s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_415_dataout;
+ wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_6_427m_dataout <= (altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_6_364q AND s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_416_dataout) WHEN s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_suppress_406_dataout = '1' ELSE s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_416_dataout;
+ wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_7_426m_dataout <= (altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_last_channel_7_363q AND s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_417_dataout) WHEN s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_suppress_406_dataout = '1' ELSE s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_cmd_src_valid_417_dataout;
+ wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_internal_valid_409m_dataout <= cmd_sink_valid AND NOT(s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_suppress_407_dataout);
+ wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_next_pending_response_count_381m_dataout <= wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add0_380_o(1) WHEN s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_nonposted_cmd_accepted_377_dataout = '1' ELSE altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_pending_response_count_1_404q;
+ wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_next_pending_response_count_382m_dataout <= wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add0_380_o(0) WHEN s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_nonposted_cmd_accepted_377_dataout = '1' ELSE altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_pending_response_count_0_405q;
+ wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_next_pending_response_count_384m_dataout <= wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add1_383_o(2) WHEN s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_response_accepted_379_dataout = '1' ELSE wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_next_pending_response_count_381m_dataout;
+ wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_next_pending_response_count_385m_dataout <= wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add1_383_o(1) WHEN s_wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_response_accepted_379_dataout = '1' ELSE wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_next_pending_response_count_382m_dataout;
+ wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add0_380_a <= ( altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_pending_response_count_1_404q & altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_pending_response_count_0_405q);
+ wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add0_380_b <= ( "0" & "1");
+ altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add0_380 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 2,
+ width_b => 2,
+ width_o => 2
+ )
+ PORT MAP (
+ a => wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add0_380_a,
+ b => wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add0_380_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add0_380_o
+ );
+ wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add1_383_a <= ( altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_pending_response_count_1_404q & altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_pending_response_count_0_405q & "1");
+ wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add1_383_b <= ( "1" & "0" & "1");
+ altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add1_383 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 3,
+ width_b => 3,
+ width_o => 3
+ )
+ PORT MAP (
+ a => wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add1_383_a,
+ b => wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add1_383_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add1_383_o
+ );
+
+ END RTL; --altera_merlin_traffic_limiter_0002
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_traffic_limiter/altera_merlin_traffic_limiter_0003.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_traffic_limiter/altera_merlin_traffic_limiter_0003.vho
new file mode 100644
index 0000000000000000000000000000000000000000..f8b153d2902bd6bc22437153b5f00b9e7f71878f
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_traffic_limiter/altera_merlin_traffic_limiter_0003.vho
@@ -0,0 +1,275 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+ LIBRARY sgate;
+ USE sgate.sgate_pack.all;
+
+--synthesis_resources = lut 13 mux21 13 oper_add 2
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_merlin_traffic_limiter_0003 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ cmd_sink_channel : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+ cmd_sink_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ cmd_sink_endofpacket : IN STD_LOGIC;
+ cmd_sink_ready : OUT STD_LOGIC;
+ cmd_sink_startofpacket : IN STD_LOGIC;
+ cmd_sink_valid : IN STD_LOGIC;
+ cmd_src_channel : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
+ cmd_src_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ cmd_src_endofpacket : OUT STD_LOGIC;
+ cmd_src_ready : IN STD_LOGIC;
+ cmd_src_startofpacket : OUT STD_LOGIC;
+ cmd_src_valid : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
+ reset : IN STD_LOGIC;
+ rsp_sink_channel : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+ rsp_sink_data : IN STD_LOGIC_VECTOR (68 DOWNTO 0);
+ rsp_sink_endofpacket : IN STD_LOGIC;
+ rsp_sink_ready : OUT STD_LOGIC;
+ rsp_sink_startofpacket : IN STD_LOGIC;
+ rsp_sink_valid : IN STD_LOGIC;
+ rsp_src_channel : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
+ rsp_src_data : OUT STD_LOGIC_VECTOR (68 DOWNTO 0);
+ rsp_src_endofpacket : OUT STD_LOGIC;
+ rsp_src_ready : IN STD_LOGIC;
+ rsp_src_startofpacket : OUT STD_LOGIC;
+ rsp_src_valid : OUT STD_LOGIC
+ );
+ END altera_merlin_traffic_limiter_0003;
+
+ ARCHITECTURE RTL OF altera_merlin_traffic_limiter_0003 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_pending_response_count_0_397q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_pending_response_count_1_396q : STD_LOGIC := '0';
+ SIGNAL wire_ni_w_lg_w471w479w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_ni_w_lg_w471w472w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_ni_w478w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_ni_w471w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_has_pending_responses_362q : STD_LOGIC := '0';
+ SIGNAL wire_nl_w476w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_channel_0_393q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_channel_1_361q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_channel_2_360q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_channel_3_359q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_channel_4_358q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_channel_5_357q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_channel_6_356q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_dest_id_0_355q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_dest_id_1_354q : STD_LOGIC := '0';
+ SIGNAL altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_dest_id_2_353q : STD_LOGIC := '0';
+ SIGNAL wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_sink_ready_400m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_0_422m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_1_421m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_2_420m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_3_419m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_4_418m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_5_417m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_6_416m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_internal_valid_401m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_next_pending_response_count_373m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_next_pending_response_count_374m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_next_pending_response_count_376m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_next_pending_response_count_377m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add0_372_a : STD_LOGIC_VECTOR (1 DOWNTO 0);
+ SIGNAL wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add0_372_b : STD_LOGIC_VECTOR (1 DOWNTO 0);
+ SIGNAL wire_gnd : STD_LOGIC;
+ SIGNAL wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add0_372_o : STD_LOGIC_VECTOR (1 DOWNTO 0);
+ SIGNAL wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add1_375_a : STD_LOGIC_VECTOR (2 DOWNTO 0);
+ SIGNAL wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add1_375_b : STD_LOGIC_VECTOR (2 DOWNTO 0);
+ SIGNAL wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add1_375_o : STD_LOGIC_VECTOR (2 DOWNTO 0);
+ SIGNAL wire_w_lg_w470w474w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w_cmd_sink_data_range154w465w483w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_cmd_sink_valid467w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w480w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w473w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_lg_w470w474w475w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_reset469w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w513w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w470w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w477w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w466w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_w_cmd_sink_data_range154w465w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_always1_378_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_402_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_403_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_404_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_405_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_406_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_407_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_408_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_nonposted_cmd_accepted_369_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_response_accepted_371_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_save_dest_id_333_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_suppress_398_dataout : STD_LOGIC;
+ SIGNAL s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_suppress_399_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ SIGNAL wire_w_cmd_sink_data_range154w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+ wire_gnd <= '0';
+ wire_w_lg_w470w474w(0) <= wire_w470w(0) AND wire_w473w(0);
+ wire_w_lg_w_lg_w_cmd_sink_data_range154w465w483w(0) <= wire_w_lg_w_cmd_sink_data_range154w465w(0) AND wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_internal_valid_401m_dataout;
+ wire_w_lg_cmd_sink_valid467w(0) <= cmd_sink_valid AND wire_w466w(0);
+ wire_w480w(0) <= s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_nonposted_cmd_accepted_369_dataout AND wire_ni_w_lg_w471w479w(0);
+ wire_w473w(0) <= s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_response_accepted_371_dataout AND wire_ni_w_lg_w471w472w(0);
+ wire_w_lg_w_lg_w470w474w475w(0) <= NOT wire_w_lg_w470w474w(0);
+ wire_w_lg_reset469w(0) <= NOT reset;
+ wire_w513w(0) <= NOT s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_always1_378_dataout;
+ wire_w470w(0) <= NOT s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_nonposted_cmd_accepted_369_dataout;
+ wire_w477w(0) <= NOT s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_response_accepted_371_dataout;
+ wire_w466w(0) <= NOT s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_suppress_399_dataout;
+ wire_w_lg_w_cmd_sink_data_range154w465w(0) <= NOT wire_w_cmd_sink_data_range154w(0);
+ cmd_sink_ready <= wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_sink_ready_400m_dataout;
+ cmd_src_channel <= ( cmd_sink_channel(6 DOWNTO 0));
+ cmd_src_data <= ( cmd_sink_data(68 DOWNTO 0));
+ cmd_src_endofpacket <= cmd_sink_endofpacket;
+ cmd_src_startofpacket <= cmd_sink_startofpacket;
+ cmd_src_valid <= ( wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_6_416m_dataout & wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_5_417m_dataout & wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_4_418m_dataout & wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_3_419m_dataout & wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_2_420m_dataout & wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_1_421m_dataout & wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_0_422m_dataout);
+ rsp_sink_ready <= rsp_src_ready;
+ rsp_src_channel <= ( rsp_sink_channel(6 DOWNTO 0));
+ rsp_src_data <= ( rsp_sink_data(68 DOWNTO 0));
+ rsp_src_endofpacket <= rsp_sink_endofpacket;
+ rsp_src_startofpacket <= rsp_sink_startofpacket;
+ rsp_src_valid <= rsp_sink_valid;
+ s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_always1_378_dataout <= (s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_nonposted_cmd_accepted_369_dataout AND s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_response_accepted_371_dataout);
+ s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_402_dataout <= (cmd_sink_valid AND cmd_sink_channel(0));
+ s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_403_dataout <= (cmd_sink_valid AND cmd_sink_channel(1));
+ s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_404_dataout <= (cmd_sink_valid AND cmd_sink_channel(2));
+ s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_405_dataout <= (cmd_sink_valid AND cmd_sink_channel(3));
+ s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_406_dataout <= (cmd_sink_valid AND cmd_sink_channel(4));
+ s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_407_dataout <= (cmd_sink_valid AND cmd_sink_channel(5));
+ s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_408_dataout <= (cmd_sink_valid AND cmd_sink_channel(6));
+ s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_nonposted_cmd_accepted_369_dataout <= (wire_w_lg_w_lg_w_cmd_sink_data_range154w465w483w(0) AND (cmd_sink_endofpacket AND cmd_src_ready));
+ s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_response_accepted_371_dataout <= (rsp_sink_endofpacket AND (rsp_sink_valid AND rsp_src_ready));
+ s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_save_dest_id_333_dataout <= (wire_w_lg_w_cmd_sink_data_range154w465w(0) AND wire_w_lg_cmd_sink_valid467w(0));
+ s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_suppress_398_dataout <= (wire_w_lg_w_cmd_sink_data_range154w465w(0) AND altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_has_pending_responses_362q);
+ s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_suppress_399_dataout <= (s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_suppress_398_dataout AND (NOT (((NOT (cmd_sink_data(65) XOR altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_dest_id_0_355q)) AND (NOT (cmd_sink_data(66) XOR altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_dest_id_1_354q))) AND (NOT (cmd_sink_data(67) XOR altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_dest_id_2_353q)))));
+ s_wire_vcc <= '1';
+ wire_w_cmd_sink_data_range154w(0) <= cmd_sink_data(51);
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_pending_response_count_0_397q <= '0';
+ altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_pending_response_count_1_396q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_always1_378_dataout = '0') THEN
+ altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_pending_response_count_0_397q <= wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_next_pending_response_count_377m_dataout;
+ altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_pending_response_count_1_396q <= wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_next_pending_response_count_376m_dataout;
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_ni_w_lg_w471w479w(0) <= wire_ni_w471w(0) AND wire_ni_w478w(0);
+ wire_ni_w_lg_w471w472w(0) <= wire_ni_w471w(0) AND altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_pending_response_count_0_397q;
+ wire_ni_w478w(0) <= NOT altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_pending_response_count_0_397q;
+ wire_ni_w471w(0) <= NOT altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_pending_response_count_1_396q;
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_has_pending_responses_362q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_has_pending_responses_362q <= (wire_nl_w476w(0) OR (wire_w477w(0) AND wire_w480w(0)));
+ END IF;
+ END PROCESS;
+ wire_nl_w476w(0) <= altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_has_pending_responses_362q AND wire_w_lg_w_lg_w470w474w475w(0);
+ PROCESS (clk, reset)
+ BEGIN
+ IF (reset = '1') THEN
+ altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_channel_0_393q <= '0';
+ altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_channel_1_361q <= '0';
+ altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_channel_2_360q <= '0';
+ altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_channel_3_359q <= '0';
+ altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_channel_4_358q <= '0';
+ altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_channel_5_357q <= '0';
+ altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_channel_6_356q <= '0';
+ altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_dest_id_0_355q <= '0';
+ altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_dest_id_1_354q <= '0';
+ altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_dest_id_2_353q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_save_dest_id_333_dataout = '1') THEN
+ altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_channel_0_393q <= cmd_sink_channel(0);
+ altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_channel_1_361q <= cmd_sink_channel(1);
+ altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_channel_2_360q <= cmd_sink_channel(2);
+ altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_channel_3_359q <= cmd_sink_channel(3);
+ altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_channel_4_358q <= cmd_sink_channel(4);
+ altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_channel_5_357q <= cmd_sink_channel(5);
+ altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_channel_6_356q <= cmd_sink_channel(6);
+ altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_dest_id_0_355q <= cmd_sink_data(65);
+ altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_dest_id_1_354q <= cmd_sink_data(66);
+ altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_dest_id_2_353q <= cmd_sink_data(67);
+ END IF;
+ END IF;
+ END PROCESS;
+ wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_sink_ready_400m_dataout <= cmd_src_ready AND NOT(s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_suppress_399_dataout);
+ wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_0_422m_dataout <= (altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_channel_0_393q AND s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_402_dataout) WHEN s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_suppress_398_dataout = '1' ELSE s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_402_dataout;
+ wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_1_421m_dataout <= (altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_channel_1_361q AND s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_403_dataout) WHEN s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_suppress_398_dataout = '1' ELSE s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_403_dataout;
+ wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_2_420m_dataout <= (altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_channel_2_360q AND s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_404_dataout) WHEN s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_suppress_398_dataout = '1' ELSE s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_404_dataout;
+ wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_3_419m_dataout <= (altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_channel_3_359q AND s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_405_dataout) WHEN s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_suppress_398_dataout = '1' ELSE s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_405_dataout;
+ wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_4_418m_dataout <= (altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_channel_4_358q AND s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_406_dataout) WHEN s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_suppress_398_dataout = '1' ELSE s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_406_dataout;
+ wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_5_417m_dataout <= (altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_channel_5_357q AND s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_407_dataout) WHEN s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_suppress_398_dataout = '1' ELSE s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_407_dataout;
+ wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_6_416m_dataout <= (altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_last_channel_6_356q AND s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_408_dataout) WHEN s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_suppress_398_dataout = '1' ELSE s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_cmd_src_valid_408_dataout;
+ wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_internal_valid_401m_dataout <= cmd_sink_valid AND NOT(s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_suppress_399_dataout);
+ wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_next_pending_response_count_373m_dataout <= wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add0_372_o(1) WHEN s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_nonposted_cmd_accepted_369_dataout = '1' ELSE altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_pending_response_count_1_396q;
+ wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_next_pending_response_count_374m_dataout <= wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add0_372_o(0) WHEN s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_nonposted_cmd_accepted_369_dataout = '1' ELSE altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_pending_response_count_0_397q;
+ wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_next_pending_response_count_376m_dataout <= wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add1_375_o(2) WHEN s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_response_accepted_371_dataout = '1' ELSE wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_next_pending_response_count_373m_dataout;
+ wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_next_pending_response_count_377m_dataout <= wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add1_375_o(1) WHEN s_wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_response_accepted_371_dataout = '1' ELSE wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_next_pending_response_count_374m_dataout;
+ wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add0_372_a <= ( altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_pending_response_count_1_396q & altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_pending_response_count_0_397q);
+ wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add0_372_b <= ( "0" & "1");
+ altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add0_372 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 2,
+ width_b => 2,
+ width_o => 2
+ )
+ PORT MAP (
+ a => wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add0_372_a,
+ b => wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add0_372_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add0_372_o
+ );
+ wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add1_375_a <= ( altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_pending_response_count_1_396q & altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_pending_response_count_0_397q & "1");
+ wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add1_375_b <= ( "1" & "0" & "1");
+ altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add1_375 : oper_add
+ GENERIC MAP (
+ sgate_representation => 0,
+ width_a => 3,
+ width_b => 3,
+ width_o => 3
+ )
+ PORT MAP (
+ a => wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add1_375_a,
+ b => wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add1_375_b,
+ cin => wire_gnd,
+ o => wire_altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add1_375_o
+ );
+
+ END RTL; --altera_merlin_traffic_limiter_0003
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_reset_controller/altera_reset_controller_0001.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_reset_controller/altera_reset_controller_0001.vho
new file mode 100644
index 0000000000000000000000000000000000000000..cc4c4d8a10a89de90480bf40c8ab70a4bcfb092a
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_reset_controller/altera_reset_controller_0001.vho
@@ -0,0 +1,79 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources = lut 3
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY altera_reset_controller_0001 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ reset_in0 : IN STD_LOGIC;
+ reset_out : OUT STD_LOGIC
+ );
+ END altera_reset_controller_0001;
+
+ ARCHITECTURE RTL OF altera_reset_controller_0001 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL altera_reset_controller_0001_altera_reset_controller_rst_controller_altera_reset_synchronizer_alt_rst_sync_uq1_altera_reset_synchronizer_int_chain_0_46q : STD_LOGIC := '0';
+ SIGNAL altera_reset_controller_0001_altera_reset_controller_rst_controller_altera_reset_synchronizer_alt_rst_sync_uq1_altera_reset_synchronizer_int_chain_1_45q : STD_LOGIC := '0';
+ SIGNAL altera_reset_controller_0001_altera_reset_controller_rst_controller_altera_reset_synchronizer_alt_rst_sync_uq1_altera_reset_synchronizer_int_chain_out_47q : STD_LOGIC := '0';
+ SIGNAL wire_w_lg_reset_in01w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_gnd : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ BEGIN
+
+ wire_w_lg_reset_in01w(0) <= NOT reset_in0;
+ reset_out <= altera_reset_controller_0001_altera_reset_controller_rst_controller_altera_reset_synchronizer_alt_rst_sync_uq1_altera_reset_synchronizer_int_chain_out_47q;
+ s_wire_gnd <= '0';
+ s_wire_vcc <= '1';
+ PROCESS (clk, reset_in0)
+ BEGIN
+ IF (reset_in0 = '1') THEN
+ altera_reset_controller_0001_altera_reset_controller_rst_controller_altera_reset_synchronizer_alt_rst_sync_uq1_altera_reset_synchronizer_int_chain_0_46q <= '1';
+ altera_reset_controller_0001_altera_reset_controller_rst_controller_altera_reset_synchronizer_alt_rst_sync_uq1_altera_reset_synchronizer_int_chain_1_45q <= '1';
+ altera_reset_controller_0001_altera_reset_controller_rst_controller_altera_reset_synchronizer_alt_rst_sync_uq1_altera_reset_synchronizer_int_chain_out_47q <= '1';
+ ELSIF (clk = '1' AND clk'event) THEN
+ altera_reset_controller_0001_altera_reset_controller_rst_controller_altera_reset_synchronizer_alt_rst_sync_uq1_altera_reset_synchronizer_int_chain_0_46q <= altera_reset_controller_0001_altera_reset_controller_rst_controller_altera_reset_synchronizer_alt_rst_sync_uq1_altera_reset_synchronizer_int_chain_1_45q;
+ altera_reset_controller_0001_altera_reset_controller_rst_controller_altera_reset_synchronizer_alt_rst_sync_uq1_altera_reset_synchronizer_int_chain_1_45q <= s_wire_gnd;
+ altera_reset_controller_0001_altera_reset_controller_rst_controller_altera_reset_synchronizer_alt_rst_sync_uq1_altera_reset_synchronizer_int_chain_out_47q <= altera_reset_controller_0001_altera_reset_controller_rst_controller_altera_reset_synchronizer_alt_rst_sync_uq1_altera_reset_synchronizer_int_chain_0_46q;
+ END IF;
+ if (now = 0 ns) then
+ altera_reset_controller_0001_altera_reset_controller_rst_controller_altera_reset_synchronizer_alt_rst_sync_uq1_altera_reset_synchronizer_int_chain_0_46q <= '1' after 1 ps;
+ end if;
+ if (now = 0 ns) then
+ altera_reset_controller_0001_altera_reset_controller_rst_controller_altera_reset_synchronizer_alt_rst_sync_uq1_altera_reset_synchronizer_int_chain_1_45q <= '1' after 1 ps;
+ end if;
+ if (now = 0 ns) then
+ altera_reset_controller_0001_altera_reset_controller_rst_controller_altera_reset_synchronizer_alt_rst_sync_uq1_altera_reset_synchronizer_int_chain_out_47q <= '1' after 1 ps;
+ end if;
+ END PROCESS;
+
+ END RTL; --altera_reset_controller_0001
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/error_adapter/error_adapter_0001.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/error_adapter/error_adapter_0001.vho
new file mode 100644
index 0000000000000000000000000000000000000000..bd8b81d413aacf94035de8c2e8edd2ff2c5a5427
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/error_adapter/error_adapter_0001.vho
@@ -0,0 +1,68 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY error_adapter_0001 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ in_data : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+ in_empty : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+ in_endofpacket : IN STD_LOGIC;
+ in_error : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
+ in_ready : OUT STD_LOGIC;
+ in_startofpacket : IN STD_LOGIC;
+ in_valid : IN STD_LOGIC;
+ out_data : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
+ out_empty : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ out_endofpacket : OUT STD_LOGIC;
+ out_error : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+ out_ready : IN STD_LOGIC;
+ out_startofpacket : OUT STD_LOGIC;
+ out_valid : OUT STD_LOGIC;
+ reset_n : IN STD_LOGIC
+ );
+ END error_adapter_0001;
+
+ ARCHITECTURE RTL OF error_adapter_0001 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ BEGIN
+
+ in_ready <= out_ready;
+ out_data <= ( in_data(63 DOWNTO 0));
+ out_empty <= ( in_empty(2 DOWNTO 0));
+ out_endofpacket <= in_endofpacket;
+ out_error <= ( "0" & in_error(0));
+ out_startofpacket <= in_startofpacket;
+ out_valid <= in_valid;
+
+ END RTL; --error_adapter_0001
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/error_adapter/error_adapter_0002.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/error_adapter/error_adapter_0002.vho
new file mode 100644
index 0000000000000000000000000000000000000000..83e3e6d8fa1133d4ca1d369b27b3ec31ab18edac
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/error_adapter/error_adapter_0002.vho
@@ -0,0 +1,56 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY error_adapter_0002 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ in_data : IN STD_LOGIC_VECTOR (39 DOWNTO 0);
+ in_error : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
+ in_valid : IN STD_LOGIC;
+ out_data : OUT STD_LOGIC_VECTOR (39 DOWNTO 0);
+ out_error : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
+ out_valid : OUT STD_LOGIC;
+ reset_n : IN STD_LOGIC
+ );
+ END error_adapter_0002;
+
+ ARCHITECTURE RTL OF error_adapter_0002 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ BEGIN
+
+ out_data <= ( in_data(39 DOWNTO 0));
+ out_error <= ( "0" & in_error(0) & in_error(1) & in_error(2) & in_error(5 DOWNTO 3));
+ out_valid <= in_valid;
+
+ END RTL; --error_adapter_0002
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/error_adapter/error_adapter_0003.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/error_adapter/error_adapter_0003.vho
new file mode 100644
index 0000000000000000000000000000000000000000..800057f264bdb94024ea413dcf0d0d19820ba4c8
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/error_adapter/error_adapter_0003.vho
@@ -0,0 +1,56 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY error_adapter_0003 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ in_data : IN STD_LOGIC_VECTOR (39 DOWNTO 0);
+ in_error : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
+ in_valid : IN STD_LOGIC;
+ out_data : OUT STD_LOGIC_VECTOR (39 DOWNTO 0);
+ out_error : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
+ out_valid : OUT STD_LOGIC;
+ reset_n : IN STD_LOGIC
+ );
+ END error_adapter_0003;
+
+ ARCHITECTURE RTL OF error_adapter_0003 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ BEGIN
+
+ out_data <= ( in_data(39 DOWNTO 0));
+ out_error <= ( in_error(0) & "0" & "0" & in_error(1) & in_error(4 DOWNTO 2));
+ out_valid <= in_valid;
+
+ END RTL; --error_adapter_0003
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g.vhd b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e923c16e6559846e88243b402f3b8e8354ffb1c2
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g.vhd
@@ -0,0 +1,7920 @@
+-- ip_stratixiv_mac_10g.vhd
+
+-- This file was auto-generated from altera_eth_10g_mac_hw.tcl. If you edit it your changes
+-- will probably be lost.
+--
+-- Generated using ACDS version 11.1sp2 259 at 2014.10.02.11:39:51
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity ip_stratixiv_mac_10g is
+ port (
+ csr_clk_clk : in std_logic := '0'; -- csr_clk.clk
+ csr_reset_reset_n : in std_logic := '0'; -- csr_reset.reset_n
+ csr_address : in std_logic_vector(12 downto 0) := (others => '0'); -- csr.address
+ csr_waitrequest : out std_logic; -- .waitrequest
+ csr_read : in std_logic := '0'; -- .read
+ csr_readdata : out std_logic_vector(31 downto 0); -- .readdata
+ csr_write : in std_logic := '0'; -- .write
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ tx_clk_clk : in std_logic := '0'; -- tx_clk.clk
+ tx_reset_reset_n : in std_logic := '0'; -- tx_reset.reset_n
+ avalon_st_tx_startofpacket : in std_logic := '0'; -- avalon_st_tx.startofpacket
+ avalon_st_tx_valid : in std_logic := '0'; -- .valid
+ avalon_st_tx_data : in std_logic_vector(63 downto 0) := (others => '0'); -- .data
+ avalon_st_tx_empty : in std_logic_vector(2 downto 0) := (others => '0'); -- .empty
+ avalon_st_tx_ready : out std_logic; -- .ready
+ avalon_st_tx_error : in std_logic_vector(0 downto 0) := (others => '0'); -- .error
+ avalon_st_tx_endofpacket : in std_logic := '0'; -- .endofpacket
+ avalon_st_pause_data : in std_logic_vector(1 downto 0) := (others => '0'); -- avalon_st_pause.data
+ xgmii_tx_data : out std_logic_vector(71 downto 0); -- xgmii_tx.data
+ avalon_st_txstatus_valid : out std_logic; -- avalon_st_txstatus.valid
+ avalon_st_txstatus_data : out std_logic_vector(39 downto 0); -- .data
+ avalon_st_txstatus_error : out std_logic_vector(6 downto 0); -- .error
+ rx_clk_clk : in std_logic := '0'; -- rx_clk.clk
+ rx_reset_reset_n : in std_logic := '0'; -- rx_reset.reset_n
+ xgmii_rx_data : in std_logic_vector(71 downto 0) := (others => '0'); -- xgmii_rx.data
+ avalon_st_rx_startofpacket : out std_logic; -- avalon_st_rx.startofpacket
+ avalon_st_rx_endofpacket : out std_logic; -- .endofpacket
+ avalon_st_rx_valid : out std_logic; -- .valid
+ avalon_st_rx_ready : in std_logic := '0'; -- .ready
+ avalon_st_rx_data : out std_logic_vector(63 downto 0); -- .data
+ avalon_st_rx_empty : out std_logic_vector(2 downto 0); -- .empty
+ avalon_st_rx_error : out std_logic_vector(5 downto 0); -- .error
+ avalon_st_rxstatus_valid : out std_logic; -- avalon_st_rxstatus.valid
+ avalon_st_rxstatus_data : out std_logic_vector(39 downto 0); -- .data
+ avalon_st_rxstatus_error : out std_logic_vector(6 downto 0); -- .error
+ link_fault_status_xgmii_rx_data : out std_logic_vector(1 downto 0) -- link_fault_status_xgmii_rx.data
+ );
+end entity ip_stratixiv_mac_10g;
+
+architecture rtl of ip_stratixiv_mac_10g is
+ component altera_merlin_master_translator_0001 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ uav_address : out std_logic_vector(14 downto 0); -- address
+ uav_burstcount : out std_logic_vector(2 downto 0); -- burstcount
+ uav_read : out std_logic; -- read
+ uav_write : out std_logic; -- write
+ uav_waitrequest : in std_logic := 'X'; -- waitrequest
+ uav_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ uav_byteenable : out std_logic_vector(3 downto 0); -- byteenable
+ uav_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ uav_writedata : out std_logic_vector(31 downto 0); -- writedata
+ uav_lock : out std_logic; -- lock
+ uav_debugaccess : out std_logic; -- debugaccess
+ av_address : in std_logic_vector(12 downto 0) := (others => 'X'); -- address
+ av_waitrequest : out std_logic; -- waitrequest
+ av_read : in std_logic := 'X'; -- read
+ av_readdata : out std_logic_vector(31 downto 0); -- readdata
+ av_write : in std_logic := 'X'; -- write
+ av_writedata : in std_logic_vector(31 downto 0) := (others => 'X') -- writedata
+ );
+ end component altera_merlin_master_translator_0001;
+
+ component altera_avalon_mm_bridge_0001 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ s0_waitrequest : out std_logic; -- waitrequest
+ s0_readdata : out std_logic_vector(31 downto 0); -- readdata
+ s0_readdatavalid : out std_logic; -- readdatavalid
+ s0_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount
+ s0_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ s0_address : in std_logic_vector(13 downto 0) := (others => 'X'); -- address
+ s0_write : in std_logic := 'X'; -- write
+ s0_read : in std_logic := 'X'; -- read
+ s0_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
+ s0_debugaccess : in std_logic := 'X'; -- debugaccess
+ m0_waitrequest : in std_logic := 'X'; -- waitrequest
+ m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ m0_burstcount : out std_logic_vector(0 downto 0); -- burstcount
+ m0_writedata : out std_logic_vector(31 downto 0); -- writedata
+ m0_address : out std_logic_vector(13 downto 0); -- address
+ m0_write : out std_logic; -- write
+ m0_read : out std_logic; -- read
+ m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
+ m0_debugaccess : out std_logic -- debugaccess
+ );
+ end component altera_avalon_mm_bridge_0001;
+
+ component altera_eth_packet_underflow_control is
+ generic (
+ BITSPERSYMBOL : integer := 8;
+ SYMBOLSPERBEAT : integer := 8;
+ ERROR_WIDTH : integer := 1
+ );
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ csr_readdata : out std_logic_vector(31 downto 0); -- readdata
+ csr_read : in std_logic := 'X'; -- read
+ csr_address : in std_logic := 'X'; -- address
+ data_sink_sop : in std_logic := 'X'; -- startofpacket
+ data_sink_valid : in std_logic := 'X'; -- valid
+ data_sink_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ data_sink_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ data_sink_ready : out std_logic; -- ready
+ data_sink_error : in std_logic_vector(0 downto 0) := (others => 'X'); -- error
+ data_sink_eop : in std_logic := 'X'; -- endofpacket
+ data_src_sop : out std_logic; -- startofpacket
+ data_src_eop : out std_logic; -- endofpacket
+ data_src_valid : out std_logic; -- valid
+ data_src_data : out std_logic_vector(63 downto 0); -- data
+ data_src_empty : out std_logic_vector(2 downto 0); -- empty
+ data_src_ready : in std_logic := 'X'; -- ready
+ data_src_error : out std_logic_vector(1 downto 0) -- error
+ );
+ end component altera_eth_packet_underflow_control;
+
+ component altera_eth_pad_inserter is
+ generic (
+ SYMBOLSPERBEAT : integer := 8;
+ ERROR_WIDTH : integer := 1
+ );
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ csr_write : in std_logic := 'X'; -- write
+ csr_read : in std_logic := 'X'; -- read
+ csr_address : in std_logic_vector(0 downto 0) := (others => 'X'); -- address
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ csr_readdata : out std_logic_vector(31 downto 0); -- readdata
+ data_src_sop : out std_logic; -- startofpacket
+ data_src_eop : out std_logic; -- endofpacket
+ data_src_valid : out std_logic; -- valid
+ data_src_ready : in std_logic := 'X'; -- ready
+ data_src_data : out std_logic_vector(63 downto 0); -- data
+ data_src_empty : out std_logic_vector(2 downto 0); -- empty
+ data_src_error : out std_logic_vector(1 downto 0); -- error
+ data_sink_sop : in std_logic := 'X'; -- startofpacket
+ data_sink_eop : in std_logic := 'X'; -- endofpacket
+ data_sink_valid : in std_logic := 'X'; -- valid
+ data_sink_ready : out std_logic; -- ready
+ data_sink_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ data_sink_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ data_sink_error : in std_logic_vector(1 downto 0) := (others => 'X') -- error
+ );
+ end component altera_eth_pad_inserter;
+
+ component altera_eth_pause_beat_conversion is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ pause_quanta_sink_valid : in std_logic := 'X'; -- valid
+ pause_quanta_sink_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- data
+ pause_beat_src_valid : out std_logic; -- valid
+ pause_beat_src_data : out std_logic_vector(31 downto 0) -- data
+ );
+ end component altera_eth_pause_beat_conversion;
+
+ component altera_eth_pause_ctrl_gen is
+ generic (
+ BITSPERSYMBOL : integer := 8;
+ SYMBOLSPERBEAT : integer := 8;
+ ERROR_WIDTH : integer := 1
+ );
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
+ csr_read : in std_logic := 'X'; -- read
+ csr_readdata : out std_logic_vector(31 downto 0); -- readdata
+ csr_write : in std_logic := 'X'; -- write
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ pause_ctrl_sink_data : in std_logic_vector(1 downto 0) := (others => 'X'); -- data
+ pause_source_sop : out std_logic; -- startofpacket
+ pause_source_eop : out std_logic; -- endofpacket
+ pause_source_valid : out std_logic; -- valid
+ pause_source_data : out std_logic_vector(63 downto 0); -- data
+ pause_source_empty : out std_logic_vector(2 downto 0); -- empty
+ pause_source_error : out std_logic_vector(0 downto 0); -- error
+ pause_source_ready : in std_logic := 'X' -- ready
+ );
+ end component altera_eth_pause_ctrl_gen;
+
+ component error_adapter_0001 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ in_ready : out std_logic; -- ready
+ in_valid : in std_logic := 'X'; -- valid
+ in_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ in_error : in std_logic_vector(0 downto 0) := (others => 'X'); -- error
+ in_startofpacket : in std_logic := 'X'; -- startofpacket
+ in_endofpacket : in std_logic := 'X'; -- endofpacket
+ in_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ out_ready : in std_logic := 'X'; -- ready
+ out_valid : out std_logic; -- valid
+ out_data : out std_logic_vector(63 downto 0); -- data
+ out_error : out std_logic_vector(1 downto 0); -- error
+ out_startofpacket : out std_logic; -- startofpacket
+ out_endofpacket : out std_logic; -- endofpacket
+ out_empty : out std_logic_vector(2 downto 0) -- empty
+ );
+ end component error_adapter_0001;
+
+ component multiplexer_0001 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ in0_valid : in std_logic := 'X'; -- valid
+ in0_ready : out std_logic; -- ready
+ in0_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ in0_error : in std_logic_vector(1 downto 0) := (others => 'X'); -- error
+ in0_startofpacket : in std_logic := 'X'; -- startofpacket
+ in0_endofpacket : in std_logic := 'X'; -- endofpacket
+ in0_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ in1_valid : in std_logic := 'X'; -- valid
+ in1_ready : out std_logic; -- ready
+ in1_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ in1_error : in std_logic_vector(1 downto 0) := (others => 'X'); -- error
+ in1_startofpacket : in std_logic := 'X'; -- startofpacket
+ in1_endofpacket : in std_logic := 'X'; -- endofpacket
+ in1_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ out_channel : out std_logic; -- channel
+ out_valid : out std_logic; -- valid
+ out_ready : in std_logic := 'X'; -- ready
+ out_data : out std_logic_vector(63 downto 0); -- data
+ out_error : out std_logic_vector(1 downto 0); -- error
+ out_startofpacket : out std_logic; -- startofpacket
+ out_endofpacket : out std_logic; -- endofpacket
+ out_empty : out std_logic_vector(2 downto 0) -- empty
+ );
+ end component multiplexer_0001;
+
+ component altera_eth_address_inserter is
+ generic (
+ BITSPERSYMBOL : integer := 8;
+ SYMBOLSPERBEAT : integer := 8;
+ ERROR_WIDTH : integer := 1
+ );
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ csr_write : in std_logic := 'X'; -- write
+ csr_read : in std_logic := 'X'; -- read
+ csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ csr_readdata : out std_logic_vector(31 downto 0); -- readdata
+ data_sink_sop : in std_logic := 'X'; -- startofpacket
+ data_sink_eop : in std_logic := 'X'; -- endofpacket
+ data_sink_valid : in std_logic := 'X'; -- valid
+ data_sink_ready : out std_logic; -- ready
+ data_sink_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ data_sink_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ data_sink_error : in std_logic_vector(1 downto 0) := (others => 'X'); -- error
+ data_src_sop : out std_logic; -- startofpacket
+ data_src_eop : out std_logic; -- endofpacket
+ data_src_valid : out std_logic; -- valid
+ data_src_ready : in std_logic := 'X'; -- ready
+ data_src_data : out std_logic_vector(63 downto 0); -- data
+ data_src_empty : out std_logic_vector(2 downto 0); -- empty
+ data_src_error : out std_logic_vector(1 downto 0) -- error
+ );
+ end component altera_eth_address_inserter;
+
+ component altera_avalon_st_pipeline_stage_0001 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ in_ready : out std_logic; -- ready
+ in_valid : in std_logic := 'X'; -- valid
+ in_startofpacket : in std_logic := 'X'; -- startofpacket
+ in_endofpacket : in std_logic := 'X'; -- endofpacket
+ in_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ in_error : in std_logic_vector(2 downto 0) := (others => 'X'); -- error
+ in_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ out_ready : in std_logic := 'X'; -- ready
+ out_valid : out std_logic; -- valid
+ out_startofpacket : out std_logic; -- startofpacket
+ out_endofpacket : out std_logic; -- endofpacket
+ out_empty : out std_logic_vector(2 downto 0); -- empty
+ out_error : out std_logic_vector(2 downto 0); -- error
+ out_data : out std_logic_vector(63 downto 0) -- data
+ );
+ end component altera_avalon_st_pipeline_stage_0001;
+
+ component altera_avalon_st_splitter_0001 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ in0_ready : out std_logic; -- ready
+ in0_valid : in std_logic := 'X'; -- valid
+ in0_startofpacket : in std_logic := 'X'; -- startofpacket
+ in0_endofpacket : in std_logic := 'X'; -- endofpacket
+ in0_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ in0_error : in std_logic_vector(2 downto 0) := (others => 'X'); -- error
+ in0_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ out0_ready : in std_logic := 'X'; -- ready
+ out0_valid : out std_logic; -- valid
+ out0_startofpacket : out std_logic; -- startofpacket
+ out0_endofpacket : out std_logic; -- endofpacket
+ out0_empty : out std_logic_vector(2 downto 0); -- empty
+ out0_error : out std_logic_vector(2 downto 0); -- error
+ out0_data : out std_logic_vector(63 downto 0); -- data
+ out1_ready : in std_logic := 'X'; -- ready
+ out1_valid : out std_logic; -- valid
+ out1_startofpacket : out std_logic; -- startofpacket
+ out1_endofpacket : out std_logic; -- endofpacket
+ out1_empty : out std_logic_vector(2 downto 0); -- empty
+ out1_error : out std_logic_vector(2 downto 0); -- error
+ out1_data : out std_logic_vector(63 downto 0) -- data
+ );
+ end component altera_avalon_st_splitter_0001;
+
+ component timing_adapter_0001 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ in_ready : out std_logic; -- ready
+ in_valid : in std_logic := 'X'; -- valid
+ in_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ in_error : in std_logic_vector(2 downto 0) := (others => 'X'); -- error
+ in_startofpacket : in std_logic := 'X'; -- startofpacket
+ in_endofpacket : in std_logic := 'X'; -- endofpacket
+ in_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ out_valid : out std_logic; -- valid
+ out_data : out std_logic_vector(63 downto 0); -- data
+ out_error : out std_logic_vector(2 downto 0); -- error
+ out_startofpacket : out std_logic; -- startofpacket
+ out_endofpacket : out std_logic; -- endofpacket
+ out_empty : out std_logic_vector(2 downto 0) -- empty
+ );
+ end component timing_adapter_0001;
+
+ component error_adapter_0002 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ in_valid : in std_logic := 'X'; -- valid
+ in_data : in std_logic_vector(39 downto 0) := (others => 'X'); -- data
+ in_error : in std_logic_vector(5 downto 0) := (others => 'X'); -- error
+ out_valid : out std_logic; -- valid
+ out_data : out std_logic_vector(39 downto 0); -- data
+ out_error : out std_logic_vector(6 downto 0) -- error
+ );
+ end component error_adapter_0002;
+
+ component timing_adapter_0002 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ in_valid : in std_logic := 'X'; -- valid
+ in_data : in std_logic_vector(39 downto 0) := (others => 'X'); -- data
+ in_error : in std_logic_vector(6 downto 0) := (others => 'X'); -- error
+ out_valid : out std_logic; -- valid
+ out_data : out std_logic_vector(39 downto 0); -- data
+ out_error : out std_logic_vector(6 downto 0); -- error
+ out_ready : in std_logic := 'X' -- ready
+ );
+ end component timing_adapter_0002;
+
+ component timing_adapter_0003 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ in_ready : out std_logic; -- ready
+ in_valid : in std_logic := 'X'; -- valid
+ in_data : in std_logic_vector(39 downto 0) := (others => 'X'); -- data
+ in_error : in std_logic_vector(6 downto 0) := (others => 'X'); -- error
+ out_valid : out std_logic; -- valid
+ out_data : out std_logic_vector(39 downto 0); -- data
+ out_error : out std_logic_vector(6 downto 0) -- error
+ );
+ end component timing_adapter_0003;
+
+ component altera_avalon_st_splitter_0002 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ in0_ready : out std_logic; -- ready
+ in0_valid : in std_logic := 'X'; -- valid
+ in0_error : in std_logic_vector(6 downto 0) := (others => 'X'); -- error
+ in0_data : in std_logic_vector(39 downto 0) := (others => 'X'); -- data
+ out0_ready : in std_logic := 'X'; -- ready
+ out0_valid : out std_logic; -- valid
+ out0_error : out std_logic_vector(6 downto 0); -- error
+ out0_data : out std_logic_vector(39 downto 0); -- data
+ out1_ready : in std_logic := 'X'; -- ready
+ out1_valid : out std_logic; -- valid
+ out1_error : out std_logic_vector(6 downto 0); -- error
+ out1_data : out std_logic_vector(39 downto 0) -- data
+ );
+ end component altera_avalon_st_splitter_0002;
+
+ component altera_eth_10gmem_statistics_collector is
+ generic (
+ ENABLE_PFC : integer := 0
+ );
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ csr_read : in std_logic := 'X'; -- read
+ csr_address : in std_logic_vector(5 downto 0) := (others => 'X'); -- address
+ csr_readdata : out std_logic_vector(31 downto 0); -- readdata
+ csr_write : in std_logic := 'X'; -- write
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ stat_sink_valid : in std_logic := 'X'; -- valid
+ stat_sink_data : in std_logic_vector(39 downto 0) := (others => 'X'); -- data
+ stat_sink_error : in std_logic_vector(6 downto 0) := (others => 'X') -- error
+ );
+ end component altera_eth_10gmem_statistics_collector;
+
+ component altera_eth_packet_formatter is
+ generic (
+ ERROR_WIDTH : integer := 1
+ );
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ data_sink_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ data_sink_sop : in std_logic := 'X'; -- startofpacket
+ data_sink_eop : in std_logic := 'X'; -- endofpacket
+ data_sink_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ data_sink_error : in std_logic_vector(2 downto 0) := (others => 'X'); -- error
+ data_sink_valid : in std_logic := 'X'; -- valid
+ data_sink_ready : out std_logic; -- ready
+ data_src_data : out std_logic_vector(71 downto 0); -- data
+ data_src_sop : out std_logic; -- startofpacket
+ data_src_eop : out std_logic; -- endofpacket
+ data_src_empty : out std_logic_vector(2 downto 0); -- empty
+ data_src_valid : out std_logic; -- valid
+ data_src_ready : in std_logic := 'X'; -- ready
+ data_sink_data_preamble : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ data_sink_valid_preamble : in std_logic := 'X'; -- valid
+ data_sink_ready_preamble : out std_logic -- ready
+ );
+ end component altera_eth_packet_formatter;
+
+ component altera_eth_xgmii_termination is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ xgmii_src_data : out std_logic_vector(71 downto 0); -- data
+ data_sink_sop : in std_logic := 'X'; -- startofpacket
+ data_sink_eop : in std_logic := 'X'; -- endofpacket
+ data_sink_valid : in std_logic := 'X'; -- valid
+ data_sink_data : in std_logic_vector(71 downto 0) := (others => 'X'); -- data
+ data_sink_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ data_sink_ready : out std_logic -- ready
+ );
+ end component altera_eth_xgmii_termination;
+
+ component altera_eth_link_fault_generation is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ mii_sink_data : in std_logic_vector(71 downto 0) := (others => 'X'); -- data
+ mii_src_data : out std_logic_vector(71 downto 0); -- data
+ link_fault_sink_data : in std_logic_vector(1 downto 0) := (others => 'X') -- data
+ );
+ end component altera_eth_link_fault_generation;
+
+ component timing_adapter_0004 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ in_data : in std_logic_vector(71 downto 0) := (others => 'X'); -- data
+ out_data : out std_logic_vector(71 downto 0); -- data
+ out_ready : in std_logic := 'X'; -- ready
+ out_valid : out std_logic -- valid
+ );
+ end component timing_adapter_0004;
+
+ component altera_avalon_st_splitter_0003 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ in0_ready : out std_logic; -- ready
+ in0_valid : in std_logic := 'X'; -- valid
+ in0_data : in std_logic_vector(71 downto 0) := (others => 'X'); -- data
+ out0_ready : in std_logic := 'X'; -- ready
+ out0_valid : out std_logic; -- valid
+ out0_data : out std_logic_vector(71 downto 0); -- data
+ out1_ready : in std_logic := 'X'; -- ready
+ out1_valid : out std_logic; -- valid
+ out1_data : out std_logic_vector(71 downto 0) -- data
+ );
+ end component altera_avalon_st_splitter_0003;
+
+ component timing_adapter_0005 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ in_ready : out std_logic; -- ready
+ in_valid : in std_logic := 'X'; -- valid
+ in_data : in std_logic_vector(71 downto 0) := (others => 'X'); -- data
+ out_data : out std_logic_vector(71 downto 0) -- data
+ );
+ end component timing_adapter_0005;
+
+ component altera_eth_link_fault_detection is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ mii_sink_data : in std_logic_vector(71 downto 0) := (others => 'X'); -- data
+ link_fault_src_data : out std_logic_vector(1 downto 0) -- data
+ );
+ end component altera_eth_link_fault_detection;
+
+ component altera_eth_lane_decoder is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ xgmii_sink_data : in std_logic_vector(71 downto 0) := (others => 'X'); -- data
+ rxdata_src_eop : out std_logic; -- endofpacket
+ rxdata_src_sop : out std_logic; -- startofpacket
+ rxdata_src_valid : out std_logic; -- valid
+ rxdata_src_data : out std_logic_vector(63 downto 0); -- data
+ rxdata_src_empty : out std_logic_vector(2 downto 0); -- empty
+ rxdata_src_error : out std_logic_vector(0 downto 0); -- error
+ csr_read : in std_logic := 'X'; -- read
+ csr_write : in std_logic := 'X'; -- write
+ csr_address : in std_logic := 'X'; -- address
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ csr_readdata : out std_logic_vector(31 downto 0); -- readdata
+ preamble_valid : out std_logic; -- valid
+ preamble_bytes : out std_logic_vector(63 downto 0) -- data
+ );
+ end component altera_eth_lane_decoder;
+
+ component timing_adapter_0006 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ in_valid : in std_logic := 'X'; -- valid
+ in_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ in_error : in std_logic := 'X'; -- error
+ in_startofpacket : in std_logic := 'X'; -- startofpacket
+ in_endofpacket : in std_logic := 'X'; -- endofpacket
+ in_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ out_valid : out std_logic; -- valid
+ out_data : out std_logic_vector(63 downto 0); -- data
+ out_error : out std_logic; -- error
+ out_startofpacket : out std_logic; -- startofpacket
+ out_endofpacket : out std_logic; -- endofpacket
+ out_empty : out std_logic_vector(2 downto 0); -- empty
+ out_ready : in std_logic := 'X' -- ready
+ );
+ end component timing_adapter_0006;
+
+ component altera_avalon_st_splitter_0004 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ in0_ready : out std_logic; -- ready
+ in0_valid : in std_logic := 'X'; -- valid
+ in0_startofpacket : in std_logic := 'X'; -- startofpacket
+ in0_endofpacket : in std_logic := 'X'; -- endofpacket
+ in0_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ in0_error : in std_logic := 'X'; -- error
+ in0_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ out0_ready : in std_logic := 'X'; -- ready
+ out0_valid : out std_logic; -- valid
+ out0_startofpacket : out std_logic; -- startofpacket
+ out0_endofpacket : out std_logic; -- endofpacket
+ out0_empty : out std_logic_vector(2 downto 0); -- empty
+ out0_error : out std_logic; -- error
+ out0_data : out std_logic_vector(63 downto 0); -- data
+ out1_ready : in std_logic := 'X'; -- ready
+ out1_valid : out std_logic; -- valid
+ out1_startofpacket : out std_logic; -- startofpacket
+ out1_endofpacket : out std_logic; -- endofpacket
+ out1_empty : out std_logic_vector(2 downto 0); -- empty
+ out1_error : out std_logic; -- error
+ out1_data : out std_logic_vector(63 downto 0) -- data
+ );
+ end component altera_avalon_st_splitter_0004;
+
+ component timing_adapter_0007 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ in_ready : out std_logic; -- ready
+ in_valid : in std_logic := 'X'; -- valid
+ in_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ in_error : in std_logic := 'X'; -- error
+ in_startofpacket : in std_logic := 'X'; -- startofpacket
+ in_endofpacket : in std_logic := 'X'; -- endofpacket
+ in_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ out_valid : out std_logic; -- valid
+ out_data : out std_logic_vector(63 downto 0); -- data
+ out_error : out std_logic; -- error
+ out_startofpacket : out std_logic; -- startofpacket
+ out_endofpacket : out std_logic; -- endofpacket
+ out_empty : out std_logic_vector(2 downto 0) -- empty
+ );
+ end component timing_adapter_0007;
+
+ component altera_eth_frame_status_merger is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ frame_decoder_data_sink_sop : in std_logic := 'X'; -- startofpacket
+ frame_decoder_data_sink_eop : in std_logic := 'X'; -- endofpacket
+ frame_decoder_data_sink_valid : in std_logic := 'X'; -- valid
+ frame_decoder_data_sink_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ frame_decoder_data_sink_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ frame_decoder_data_sink_error : in std_logic_vector(3 downto 0) := (others => 'X'); -- error
+ crc_checker_data_sink_sop : in std_logic := 'X'; -- startofpacket
+ crc_checker_data_sink_eop : in std_logic := 'X'; -- endofpacket
+ crc_checker_data_sink_valid : in std_logic := 'X'; -- valid
+ crc_checker_data_sink_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ crc_checker_data_sink_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ crc_checker_data_sink_error : in std_logic_vector(1 downto 0) := (others => 'X'); -- error
+ data_src_sop : out std_logic; -- startofpacket
+ data_src_eop : out std_logic; -- endofpacket
+ data_src_valid : out std_logic; -- valid
+ data_src_data : out std_logic_vector(63 downto 0); -- data
+ data_src_empty : out std_logic_vector(2 downto 0); -- empty
+ data_src_error : out std_logic_vector(4 downto 0); -- error
+ pauselen_sink_valid : in std_logic := 'X'; -- valid
+ pauselen_sink_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- data
+ pauselen_src_valid : out std_logic; -- valid
+ pauselen_src_data : out std_logic_vector(15 downto 0); -- data
+ rxstatus_sink_valid : in std_logic := 'X'; -- valid
+ rxstatus_sink_data : in std_logic_vector(39 downto 0) := (others => 'X'); -- data
+ rxstatus_sink_error : in std_logic_vector(3 downto 0) := (others => 'X'); -- error
+ rxstatus_src_valid : out std_logic; -- valid
+ rxstatus_src_data : out std_logic_vector(39 downto 0); -- data
+ rxstatus_src_error : out std_logic_vector(4 downto 0); -- error
+ pfc_pause_quanta_sink_valid : in std_logic := 'X'; -- valid
+ pfc_pause_quanta_sink_data : in std_logic_vector(135 downto 0) := (others => 'X'); -- data
+ pfc_pause_quanta_src_valid : out std_logic; -- valid
+ pfc_pause_quanta_src_data : out std_logic_vector(135 downto 0) -- data
+ );
+ end component altera_eth_frame_status_merger;
+
+ component altera_eth_crc_pad_rem is
+ generic (
+ BITSPERSYMBOL : integer := 8;
+ SYMBOLSPERBEAT : integer := 8;
+ ERRORWIDTH : integer := 5
+ );
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ csr_read : in std_logic := 'X'; -- read
+ csr_write : in std_logic := 'X'; -- write
+ csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ csr_readdata : out std_logic_vector(31 downto 0); -- readdata
+ data_sink_sop : in std_logic := 'X'; -- startofpacket
+ data_sink_eop : in std_logic := 'X'; -- endofpacket
+ data_sink_valid : in std_logic := 'X'; -- valid
+ data_sink_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ data_sink_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ data_sink_error : in std_logic_vector(4 downto 0) := (others => 'X'); -- error
+ status_sink_valid : in std_logic := 'X'; -- valid
+ status_sink_data : in std_logic_vector(22 downto 0) := (others => 'X'); -- data
+ data_source_sop : out std_logic; -- startofpacket
+ data_source_eop : out std_logic; -- endofpacket
+ data_source_valid : out std_logic; -- valid
+ data_source_data : out std_logic_vector(63 downto 0); -- data
+ data_source_empty : out std_logic_vector(2 downto 0); -- empty
+ data_source_error : out std_logic_vector(4 downto 0) -- error
+ );
+ end component altera_eth_crc_pad_rem;
+
+ component altera_eth_packet_overflow_control is
+ generic (
+ BITSPERSYMBOL : integer := 8;
+ SYMBOLSPERBEAT : integer := 8;
+ ERROR_WIDTH : integer := 1
+ );
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ data_sink_sop : in std_logic := 'X'; -- startofpacket
+ data_sink_eop : in std_logic := 'X'; -- endofpacket
+ data_sink_valid : in std_logic := 'X'; -- valid
+ data_sink_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ data_sink_error : in std_logic_vector(4 downto 0) := (others => 'X'); -- error
+ data_sink_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ data_src_sop : out std_logic; -- startofpacket
+ data_src_eop : out std_logic; -- endofpacket
+ data_src_valid : out std_logic; -- valid
+ data_src_ready : in std_logic := 'X'; -- ready
+ data_src_data : out std_logic_vector(63 downto 0); -- data
+ data_src_empty : out std_logic_vector(2 downto 0); -- empty
+ data_src_error : out std_logic_vector(5 downto 0); -- error
+ csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
+ csr_read : in std_logic := 'X'; -- read
+ csr_readdata : out std_logic_vector(31 downto 0) -- readdata
+ );
+ end component altera_eth_packet_overflow_control;
+
+ component altera_avalon_st_delay_0001 is
+ port (
+ in0_valid : in std_logic := 'X'; -- valid
+ in0_data : in std_logic_vector(39 downto 0) := (others => 'X'); -- data
+ in0_error : in std_logic_vector(6 downto 0) := (others => 'X'); -- error
+ out0_valid : out std_logic; -- valid
+ out0_data : out std_logic_vector(39 downto 0); -- data
+ out0_error : out std_logic_vector(6 downto 0); -- error
+ clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X' -- reset_n
+ );
+ end component altera_avalon_st_delay_0001;
+
+ component error_adapter_0003 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ in_valid : in std_logic := 'X'; -- valid
+ in_data : in std_logic_vector(39 downto 0) := (others => 'X'); -- data
+ in_error : in std_logic_vector(4 downto 0) := (others => 'X'); -- error
+ out_valid : out std_logic; -- valid
+ out_data : out std_logic_vector(39 downto 0); -- data
+ out_error : out std_logic_vector(6 downto 0) -- error
+ );
+ end component error_adapter_0003;
+
+ component altera_avalon_st_delay_0002 is
+ port (
+ in0_valid : in std_logic := 'X'; -- valid
+ in0_data : in std_logic_vector(39 downto 0) := (others => 'X'); -- data
+ in0_error : in std_logic_vector(6 downto 0) := (others => 'X'); -- error
+ out0_valid : out std_logic; -- valid
+ out0_data : out std_logic_vector(39 downto 0); -- data
+ out0_error : out std_logic_vector(6 downto 0); -- error
+ clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X' -- reset_n
+ );
+ end component altera_avalon_st_delay_0002;
+
+ component timing_adapter_0008 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ in_data : in std_logic_vector(1 downto 0) := (others => 'X'); -- data
+ out_data : out std_logic_vector(1 downto 0); -- data
+ out_ready : in std_logic := 'X'; -- ready
+ out_valid : out std_logic -- valid
+ );
+ end component timing_adapter_0008;
+
+ component altera_avalon_st_splitter_0005 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ in0_ready : out std_logic; -- ready
+ in0_valid : in std_logic := 'X'; -- valid
+ in0_data : in std_logic_vector(1 downto 0) := (others => 'X'); -- data
+ out0_ready : in std_logic := 'X'; -- ready
+ out0_valid : out std_logic; -- valid
+ out0_data : out std_logic_vector(1 downto 0); -- data
+ out1_ready : in std_logic := 'X'; -- ready
+ out1_valid : out std_logic; -- valid
+ out1_data : out std_logic_vector(1 downto 0) -- data
+ );
+ end component altera_avalon_st_splitter_0005;
+
+ component timing_adapter_0009 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ in_ready : out std_logic; -- ready
+ in_valid : in std_logic := 'X'; -- valid
+ in_data : in std_logic_vector(1 downto 0) := (others => 'X'); -- data
+ out_data : out std_logic_vector(1 downto 0) -- data
+ );
+ end component timing_adapter_0009;
+
+ component altera_avalon_dc_fifo_0001 is
+ port (
+ in_clk : in std_logic := 'X'; -- clk
+ in_reset_n : in std_logic := 'X'; -- reset_n
+ out_clk : in std_logic := 'X'; -- clk
+ out_reset_n : in std_logic := 'X'; -- reset_n
+ in_data : in std_logic_vector(1 downto 0) := (others => 'X'); -- data
+ in_valid : in std_logic := 'X'; -- valid
+ in_ready : out std_logic; -- ready
+ out_data : out std_logic_vector(1 downto 0); -- data
+ out_valid : out std_logic; -- valid
+ out_ready : in std_logic := 'X' -- ready
+ );
+ end component altera_avalon_dc_fifo_0001;
+
+ component timing_adapter_0010 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ in_valid : in std_logic := 'X'; -- valid
+ in_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- data
+ out_valid : out std_logic; -- valid
+ out_data : out std_logic_vector(15 downto 0); -- data
+ out_ready : in std_logic := 'X' -- ready
+ );
+ end component timing_adapter_0010;
+
+ component altera_avalon_dc_fifo_0002 is
+ port (
+ in_clk : in std_logic := 'X'; -- clk
+ in_reset_n : in std_logic := 'X'; -- reset_n
+ out_clk : in std_logic := 'X'; -- clk
+ out_reset_n : in std_logic := 'X'; -- reset_n
+ in_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- data
+ in_valid : in std_logic := 'X'; -- valid
+ in_ready : out std_logic; -- ready
+ out_data : out std_logic_vector(15 downto 0); -- data
+ out_valid : out std_logic; -- valid
+ out_ready : in std_logic := 'X' -- ready
+ );
+ end component altera_avalon_dc_fifo_0002;
+
+ component timing_adapter_0011 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ in_ready : out std_logic; -- ready
+ in_valid : in std_logic := 'X'; -- valid
+ in_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- data
+ out_valid : out std_logic; -- valid
+ out_data : out std_logic_vector(15 downto 0) -- data
+ );
+ end component timing_adapter_0011;
+
+ component altera_merlin_master_translator_0002 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ uav_address : out std_logic_vector(14 downto 0); -- address
+ uav_burstcount : out std_logic_vector(2 downto 0); -- burstcount
+ uav_read : out std_logic; -- read
+ uav_write : out std_logic; -- write
+ uav_waitrequest : in std_logic := 'X'; -- waitrequest
+ uav_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ uav_byteenable : out std_logic_vector(3 downto 0); -- byteenable
+ uav_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ uav_writedata : out std_logic_vector(31 downto 0); -- writedata
+ uav_lock : out std_logic; -- lock
+ uav_debugaccess : out std_logic; -- debugaccess
+ av_address : in std_logic_vector(14 downto 0) := (others => 'X'); -- address
+ av_waitrequest : out std_logic; -- waitrequest
+ av_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
+ av_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
+ av_read : in std_logic := 'X'; -- read
+ av_readdata : out std_logic_vector(31 downto 0); -- readdata
+ av_readdatavalid : out std_logic; -- readdatavalid
+ av_write : in std_logic := 'X'; -- write
+ av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ av_lock : in std_logic := 'X'; -- lock
+ av_debugaccess : in std_logic := 'X' -- debugaccess
+ );
+ end component altera_merlin_master_translator_0002;
+
+ component altera_merlin_slave_translator_0001 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ uav_address : in std_logic_vector(14 downto 0) := (others => 'X'); -- address
+ uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
+ uav_read : in std_logic := 'X'; -- read
+ uav_write : in std_logic := 'X'; -- write
+ uav_waitrequest : out std_logic; -- waitrequest
+ uav_readdatavalid : out std_logic; -- readdatavalid
+ uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
+ uav_readdata : out std_logic_vector(31 downto 0); -- readdata
+ uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ uav_lock : in std_logic := 'X'; -- lock
+ uav_debugaccess : in std_logic := 'X'; -- debugaccess
+ av_address : out std_logic_vector(13 downto 0); -- address
+ av_write : out std_logic; -- write
+ av_read : out std_logic; -- read
+ av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ av_writedata : out std_logic_vector(31 downto 0); -- writedata
+ av_burstcount : out std_logic; -- burstcount
+ av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
+ av_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ av_waitrequest : in std_logic := 'X'; -- waitrequest
+ av_debugaccess : out std_logic -- debugaccess
+ );
+ end component altera_merlin_slave_translator_0001;
+
+ component altera_merlin_master_translator_0003 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ uav_address : out std_logic_vector(13 downto 0); -- address
+ uav_burstcount : out std_logic_vector(2 downto 0); -- burstcount
+ uav_read : out std_logic; -- read
+ uav_write : out std_logic; -- write
+ uav_waitrequest : in std_logic := 'X'; -- waitrequest
+ uav_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ uav_byteenable : out std_logic_vector(3 downto 0); -- byteenable
+ uav_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ uav_writedata : out std_logic_vector(31 downto 0); -- writedata
+ uav_lock : out std_logic; -- lock
+ uav_debugaccess : out std_logic; -- debugaccess
+ av_address : in std_logic_vector(13 downto 0) := (others => 'X'); -- address
+ av_waitrequest : out std_logic; -- waitrequest
+ av_burstcount : in std_logic := 'X'; -- burstcount
+ av_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
+ av_read : in std_logic := 'X'; -- read
+ av_readdata : out std_logic_vector(31 downto 0); -- readdata
+ av_readdatavalid : out std_logic; -- readdatavalid
+ av_write : in std_logic := 'X'; -- write
+ av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ av_debugaccess : in std_logic := 'X' -- debugaccess
+ );
+ end component altera_merlin_master_translator_0003;
+
+ component altera_merlin_slave_translator_0002 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ uav_address : in std_logic_vector(13 downto 0) := (others => 'X'); -- address
+ uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
+ uav_read : in std_logic := 'X'; -- read
+ uav_write : in std_logic := 'X'; -- write
+ uav_waitrequest : out std_logic; -- waitrequest
+ uav_readdatavalid : out std_logic; -- readdatavalid
+ uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
+ uav_readdata : out std_logic_vector(31 downto 0); -- readdata
+ uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ uav_lock : in std_logic := 'X'; -- lock
+ uav_debugaccess : in std_logic := 'X'; -- debugaccess
+ av_address : out std_logic; -- address
+ av_write : out std_logic; -- write
+ av_read : out std_logic; -- read
+ av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ av_writedata : out std_logic_vector(31 downto 0) -- writedata
+ );
+ end component altera_merlin_slave_translator_0002;
+
+ component altera_merlin_slave_translator_0003 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ uav_address : in std_logic_vector(13 downto 0) := (others => 'X'); -- address
+ uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
+ uav_read : in std_logic := 'X'; -- read
+ uav_write : in std_logic := 'X'; -- write
+ uav_waitrequest : out std_logic; -- waitrequest
+ uav_readdatavalid : out std_logic; -- readdatavalid
+ uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
+ uav_readdata : out std_logic_vector(31 downto 0); -- readdata
+ uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ uav_lock : in std_logic := 'X'; -- lock
+ uav_debugaccess : in std_logic := 'X'; -- debugaccess
+ av_address : out std_logic_vector(1 downto 0); -- address
+ av_write : out std_logic; -- write
+ av_read : out std_logic; -- read
+ av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ av_writedata : out std_logic_vector(31 downto 0) -- writedata
+ );
+ end component altera_merlin_slave_translator_0003;
+
+ component altera_merlin_slave_translator_0004 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ uav_address : in std_logic_vector(13 downto 0) := (others => 'X'); -- address
+ uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
+ uav_read : in std_logic := 'X'; -- read
+ uav_write : in std_logic := 'X'; -- write
+ uav_waitrequest : out std_logic; -- waitrequest
+ uav_readdatavalid : out std_logic; -- readdatavalid
+ uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
+ uav_readdata : out std_logic_vector(31 downto 0); -- readdata
+ uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ uav_lock : in std_logic := 'X'; -- lock
+ uav_debugaccess : in std_logic := 'X'; -- debugaccess
+ av_address : out std_logic; -- address
+ av_read : out std_logic; -- read
+ av_readdata : in std_logic_vector(31 downto 0) := (others => 'X') -- readdata
+ );
+ end component altera_merlin_slave_translator_0004;
+
+ component altera_merlin_slave_translator_0005 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ uav_address : in std_logic_vector(13 downto 0) := (others => 'X'); -- address
+ uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
+ uav_read : in std_logic := 'X'; -- read
+ uav_write : in std_logic := 'X'; -- write
+ uav_waitrequest : out std_logic; -- waitrequest
+ uav_readdatavalid : out std_logic; -- readdatavalid
+ uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
+ uav_readdata : out std_logic_vector(31 downto 0); -- readdata
+ uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ uav_lock : in std_logic := 'X'; -- lock
+ uav_debugaccess : in std_logic := 'X'; -- debugaccess
+ av_address : out std_logic_vector(4 downto 0); -- address
+ av_write : out std_logic; -- write
+ av_read : out std_logic; -- read
+ av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ av_writedata : out std_logic_vector(31 downto 0) -- writedata
+ );
+ end component altera_merlin_slave_translator_0005;
+
+ component altera_merlin_slave_translator_0006 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ uav_address : in std_logic_vector(13 downto 0) := (others => 'X'); -- address
+ uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
+ uav_read : in std_logic := 'X'; -- read
+ uav_write : in std_logic := 'X'; -- write
+ uav_waitrequest : out std_logic; -- waitrequest
+ uav_readdatavalid : out std_logic; -- readdatavalid
+ uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
+ uav_readdata : out std_logic_vector(31 downto 0); -- readdata
+ uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ uav_lock : in std_logic := 'X'; -- lock
+ uav_debugaccess : in std_logic := 'X'; -- debugaccess
+ av_address : out std_logic_vector(5 downto 0); -- address
+ av_write : out std_logic; -- write
+ av_read : out std_logic; -- read
+ av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ av_writedata : out std_logic_vector(31 downto 0) -- writedata
+ );
+ end component altera_merlin_slave_translator_0006;
+
+ component altera_merlin_slave_translator_0007 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ uav_address : in std_logic_vector(13 downto 0) := (others => 'X'); -- address
+ uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
+ uav_read : in std_logic := 'X'; -- read
+ uav_write : in std_logic := 'X'; -- write
+ uav_waitrequest : out std_logic; -- waitrequest
+ uav_readdatavalid : out std_logic; -- readdatavalid
+ uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
+ uav_readdata : out std_logic_vector(31 downto 0); -- readdata
+ uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ uav_lock : in std_logic := 'X'; -- lock
+ uav_debugaccess : in std_logic := 'X'; -- debugaccess
+ av_address : out std_logic_vector(1 downto 0); -- address
+ av_read : out std_logic; -- read
+ av_readdata : in std_logic_vector(31 downto 0) := (others => 'X') -- readdata
+ );
+ end component altera_merlin_slave_translator_0007;
+
+ component altera_merlin_slave_agent_0001 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ m0_address : out std_logic_vector(14 downto 0); -- address
+ m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
+ m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
+ m0_debugaccess : out std_logic; -- debugaccess
+ m0_lock : out std_logic; -- lock
+ m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ m0_read : out std_logic; -- read
+ m0_waitrequest : in std_logic := 'X'; -- waitrequest
+ m0_writedata : out std_logic_vector(31 downto 0); -- writedata
+ m0_write : out std_logic; -- write
+ rp_endofpacket : out std_logic; -- endofpacket
+ rp_ready : in std_logic := 'X'; -- ready
+ rp_valid : out std_logic; -- valid
+ rp_data : out std_logic_vector(65 downto 0); -- data
+ rp_startofpacket : out std_logic; -- startofpacket
+ cp_ready : out std_logic; -- ready
+ cp_valid : in std_logic := 'X'; -- valid
+ cp_data : in std_logic_vector(65 downto 0) := (others => 'X'); -- data
+ cp_startofpacket : in std_logic := 'X'; -- startofpacket
+ cp_endofpacket : in std_logic := 'X'; -- endofpacket
+ cp_channel : in std_logic_vector(1 downto 0) := (others => 'X'); -- channel
+ rf_sink_ready : out std_logic; -- ready
+ rf_sink_valid : in std_logic := 'X'; -- valid
+ rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ rf_sink_data : in std_logic_vector(66 downto 0) := (others => 'X'); -- data
+ rf_source_ready : in std_logic := 'X'; -- ready
+ rf_source_valid : out std_logic; -- valid
+ rf_source_startofpacket : out std_logic; -- startofpacket
+ rf_source_endofpacket : out std_logic; -- endofpacket
+ rf_source_data : out std_logic_vector(66 downto 0); -- data
+ rdata_fifo_sink_ready : out std_logic; -- ready
+ rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
+ rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
+ rdata_fifo_src_ready : in std_logic := 'X'; -- ready
+ rdata_fifo_src_valid : out std_logic; -- valid
+ rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
+ );
+ end component altera_merlin_slave_agent_0001;
+
+ component altera_avalon_sc_fifo_0001 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ in_data : in std_logic_vector(66 downto 0) := (others => 'X'); -- data
+ in_valid : in std_logic := 'X'; -- valid
+ in_ready : out std_logic; -- ready
+ in_startofpacket : in std_logic := 'X'; -- startofpacket
+ in_endofpacket : in std_logic := 'X'; -- endofpacket
+ out_data : out std_logic_vector(66 downto 0); -- data
+ out_valid : out std_logic; -- valid
+ out_ready : in std_logic := 'X'; -- ready
+ out_startofpacket : out std_logic; -- startofpacket
+ out_endofpacket : out std_logic -- endofpacket
+ );
+ end component altera_avalon_sc_fifo_0001;
+
+ component altera_avalon_sc_fifo_0002 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ in_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
+ in_valid : in std_logic := 'X'; -- valid
+ in_ready : out std_logic; -- ready
+ out_data : out std_logic_vector(31 downto 0); -- data
+ out_valid : out std_logic; -- valid
+ out_ready : in std_logic := 'X' -- ready
+ );
+ end component altera_avalon_sc_fifo_0002;
+
+ component altera_merlin_master_agent_0001 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ av_address : in std_logic_vector(14 downto 0) := (others => 'X'); -- address
+ av_write : in std_logic := 'X'; -- write
+ av_read : in std_logic := 'X'; -- read
+ av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ av_readdata : out std_logic_vector(31 downto 0); -- readdata
+ av_waitrequest : out std_logic; -- waitrequest
+ av_readdatavalid : out std_logic; -- readdatavalid
+ av_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
+ av_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
+ av_debugaccess : in std_logic := 'X'; -- debugaccess
+ av_lock : in std_logic := 'X'; -- lock
+ cp_valid : out std_logic; -- valid
+ cp_data : out std_logic_vector(65 downto 0); -- data
+ cp_startofpacket : out std_logic; -- startofpacket
+ cp_endofpacket : out std_logic; -- endofpacket
+ cp_ready : in std_logic := 'X'; -- ready
+ rp_valid : in std_logic := 'X'; -- valid
+ rp_data : in std_logic_vector(65 downto 0) := (others => 'X'); -- data
+ rp_channel : in std_logic_vector(1 downto 0) := (others => 'X'); -- channel
+ rp_startofpacket : in std_logic := 'X'; -- startofpacket
+ rp_endofpacket : in std_logic := 'X'; -- endofpacket
+ rp_ready : out std_logic -- ready
+ );
+ end component altera_merlin_master_agent_0001;
+
+ component altera_merlin_slave_agent_0002 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ m0_address : out std_logic_vector(14 downto 0); -- address
+ m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
+ m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
+ m0_debugaccess : out std_logic; -- debugaccess
+ m0_lock : out std_logic; -- lock
+ m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ m0_read : out std_logic; -- read
+ m0_waitrequest : in std_logic := 'X'; -- waitrequest
+ m0_writedata : out std_logic_vector(31 downto 0); -- writedata
+ m0_write : out std_logic; -- write
+ rp_endofpacket : out std_logic; -- endofpacket
+ rp_ready : in std_logic := 'X'; -- ready
+ rp_valid : out std_logic; -- valid
+ rp_data : out std_logic_vector(65 downto 0); -- data
+ rp_startofpacket : out std_logic; -- startofpacket
+ cp_ready : out std_logic; -- ready
+ cp_valid : in std_logic := 'X'; -- valid
+ cp_data : in std_logic_vector(65 downto 0) := (others => 'X'); -- data
+ cp_startofpacket : in std_logic := 'X'; -- startofpacket
+ cp_endofpacket : in std_logic := 'X'; -- endofpacket
+ cp_channel : in std_logic_vector(1 downto 0) := (others => 'X'); -- channel
+ rf_sink_ready : out std_logic; -- ready
+ rf_sink_valid : in std_logic := 'X'; -- valid
+ rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ rf_sink_data : in std_logic_vector(66 downto 0) := (others => 'X'); -- data
+ rf_source_ready : in std_logic := 'X'; -- ready
+ rf_source_valid : out std_logic; -- valid
+ rf_source_startofpacket : out std_logic; -- startofpacket
+ rf_source_endofpacket : out std_logic; -- endofpacket
+ rf_source_data : out std_logic_vector(66 downto 0); -- data
+ rdata_fifo_sink_ready : out std_logic; -- ready
+ rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
+ rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
+ rdata_fifo_src_ready : in std_logic := 'X'; -- ready
+ rdata_fifo_src_valid : out std_logic; -- valid
+ rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
+ );
+ end component altera_merlin_slave_agent_0002;
+
+ component altera_merlin_slave_agent_0003 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ m0_address : out std_logic_vector(13 downto 0); -- address
+ m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
+ m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
+ m0_debugaccess : out std_logic; -- debugaccess
+ m0_lock : out std_logic; -- lock
+ m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ m0_read : out std_logic; -- read
+ m0_waitrequest : in std_logic := 'X'; -- waitrequest
+ m0_writedata : out std_logic_vector(31 downto 0); -- writedata
+ m0_write : out std_logic; -- write
+ rp_endofpacket : out std_logic; -- endofpacket
+ rp_ready : in std_logic := 'X'; -- ready
+ rp_valid : out std_logic; -- valid
+ rp_data : out std_logic_vector(68 downto 0); -- data
+ rp_startofpacket : out std_logic; -- startofpacket
+ cp_ready : out std_logic; -- ready
+ cp_valid : in std_logic := 'X'; -- valid
+ cp_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ cp_startofpacket : in std_logic := 'X'; -- startofpacket
+ cp_endofpacket : in std_logic := 'X'; -- endofpacket
+ cp_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
+ rf_sink_ready : out std_logic; -- ready
+ rf_sink_valid : in std_logic := 'X'; -- valid
+ rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ rf_sink_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
+ rf_source_ready : in std_logic := 'X'; -- ready
+ rf_source_valid : out std_logic; -- valid
+ rf_source_startofpacket : out std_logic; -- startofpacket
+ rf_source_endofpacket : out std_logic; -- endofpacket
+ rf_source_data : out std_logic_vector(69 downto 0); -- data
+ rdata_fifo_sink_ready : out std_logic; -- ready
+ rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
+ rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
+ rdata_fifo_src_ready : in std_logic := 'X'; -- ready
+ rdata_fifo_src_valid : out std_logic; -- valid
+ rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
+ );
+ end component altera_merlin_slave_agent_0003;
+
+ component altera_avalon_sc_fifo_0003 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ in_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
+ in_valid : in std_logic := 'X'; -- valid
+ in_ready : out std_logic; -- ready
+ in_startofpacket : in std_logic := 'X'; -- startofpacket
+ in_endofpacket : in std_logic := 'X'; -- endofpacket
+ out_data : out std_logic_vector(69 downto 0); -- data
+ out_valid : out std_logic; -- valid
+ out_ready : in std_logic := 'X'; -- ready
+ out_startofpacket : out std_logic; -- startofpacket
+ out_endofpacket : out std_logic -- endofpacket
+ );
+ end component altera_avalon_sc_fifo_0003;
+
+ component altera_merlin_slave_agent_0004 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ m0_address : out std_logic_vector(13 downto 0); -- address
+ m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
+ m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
+ m0_debugaccess : out std_logic; -- debugaccess
+ m0_lock : out std_logic; -- lock
+ m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ m0_read : out std_logic; -- read
+ m0_waitrequest : in std_logic := 'X'; -- waitrequest
+ m0_writedata : out std_logic_vector(31 downto 0); -- writedata
+ m0_write : out std_logic; -- write
+ rp_endofpacket : out std_logic; -- endofpacket
+ rp_ready : in std_logic := 'X'; -- ready
+ rp_valid : out std_logic; -- valid
+ rp_data : out std_logic_vector(68 downto 0); -- data
+ rp_startofpacket : out std_logic; -- startofpacket
+ cp_ready : out std_logic; -- ready
+ cp_valid : in std_logic := 'X'; -- valid
+ cp_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ cp_startofpacket : in std_logic := 'X'; -- startofpacket
+ cp_endofpacket : in std_logic := 'X'; -- endofpacket
+ cp_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
+ rf_sink_ready : out std_logic; -- ready
+ rf_sink_valid : in std_logic := 'X'; -- valid
+ rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ rf_sink_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
+ rf_source_ready : in std_logic := 'X'; -- ready
+ rf_source_valid : out std_logic; -- valid
+ rf_source_startofpacket : out std_logic; -- startofpacket
+ rf_source_endofpacket : out std_logic; -- endofpacket
+ rf_source_data : out std_logic_vector(69 downto 0); -- data
+ rdata_fifo_sink_ready : out std_logic; -- ready
+ rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
+ rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
+ rdata_fifo_src_ready : in std_logic := 'X'; -- ready
+ rdata_fifo_src_valid : out std_logic; -- valid
+ rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
+ );
+ end component altera_merlin_slave_agent_0004;
+
+ component altera_avalon_sc_fifo_0004 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ in_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
+ in_valid : in std_logic := 'X'; -- valid
+ in_ready : out std_logic; -- ready
+ in_startofpacket : in std_logic := 'X'; -- startofpacket
+ in_endofpacket : in std_logic := 'X'; -- endofpacket
+ out_data : out std_logic_vector(69 downto 0); -- data
+ out_valid : out std_logic; -- valid
+ out_ready : in std_logic := 'X'; -- ready
+ out_startofpacket : out std_logic; -- startofpacket
+ out_endofpacket : out std_logic -- endofpacket
+ );
+ end component altera_avalon_sc_fifo_0004;
+
+ component altera_merlin_master_agent_0002 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ av_address : in std_logic_vector(13 downto 0) := (others => 'X'); -- address
+ av_write : in std_logic := 'X'; -- write
+ av_read : in std_logic := 'X'; -- read
+ av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ av_readdata : out std_logic_vector(31 downto 0); -- readdata
+ av_waitrequest : out std_logic; -- waitrequest
+ av_readdatavalid : out std_logic; -- readdatavalid
+ av_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
+ av_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
+ av_debugaccess : in std_logic := 'X'; -- debugaccess
+ av_lock : in std_logic := 'X'; -- lock
+ cp_valid : out std_logic; -- valid
+ cp_data : out std_logic_vector(68 downto 0); -- data
+ cp_startofpacket : out std_logic; -- startofpacket
+ cp_endofpacket : out std_logic; -- endofpacket
+ cp_ready : in std_logic := 'X'; -- ready
+ rp_valid : in std_logic := 'X'; -- valid
+ rp_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ rp_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
+ rp_startofpacket : in std_logic := 'X'; -- startofpacket
+ rp_endofpacket : in std_logic := 'X'; -- endofpacket
+ rp_ready : out std_logic -- ready
+ );
+ end component altera_merlin_master_agent_0002;
+
+ component altera_merlin_slave_agent_0005 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ m0_address : out std_logic_vector(13 downto 0); -- address
+ m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
+ m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
+ m0_debugaccess : out std_logic; -- debugaccess
+ m0_lock : out std_logic; -- lock
+ m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ m0_read : out std_logic; -- read
+ m0_waitrequest : in std_logic := 'X'; -- waitrequest
+ m0_writedata : out std_logic_vector(31 downto 0); -- writedata
+ m0_write : out std_logic; -- write
+ rp_endofpacket : out std_logic; -- endofpacket
+ rp_ready : in std_logic := 'X'; -- ready
+ rp_valid : out std_logic; -- valid
+ rp_data : out std_logic_vector(68 downto 0); -- data
+ rp_startofpacket : out std_logic; -- startofpacket
+ cp_ready : out std_logic; -- ready
+ cp_valid : in std_logic := 'X'; -- valid
+ cp_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ cp_startofpacket : in std_logic := 'X'; -- startofpacket
+ cp_endofpacket : in std_logic := 'X'; -- endofpacket
+ cp_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
+ rf_sink_ready : out std_logic; -- ready
+ rf_sink_valid : in std_logic := 'X'; -- valid
+ rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ rf_sink_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
+ rf_source_ready : in std_logic := 'X'; -- ready
+ rf_source_valid : out std_logic; -- valid
+ rf_source_startofpacket : out std_logic; -- startofpacket
+ rf_source_endofpacket : out std_logic; -- endofpacket
+ rf_source_data : out std_logic_vector(69 downto 0); -- data
+ rdata_fifo_sink_ready : out std_logic; -- ready
+ rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
+ rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
+ rdata_fifo_src_ready : in std_logic := 'X'; -- ready
+ rdata_fifo_src_valid : out std_logic; -- valid
+ rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
+ );
+ end component altera_merlin_slave_agent_0005;
+
+ component altera_merlin_slave_agent_0006 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ m0_address : out std_logic_vector(13 downto 0); -- address
+ m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
+ m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
+ m0_debugaccess : out std_logic; -- debugaccess
+ m0_lock : out std_logic; -- lock
+ m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ m0_read : out std_logic; -- read
+ m0_waitrequest : in std_logic := 'X'; -- waitrequest
+ m0_writedata : out std_logic_vector(31 downto 0); -- writedata
+ m0_write : out std_logic; -- write
+ rp_endofpacket : out std_logic; -- endofpacket
+ rp_ready : in std_logic := 'X'; -- ready
+ rp_valid : out std_logic; -- valid
+ rp_data : out std_logic_vector(68 downto 0); -- data
+ rp_startofpacket : out std_logic; -- startofpacket
+ cp_ready : out std_logic; -- ready
+ cp_valid : in std_logic := 'X'; -- valid
+ cp_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ cp_startofpacket : in std_logic := 'X'; -- startofpacket
+ cp_endofpacket : in std_logic := 'X'; -- endofpacket
+ cp_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
+ rf_sink_ready : out std_logic; -- ready
+ rf_sink_valid : in std_logic := 'X'; -- valid
+ rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ rf_sink_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
+ rf_source_ready : in std_logic := 'X'; -- ready
+ rf_source_valid : out std_logic; -- valid
+ rf_source_startofpacket : out std_logic; -- startofpacket
+ rf_source_endofpacket : out std_logic; -- endofpacket
+ rf_source_data : out std_logic_vector(69 downto 0); -- data
+ rdata_fifo_sink_ready : out std_logic; -- ready
+ rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
+ rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
+ rdata_fifo_src_ready : in std_logic := 'X'; -- ready
+ rdata_fifo_src_valid : out std_logic; -- valid
+ rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
+ );
+ end component altera_merlin_slave_agent_0006;
+
+ component altera_merlin_slave_agent_0007 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ m0_address : out std_logic_vector(13 downto 0); -- address
+ m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
+ m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
+ m0_debugaccess : out std_logic; -- debugaccess
+ m0_lock : out std_logic; -- lock
+ m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ m0_read : out std_logic; -- read
+ m0_waitrequest : in std_logic := 'X'; -- waitrequest
+ m0_writedata : out std_logic_vector(31 downto 0); -- writedata
+ m0_write : out std_logic; -- write
+ rp_endofpacket : out std_logic; -- endofpacket
+ rp_ready : in std_logic := 'X'; -- ready
+ rp_valid : out std_logic; -- valid
+ rp_data : out std_logic_vector(68 downto 0); -- data
+ rp_startofpacket : out std_logic; -- startofpacket
+ cp_ready : out std_logic; -- ready
+ cp_valid : in std_logic := 'X'; -- valid
+ cp_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ cp_startofpacket : in std_logic := 'X'; -- startofpacket
+ cp_endofpacket : in std_logic := 'X'; -- endofpacket
+ cp_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
+ rf_sink_ready : out std_logic; -- ready
+ rf_sink_valid : in std_logic := 'X'; -- valid
+ rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ rf_sink_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
+ rf_source_ready : in std_logic := 'X'; -- ready
+ rf_source_valid : out std_logic; -- valid
+ rf_source_startofpacket : out std_logic; -- startofpacket
+ rf_source_endofpacket : out std_logic; -- endofpacket
+ rf_source_data : out std_logic_vector(69 downto 0); -- data
+ rdata_fifo_sink_ready : out std_logic; -- ready
+ rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
+ rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
+ rdata_fifo_src_ready : in std_logic := 'X'; -- ready
+ rdata_fifo_src_valid : out std_logic; -- valid
+ rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
+ );
+ end component altera_merlin_slave_agent_0007;
+
+ component altera_merlin_slave_agent_0008 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ m0_address : out std_logic_vector(13 downto 0); -- address
+ m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
+ m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
+ m0_debugaccess : out std_logic; -- debugaccess
+ m0_lock : out std_logic; -- lock
+ m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ m0_read : out std_logic; -- read
+ m0_waitrequest : in std_logic := 'X'; -- waitrequest
+ m0_writedata : out std_logic_vector(31 downto 0); -- writedata
+ m0_write : out std_logic; -- write
+ rp_endofpacket : out std_logic; -- endofpacket
+ rp_ready : in std_logic := 'X'; -- ready
+ rp_valid : out std_logic; -- valid
+ rp_data : out std_logic_vector(68 downto 0); -- data
+ rp_startofpacket : out std_logic; -- startofpacket
+ cp_ready : out std_logic; -- ready
+ cp_valid : in std_logic := 'X'; -- valid
+ cp_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ cp_startofpacket : in std_logic := 'X'; -- startofpacket
+ cp_endofpacket : in std_logic := 'X'; -- endofpacket
+ cp_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
+ rf_sink_ready : out std_logic; -- ready
+ rf_sink_valid : in std_logic := 'X'; -- valid
+ rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ rf_sink_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
+ rf_source_ready : in std_logic := 'X'; -- ready
+ rf_source_valid : out std_logic; -- valid
+ rf_source_startofpacket : out std_logic; -- startofpacket
+ rf_source_endofpacket : out std_logic; -- endofpacket
+ rf_source_data : out std_logic_vector(69 downto 0); -- data
+ rdata_fifo_sink_ready : out std_logic; -- ready
+ rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
+ rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
+ rdata_fifo_src_ready : in std_logic := 'X'; -- ready
+ rdata_fifo_src_valid : out std_logic; -- valid
+ rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
+ );
+ end component altera_merlin_slave_agent_0008;
+
+ component altera_merlin_slave_agent_0009 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ m0_address : out std_logic_vector(13 downto 0); -- address
+ m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
+ m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
+ m0_debugaccess : out std_logic; -- debugaccess
+ m0_lock : out std_logic; -- lock
+ m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ m0_read : out std_logic; -- read
+ m0_waitrequest : in std_logic := 'X'; -- waitrequest
+ m0_writedata : out std_logic_vector(31 downto 0); -- writedata
+ m0_write : out std_logic; -- write
+ rp_endofpacket : out std_logic; -- endofpacket
+ rp_ready : in std_logic := 'X'; -- ready
+ rp_valid : out std_logic; -- valid
+ rp_data : out std_logic_vector(68 downto 0); -- data
+ rp_startofpacket : out std_logic; -- startofpacket
+ cp_ready : out std_logic; -- ready
+ cp_valid : in std_logic := 'X'; -- valid
+ cp_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ cp_startofpacket : in std_logic := 'X'; -- startofpacket
+ cp_endofpacket : in std_logic := 'X'; -- endofpacket
+ cp_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
+ rf_sink_ready : out std_logic; -- ready
+ rf_sink_valid : in std_logic := 'X'; -- valid
+ rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ rf_sink_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
+ rf_source_ready : in std_logic := 'X'; -- ready
+ rf_source_valid : out std_logic; -- valid
+ rf_source_startofpacket : out std_logic; -- startofpacket
+ rf_source_endofpacket : out std_logic; -- endofpacket
+ rf_source_data : out std_logic_vector(69 downto 0); -- data
+ rdata_fifo_sink_ready : out std_logic; -- ready
+ rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
+ rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
+ rdata_fifo_src_ready : in std_logic := 'X'; -- ready
+ rdata_fifo_src_valid : out std_logic; -- valid
+ rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
+ );
+ end component altera_merlin_slave_agent_0009;
+
+ component altera_merlin_slave_agent_0010 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ m0_address : out std_logic_vector(13 downto 0); -- address
+ m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
+ m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
+ m0_debugaccess : out std_logic; -- debugaccess
+ m0_lock : out std_logic; -- lock
+ m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ m0_read : out std_logic; -- read
+ m0_waitrequest : in std_logic := 'X'; -- waitrequest
+ m0_writedata : out std_logic_vector(31 downto 0); -- writedata
+ m0_write : out std_logic; -- write
+ rp_endofpacket : out std_logic; -- endofpacket
+ rp_ready : in std_logic := 'X'; -- ready
+ rp_valid : out std_logic; -- valid
+ rp_data : out std_logic_vector(68 downto 0); -- data
+ rp_startofpacket : out std_logic; -- startofpacket
+ cp_ready : out std_logic; -- ready
+ cp_valid : in std_logic := 'X'; -- valid
+ cp_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ cp_startofpacket : in std_logic := 'X'; -- startofpacket
+ cp_endofpacket : in std_logic := 'X'; -- endofpacket
+ cp_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
+ rf_sink_ready : out std_logic; -- ready
+ rf_sink_valid : in std_logic := 'X'; -- valid
+ rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ rf_sink_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
+ rf_source_ready : in std_logic := 'X'; -- ready
+ rf_source_valid : out std_logic; -- valid
+ rf_source_startofpacket : out std_logic; -- startofpacket
+ rf_source_endofpacket : out std_logic; -- endofpacket
+ rf_source_data : out std_logic_vector(69 downto 0); -- data
+ rdata_fifo_sink_ready : out std_logic; -- ready
+ rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
+ rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
+ rdata_fifo_src_ready : in std_logic := 'X'; -- ready
+ rdata_fifo_src_valid : out std_logic; -- valid
+ rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
+ );
+ end component altera_merlin_slave_agent_0010;
+
+ component altera_merlin_slave_agent_0011 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ m0_address : out std_logic_vector(13 downto 0); -- address
+ m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
+ m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
+ m0_debugaccess : out std_logic; -- debugaccess
+ m0_lock : out std_logic; -- lock
+ m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ m0_read : out std_logic; -- read
+ m0_waitrequest : in std_logic := 'X'; -- waitrequest
+ m0_writedata : out std_logic_vector(31 downto 0); -- writedata
+ m0_write : out std_logic; -- write
+ rp_endofpacket : out std_logic; -- endofpacket
+ rp_ready : in std_logic := 'X'; -- ready
+ rp_valid : out std_logic; -- valid
+ rp_data : out std_logic_vector(68 downto 0); -- data
+ rp_startofpacket : out std_logic; -- startofpacket
+ cp_ready : out std_logic; -- ready
+ cp_valid : in std_logic := 'X'; -- valid
+ cp_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ cp_startofpacket : in std_logic := 'X'; -- startofpacket
+ cp_endofpacket : in std_logic := 'X'; -- endofpacket
+ cp_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
+ rf_sink_ready : out std_logic; -- ready
+ rf_sink_valid : in std_logic := 'X'; -- valid
+ rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ rf_sink_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
+ rf_source_ready : in std_logic := 'X'; -- ready
+ rf_source_valid : out std_logic; -- valid
+ rf_source_startofpacket : out std_logic; -- startofpacket
+ rf_source_endofpacket : out std_logic; -- endofpacket
+ rf_source_data : out std_logic_vector(69 downto 0); -- data
+ rdata_fifo_sink_ready : out std_logic; -- ready
+ rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
+ rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
+ rdata_fifo_src_ready : in std_logic := 'X'; -- ready
+ rdata_fifo_src_valid : out std_logic; -- valid
+ rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
+ );
+ end component altera_merlin_slave_agent_0011;
+
+ component altera_merlin_slave_agent_0012 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ m0_address : out std_logic_vector(13 downto 0); -- address
+ m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
+ m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
+ m0_debugaccess : out std_logic; -- debugaccess
+ m0_lock : out std_logic; -- lock
+ m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ m0_read : out std_logic; -- read
+ m0_waitrequest : in std_logic := 'X'; -- waitrequest
+ m0_writedata : out std_logic_vector(31 downto 0); -- writedata
+ m0_write : out std_logic; -- write
+ rp_endofpacket : out std_logic; -- endofpacket
+ rp_ready : in std_logic := 'X'; -- ready
+ rp_valid : out std_logic; -- valid
+ rp_data : out std_logic_vector(68 downto 0); -- data
+ rp_startofpacket : out std_logic; -- startofpacket
+ cp_ready : out std_logic; -- ready
+ cp_valid : in std_logic := 'X'; -- valid
+ cp_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ cp_startofpacket : in std_logic := 'X'; -- startofpacket
+ cp_endofpacket : in std_logic := 'X'; -- endofpacket
+ cp_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
+ rf_sink_ready : out std_logic; -- ready
+ rf_sink_valid : in std_logic := 'X'; -- valid
+ rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ rf_sink_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
+ rf_source_ready : in std_logic := 'X'; -- ready
+ rf_source_valid : out std_logic; -- valid
+ rf_source_startofpacket : out std_logic; -- startofpacket
+ rf_source_endofpacket : out std_logic; -- endofpacket
+ rf_source_data : out std_logic_vector(69 downto 0); -- data
+ rdata_fifo_sink_ready : out std_logic; -- ready
+ rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
+ rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
+ rdata_fifo_src_ready : in std_logic := 'X'; -- ready
+ rdata_fifo_src_valid : out std_logic; -- valid
+ rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
+ );
+ end component altera_merlin_slave_agent_0012;
+
+ component altera_merlin_slave_agent_0013 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ m0_address : out std_logic_vector(13 downto 0); -- address
+ m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
+ m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
+ m0_debugaccess : out std_logic; -- debugaccess
+ m0_lock : out std_logic; -- lock
+ m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ m0_read : out std_logic; -- read
+ m0_waitrequest : in std_logic := 'X'; -- waitrequest
+ m0_writedata : out std_logic_vector(31 downto 0); -- writedata
+ m0_write : out std_logic; -- write
+ rp_endofpacket : out std_logic; -- endofpacket
+ rp_ready : in std_logic := 'X'; -- ready
+ rp_valid : out std_logic; -- valid
+ rp_data : out std_logic_vector(68 downto 0); -- data
+ rp_startofpacket : out std_logic; -- startofpacket
+ cp_ready : out std_logic; -- ready
+ cp_valid : in std_logic := 'X'; -- valid
+ cp_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ cp_startofpacket : in std_logic := 'X'; -- startofpacket
+ cp_endofpacket : in std_logic := 'X'; -- endofpacket
+ cp_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
+ rf_sink_ready : out std_logic; -- ready
+ rf_sink_valid : in std_logic := 'X'; -- valid
+ rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ rf_sink_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
+ rf_source_ready : in std_logic := 'X'; -- ready
+ rf_source_valid : out std_logic; -- valid
+ rf_source_startofpacket : out std_logic; -- startofpacket
+ rf_source_endofpacket : out std_logic; -- endofpacket
+ rf_source_data : out std_logic_vector(69 downto 0); -- data
+ rdata_fifo_sink_ready : out std_logic; -- ready
+ rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
+ rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
+ rdata_fifo_src_ready : in std_logic := 'X'; -- ready
+ rdata_fifo_src_valid : out std_logic; -- valid
+ rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
+ );
+ end component altera_merlin_slave_agent_0013;
+
+ component altera_merlin_slave_agent_0014 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ m0_address : out std_logic_vector(13 downto 0); -- address
+ m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
+ m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
+ m0_debugaccess : out std_logic; -- debugaccess
+ m0_lock : out std_logic; -- lock
+ m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ m0_read : out std_logic; -- read
+ m0_waitrequest : in std_logic := 'X'; -- waitrequest
+ m0_writedata : out std_logic_vector(31 downto 0); -- writedata
+ m0_write : out std_logic; -- write
+ rp_endofpacket : out std_logic; -- endofpacket
+ rp_ready : in std_logic := 'X'; -- ready
+ rp_valid : out std_logic; -- valid
+ rp_data : out std_logic_vector(68 downto 0); -- data
+ rp_startofpacket : out std_logic; -- startofpacket
+ cp_ready : out std_logic; -- ready
+ cp_valid : in std_logic := 'X'; -- valid
+ cp_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ cp_startofpacket : in std_logic := 'X'; -- startofpacket
+ cp_endofpacket : in std_logic := 'X'; -- endofpacket
+ cp_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
+ rf_sink_ready : out std_logic; -- ready
+ rf_sink_valid : in std_logic := 'X'; -- valid
+ rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ rf_sink_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
+ rf_source_ready : in std_logic := 'X'; -- ready
+ rf_source_valid : out std_logic; -- valid
+ rf_source_startofpacket : out std_logic; -- startofpacket
+ rf_source_endofpacket : out std_logic; -- endofpacket
+ rf_source_data : out std_logic_vector(69 downto 0); -- data
+ rdata_fifo_sink_ready : out std_logic; -- ready
+ rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
+ rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
+ rdata_fifo_src_ready : in std_logic := 'X'; -- ready
+ rdata_fifo_src_valid : out std_logic; -- valid
+ rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
+ );
+ end component altera_merlin_slave_agent_0014;
+
+ component altera_merlin_slave_agent_0015 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ m0_address : out std_logic_vector(13 downto 0); -- address
+ m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
+ m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
+ m0_debugaccess : out std_logic; -- debugaccess
+ m0_lock : out std_logic; -- lock
+ m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ m0_read : out std_logic; -- read
+ m0_waitrequest : in std_logic := 'X'; -- waitrequest
+ m0_writedata : out std_logic_vector(31 downto 0); -- writedata
+ m0_write : out std_logic; -- write
+ rp_endofpacket : out std_logic; -- endofpacket
+ rp_ready : in std_logic := 'X'; -- ready
+ rp_valid : out std_logic; -- valid
+ rp_data : out std_logic_vector(68 downto 0); -- data
+ rp_startofpacket : out std_logic; -- startofpacket
+ cp_ready : out std_logic; -- ready
+ cp_valid : in std_logic := 'X'; -- valid
+ cp_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ cp_startofpacket : in std_logic := 'X'; -- startofpacket
+ cp_endofpacket : in std_logic := 'X'; -- endofpacket
+ cp_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
+ rf_sink_ready : out std_logic; -- ready
+ rf_sink_valid : in std_logic := 'X'; -- valid
+ rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ rf_sink_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
+ rf_source_ready : in std_logic := 'X'; -- ready
+ rf_source_valid : out std_logic; -- valid
+ rf_source_startofpacket : out std_logic; -- startofpacket
+ rf_source_endofpacket : out std_logic; -- endofpacket
+ rf_source_data : out std_logic_vector(69 downto 0); -- data
+ rdata_fifo_sink_ready : out std_logic; -- ready
+ rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
+ rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
+ rdata_fifo_src_ready : in std_logic := 'X'; -- ready
+ rdata_fifo_src_valid : out std_logic; -- valid
+ rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
+ );
+ end component altera_merlin_slave_agent_0015;
+
+ component altera_merlin_slave_agent_0016 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ m0_address : out std_logic_vector(13 downto 0); -- address
+ m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
+ m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
+ m0_debugaccess : out std_logic; -- debugaccess
+ m0_lock : out std_logic; -- lock
+ m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ m0_read : out std_logic; -- read
+ m0_waitrequest : in std_logic := 'X'; -- waitrequest
+ m0_writedata : out std_logic_vector(31 downto 0); -- writedata
+ m0_write : out std_logic; -- write
+ rp_endofpacket : out std_logic; -- endofpacket
+ rp_ready : in std_logic := 'X'; -- ready
+ rp_valid : out std_logic; -- valid
+ rp_data : out std_logic_vector(68 downto 0); -- data
+ rp_startofpacket : out std_logic; -- startofpacket
+ cp_ready : out std_logic; -- ready
+ cp_valid : in std_logic := 'X'; -- valid
+ cp_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ cp_startofpacket : in std_logic := 'X'; -- startofpacket
+ cp_endofpacket : in std_logic := 'X'; -- endofpacket
+ cp_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
+ rf_sink_ready : out std_logic; -- ready
+ rf_sink_valid : in std_logic := 'X'; -- valid
+ rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ rf_sink_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
+ rf_source_ready : in std_logic := 'X'; -- ready
+ rf_source_valid : out std_logic; -- valid
+ rf_source_startofpacket : out std_logic; -- startofpacket
+ rf_source_endofpacket : out std_logic; -- endofpacket
+ rf_source_data : out std_logic_vector(69 downto 0); -- data
+ rdata_fifo_sink_ready : out std_logic; -- ready
+ rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
+ rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
+ rdata_fifo_src_ready : in std_logic := 'X'; -- ready
+ rdata_fifo_src_valid : out std_logic; -- valid
+ rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
+ );
+ end component altera_merlin_slave_agent_0016;
+
+ component altera_merlin_master_agent_0003 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ av_address : in std_logic_vector(13 downto 0) := (others => 'X'); -- address
+ av_write : in std_logic := 'X'; -- write
+ av_read : in std_logic := 'X'; -- read
+ av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ av_readdata : out std_logic_vector(31 downto 0); -- readdata
+ av_waitrequest : out std_logic; -- waitrequest
+ av_readdatavalid : out std_logic; -- readdatavalid
+ av_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
+ av_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
+ av_debugaccess : in std_logic := 'X'; -- debugaccess
+ av_lock : in std_logic := 'X'; -- lock
+ cp_valid : out std_logic; -- valid
+ cp_data : out std_logic_vector(68 downto 0); -- data
+ cp_startofpacket : out std_logic; -- startofpacket
+ cp_endofpacket : out std_logic; -- endofpacket
+ cp_ready : in std_logic := 'X'; -- ready
+ rp_valid : in std_logic := 'X'; -- valid
+ rp_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ rp_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
+ rp_startofpacket : in std_logic := 'X'; -- startofpacket
+ rp_endofpacket : in std_logic := 'X'; -- endofpacket
+ rp_ready : out std_logic -- ready
+ );
+ end component altera_merlin_master_agent_0003;
+
+ component altera_merlin_slave_agent_0017 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ m0_address : out std_logic_vector(13 downto 0); -- address
+ m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
+ m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
+ m0_debugaccess : out std_logic; -- debugaccess
+ m0_lock : out std_logic; -- lock
+ m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ m0_read : out std_logic; -- read
+ m0_waitrequest : in std_logic := 'X'; -- waitrequest
+ m0_writedata : out std_logic_vector(31 downto 0); -- writedata
+ m0_write : out std_logic; -- write
+ rp_endofpacket : out std_logic; -- endofpacket
+ rp_ready : in std_logic := 'X'; -- ready
+ rp_valid : out std_logic; -- valid
+ rp_data : out std_logic_vector(68 downto 0); -- data
+ rp_startofpacket : out std_logic; -- startofpacket
+ cp_ready : out std_logic; -- ready
+ cp_valid : in std_logic := 'X'; -- valid
+ cp_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ cp_startofpacket : in std_logic := 'X'; -- startofpacket
+ cp_endofpacket : in std_logic := 'X'; -- endofpacket
+ cp_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
+ rf_sink_ready : out std_logic; -- ready
+ rf_sink_valid : in std_logic := 'X'; -- valid
+ rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ rf_sink_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
+ rf_source_ready : in std_logic := 'X'; -- ready
+ rf_source_valid : out std_logic; -- valid
+ rf_source_startofpacket : out std_logic; -- startofpacket
+ rf_source_endofpacket : out std_logic; -- endofpacket
+ rf_source_data : out std_logic_vector(69 downto 0); -- data
+ rdata_fifo_sink_ready : out std_logic; -- ready
+ rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
+ rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
+ rdata_fifo_src_ready : in std_logic := 'X'; -- ready
+ rdata_fifo_src_valid : out std_logic; -- valid
+ rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
+ );
+ end component altera_merlin_slave_agent_0017;
+
+ component altera_merlin_router_0001 is
+ port (
+ sink_ready : out std_logic; -- ready
+ sink_valid : in std_logic := 'X'; -- valid
+ sink_data : in std_logic_vector(65 downto 0) := (others => 'X'); -- data
+ sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ src_ready : in std_logic := 'X'; -- ready
+ src_valid : out std_logic; -- valid
+ src_data : out std_logic_vector(65 downto 0); -- data
+ src_channel : out std_logic_vector(1 downto 0); -- channel
+ src_startofpacket : out std_logic; -- startofpacket
+ src_endofpacket : out std_logic -- endofpacket
+ );
+ end component altera_merlin_router_0001;
+
+ component altera_merlin_router_0002 is
+ port (
+ sink_ready : out std_logic; -- ready
+ sink_valid : in std_logic := 'X'; -- valid
+ sink_data : in std_logic_vector(65 downto 0) := (others => 'X'); -- data
+ sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ src_ready : in std_logic := 'X'; -- ready
+ src_valid : out std_logic; -- valid
+ src_data : out std_logic_vector(65 downto 0); -- data
+ src_channel : out std_logic_vector(1 downto 0); -- channel
+ src_startofpacket : out std_logic; -- startofpacket
+ src_endofpacket : out std_logic -- endofpacket
+ );
+ end component altera_merlin_router_0002;
+
+ component altera_merlin_router_0003 is
+ port (
+ sink_ready : out std_logic; -- ready
+ sink_valid : in std_logic := 'X'; -- valid
+ sink_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ src_ready : in std_logic := 'X'; -- ready
+ src_valid : out std_logic; -- valid
+ src_data : out std_logic_vector(68 downto 0); -- data
+ src_channel : out std_logic_vector(7 downto 0); -- channel
+ src_startofpacket : out std_logic; -- startofpacket
+ src_endofpacket : out std_logic -- endofpacket
+ );
+ end component altera_merlin_router_0003;
+
+ component altera_merlin_router_0004 is
+ port (
+ sink_ready : out std_logic; -- ready
+ sink_valid : in std_logic := 'X'; -- valid
+ sink_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ src_ready : in std_logic := 'X'; -- ready
+ src_valid : out std_logic; -- valid
+ src_data : out std_logic_vector(68 downto 0); -- data
+ src_channel : out std_logic_vector(7 downto 0); -- channel
+ src_startofpacket : out std_logic; -- startofpacket
+ src_endofpacket : out std_logic -- endofpacket
+ );
+ end component altera_merlin_router_0004;
+
+ component altera_merlin_router_0005 is
+ port (
+ sink_ready : out std_logic; -- ready
+ sink_valid : in std_logic := 'X'; -- valid
+ sink_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ src_ready : in std_logic := 'X'; -- ready
+ src_valid : out std_logic; -- valid
+ src_data : out std_logic_vector(68 downto 0); -- data
+ src_channel : out std_logic_vector(6 downto 0); -- channel
+ src_startofpacket : out std_logic; -- startofpacket
+ src_endofpacket : out std_logic -- endofpacket
+ );
+ end component altera_merlin_router_0005;
+
+ component altera_merlin_router_0006 is
+ port (
+ sink_ready : out std_logic; -- ready
+ sink_valid : in std_logic := 'X'; -- valid
+ sink_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ src_ready : in std_logic := 'X'; -- ready
+ src_valid : out std_logic; -- valid
+ src_data : out std_logic_vector(68 downto 0); -- data
+ src_channel : out std_logic_vector(6 downto 0); -- channel
+ src_startofpacket : out std_logic; -- startofpacket
+ src_endofpacket : out std_logic -- endofpacket
+ );
+ end component altera_merlin_router_0006;
+
+ component altera_merlin_traffic_limiter_0001 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ cmd_sink_ready : out std_logic; -- ready
+ cmd_sink_valid : in std_logic := 'X'; -- valid
+ cmd_sink_data : in std_logic_vector(65 downto 0) := (others => 'X'); -- data
+ cmd_sink_channel : in std_logic_vector(1 downto 0) := (others => 'X'); -- channel
+ cmd_sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ cmd_sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ cmd_src_ready : in std_logic := 'X'; -- ready
+ cmd_src_data : out std_logic_vector(65 downto 0); -- data
+ cmd_src_channel : out std_logic_vector(1 downto 0); -- channel
+ cmd_src_startofpacket : out std_logic; -- startofpacket
+ cmd_src_endofpacket : out std_logic; -- endofpacket
+ rsp_sink_ready : out std_logic; -- ready
+ rsp_sink_valid : in std_logic := 'X'; -- valid
+ rsp_sink_channel : in std_logic_vector(1 downto 0) := (others => 'X'); -- channel
+ rsp_sink_data : in std_logic_vector(65 downto 0) := (others => 'X'); -- data
+ rsp_sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ rsp_sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ rsp_src_ready : in std_logic := 'X'; -- ready
+ rsp_src_valid : out std_logic; -- valid
+ rsp_src_data : out std_logic_vector(65 downto 0); -- data
+ rsp_src_channel : out std_logic_vector(1 downto 0); -- channel
+ rsp_src_startofpacket : out std_logic; -- startofpacket
+ rsp_src_endofpacket : out std_logic; -- endofpacket
+ cmd_src_valid : out std_logic_vector(1 downto 0) -- data
+ );
+ end component altera_merlin_traffic_limiter_0001;
+
+ component altera_merlin_traffic_limiter_0002 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ cmd_sink_ready : out std_logic; -- ready
+ cmd_sink_valid : in std_logic := 'X'; -- valid
+ cmd_sink_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ cmd_sink_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
+ cmd_sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ cmd_sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ cmd_src_ready : in std_logic := 'X'; -- ready
+ cmd_src_data : out std_logic_vector(68 downto 0); -- data
+ cmd_src_channel : out std_logic_vector(7 downto 0); -- channel
+ cmd_src_startofpacket : out std_logic; -- startofpacket
+ cmd_src_endofpacket : out std_logic; -- endofpacket
+ rsp_sink_ready : out std_logic; -- ready
+ rsp_sink_valid : in std_logic := 'X'; -- valid
+ rsp_sink_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
+ rsp_sink_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ rsp_sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ rsp_sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ rsp_src_ready : in std_logic := 'X'; -- ready
+ rsp_src_valid : out std_logic; -- valid
+ rsp_src_data : out std_logic_vector(68 downto 0); -- data
+ rsp_src_channel : out std_logic_vector(7 downto 0); -- channel
+ rsp_src_startofpacket : out std_logic; -- startofpacket
+ rsp_src_endofpacket : out std_logic; -- endofpacket
+ cmd_src_valid : out std_logic_vector(7 downto 0) -- data
+ );
+ end component altera_merlin_traffic_limiter_0002;
+
+ component altera_merlin_traffic_limiter_0003 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ cmd_sink_ready : out std_logic; -- ready
+ cmd_sink_valid : in std_logic := 'X'; -- valid
+ cmd_sink_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ cmd_sink_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
+ cmd_sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ cmd_sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ cmd_src_ready : in std_logic := 'X'; -- ready
+ cmd_src_data : out std_logic_vector(68 downto 0); -- data
+ cmd_src_channel : out std_logic_vector(6 downto 0); -- channel
+ cmd_src_startofpacket : out std_logic; -- startofpacket
+ cmd_src_endofpacket : out std_logic; -- endofpacket
+ rsp_sink_ready : out std_logic; -- ready
+ rsp_sink_valid : in std_logic := 'X'; -- valid
+ rsp_sink_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
+ rsp_sink_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ rsp_sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ rsp_sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ rsp_src_ready : in std_logic := 'X'; -- ready
+ rsp_src_valid : out std_logic; -- valid
+ rsp_src_data : out std_logic_vector(68 downto 0); -- data
+ rsp_src_channel : out std_logic_vector(6 downto 0); -- channel
+ rsp_src_startofpacket : out std_logic; -- startofpacket
+ rsp_src_endofpacket : out std_logic; -- endofpacket
+ cmd_src_valid : out std_logic_vector(6 downto 0) -- data
+ );
+ end component altera_merlin_traffic_limiter_0003;
+
+ component altera_reset_controller_0001 is
+ port (
+ reset_in0 : in std_logic := 'X'; -- reset
+ clk : in std_logic := 'X'; -- clk
+ reset_out : out std_logic -- reset
+ );
+ end component altera_reset_controller_0001;
+
+ component altera_merlin_demultiplexer_0001 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ sink_ready : out std_logic; -- ready
+ sink_channel : in std_logic_vector(1 downto 0) := (others => 'X'); -- channel
+ sink_data : in std_logic_vector(65 downto 0) := (others => 'X'); -- data
+ sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ sink_valid : in std_logic_vector(1 downto 0) := (others => 'X'); -- data
+ src0_ready : in std_logic := 'X'; -- ready
+ src0_valid : out std_logic; -- valid
+ src0_data : out std_logic_vector(65 downto 0); -- data
+ src0_channel : out std_logic_vector(1 downto 0); -- channel
+ src0_startofpacket : out std_logic; -- startofpacket
+ src0_endofpacket : out std_logic; -- endofpacket
+ src1_ready : in std_logic := 'X'; -- ready
+ src1_valid : out std_logic; -- valid
+ src1_data : out std_logic_vector(65 downto 0); -- data
+ src1_channel : out std_logic_vector(1 downto 0); -- channel
+ src1_startofpacket : out std_logic; -- startofpacket
+ src1_endofpacket : out std_logic -- endofpacket
+ );
+ end component altera_merlin_demultiplexer_0001;
+
+ component altera_merlin_demultiplexer_0002 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ sink_ready : out std_logic; -- ready
+ sink_channel : in std_logic_vector(1 downto 0) := (others => 'X'); -- channel
+ sink_data : in std_logic_vector(65 downto 0) := (others => 'X'); -- data
+ sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
+ src0_ready : in std_logic := 'X'; -- ready
+ src0_valid : out std_logic; -- valid
+ src0_data : out std_logic_vector(65 downto 0); -- data
+ src0_channel : out std_logic_vector(1 downto 0); -- channel
+ src0_startofpacket : out std_logic; -- startofpacket
+ src0_endofpacket : out std_logic -- endofpacket
+ );
+ end component altera_merlin_demultiplexer_0002;
+
+ component altera_merlin_multiplexer_0001 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ src_ready : in std_logic := 'X'; -- ready
+ src_valid : out std_logic; -- valid
+ src_data : out std_logic_vector(65 downto 0); -- data
+ src_channel : out std_logic_vector(1 downto 0); -- channel
+ src_startofpacket : out std_logic; -- startofpacket
+ src_endofpacket : out std_logic; -- endofpacket
+ sink0_ready : out std_logic; -- ready
+ sink0_valid : in std_logic := 'X'; -- valid
+ sink0_channel : in std_logic_vector(1 downto 0) := (others => 'X'); -- channel
+ sink0_data : in std_logic_vector(65 downto 0) := (others => 'X'); -- data
+ sink0_startofpacket : in std_logic := 'X'; -- startofpacket
+ sink0_endofpacket : in std_logic := 'X'; -- endofpacket
+ sink1_ready : out std_logic; -- ready
+ sink1_valid : in std_logic := 'X'; -- valid
+ sink1_channel : in std_logic_vector(1 downto 0) := (others => 'X'); -- channel
+ sink1_data : in std_logic_vector(65 downto 0) := (others => 'X'); -- data
+ sink1_startofpacket : in std_logic := 'X'; -- startofpacket
+ sink1_endofpacket : in std_logic := 'X' -- endofpacket
+ );
+ end component altera_merlin_multiplexer_0001;
+
+ component altera_merlin_demultiplexer_0003 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ sink_ready : out std_logic; -- ready
+ sink_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
+ sink_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ sink_valid : in std_logic_vector(7 downto 0) := (others => 'X'); -- data
+ src0_ready : in std_logic := 'X'; -- ready
+ src0_valid : out std_logic; -- valid
+ src0_data : out std_logic_vector(68 downto 0); -- data
+ src0_channel : out std_logic_vector(7 downto 0); -- channel
+ src0_startofpacket : out std_logic; -- startofpacket
+ src0_endofpacket : out std_logic; -- endofpacket
+ src1_ready : in std_logic := 'X'; -- ready
+ src1_valid : out std_logic; -- valid
+ src1_data : out std_logic_vector(68 downto 0); -- data
+ src1_channel : out std_logic_vector(7 downto 0); -- channel
+ src1_startofpacket : out std_logic; -- startofpacket
+ src1_endofpacket : out std_logic; -- endofpacket
+ src2_ready : in std_logic := 'X'; -- ready
+ src2_valid : out std_logic; -- valid
+ src2_data : out std_logic_vector(68 downto 0); -- data
+ src2_channel : out std_logic_vector(7 downto 0); -- channel
+ src2_startofpacket : out std_logic; -- startofpacket
+ src2_endofpacket : out std_logic; -- endofpacket
+ src3_ready : in std_logic := 'X'; -- ready
+ src3_valid : out std_logic; -- valid
+ src3_data : out std_logic_vector(68 downto 0); -- data
+ src3_channel : out std_logic_vector(7 downto 0); -- channel
+ src3_startofpacket : out std_logic; -- startofpacket
+ src3_endofpacket : out std_logic; -- endofpacket
+ src4_ready : in std_logic := 'X'; -- ready
+ src4_valid : out std_logic; -- valid
+ src4_data : out std_logic_vector(68 downto 0); -- data
+ src4_channel : out std_logic_vector(7 downto 0); -- channel
+ src4_startofpacket : out std_logic; -- startofpacket
+ src4_endofpacket : out std_logic; -- endofpacket
+ src5_ready : in std_logic := 'X'; -- ready
+ src5_valid : out std_logic; -- valid
+ src5_data : out std_logic_vector(68 downto 0); -- data
+ src5_channel : out std_logic_vector(7 downto 0); -- channel
+ src5_startofpacket : out std_logic; -- startofpacket
+ src5_endofpacket : out std_logic; -- endofpacket
+ src6_ready : in std_logic := 'X'; -- ready
+ src6_valid : out std_logic; -- valid
+ src6_data : out std_logic_vector(68 downto 0); -- data
+ src6_channel : out std_logic_vector(7 downto 0); -- channel
+ src6_startofpacket : out std_logic; -- startofpacket
+ src6_endofpacket : out std_logic; -- endofpacket
+ src7_ready : in std_logic := 'X'; -- ready
+ src7_valid : out std_logic; -- valid
+ src7_data : out std_logic_vector(68 downto 0); -- data
+ src7_channel : out std_logic_vector(7 downto 0); -- channel
+ src7_startofpacket : out std_logic; -- startofpacket
+ src7_endofpacket : out std_logic -- endofpacket
+ );
+ end component altera_merlin_demultiplexer_0003;
+
+ component altera_merlin_demultiplexer_0004 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ sink_ready : out std_logic; -- ready
+ sink_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
+ sink_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
+ src0_ready : in std_logic := 'X'; -- ready
+ src0_valid : out std_logic; -- valid
+ src0_data : out std_logic_vector(68 downto 0); -- data
+ src0_channel : out std_logic_vector(7 downto 0); -- channel
+ src0_startofpacket : out std_logic; -- startofpacket
+ src0_endofpacket : out std_logic -- endofpacket
+ );
+ end component altera_merlin_demultiplexer_0004;
+
+ component altera_merlin_multiplexer_0002 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ src_ready : in std_logic := 'X'; -- ready
+ src_valid : out std_logic; -- valid
+ src_data : out std_logic_vector(68 downto 0); -- data
+ src_channel : out std_logic_vector(7 downto 0); -- channel
+ src_startofpacket : out std_logic; -- startofpacket
+ src_endofpacket : out std_logic; -- endofpacket
+ sink0_ready : out std_logic; -- ready
+ sink0_valid : in std_logic := 'X'; -- valid
+ sink0_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
+ sink0_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ sink0_startofpacket : in std_logic := 'X'; -- startofpacket
+ sink0_endofpacket : in std_logic := 'X'; -- endofpacket
+ sink1_ready : out std_logic; -- ready
+ sink1_valid : in std_logic := 'X'; -- valid
+ sink1_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
+ sink1_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ sink1_startofpacket : in std_logic := 'X'; -- startofpacket
+ sink1_endofpacket : in std_logic := 'X'; -- endofpacket
+ sink2_ready : out std_logic; -- ready
+ sink2_valid : in std_logic := 'X'; -- valid
+ sink2_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
+ sink2_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ sink2_startofpacket : in std_logic := 'X'; -- startofpacket
+ sink2_endofpacket : in std_logic := 'X'; -- endofpacket
+ sink3_ready : out std_logic; -- ready
+ sink3_valid : in std_logic := 'X'; -- valid
+ sink3_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
+ sink3_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ sink3_startofpacket : in std_logic := 'X'; -- startofpacket
+ sink3_endofpacket : in std_logic := 'X'; -- endofpacket
+ sink4_ready : out std_logic; -- ready
+ sink4_valid : in std_logic := 'X'; -- valid
+ sink4_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
+ sink4_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ sink4_startofpacket : in std_logic := 'X'; -- startofpacket
+ sink4_endofpacket : in std_logic := 'X'; -- endofpacket
+ sink5_ready : out std_logic; -- ready
+ sink5_valid : in std_logic := 'X'; -- valid
+ sink5_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
+ sink5_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ sink5_startofpacket : in std_logic := 'X'; -- startofpacket
+ sink5_endofpacket : in std_logic := 'X'; -- endofpacket
+ sink6_ready : out std_logic; -- ready
+ sink6_valid : in std_logic := 'X'; -- valid
+ sink6_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
+ sink6_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ sink6_startofpacket : in std_logic := 'X'; -- startofpacket
+ sink6_endofpacket : in std_logic := 'X'; -- endofpacket
+ sink7_ready : out std_logic; -- ready
+ sink7_valid : in std_logic := 'X'; -- valid
+ sink7_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
+ sink7_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ sink7_startofpacket : in std_logic := 'X'; -- startofpacket
+ sink7_endofpacket : in std_logic := 'X' -- endofpacket
+ );
+ end component altera_merlin_multiplexer_0002;
+
+ component altera_merlin_demultiplexer_0005 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ sink_ready : out std_logic; -- ready
+ sink_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
+ sink_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ sink_valid : in std_logic_vector(6 downto 0) := (others => 'X'); -- data
+ src0_ready : in std_logic := 'X'; -- ready
+ src0_valid : out std_logic; -- valid
+ src0_data : out std_logic_vector(68 downto 0); -- data
+ src0_channel : out std_logic_vector(6 downto 0); -- channel
+ src0_startofpacket : out std_logic; -- startofpacket
+ src0_endofpacket : out std_logic; -- endofpacket
+ src1_ready : in std_logic := 'X'; -- ready
+ src1_valid : out std_logic; -- valid
+ src1_data : out std_logic_vector(68 downto 0); -- data
+ src1_channel : out std_logic_vector(6 downto 0); -- channel
+ src1_startofpacket : out std_logic; -- startofpacket
+ src1_endofpacket : out std_logic; -- endofpacket
+ src2_ready : in std_logic := 'X'; -- ready
+ src2_valid : out std_logic; -- valid
+ src2_data : out std_logic_vector(68 downto 0); -- data
+ src2_channel : out std_logic_vector(6 downto 0); -- channel
+ src2_startofpacket : out std_logic; -- startofpacket
+ src2_endofpacket : out std_logic; -- endofpacket
+ src3_ready : in std_logic := 'X'; -- ready
+ src3_valid : out std_logic; -- valid
+ src3_data : out std_logic_vector(68 downto 0); -- data
+ src3_channel : out std_logic_vector(6 downto 0); -- channel
+ src3_startofpacket : out std_logic; -- startofpacket
+ src3_endofpacket : out std_logic; -- endofpacket
+ src4_ready : in std_logic := 'X'; -- ready
+ src4_valid : out std_logic; -- valid
+ src4_data : out std_logic_vector(68 downto 0); -- data
+ src4_channel : out std_logic_vector(6 downto 0); -- channel
+ src4_startofpacket : out std_logic; -- startofpacket
+ src4_endofpacket : out std_logic; -- endofpacket
+ src5_ready : in std_logic := 'X'; -- ready
+ src5_valid : out std_logic; -- valid
+ src5_data : out std_logic_vector(68 downto 0); -- data
+ src5_channel : out std_logic_vector(6 downto 0); -- channel
+ src5_startofpacket : out std_logic; -- startofpacket
+ src5_endofpacket : out std_logic; -- endofpacket
+ src6_ready : in std_logic := 'X'; -- ready
+ src6_valid : out std_logic; -- valid
+ src6_data : out std_logic_vector(68 downto 0); -- data
+ src6_channel : out std_logic_vector(6 downto 0); -- channel
+ src6_startofpacket : out std_logic; -- startofpacket
+ src6_endofpacket : out std_logic -- endofpacket
+ );
+ end component altera_merlin_demultiplexer_0005;
+
+ component altera_merlin_demultiplexer_0006 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ sink_ready : out std_logic; -- ready
+ sink_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
+ sink_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ sink_startofpacket : in std_logic := 'X'; -- startofpacket
+ sink_endofpacket : in std_logic := 'X'; -- endofpacket
+ sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
+ src0_ready : in std_logic := 'X'; -- ready
+ src0_valid : out std_logic; -- valid
+ src0_data : out std_logic_vector(68 downto 0); -- data
+ src0_channel : out std_logic_vector(6 downto 0); -- channel
+ src0_startofpacket : out std_logic; -- startofpacket
+ src0_endofpacket : out std_logic -- endofpacket
+ );
+ end component altera_merlin_demultiplexer_0006;
+
+ component altera_merlin_multiplexer_0003 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ src_ready : in std_logic := 'X'; -- ready
+ src_valid : out std_logic; -- valid
+ src_data : out std_logic_vector(68 downto 0); -- data
+ src_channel : out std_logic_vector(6 downto 0); -- channel
+ src_startofpacket : out std_logic; -- startofpacket
+ src_endofpacket : out std_logic; -- endofpacket
+ sink0_ready : out std_logic; -- ready
+ sink0_valid : in std_logic := 'X'; -- valid
+ sink0_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
+ sink0_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ sink0_startofpacket : in std_logic := 'X'; -- startofpacket
+ sink0_endofpacket : in std_logic := 'X'; -- endofpacket
+ sink1_ready : out std_logic; -- ready
+ sink1_valid : in std_logic := 'X'; -- valid
+ sink1_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
+ sink1_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ sink1_startofpacket : in std_logic := 'X'; -- startofpacket
+ sink1_endofpacket : in std_logic := 'X'; -- endofpacket
+ sink2_ready : out std_logic; -- ready
+ sink2_valid : in std_logic := 'X'; -- valid
+ sink2_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
+ sink2_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ sink2_startofpacket : in std_logic := 'X'; -- startofpacket
+ sink2_endofpacket : in std_logic := 'X'; -- endofpacket
+ sink3_ready : out std_logic; -- ready
+ sink3_valid : in std_logic := 'X'; -- valid
+ sink3_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
+ sink3_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ sink3_startofpacket : in std_logic := 'X'; -- startofpacket
+ sink3_endofpacket : in std_logic := 'X'; -- endofpacket
+ sink4_ready : out std_logic; -- ready
+ sink4_valid : in std_logic := 'X'; -- valid
+ sink4_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
+ sink4_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ sink4_startofpacket : in std_logic := 'X'; -- startofpacket
+ sink4_endofpacket : in std_logic := 'X'; -- endofpacket
+ sink5_ready : out std_logic; -- ready
+ sink5_valid : in std_logic := 'X'; -- valid
+ sink5_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
+ sink5_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ sink5_startofpacket : in std_logic := 'X'; -- startofpacket
+ sink5_endofpacket : in std_logic := 'X'; -- endofpacket
+ sink6_ready : out std_logic; -- ready
+ sink6_valid : in std_logic := 'X'; -- valid
+ sink6_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
+ sink6_data : in std_logic_vector(68 downto 0) := (others => 'X'); -- data
+ sink6_startofpacket : in std_logic := 'X'; -- startofpacket
+ sink6_endofpacket : in std_logic := 'X' -- endofpacket
+ );
+ end component altera_merlin_multiplexer_0003;
+
+ component altera_avalon_st_handshake_clock_crosser_0001 is
+ port (
+ in_clk : in std_logic := 'X'; -- clk
+ in_reset : in std_logic := 'X'; -- reset
+ out_clk : in std_logic := 'X'; -- clk
+ out_reset : in std_logic := 'X'; -- reset
+ in_ready : out std_logic; -- ready
+ in_valid : in std_logic := 'X'; -- valid
+ in_startofpacket : in std_logic := 'X'; -- startofpacket
+ in_endofpacket : in std_logic := 'X'; -- endofpacket
+ in_channel : in std_logic_vector(1 downto 0) := (others => 'X'); -- channel
+ in_data : in std_logic_vector(65 downto 0) := (others => 'X'); -- data
+ out_ready : in std_logic := 'X'; -- ready
+ out_valid : out std_logic; -- valid
+ out_startofpacket : out std_logic; -- startofpacket
+ out_endofpacket : out std_logic; -- endofpacket
+ out_channel : out std_logic_vector(1 downto 0); -- channel
+ out_data : out std_logic_vector(65 downto 0) -- data
+ );
+ end component altera_avalon_st_handshake_clock_crosser_0001;
+
+ component ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control is
+ generic (
+ BITSPERSYMBOL : integer := 8;
+ SYMBOLSPERBEAT : integer := 8;
+ ERROR_WIDTH : integer := 1;
+ USE_READY : integer := 1
+ );
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ csr_write : in std_logic := 'X'; -- write
+ csr_read : in std_logic := 'X'; -- read
+ csr_address : in std_logic_vector(0 downto 0) := (others => 'X'); -- address
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ csr_readdata : out std_logic_vector(31 downto 0); -- readdata
+ data_src_sop : out std_logic; -- startofpacket
+ data_src_eop : out std_logic; -- endofpacket
+ data_src_valid : out std_logic; -- valid
+ data_src_ready : in std_logic := 'X'; -- ready
+ data_src_data : out std_logic_vector(63 downto 0); -- data
+ data_src_empty : out std_logic_vector(2 downto 0); -- empty
+ data_src_error : out std_logic_vector(1 downto 0); -- error
+ data_sink_sop : in std_logic := 'X'; -- startofpacket
+ data_sink_eop : in std_logic := 'X'; -- endofpacket
+ data_sink_valid : in std_logic := 'X'; -- valid
+ data_sink_ready : out std_logic; -- ready
+ data_sink_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ data_sink_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ data_sink_error : in std_logic_vector(1 downto 0) := (others => 'X'); -- error
+ pausebeats_sink_valid : in std_logic := 'X'; -- valid
+ pausebeats_sink_data : in std_logic_vector(31 downto 0) := (others => 'X') -- data
+ );
+ end component ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control;
+
+ component ip_stratixiv_mac_10g_rx_eth_pkt_backpressure_control is
+ generic (
+ BITSPERSYMBOL : integer := 8;
+ SYMBOLSPERBEAT : integer := 8;
+ ERROR_WIDTH : integer := 1;
+ USE_READY : integer := 1
+ );
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ csr_write : in std_logic := 'X'; -- write
+ csr_read : in std_logic := 'X'; -- read
+ csr_address : in std_logic_vector(0 downto 0) := (others => 'X'); -- address
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ csr_readdata : out std_logic_vector(31 downto 0); -- readdata
+ data_src_sop : out std_logic; -- startofpacket
+ data_src_eop : out std_logic; -- endofpacket
+ data_src_valid : out std_logic; -- valid
+ data_src_data : out std_logic_vector(63 downto 0); -- data
+ data_src_empty : out std_logic_vector(2 downto 0); -- empty
+ data_src_error : out std_logic_vector(0 downto 0); -- error
+ data_sink_sop : in std_logic := 'X'; -- startofpacket
+ data_sink_eop : in std_logic := 'X'; -- endofpacket
+ data_sink_valid : in std_logic := 'X'; -- valid
+ data_sink_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ data_sink_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ data_sink_error : in std_logic_vector(0 downto 0) := (others => 'X'); -- error
+ data_src_ready : in std_logic := 'X'; -- ready
+ data_sink_ready : out std_logic; -- ready
+ pausebeats_sink_valid : in std_logic := 'X'; -- valid
+ pausebeats_sink_data : in std_logic_vector(31 downto 0) := (others => 'X') -- data
+ );
+ end component ip_stratixiv_mac_10g_rx_eth_pkt_backpressure_control;
+
+ component ip_stratixiv_mac_10g_tx_eth_frame_decoder is
+ generic (
+ BITSPERSYMBOL : integer := 8;
+ SYMBOLSPERBEAT : integer := 8;
+ ERROR_WIDTH : integer := 2;
+ ENABLE_SUPP_ADDR : integer := 1;
+ ENABLE_PFC : integer := 0;
+ PFC_PRIORITY_NUM : integer := 8
+ );
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ csr_readdata : out std_logic_vector(31 downto 0); -- readdata
+ csr_write : in std_logic := 'X'; -- write
+ csr_read : in std_logic := 'X'; -- read
+ csr_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ data_sink_sop : in std_logic := 'X'; -- startofpacket
+ data_sink_eop : in std_logic := 'X'; -- endofpacket
+ data_sink_valid : in std_logic := 'X'; -- valid
+ data_sink_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ data_sink_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ data_sink_error : in std_logic_vector(2 downto 0) := (others => 'X'); -- error
+ rxstatus_src_valid : out std_logic; -- valid
+ rxstatus_src_data : out std_logic_vector(39 downto 0); -- data
+ rxstatus_src_error : out std_logic_vector(5 downto 0); -- error
+ data_sink_ready : out std_logic; -- ready
+ data_src_sop : out std_logic; -- startofpacket
+ data_src_eop : out std_logic; -- endofpacket
+ data_src_valid : out std_logic; -- valid
+ data_src_ready : in std_logic := 'X'; -- ready
+ data_src_data : out std_logic_vector(63 downto 0); -- data
+ data_src_empty : out std_logic_vector(2 downto 0); -- empty
+ data_src_error : out std_logic_vector(5 downto 0); -- error
+ pauselen_src_valid : out std_logic; -- valid
+ pauselen_src_data : out std_logic_vector(15 downto 0); -- data
+ pfc_pause_quanta_src_valid : out std_logic; -- valid
+ pfc_pause_quanta_src_data : out std_logic_vector(135 downto 0); -- data
+ pfc_status_src_valid : out std_logic; -- valid
+ pfc_status_src_data : out std_logic_vector(15 downto 0); -- data
+ pktinfo_src_valid : out std_logic; -- valid
+ pktinfo_src_data : out std_logic_vector(22 downto 0) -- data
+ );
+ end component ip_stratixiv_mac_10g_tx_eth_frame_decoder;
+
+ component ip_stratixiv_mac_10g_rx_eth_frame_decoder is
+ generic (
+ BITSPERSYMBOL : integer := 8;
+ SYMBOLSPERBEAT : integer := 8;
+ ERROR_WIDTH : integer := 2;
+ ENABLE_SUPP_ADDR : integer := 1;
+ ENABLE_PFC : integer := 0;
+ PFC_PRIORITY_NUM : integer := 8
+ );
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ csr_readdata : out std_logic_vector(31 downto 0); -- readdata
+ csr_write : in std_logic := 'X'; -- write
+ csr_read : in std_logic := 'X'; -- read
+ csr_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ data_sink_sop : in std_logic := 'X'; -- startofpacket
+ data_sink_eop : in std_logic := 'X'; -- endofpacket
+ data_sink_valid : in std_logic := 'X'; -- valid
+ data_sink_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ data_sink_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ data_sink_error : in std_logic_vector(0 downto 0) := (others => 'X'); -- error
+ data_src_sop : out std_logic; -- startofpacket
+ data_src_eop : out std_logic; -- endofpacket
+ data_src_valid : out std_logic; -- valid
+ data_src_data : out std_logic_vector(63 downto 0); -- data
+ data_src_empty : out std_logic_vector(2 downto 0); -- empty
+ data_src_error : out std_logic_vector(3 downto 0); -- error
+ pauselen_src_valid : out std_logic; -- valid
+ pauselen_src_data : out std_logic_vector(15 downto 0); -- data
+ rxstatus_src_valid : out std_logic; -- valid
+ rxstatus_src_data : out std_logic_vector(39 downto 0); -- data
+ rxstatus_src_error : out std_logic_vector(3 downto 0); -- error
+ pktinfo_src_valid : out std_logic; -- valid
+ pktinfo_src_data : out std_logic_vector(22 downto 0); -- data
+ data_sink_ready : out std_logic; -- ready
+ data_src_ready : in std_logic := 'X'; -- ready
+ pfc_pause_quanta_src_valid : out std_logic; -- valid
+ pfc_pause_quanta_src_data : out std_logic_vector(135 downto 0); -- data
+ pfc_status_src_valid : out std_logic; -- valid
+ pfc_status_src_data : out std_logic_vector(15 downto 0) -- data
+ );
+ end component ip_stratixiv_mac_10g_rx_eth_frame_decoder;
+
+ component ip_stratixiv_mac_10g_tx_eth_crc_inserter is
+ generic (
+ BITSPERSYMBOL : integer := 8;
+ SYMBOLSPERBEAT : integer := 8;
+ ERROR_WIDTH : integer := 2;
+ MODE_CHECKER_0_INSERTER_1 : integer := 1
+ );
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ csr_write : in std_logic := 'X'; -- write
+ csr_read : in std_logic := 'X'; -- read
+ csr_address : in std_logic := 'X'; -- address
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ csr_readdata : out std_logic_vector(31 downto 0); -- readdata
+ data_sink_sop : in std_logic := 'X'; -- startofpacket
+ data_sink_eop : in std_logic := 'X'; -- endofpacket
+ data_sink_valid : in std_logic := 'X'; -- valid
+ data_sink_ready : out std_logic; -- ready
+ data_sink_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ data_sink_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ data_sink_error : in std_logic_vector(1 downto 0) := (others => 'X'); -- error
+ data_src_sop : out std_logic; -- startofpacket
+ data_src_eop : out std_logic; -- endofpacket
+ data_src_valid : out std_logic; -- valid
+ data_src_ready : in std_logic := 'X'; -- ready
+ data_src_data : out std_logic_vector(63 downto 0); -- data
+ data_src_empty : out std_logic_vector(2 downto 0); -- empty
+ data_src_error : out std_logic_vector(2 downto 0) -- error
+ );
+ end component ip_stratixiv_mac_10g_tx_eth_crc_inserter;
+
+ component ip_stratixiv_mac_10g_rx_eth_crc_checker is
+ generic (
+ BITSPERSYMBOL : integer := 8;
+ SYMBOLSPERBEAT : integer := 8;
+ ERROR_WIDTH : integer := 2;
+ MODE_CHECKER_0_INSERTER_1 : integer := 1
+ );
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ csr_write : in std_logic := 'X'; -- write
+ csr_read : in std_logic := 'X'; -- read
+ csr_address : in std_logic := 'X'; -- address
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ csr_readdata : out std_logic_vector(31 downto 0); -- readdata
+ data_sink_sop : in std_logic := 'X'; -- startofpacket
+ data_sink_eop : in std_logic := 'X'; -- endofpacket
+ data_sink_valid : in std_logic := 'X'; -- valid
+ data_sink_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ data_sink_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ data_sink_error : in std_logic_vector(0 downto 0) := (others => 'X'); -- error
+ data_src_sop : out std_logic; -- startofpacket
+ data_src_eop : out std_logic; -- endofpacket
+ data_src_valid : out std_logic; -- valid
+ data_src_data : out std_logic_vector(63 downto 0); -- data
+ data_src_empty : out std_logic_vector(2 downto 0); -- empty
+ data_src_error : out std_logic_vector(1 downto 0); -- error
+ data_sink_ready : out std_logic; -- ready
+ data_src_ready : in std_logic := 'X' -- ready
+ );
+ end component ip_stratixiv_mac_10g_rx_eth_crc_checker;
+
+ signal tx_eth_packet_underflow_control_avalon_streaming_source_endofpacket : std_logic; -- tx_eth_packet_underflow_control:data_src_eop -> tx_eth_pad_inserter:data_sink_eop
+ signal tx_eth_packet_underflow_control_avalon_streaming_source_valid : std_logic; -- tx_eth_packet_underflow_control:data_src_valid -> tx_eth_pad_inserter:data_sink_valid
+ signal tx_eth_packet_underflow_control_avalon_streaming_source_startofpacket : std_logic; -- tx_eth_packet_underflow_control:data_src_sop -> tx_eth_pad_inserter:data_sink_sop
+ signal tx_eth_packet_underflow_control_avalon_streaming_source_error : std_logic_vector(1 downto 0); -- tx_eth_packet_underflow_control:data_src_error -> tx_eth_pad_inserter:data_sink_error
+ signal tx_eth_packet_underflow_control_avalon_streaming_source_empty : std_logic_vector(2 downto 0); -- tx_eth_packet_underflow_control:data_src_empty -> tx_eth_pad_inserter:data_sink_empty
+ signal tx_eth_packet_underflow_control_avalon_streaming_source_data : std_logic_vector(63 downto 0); -- tx_eth_packet_underflow_control:data_src_data -> tx_eth_pad_inserter:data_sink_data
+ signal tx_eth_packet_underflow_control_avalon_streaming_source_ready : std_logic; -- tx_eth_pad_inserter:data_sink_ready -> tx_eth_packet_underflow_control:data_src_ready
+ signal tx_eth_pause_beat_conversion_pause_beat_src_valid : std_logic; -- tx_eth_pause_beat_conversion:pause_beat_src_valid -> tx_eth_pkt_backpressure_control:pausebeats_sink_valid
+ signal tx_eth_pause_beat_conversion_pause_beat_src_data : std_logic_vector(31 downto 0); -- tx_eth_pause_beat_conversion:pause_beat_src_data -> tx_eth_pkt_backpressure_control:pausebeats_sink_data
+ signal tx_eth_pad_inserter_avalon_st_source_data_endofpacket : std_logic; -- tx_eth_pad_inserter:data_src_eop -> tx_eth_pkt_backpressure_control:data_sink_eop
+ signal tx_eth_pad_inserter_avalon_st_source_data_valid : std_logic; -- tx_eth_pad_inserter:data_src_valid -> tx_eth_pkt_backpressure_control:data_sink_valid
+ signal tx_eth_pad_inserter_avalon_st_source_data_startofpacket : std_logic; -- tx_eth_pad_inserter:data_src_sop -> tx_eth_pkt_backpressure_control:data_sink_sop
+ signal tx_eth_pad_inserter_avalon_st_source_data_error : std_logic_vector(1 downto 0); -- tx_eth_pad_inserter:data_src_error -> tx_eth_pkt_backpressure_control:data_sink_error
+ signal tx_eth_pad_inserter_avalon_st_source_data_empty : std_logic_vector(2 downto 0); -- tx_eth_pad_inserter:data_src_empty -> tx_eth_pkt_backpressure_control:data_sink_empty
+ signal tx_eth_pad_inserter_avalon_st_source_data_data : std_logic_vector(63 downto 0); -- tx_eth_pad_inserter:data_src_data -> tx_eth_pkt_backpressure_control:data_sink_data
+ signal tx_eth_pad_inserter_avalon_st_source_data_ready : std_logic; -- tx_eth_pkt_backpressure_control:data_sink_ready -> tx_eth_pad_inserter:data_src_ready
+ signal tx_eth_pause_ctrl_gen_pause_packet_endofpacket : std_logic; -- tx_eth_pause_ctrl_gen:pause_source_eop -> tx_st_pause_ctrl_error_adapter:in_endofpacket
+ signal tx_eth_pause_ctrl_gen_pause_packet_valid : std_logic; -- tx_eth_pause_ctrl_gen:pause_source_valid -> tx_st_pause_ctrl_error_adapter:in_valid
+ signal tx_eth_pause_ctrl_gen_pause_packet_startofpacket : std_logic; -- tx_eth_pause_ctrl_gen:pause_source_sop -> tx_st_pause_ctrl_error_adapter:in_startofpacket
+ signal tx_eth_pause_ctrl_gen_pause_packet_error : std_logic_vector(0 downto 0); -- tx_eth_pause_ctrl_gen:pause_source_error -> tx_st_pause_ctrl_error_adapter:in_error
+ signal tx_eth_pause_ctrl_gen_pause_packet_empty : std_logic_vector(2 downto 0); -- tx_eth_pause_ctrl_gen:pause_source_empty -> tx_st_pause_ctrl_error_adapter:in_empty
+ signal tx_eth_pause_ctrl_gen_pause_packet_data : std_logic_vector(63 downto 0); -- tx_eth_pause_ctrl_gen:pause_source_data -> tx_st_pause_ctrl_error_adapter:in_data
+ signal tx_eth_pause_ctrl_gen_pause_packet_ready : std_logic; -- tx_st_pause_ctrl_error_adapter:in_ready -> tx_eth_pause_ctrl_gen:pause_source_ready
+ signal tx_eth_pkt_backpressure_control_avalon_st_source_data_endofpacket : std_logic; -- tx_eth_pkt_backpressure_control:data_src_eop -> tx_st_mux_flow_control_user_frame:in0_endofpacket
+ signal tx_eth_pkt_backpressure_control_avalon_st_source_data_valid : std_logic; -- tx_eth_pkt_backpressure_control:data_src_valid -> tx_st_mux_flow_control_user_frame:in0_valid
+ signal tx_eth_pkt_backpressure_control_avalon_st_source_data_startofpacket : std_logic; -- tx_eth_pkt_backpressure_control:data_src_sop -> tx_st_mux_flow_control_user_frame:in0_startofpacket
+ signal tx_eth_pkt_backpressure_control_avalon_st_source_data_error : std_logic_vector(1 downto 0); -- tx_eth_pkt_backpressure_control:data_src_error -> tx_st_mux_flow_control_user_frame:in0_error
+ signal tx_eth_pkt_backpressure_control_avalon_st_source_data_empty : std_logic_vector(2 downto 0); -- tx_eth_pkt_backpressure_control:data_src_empty -> tx_st_mux_flow_control_user_frame:in0_empty
+ signal tx_eth_pkt_backpressure_control_avalon_st_source_data_data : std_logic_vector(63 downto 0); -- tx_eth_pkt_backpressure_control:data_src_data -> tx_st_mux_flow_control_user_frame:in0_data
+ signal tx_eth_pkt_backpressure_control_avalon_st_source_data_ready : std_logic; -- tx_st_mux_flow_control_user_frame:in0_ready -> tx_eth_pkt_backpressure_control:data_src_ready
+ signal tx_st_pause_ctrl_error_adapter_out_endofpacket : std_logic; -- tx_st_pause_ctrl_error_adapter:out_endofpacket -> tx_st_mux_flow_control_user_frame:in1_endofpacket
+ signal tx_st_pause_ctrl_error_adapter_out_valid : std_logic; -- tx_st_pause_ctrl_error_adapter:out_valid -> tx_st_mux_flow_control_user_frame:in1_valid
+ signal tx_st_pause_ctrl_error_adapter_out_startofpacket : std_logic; -- tx_st_pause_ctrl_error_adapter:out_startofpacket -> tx_st_mux_flow_control_user_frame:in1_startofpacket
+ signal tx_st_pause_ctrl_error_adapter_out_error : std_logic_vector(1 downto 0); -- tx_st_pause_ctrl_error_adapter:out_error -> tx_st_mux_flow_control_user_frame:in1_error
+ signal tx_st_pause_ctrl_error_adapter_out_empty : std_logic_vector(2 downto 0); -- tx_st_pause_ctrl_error_adapter:out_empty -> tx_st_mux_flow_control_user_frame:in1_empty
+ signal tx_st_pause_ctrl_error_adapter_out_data : std_logic_vector(63 downto 0); -- tx_st_pause_ctrl_error_adapter:out_data -> tx_st_mux_flow_control_user_frame:in1_data
+ signal tx_st_pause_ctrl_error_adapter_out_ready : std_logic; -- tx_st_mux_flow_control_user_frame:in1_ready -> tx_st_pause_ctrl_error_adapter:out_ready
+ signal tx_st_mux_flow_control_user_frame_out_endofpacket : std_logic; -- tx_st_mux_flow_control_user_frame:out_endofpacket -> tx_eth_address_inserter:data_sink_eop
+ signal tx_st_mux_flow_control_user_frame_out_valid : std_logic; -- tx_st_mux_flow_control_user_frame:out_valid -> tx_eth_address_inserter:data_sink_valid
+ signal tx_st_mux_flow_control_user_frame_out_startofpacket : std_logic; -- tx_st_mux_flow_control_user_frame:out_startofpacket -> tx_eth_address_inserter:data_sink_sop
+ signal tx_st_mux_flow_control_user_frame_out_error : std_logic_vector(1 downto 0); -- tx_st_mux_flow_control_user_frame:out_error -> tx_eth_address_inserter:data_sink_error
+ signal tx_st_mux_flow_control_user_frame_out_empty : std_logic_vector(2 downto 0); -- tx_st_mux_flow_control_user_frame:out_empty -> tx_eth_address_inserter:data_sink_empty
+ signal tx_st_mux_flow_control_user_frame_out_data : std_logic_vector(63 downto 0); -- tx_st_mux_flow_control_user_frame:out_data -> tx_eth_address_inserter:data_sink_data
+ signal tx_st_mux_flow_control_user_frame_out_ready : std_logic; -- tx_eth_address_inserter:data_sink_ready -> tx_st_mux_flow_control_user_frame:out_ready
+ signal tx_eth_address_inserter_avalon_streaming_source_endofpacket : std_logic; -- tx_eth_address_inserter:data_src_eop -> tx_eth_crc_inserter:data_sink_eop
+ signal tx_eth_address_inserter_avalon_streaming_source_valid : std_logic; -- tx_eth_address_inserter:data_src_valid -> tx_eth_crc_inserter:data_sink_valid
+ signal tx_eth_address_inserter_avalon_streaming_source_startofpacket : std_logic; -- tx_eth_address_inserter:data_src_sop -> tx_eth_crc_inserter:data_sink_sop
+ signal tx_eth_address_inserter_avalon_streaming_source_error : std_logic_vector(1 downto 0); -- tx_eth_address_inserter:data_src_error -> tx_eth_crc_inserter:data_sink_error
+ signal tx_eth_address_inserter_avalon_streaming_source_empty : std_logic_vector(2 downto 0); -- tx_eth_address_inserter:data_src_empty -> tx_eth_crc_inserter:data_sink_empty
+ signal tx_eth_address_inserter_avalon_streaming_source_data : std_logic_vector(63 downto 0); -- tx_eth_address_inserter:data_src_data -> tx_eth_crc_inserter:data_sink_data
+ signal tx_eth_address_inserter_avalon_streaming_source_ready : std_logic; -- tx_eth_crc_inserter:data_sink_ready -> tx_eth_address_inserter:data_src_ready
+ signal tx_eth_crc_inserter_avalon_streaming_source_endofpacket : std_logic; -- tx_eth_crc_inserter:data_src_eop -> tx_st_pipeline_stage_rs:in_endofpacket
+ signal tx_eth_crc_inserter_avalon_streaming_source_valid : std_logic; -- tx_eth_crc_inserter:data_src_valid -> tx_st_pipeline_stage_rs:in_valid
+ signal tx_eth_crc_inserter_avalon_streaming_source_startofpacket : std_logic; -- tx_eth_crc_inserter:data_src_sop -> tx_st_pipeline_stage_rs:in_startofpacket
+ signal tx_eth_crc_inserter_avalon_streaming_source_error : std_logic_vector(2 downto 0); -- tx_eth_crc_inserter:data_src_error -> tx_st_pipeline_stage_rs:in_error
+ signal tx_eth_crc_inserter_avalon_streaming_source_empty : std_logic_vector(2 downto 0); -- tx_eth_crc_inserter:data_src_empty -> tx_st_pipeline_stage_rs:in_empty
+ signal tx_eth_crc_inserter_avalon_streaming_source_data : std_logic_vector(63 downto 0); -- tx_eth_crc_inserter:data_src_data -> tx_st_pipeline_stage_rs:in_data
+ signal tx_eth_crc_inserter_avalon_streaming_source_ready : std_logic; -- tx_st_pipeline_stage_rs:in_ready -> tx_eth_crc_inserter:data_src_ready
+ signal tx_st_pipeline_stage_rs_source0_endofpacket : std_logic; -- tx_st_pipeline_stage_rs:out_endofpacket -> tx_st_splitter_1:in0_endofpacket
+ signal tx_st_pipeline_stage_rs_source0_valid : std_logic; -- tx_st_pipeline_stage_rs:out_valid -> tx_st_splitter_1:in0_valid
+ signal tx_st_pipeline_stage_rs_source0_startofpacket : std_logic; -- tx_st_pipeline_stage_rs:out_startofpacket -> tx_st_splitter_1:in0_startofpacket
+ signal tx_st_pipeline_stage_rs_source0_error : std_logic_vector(2 downto 0); -- tx_st_pipeline_stage_rs:out_error -> tx_st_splitter_1:in0_error
+ signal tx_st_pipeline_stage_rs_source0_data : std_logic_vector(63 downto 0); -- tx_st_pipeline_stage_rs:out_data -> tx_st_splitter_1:in0_data
+ signal tx_st_pipeline_stage_rs_source0_empty : std_logic_vector(2 downto 0); -- tx_st_pipeline_stage_rs:out_empty -> tx_st_splitter_1:in0_empty
+ signal tx_st_pipeline_stage_rs_source0_ready : std_logic; -- tx_st_splitter_1:in0_ready -> tx_st_pipeline_stage_rs:out_ready
+ signal tx_st_splitter_1_out0_endofpacket : std_logic; -- tx_st_splitter_1:out0_endofpacket -> tx_st_timing_adapter_frame_decoder:in_endofpacket
+ signal tx_st_splitter_1_out0_valid : std_logic; -- tx_st_splitter_1:out0_valid -> tx_st_timing_adapter_frame_decoder:in_valid
+ signal tx_st_splitter_1_out0_startofpacket : std_logic; -- tx_st_splitter_1:out0_startofpacket -> tx_st_timing_adapter_frame_decoder:in_startofpacket
+ signal tx_st_splitter_1_out0_error : std_logic_vector(2 downto 0); -- tx_st_splitter_1:out0_error -> tx_st_timing_adapter_frame_decoder:in_error
+ signal tx_st_splitter_1_out0_data : std_logic_vector(63 downto 0); -- tx_st_splitter_1:out0_data -> tx_st_timing_adapter_frame_decoder:in_data
+ signal tx_st_splitter_1_out0_empty : std_logic_vector(2 downto 0); -- tx_st_splitter_1:out0_empty -> tx_st_timing_adapter_frame_decoder:in_empty
+ signal tx_st_splitter_1_out0_ready : std_logic; -- tx_st_timing_adapter_frame_decoder:in_ready -> tx_st_splitter_1:out0_ready
+ signal tx_st_splitter_1_out1_endofpacket : std_logic; -- tx_st_splitter_1:out1_endofpacket -> tx_eth_packet_formatter:data_sink_eop
+ signal tx_st_splitter_1_out1_valid : std_logic; -- tx_st_splitter_1:out1_valid -> tx_eth_packet_formatter:data_sink_valid
+ signal tx_st_splitter_1_out1_startofpacket : std_logic; -- tx_st_splitter_1:out1_startofpacket -> tx_eth_packet_formatter:data_sink_sop
+ signal tx_st_splitter_1_out1_error : std_logic_vector(2 downto 0); -- tx_st_splitter_1:out1_error -> tx_eth_packet_formatter:data_sink_error
+ signal tx_st_splitter_1_out1_data : std_logic_vector(63 downto 0); -- tx_st_splitter_1:out1_data -> tx_eth_packet_formatter:data_sink_data
+ signal tx_st_splitter_1_out1_empty : std_logic_vector(2 downto 0); -- tx_st_splitter_1:out1_empty -> tx_eth_packet_formatter:data_sink_empty
+ signal tx_st_splitter_1_out1_ready : std_logic; -- tx_eth_packet_formatter:data_sink_ready -> tx_st_splitter_1:out1_ready
+ signal tx_st_timing_adapter_frame_decoder_out_endofpacket : std_logic; -- tx_st_timing_adapter_frame_decoder:out_endofpacket -> tx_eth_frame_decoder:data_sink_eop
+ signal tx_st_timing_adapter_frame_decoder_out_valid : std_logic; -- tx_st_timing_adapter_frame_decoder:out_valid -> tx_eth_frame_decoder:data_sink_valid
+ signal tx_st_timing_adapter_frame_decoder_out_startofpacket : std_logic; -- tx_st_timing_adapter_frame_decoder:out_startofpacket -> tx_eth_frame_decoder:data_sink_sop
+ signal tx_st_timing_adapter_frame_decoder_out_error : std_logic_vector(2 downto 0); -- tx_st_timing_adapter_frame_decoder:out_error -> tx_eth_frame_decoder:data_sink_error
+ signal tx_st_timing_adapter_frame_decoder_out_empty : std_logic_vector(2 downto 0); -- tx_st_timing_adapter_frame_decoder:out_empty -> tx_eth_frame_decoder:data_sink_empty
+ signal tx_st_timing_adapter_frame_decoder_out_data : std_logic_vector(63 downto 0); -- tx_st_timing_adapter_frame_decoder:out_data -> tx_eth_frame_decoder:data_sink_data
+ signal tx_eth_frame_decoder_avalon_st_rxstatus_src_valid : std_logic; -- tx_eth_frame_decoder:rxstatus_src_valid -> tx_st_error_adapter_stat:in_valid
+ signal tx_eth_frame_decoder_avalon_st_rxstatus_src_error : std_logic_vector(5 downto 0); -- tx_eth_frame_decoder:rxstatus_src_error -> tx_st_error_adapter_stat:in_error
+ signal tx_eth_frame_decoder_avalon_st_rxstatus_src_data : std_logic_vector(39 downto 0); -- tx_eth_frame_decoder:rxstatus_src_data -> tx_st_error_adapter_stat:in_data
+ signal tx_st_error_adapter_stat_out_valid : std_logic; -- tx_st_error_adapter_stat:out_valid -> tx_st_timing_adapter_splitter_status_in:in_valid
+ signal tx_st_error_adapter_stat_out_error : std_logic_vector(6 downto 0); -- tx_st_error_adapter_stat:out_error -> tx_st_timing_adapter_splitter_status_in:in_error
+ signal tx_st_error_adapter_stat_out_data : std_logic_vector(39 downto 0); -- tx_st_error_adapter_stat:out_data -> tx_st_timing_adapter_splitter_status_in:in_data
+ signal tx_st_timing_adapter_splitter_status_in_out_valid : std_logic; -- tx_st_timing_adapter_splitter_status_in:out_valid -> tx_st_status_splitter:in0_valid
+ signal tx_st_timing_adapter_splitter_status_in_out_error : std_logic_vector(6 downto 0); -- tx_st_timing_adapter_splitter_status_in:out_error -> tx_st_status_splitter:in0_error
+ signal tx_st_timing_adapter_splitter_status_in_out_data : std_logic_vector(39 downto 0); -- tx_st_timing_adapter_splitter_status_in:out_data -> tx_st_status_splitter:in0_data
+ signal tx_st_timing_adapter_splitter_status_in_out_ready : std_logic; -- tx_st_status_splitter:in0_ready -> tx_st_timing_adapter_splitter_status_in:out_ready
+ signal tx_st_status_splitter_out0_valid : std_logic; -- tx_st_status_splitter:out0_valid -> tx_st_timing_adapter_splitter_status_statistics:in_valid
+ signal tx_st_status_splitter_out0_error : std_logic_vector(6 downto 0); -- tx_st_status_splitter:out0_error -> tx_st_timing_adapter_splitter_status_statistics:in_error
+ signal tx_st_status_splitter_out0_data : std_logic_vector(39 downto 0); -- tx_st_status_splitter:out0_data -> tx_st_timing_adapter_splitter_status_statistics:in_data
+ signal tx_st_status_splitter_out0_ready : std_logic; -- tx_st_timing_adapter_splitter_status_statistics:in_ready -> tx_st_status_splitter:out0_ready
+ signal tx_st_timing_adapter_splitter_status_statistics_out_valid : std_logic; -- tx_st_timing_adapter_splitter_status_statistics:out_valid -> tx_eth_statistics_collector:stat_sink_valid
+ signal tx_st_timing_adapter_splitter_status_statistics_out_error : std_logic_vector(6 downto 0); -- tx_st_timing_adapter_splitter_status_statistics:out_error -> tx_eth_statistics_collector:stat_sink_error
+ signal tx_st_timing_adapter_splitter_status_statistics_out_data : std_logic_vector(39 downto 0); -- tx_st_timing_adapter_splitter_status_statistics:out_data -> tx_eth_statistics_collector:stat_sink_data
+ signal tx_st_status_splitter_out1_valid : std_logic; -- tx_st_status_splitter:out1_valid -> tx_st_timing_adapter_splitter_status_output:in_valid
+ signal tx_st_status_splitter_out1_error : std_logic_vector(6 downto 0); -- tx_st_status_splitter:out1_error -> tx_st_timing_adapter_splitter_status_output:in_error
+ signal tx_st_status_splitter_out1_data : std_logic_vector(39 downto 0); -- tx_st_status_splitter:out1_data -> tx_st_timing_adapter_splitter_status_output:in_data
+ signal tx_st_status_splitter_out1_ready : std_logic; -- tx_st_timing_adapter_splitter_status_output:in_ready -> tx_st_status_splitter:out1_ready
+ signal tx_eth_packet_formatter_data_src_endofpacket : std_logic; -- tx_eth_packet_formatter:data_src_eop -> tx_eth_xgmii_termination:data_sink_eop
+ signal tx_eth_packet_formatter_data_src_valid : std_logic; -- tx_eth_packet_formatter:data_src_valid -> tx_eth_xgmii_termination:data_sink_valid
+ signal tx_eth_packet_formatter_data_src_startofpacket : std_logic; -- tx_eth_packet_formatter:data_src_sop -> tx_eth_xgmii_termination:data_sink_sop
+ signal tx_eth_packet_formatter_data_src_empty : std_logic_vector(2 downto 0); -- tx_eth_packet_formatter:data_src_empty -> tx_eth_xgmii_termination:data_sink_empty
+ signal tx_eth_packet_formatter_data_src_data : std_logic_vector(71 downto 0); -- tx_eth_packet_formatter:data_src_data -> tx_eth_xgmii_termination:data_sink_data
+ signal tx_eth_packet_formatter_data_src_ready : std_logic; -- tx_eth_xgmii_termination:data_sink_ready -> tx_eth_packet_formatter:data_src_ready
+ signal tx_eth_xgmii_termination_avalon_streaming_source_data : std_logic_vector(71 downto 0); -- tx_eth_xgmii_termination:xgmii_src_data -> tx_eth_link_fault_generation:mii_sink_data
+ signal rx_st_timing_adapter_interface_conversion_out_valid : std_logic; -- rx_st_timing_adapter_interface_conversion:out_valid -> rx_st_splitter_xgmii:in0_valid
+ signal rx_st_timing_adapter_interface_conversion_out_data : std_logic_vector(71 downto 0); -- rx_st_timing_adapter_interface_conversion:out_data -> rx_st_splitter_xgmii:in0_data
+ signal rx_st_timing_adapter_interface_conversion_out_ready : std_logic; -- rx_st_splitter_xgmii:in0_ready -> rx_st_timing_adapter_interface_conversion:out_ready
+ signal rx_st_splitter_xgmii_out0_valid : std_logic; -- rx_st_splitter_xgmii:out0_valid -> rx_st_timing_adapter_lane_decoder:in_valid
+ signal rx_st_splitter_xgmii_out0_data : std_logic_vector(71 downto 0); -- rx_st_splitter_xgmii:out0_data -> rx_st_timing_adapter_lane_decoder:in_data
+ signal rx_st_splitter_xgmii_out0_ready : std_logic; -- rx_st_timing_adapter_lane_decoder:in_ready -> rx_st_splitter_xgmii:out0_ready
+ signal rx_st_timing_adapter_lane_decoder_out_data : std_logic_vector(71 downto 0); -- rx_st_timing_adapter_lane_decoder:out_data -> rx_eth_lane_decoder:xgmii_sink_data
+ signal rx_st_splitter_xgmii_out1_valid : std_logic; -- rx_st_splitter_xgmii:out1_valid -> rx_st_timing_adapter_link_fault_detection:in_valid
+ signal rx_st_splitter_xgmii_out1_data : std_logic_vector(71 downto 0); -- rx_st_splitter_xgmii:out1_data -> rx_st_timing_adapter_link_fault_detection:in_data
+ signal rx_st_splitter_xgmii_out1_ready : std_logic; -- rx_st_timing_adapter_link_fault_detection:in_ready -> rx_st_splitter_xgmii:out1_ready
+ signal rx_st_timing_adapter_link_fault_detection_out_data : std_logic_vector(71 downto 0); -- rx_st_timing_adapter_link_fault_detection:out_data -> rx_eth_link_fault_detection:mii_sink_data
+ signal rx_eth_pkt_backpressure_control_avalon_st_source_data_endofpacket : std_logic; -- rx_eth_pkt_backpressure_control:data_src_eop -> rx_st_timing_adapter_frame_status_in:in_endofpacket
+ signal rx_eth_pkt_backpressure_control_avalon_st_source_data_valid : std_logic; -- rx_eth_pkt_backpressure_control:data_src_valid -> rx_st_timing_adapter_frame_status_in:in_valid
+ signal rx_eth_pkt_backpressure_control_avalon_st_source_data_startofpacket : std_logic; -- rx_eth_pkt_backpressure_control:data_src_sop -> rx_st_timing_adapter_frame_status_in:in_startofpacket
+ signal rx_eth_pkt_backpressure_control_avalon_st_source_data_error : std_logic_vector(0 downto 0); -- rx_eth_pkt_backpressure_control:data_src_error -> rx_st_timing_adapter_frame_status_in:in_error
+ signal rx_eth_pkt_backpressure_control_avalon_st_source_data_empty : std_logic_vector(2 downto 0); -- rx_eth_pkt_backpressure_control:data_src_empty -> rx_st_timing_adapter_frame_status_in:in_empty
+ signal rx_eth_pkt_backpressure_control_avalon_st_source_data_data : std_logic_vector(63 downto 0); -- rx_eth_pkt_backpressure_control:data_src_data -> rx_st_timing_adapter_frame_status_in:in_data
+ signal rx_st_timing_adapter_frame_status_in_out_endofpacket : std_logic; -- rx_st_timing_adapter_frame_status_in:out_endofpacket -> rx_st_frame_status_splitter:in0_endofpacket
+ signal rx_st_timing_adapter_frame_status_in_out_valid : std_logic; -- rx_st_timing_adapter_frame_status_in:out_valid -> rx_st_frame_status_splitter:in0_valid
+ signal rx_st_timing_adapter_frame_status_in_out_startofpacket : std_logic; -- rx_st_timing_adapter_frame_status_in:out_startofpacket -> rx_st_frame_status_splitter:in0_startofpacket
+ signal rx_st_timing_adapter_frame_status_in_out_error : std_logic; -- rx_st_timing_adapter_frame_status_in:out_error -> rx_st_frame_status_splitter:in0_error
+ signal rx_st_timing_adapter_frame_status_in_out_empty : std_logic_vector(2 downto 0); -- rx_st_timing_adapter_frame_status_in:out_empty -> rx_st_frame_status_splitter:in0_empty
+ signal rx_st_timing_adapter_frame_status_in_out_data : std_logic_vector(63 downto 0); -- rx_st_timing_adapter_frame_status_in:out_data -> rx_st_frame_status_splitter:in0_data
+ signal rx_st_timing_adapter_frame_status_in_out_ready : std_logic; -- rx_st_frame_status_splitter:in0_ready -> rx_st_timing_adapter_frame_status_in:out_ready
+ signal rx_st_frame_status_splitter_out0_endofpacket : std_logic; -- rx_st_frame_status_splitter:out0_endofpacket -> rx_timing_adapter_frame_status_out_frame_decoder:in_endofpacket
+ signal rx_st_frame_status_splitter_out0_valid : std_logic; -- rx_st_frame_status_splitter:out0_valid -> rx_timing_adapter_frame_status_out_frame_decoder:in_valid
+ signal rx_st_frame_status_splitter_out0_startofpacket : std_logic; -- rx_st_frame_status_splitter:out0_startofpacket -> rx_timing_adapter_frame_status_out_frame_decoder:in_startofpacket
+ signal rx_st_frame_status_splitter_out0_error : std_logic; -- rx_st_frame_status_splitter:out0_error -> rx_timing_adapter_frame_status_out_frame_decoder:in_error
+ signal rx_st_frame_status_splitter_out0_data : std_logic_vector(63 downto 0); -- rx_st_frame_status_splitter:out0_data -> rx_timing_adapter_frame_status_out_frame_decoder:in_data
+ signal rx_st_frame_status_splitter_out0_empty : std_logic_vector(2 downto 0); -- rx_st_frame_status_splitter:out0_empty -> rx_timing_adapter_frame_status_out_frame_decoder:in_empty
+ signal rx_st_frame_status_splitter_out0_ready : std_logic; -- rx_timing_adapter_frame_status_out_frame_decoder:in_ready -> rx_st_frame_status_splitter:out0_ready
+ signal rx_timing_adapter_frame_status_out_frame_decoder_out_endofpacket : std_logic; -- rx_timing_adapter_frame_status_out_frame_decoder:out_endofpacket -> rx_eth_frame_decoder:data_sink_eop
+ signal rx_timing_adapter_frame_status_out_frame_decoder_out_valid : std_logic; -- rx_timing_adapter_frame_status_out_frame_decoder:out_valid -> rx_eth_frame_decoder:data_sink_valid
+ signal rx_timing_adapter_frame_status_out_frame_decoder_out_startofpacket : std_logic; -- rx_timing_adapter_frame_status_out_frame_decoder:out_startofpacket -> rx_eth_frame_decoder:data_sink_sop
+ signal rx_timing_adapter_frame_status_out_frame_decoder_out_error : std_logic; -- rx_timing_adapter_frame_status_out_frame_decoder:out_error -> rx_eth_frame_decoder:data_sink_error
+ signal rx_timing_adapter_frame_status_out_frame_decoder_out_empty : std_logic_vector(2 downto 0); -- rx_timing_adapter_frame_status_out_frame_decoder:out_empty -> rx_eth_frame_decoder:data_sink_empty
+ signal rx_timing_adapter_frame_status_out_frame_decoder_out_data : std_logic_vector(63 downto 0); -- rx_timing_adapter_frame_status_out_frame_decoder:out_data -> rx_eth_frame_decoder:data_sink_data
+ signal rx_eth_frame_decoder_avalon_st_data_src_endofpacket : std_logic; -- rx_eth_frame_decoder:data_src_eop -> rx_eth_frame_status_merger:frame_decoder_data_sink_eop
+ signal rx_eth_frame_decoder_avalon_st_data_src_valid : std_logic; -- rx_eth_frame_decoder:data_src_valid -> rx_eth_frame_status_merger:frame_decoder_data_sink_valid
+ signal rx_eth_frame_decoder_avalon_st_data_src_startofpacket : std_logic; -- rx_eth_frame_decoder:data_src_sop -> rx_eth_frame_status_merger:frame_decoder_data_sink_sop
+ signal rx_eth_frame_decoder_avalon_st_data_src_error : std_logic_vector(3 downto 0); -- rx_eth_frame_decoder:data_src_error -> rx_eth_frame_status_merger:frame_decoder_data_sink_error
+ signal rx_eth_frame_decoder_avalon_st_data_src_empty : std_logic_vector(2 downto 0); -- rx_eth_frame_decoder:data_src_empty -> rx_eth_frame_status_merger:frame_decoder_data_sink_empty
+ signal rx_eth_frame_decoder_avalon_st_data_src_data : std_logic_vector(63 downto 0); -- rx_eth_frame_decoder:data_src_data -> rx_eth_frame_status_merger:frame_decoder_data_sink_data
+ signal rx_eth_frame_decoder_avalon_st_pauselen_src_valid : std_logic; -- rx_eth_frame_decoder:pauselen_src_valid -> rx_eth_frame_status_merger:pauselen_sink_valid
+ signal rx_eth_frame_decoder_avalon_st_pauselen_src_data : std_logic_vector(15 downto 0); -- rx_eth_frame_decoder:pauselen_src_data -> rx_eth_frame_status_merger:pauselen_sink_data
+ signal rx_st_frame_status_splitter_out1_endofpacket : std_logic; -- rx_st_frame_status_splitter:out1_endofpacket -> rx_timing_adapter_frame_status_out_crc_checker:in_endofpacket
+ signal rx_st_frame_status_splitter_out1_valid : std_logic; -- rx_st_frame_status_splitter:out1_valid -> rx_timing_adapter_frame_status_out_crc_checker:in_valid
+ signal rx_st_frame_status_splitter_out1_startofpacket : std_logic; -- rx_st_frame_status_splitter:out1_startofpacket -> rx_timing_adapter_frame_status_out_crc_checker:in_startofpacket
+ signal rx_st_frame_status_splitter_out1_error : std_logic; -- rx_st_frame_status_splitter:out1_error -> rx_timing_adapter_frame_status_out_crc_checker:in_error
+ signal rx_st_frame_status_splitter_out1_data : std_logic_vector(63 downto 0); -- rx_st_frame_status_splitter:out1_data -> rx_timing_adapter_frame_status_out_crc_checker:in_data
+ signal rx_st_frame_status_splitter_out1_empty : std_logic_vector(2 downto 0); -- rx_st_frame_status_splitter:out1_empty -> rx_timing_adapter_frame_status_out_crc_checker:in_empty
+ signal rx_st_frame_status_splitter_out1_ready : std_logic; -- rx_timing_adapter_frame_status_out_crc_checker:in_ready -> rx_st_frame_status_splitter:out1_ready
+ signal rx_timing_adapter_frame_status_out_crc_checker_out_endofpacket : std_logic; -- rx_timing_adapter_frame_status_out_crc_checker:out_endofpacket -> rx_eth_crc_checker:data_sink_eop
+ signal rx_timing_adapter_frame_status_out_crc_checker_out_valid : std_logic; -- rx_timing_adapter_frame_status_out_crc_checker:out_valid -> rx_eth_crc_checker:data_sink_valid
+ signal rx_timing_adapter_frame_status_out_crc_checker_out_startofpacket : std_logic; -- rx_timing_adapter_frame_status_out_crc_checker:out_startofpacket -> rx_eth_crc_checker:data_sink_sop
+ signal rx_timing_adapter_frame_status_out_crc_checker_out_error : std_logic; -- rx_timing_adapter_frame_status_out_crc_checker:out_error -> rx_eth_crc_checker:data_sink_error
+ signal rx_timing_adapter_frame_status_out_crc_checker_out_empty : std_logic_vector(2 downto 0); -- rx_timing_adapter_frame_status_out_crc_checker:out_empty -> rx_eth_crc_checker:data_sink_empty
+ signal rx_timing_adapter_frame_status_out_crc_checker_out_data : std_logic_vector(63 downto 0); -- rx_timing_adapter_frame_status_out_crc_checker:out_data -> rx_eth_crc_checker:data_sink_data
+ signal rx_eth_frame_status_merger_data_src_endofpacket : std_logic; -- rx_eth_frame_status_merger:data_src_eop -> rx_eth_crc_pad_rem:data_sink_eop
+ signal rx_eth_frame_status_merger_data_src_valid : std_logic; -- rx_eth_frame_status_merger:data_src_valid -> rx_eth_crc_pad_rem:data_sink_valid
+ signal rx_eth_frame_status_merger_data_src_startofpacket : std_logic; -- rx_eth_frame_status_merger:data_src_sop -> rx_eth_crc_pad_rem:data_sink_sop
+ signal rx_eth_frame_status_merger_data_src_error : std_logic_vector(4 downto 0); -- rx_eth_frame_status_merger:data_src_error -> rx_eth_crc_pad_rem:data_sink_error
+ signal rx_eth_frame_status_merger_data_src_empty : std_logic_vector(2 downto 0); -- rx_eth_frame_status_merger:data_src_empty -> rx_eth_crc_pad_rem:data_sink_empty
+ signal rx_eth_frame_status_merger_data_src_data : std_logic_vector(63 downto 0); -- rx_eth_frame_status_merger:data_src_data -> rx_eth_crc_pad_rem:data_sink_data
+ signal rx_eth_frame_decoder_avalon_st_pktinfo_src_valid : std_logic; -- rx_eth_frame_decoder:pktinfo_src_valid -> rx_eth_crc_pad_rem:status_sink_valid
+ signal rx_eth_frame_decoder_avalon_st_pktinfo_src_data : std_logic_vector(22 downto 0); -- rx_eth_frame_decoder:pktinfo_src_data -> rx_eth_crc_pad_rem:status_sink_data
+ signal rx_eth_crc_pad_rem_avalon_streaming_source_data_endofpacket : std_logic; -- rx_eth_crc_pad_rem:data_source_eop -> rx_eth_packet_overflow_control:data_sink_eop
+ signal rx_eth_crc_pad_rem_avalon_streaming_source_data_valid : std_logic; -- rx_eth_crc_pad_rem:data_source_valid -> rx_eth_packet_overflow_control:data_sink_valid
+ signal rx_eth_crc_pad_rem_avalon_streaming_source_data_startofpacket : std_logic; -- rx_eth_crc_pad_rem:data_source_sop -> rx_eth_packet_overflow_control:data_sink_sop
+ signal rx_eth_crc_pad_rem_avalon_streaming_source_data_error : std_logic_vector(4 downto 0); -- rx_eth_crc_pad_rem:data_source_error -> rx_eth_packet_overflow_control:data_sink_error
+ signal rx_eth_crc_pad_rem_avalon_streaming_source_data_empty : std_logic_vector(2 downto 0); -- rx_eth_crc_pad_rem:data_source_empty -> rx_eth_packet_overflow_control:data_sink_empty
+ signal rx_eth_crc_pad_rem_avalon_streaming_source_data_data : std_logic_vector(63 downto 0); -- rx_eth_crc_pad_rem:data_source_data -> rx_eth_packet_overflow_control:data_sink_data
+ signal rx_eth_crc_checker_avalon_streaming_source_endofpacket : std_logic; -- rx_eth_crc_checker:data_src_eop -> rx_eth_frame_status_merger:crc_checker_data_sink_eop
+ signal rx_eth_crc_checker_avalon_streaming_source_valid : std_logic; -- rx_eth_crc_checker:data_src_valid -> rx_eth_frame_status_merger:crc_checker_data_sink_valid
+ signal rx_eth_crc_checker_avalon_streaming_source_startofpacket : std_logic; -- rx_eth_crc_checker:data_src_sop -> rx_eth_frame_status_merger:crc_checker_data_sink_sop
+ signal rx_eth_crc_checker_avalon_streaming_source_error : std_logic_vector(1 downto 0); -- rx_eth_crc_checker:data_src_error -> rx_eth_frame_status_merger:crc_checker_data_sink_error
+ signal rx_eth_crc_checker_avalon_streaming_source_empty : std_logic_vector(2 downto 0); -- rx_eth_crc_checker:data_src_empty -> rx_eth_frame_status_merger:crc_checker_data_sink_empty
+ signal rx_eth_crc_checker_avalon_streaming_source_data : std_logic_vector(63 downto 0); -- rx_eth_crc_checker:data_src_data -> rx_eth_frame_status_merger:crc_checker_data_sink_data
+ signal rx_eth_frame_decoder_avalon_st_rxstatus_src_valid : std_logic; -- rx_eth_frame_decoder:rxstatus_src_valid -> rx_eth_frame_status_merger:rxstatus_sink_valid
+ signal rx_eth_frame_decoder_avalon_st_rxstatus_src_error : std_logic_vector(3 downto 0); -- rx_eth_frame_decoder:rxstatus_src_error -> rx_eth_frame_status_merger:rxstatus_sink_error
+ signal rx_eth_frame_decoder_avalon_st_rxstatus_src_data : std_logic_vector(39 downto 0); -- rx_eth_frame_decoder:rxstatus_src_data -> rx_eth_frame_status_merger:rxstatus_sink_data
+ signal rx_eth_frame_status_merger_rxstatus_src_valid : std_logic; -- rx_eth_frame_status_merger:rxstatus_src_valid -> rx_st_error_adapter_stat:in_valid
+ signal rx_eth_frame_status_merger_rxstatus_src_error : std_logic_vector(4 downto 0); -- rx_eth_frame_status_merger:rxstatus_src_error -> rx_st_error_adapter_stat:in_error
+ signal rx_eth_frame_status_merger_rxstatus_src_data : std_logic_vector(39 downto 0); -- rx_eth_frame_status_merger:rxstatus_src_data -> rx_st_error_adapter_stat:in_data
+ signal rx_st_error_adapter_stat_out_valid : std_logic; -- rx_st_error_adapter_stat:out_valid -> rx_st_timing_adapter_splitter_status_in:in_valid
+ signal rx_st_error_adapter_stat_out_error : std_logic_vector(6 downto 0); -- rx_st_error_adapter_stat:out_error -> rx_st_timing_adapter_splitter_status_in:in_error
+ signal rx_st_error_adapter_stat_out_data : std_logic_vector(39 downto 0); -- rx_st_error_adapter_stat:out_data -> rx_st_timing_adapter_splitter_status_in:in_data
+ signal rx_st_timing_adapter_splitter_status_in_out_valid : std_logic; -- rx_st_timing_adapter_splitter_status_in:out_valid -> rx_st_status_splitter:in0_valid
+ signal rx_st_timing_adapter_splitter_status_in_out_error : std_logic_vector(6 downto 0); -- rx_st_timing_adapter_splitter_status_in:out_error -> rx_st_status_splitter:in0_error
+ signal rx_st_timing_adapter_splitter_status_in_out_data : std_logic_vector(39 downto 0); -- rx_st_timing_adapter_splitter_status_in:out_data -> rx_st_status_splitter:in0_data
+ signal rx_st_timing_adapter_splitter_status_in_out_ready : std_logic; -- rx_st_status_splitter:in0_ready -> rx_st_timing_adapter_splitter_status_in:out_ready
+ signal rx_st_status_splitter_out0_valid : std_logic; -- rx_st_status_splitter:out0_valid -> rx_st_timing_adapter_splitter_status_statistics:in_valid
+ signal rx_st_status_splitter_out0_error : std_logic_vector(6 downto 0); -- rx_st_status_splitter:out0_error -> rx_st_timing_adapter_splitter_status_statistics:in_error
+ signal rx_st_status_splitter_out0_data : std_logic_vector(39 downto 0); -- rx_st_status_splitter:out0_data -> rx_st_timing_adapter_splitter_status_statistics:in_data
+ signal rx_st_status_splitter_out0_ready : std_logic; -- rx_st_timing_adapter_splitter_status_statistics:in_ready -> rx_st_status_splitter:out0_ready
+ signal rx_st_timing_adapter_splitter_status_statistics_out_valid : std_logic; -- rx_st_timing_adapter_splitter_status_statistics:out_valid -> rx_st_status_statistics_delay:in0_valid
+ signal rx_st_timing_adapter_splitter_status_statistics_out_error : std_logic_vector(6 downto 0); -- rx_st_timing_adapter_splitter_status_statistics:out_error -> rx_st_status_statistics_delay:in0_error
+ signal rx_st_timing_adapter_splitter_status_statistics_out_data : std_logic_vector(39 downto 0); -- rx_st_timing_adapter_splitter_status_statistics:out_data -> rx_st_status_statistics_delay:in0_data
+ signal rx_st_status_statistics_delay_out_valid : std_logic; -- rx_st_status_statistics_delay:out0_valid -> rx_eth_statistics_collector:stat_sink_valid
+ signal rx_st_status_statistics_delay_out_error : std_logic_vector(6 downto 0); -- rx_st_status_statistics_delay:out0_error -> rx_eth_statistics_collector:stat_sink_error
+ signal rx_st_status_statistics_delay_out_data : std_logic_vector(39 downto 0); -- rx_st_status_statistics_delay:out0_data -> rx_eth_statistics_collector:stat_sink_data
+ signal rx_st_status_splitter_out1_valid : std_logic; -- rx_st_status_splitter:out1_valid -> rx_st_timing_adapter_splitter_status_output:in_valid
+ signal rx_st_status_splitter_out1_error : std_logic_vector(6 downto 0); -- rx_st_status_splitter:out1_error -> rx_st_timing_adapter_splitter_status_output:in_error
+ signal rx_st_status_splitter_out1_data : std_logic_vector(39 downto 0); -- rx_st_status_splitter:out1_data -> rx_st_timing_adapter_splitter_status_output:in_data
+ signal rx_st_status_splitter_out1_ready : std_logic; -- rx_st_timing_adapter_splitter_status_output:in_ready -> rx_st_status_splitter:out1_ready
+ signal rx_st_timing_adapter_splitter_status_output_out_valid : std_logic; -- rx_st_timing_adapter_splitter_status_output:out_valid -> rx_st_status_output_delay:in0_valid
+ signal rx_st_timing_adapter_splitter_status_output_out_error : std_logic_vector(6 downto 0); -- rx_st_timing_adapter_splitter_status_output:out_error -> rx_st_status_output_delay:in0_error
+ signal rx_st_timing_adapter_splitter_status_output_out_data : std_logic_vector(39 downto 0); -- rx_st_timing_adapter_splitter_status_output:out_data -> rx_st_status_output_delay:in0_data
+ signal rx_eth_lane_decoder_avalon_streaming_source_endofpacket : std_logic; -- rx_eth_lane_decoder:rxdata_src_eop -> rx_eth_pkt_backpressure_control:data_sink_eop
+ signal rx_eth_lane_decoder_avalon_streaming_source_valid : std_logic; -- rx_eth_lane_decoder:rxdata_src_valid -> rx_eth_pkt_backpressure_control:data_sink_valid
+ signal rx_eth_lane_decoder_avalon_streaming_source_startofpacket : std_logic; -- rx_eth_lane_decoder:rxdata_src_sop -> rx_eth_pkt_backpressure_control:data_sink_sop
+ signal rx_eth_lane_decoder_avalon_streaming_source_error : std_logic_vector(0 downto 0); -- rx_eth_lane_decoder:rxdata_src_error -> rx_eth_pkt_backpressure_control:data_sink_error
+ signal rx_eth_lane_decoder_avalon_streaming_source_empty : std_logic_vector(2 downto 0); -- rx_eth_lane_decoder:rxdata_src_empty -> rx_eth_pkt_backpressure_control:data_sink_empty
+ signal rx_eth_lane_decoder_avalon_streaming_source_data : std_logic_vector(63 downto 0); -- rx_eth_lane_decoder:rxdata_src_data -> rx_eth_pkt_backpressure_control:data_sink_data
+ signal rx_eth_link_fault_detection_link_fault_src_data : std_logic_vector(1 downto 0); -- rx_eth_link_fault_detection:link_fault_src_data -> txrx_timing_adapter_link_fault_status_rx:in_data
+ signal txrx_timing_adapter_link_fault_status_rx_out_valid : std_logic; -- txrx_timing_adapter_link_fault_status_rx:out_valid -> txrx_st_splitter_link_fault_status:in0_valid
+ signal txrx_timing_adapter_link_fault_status_rx_out_data : std_logic_vector(1 downto 0); -- txrx_timing_adapter_link_fault_status_rx:out_data -> txrx_st_splitter_link_fault_status:in0_data
+ signal txrx_timing_adapter_link_fault_status_rx_out_ready : std_logic; -- txrx_st_splitter_link_fault_status:in0_ready -> txrx_timing_adapter_link_fault_status_rx:out_ready
+ signal txrx_st_splitter_link_fault_status_out0_valid : std_logic; -- txrx_st_splitter_link_fault_status:out0_valid -> txrx_timing_adapter_link_fault_status_export:in_valid
+ signal txrx_st_splitter_link_fault_status_out0_data : std_logic_vector(1 downto 0); -- txrx_st_splitter_link_fault_status:out0_data -> txrx_timing_adapter_link_fault_status_export:in_data
+ signal txrx_st_splitter_link_fault_status_out0_ready : std_logic; -- txrx_timing_adapter_link_fault_status_export:in_ready -> txrx_st_splitter_link_fault_status:out0_ready
+ signal txrx_st_splitter_link_fault_status_out1_valid : std_logic; -- txrx_st_splitter_link_fault_status:out1_valid -> rxtx_dc_fifo_link_fault_status:in_valid
+ signal txrx_st_splitter_link_fault_status_out1_data : std_logic_vector(1 downto 0); -- txrx_st_splitter_link_fault_status:out1_data -> rxtx_dc_fifo_link_fault_status:in_data
+ signal txrx_st_splitter_link_fault_status_out1_ready : std_logic; -- rxtx_dc_fifo_link_fault_status:in_ready -> txrx_st_splitter_link_fault_status:out1_ready
+ signal rxtx_dc_fifo_link_fault_status_out_valid : std_logic; -- rxtx_dc_fifo_link_fault_status:out_valid -> rxtx_timing_adapter_link_fault_status_tx:in_valid
+ signal rxtx_dc_fifo_link_fault_status_out_data : std_logic_vector(1 downto 0); -- rxtx_dc_fifo_link_fault_status:out_data -> rxtx_timing_adapter_link_fault_status_tx:in_data
+ signal rxtx_dc_fifo_link_fault_status_out_ready : std_logic; -- rxtx_timing_adapter_link_fault_status_tx:in_ready -> rxtx_dc_fifo_link_fault_status:out_ready
+ signal rxtx_timing_adapter_link_fault_status_tx_out_data : std_logic_vector(1 downto 0); -- rxtx_timing_adapter_link_fault_status_tx:out_data -> tx_eth_link_fault_generation:link_fault_sink_data
+ signal rx_eth_frame_status_merger_pauselen_src_valid : std_logic; -- rx_eth_frame_status_merger:pauselen_src_valid -> rxtx_timing_adapter_pauselen_rx:in_valid
+ signal rx_eth_frame_status_merger_pauselen_src_data : std_logic_vector(15 downto 0); -- rx_eth_frame_status_merger:pauselen_src_data -> rxtx_timing_adapter_pauselen_rx:in_data
+ signal rxtx_timing_adapter_pauselen_rx_out_valid : std_logic; -- rxtx_timing_adapter_pauselen_rx:out_valid -> rxtx_dc_fifo_pauselen:in_valid
+ signal rxtx_timing_adapter_pauselen_rx_out_data : std_logic_vector(15 downto 0); -- rxtx_timing_adapter_pauselen_rx:out_data -> rxtx_dc_fifo_pauselen:in_data
+ signal rxtx_timing_adapter_pauselen_rx_out_ready : std_logic; -- rxtx_dc_fifo_pauselen:in_ready -> rxtx_timing_adapter_pauselen_rx:out_ready
+ signal rxtx_dc_fifo_pauselen_out_valid : std_logic; -- rxtx_dc_fifo_pauselen:out_valid -> rxtx_timing_adapter_pauselen_tx:in_valid
+ signal rxtx_dc_fifo_pauselen_out_data : std_logic_vector(15 downto 0); -- rxtx_dc_fifo_pauselen:out_data -> rxtx_timing_adapter_pauselen_tx:in_data
+ signal rxtx_dc_fifo_pauselen_out_ready : std_logic; -- rxtx_timing_adapter_pauselen_tx:in_ready -> rxtx_dc_fifo_pauselen:out_ready
+ signal rxtx_timing_adapter_pauselen_tx_out_valid : std_logic; -- rxtx_timing_adapter_pauselen_tx:out_valid -> tx_eth_pause_beat_conversion:pause_quanta_sink_valid
+ signal rxtx_timing_adapter_pauselen_tx_out_data : std_logic_vector(15 downto 0); -- rxtx_timing_adapter_pauselen_tx:out_data -> tx_eth_pause_beat_conversion:pause_quanta_sink_data
+ signal merlin_master_translator_avalon_universal_master_0_waitrequest : std_logic; -- merlin_master_translator_avalon_universal_master_0_translator:av_waitrequest -> merlin_master_translator:uav_waitrequest
+ signal merlin_master_translator_avalon_universal_master_0_burstcount : std_logic_vector(2 downto 0); -- merlin_master_translator:uav_burstcount -> merlin_master_translator_avalon_universal_master_0_translator:av_burstcount
+ signal merlin_master_translator_avalon_universal_master_0_writedata : std_logic_vector(31 downto 0); -- merlin_master_translator:uav_writedata -> merlin_master_translator_avalon_universal_master_0_translator:av_writedata
+ signal merlin_master_translator_avalon_universal_master_0_address : std_logic_vector(14 downto 0); -- merlin_master_translator:uav_address -> merlin_master_translator_avalon_universal_master_0_translator:av_address
+ signal merlin_master_translator_avalon_universal_master_0_lock : std_logic; -- merlin_master_translator:uav_lock -> merlin_master_translator_avalon_universal_master_0_translator:av_lock
+ signal merlin_master_translator_avalon_universal_master_0_write : std_logic; -- merlin_master_translator:uav_write -> merlin_master_translator_avalon_universal_master_0_translator:av_write
+ signal merlin_master_translator_avalon_universal_master_0_read : std_logic; -- merlin_master_translator:uav_read -> merlin_master_translator_avalon_universal_master_0_translator:av_read
+ signal merlin_master_translator_avalon_universal_master_0_readdata : std_logic_vector(31 downto 0); -- merlin_master_translator_avalon_universal_master_0_translator:av_readdata -> merlin_master_translator:uav_readdata
+ signal merlin_master_translator_avalon_universal_master_0_debugaccess : std_logic; -- merlin_master_translator:uav_debugaccess -> merlin_master_translator_avalon_universal_master_0_translator:av_debugaccess
+ signal merlin_master_translator_avalon_universal_master_0_byteenable : std_logic_vector(3 downto 0); -- merlin_master_translator:uav_byteenable -> merlin_master_translator_avalon_universal_master_0_translator:av_byteenable
+ signal merlin_master_translator_avalon_universal_master_0_readdatavalid : std_logic; -- merlin_master_translator_avalon_universal_master_0_translator:av_readdatavalid -> merlin_master_translator:uav_readdatavalid
+ signal tx_bridge_s0_translator_avalon_anti_slave_0_waitrequest : std_logic; -- tx_bridge:s0_waitrequest -> tx_bridge_s0_translator:av_waitrequest
+ signal tx_bridge_s0_translator_avalon_anti_slave_0_burstcount : std_logic; -- tx_bridge_s0_translator:av_burstcount -> tx_bridge:s0_burstcount
+ signal tx_bridge_s0_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- tx_bridge_s0_translator:av_writedata -> tx_bridge:s0_writedata
+ signal tx_bridge_s0_translator_avalon_anti_slave_0_address : std_logic_vector(13 downto 0); -- tx_bridge_s0_translator:av_address -> tx_bridge:s0_address
+ signal tx_bridge_s0_translator_avalon_anti_slave_0_write : std_logic; -- tx_bridge_s0_translator:av_write -> tx_bridge:s0_write
+ signal tx_bridge_s0_translator_avalon_anti_slave_0_read : std_logic; -- tx_bridge_s0_translator:av_read -> tx_bridge:s0_read
+ signal tx_bridge_s0_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- tx_bridge:s0_readdata -> tx_bridge_s0_translator:av_readdata
+ signal tx_bridge_s0_translator_avalon_anti_slave_0_debugaccess : std_logic; -- tx_bridge_s0_translator:av_debugaccess -> tx_bridge:s0_debugaccess
+ signal tx_bridge_s0_translator_avalon_anti_slave_0_readdatavalid : std_logic; -- tx_bridge:s0_readdatavalid -> tx_bridge_s0_translator:av_readdatavalid
+ signal tx_bridge_s0_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- tx_bridge_s0_translator:av_byteenable -> tx_bridge:s0_byteenable
+ signal rx_bridge_s0_translator_avalon_anti_slave_0_waitrequest : std_logic; -- rx_bridge:s0_waitrequest -> rx_bridge_s0_translator:av_waitrequest
+ signal rx_bridge_s0_translator_avalon_anti_slave_0_burstcount : std_logic; -- rx_bridge_s0_translator:av_burstcount -> rx_bridge:s0_burstcount
+ signal rx_bridge_s0_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- rx_bridge_s0_translator:av_writedata -> rx_bridge:s0_writedata
+ signal rx_bridge_s0_translator_avalon_anti_slave_0_address : std_logic_vector(13 downto 0); -- rx_bridge_s0_translator:av_address -> rx_bridge:s0_address
+ signal rx_bridge_s0_translator_avalon_anti_slave_0_write : std_logic; -- rx_bridge_s0_translator:av_write -> rx_bridge:s0_write
+ signal rx_bridge_s0_translator_avalon_anti_slave_0_read : std_logic; -- rx_bridge_s0_translator:av_read -> rx_bridge:s0_read
+ signal rx_bridge_s0_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- rx_bridge:s0_readdata -> rx_bridge_s0_translator:av_readdata
+ signal rx_bridge_s0_translator_avalon_anti_slave_0_debugaccess : std_logic; -- rx_bridge_s0_translator:av_debugaccess -> rx_bridge:s0_debugaccess
+ signal rx_bridge_s0_translator_avalon_anti_slave_0_readdatavalid : std_logic; -- rx_bridge:s0_readdatavalid -> rx_bridge_s0_translator:av_readdatavalid
+ signal rx_bridge_s0_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- rx_bridge_s0_translator:av_byteenable -> rx_bridge:s0_byteenable
+ signal tx_bridge_m0_burstcount : std_logic_vector(0 downto 0); -- tx_bridge:m0_burstcount -> tx_bridge_m0_translator:av_burstcount
+ signal tx_bridge_m0_waitrequest : std_logic; -- tx_bridge_m0_translator:av_waitrequest -> tx_bridge:m0_waitrequest
+ signal tx_bridge_m0_address : std_logic_vector(13 downto 0); -- tx_bridge:m0_address -> tx_bridge_m0_translator:av_address
+ signal tx_bridge_m0_writedata : std_logic_vector(31 downto 0); -- tx_bridge:m0_writedata -> tx_bridge_m0_translator:av_writedata
+ signal tx_bridge_m0_write : std_logic; -- tx_bridge:m0_write -> tx_bridge_m0_translator:av_write
+ signal tx_bridge_m0_read : std_logic; -- tx_bridge:m0_read -> tx_bridge_m0_translator:av_read
+ signal tx_bridge_m0_readdata : std_logic_vector(31 downto 0); -- tx_bridge_m0_translator:av_readdata -> tx_bridge:m0_readdata
+ signal tx_bridge_m0_debugaccess : std_logic; -- tx_bridge:m0_debugaccess -> tx_bridge_m0_translator:av_debugaccess
+ signal tx_bridge_m0_byteenable : std_logic_vector(3 downto 0); -- tx_bridge:m0_byteenable -> tx_bridge_m0_translator:av_byteenable
+ signal tx_bridge_m0_readdatavalid : std_logic; -- tx_bridge_m0_translator:av_readdatavalid -> tx_bridge:m0_readdatavalid
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- tx_eth_pkt_backpressure_control_csr_translator:av_writedata -> tx_eth_pkt_backpressure_control:csr_writedata
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_address : std_logic; -- tx_eth_pkt_backpressure_control_csr_translator:av_address -> tx_eth_pkt_backpressure_control:csr_address
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_write : std_logic; -- tx_eth_pkt_backpressure_control_csr_translator:av_write -> tx_eth_pkt_backpressure_control:csr_write
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_read : std_logic; -- tx_eth_pkt_backpressure_control_csr_translator:av_read -> tx_eth_pkt_backpressure_control:csr_read
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- tx_eth_pkt_backpressure_control:csr_readdata -> tx_eth_pkt_backpressure_control_csr_translator:av_readdata
+ signal tx_eth_pad_inserter_csr_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- tx_eth_pad_inserter_csr_translator:av_writedata -> tx_eth_pad_inserter:csr_writedata
+ signal tx_eth_pad_inserter_csr_translator_avalon_anti_slave_0_address : std_logic; -- tx_eth_pad_inserter_csr_translator:av_address -> tx_eth_pad_inserter:csr_address
+ signal tx_eth_pad_inserter_csr_translator_avalon_anti_slave_0_write : std_logic; -- tx_eth_pad_inserter_csr_translator:av_write -> tx_eth_pad_inserter:csr_write
+ signal tx_eth_pad_inserter_csr_translator_avalon_anti_slave_0_read : std_logic; -- tx_eth_pad_inserter_csr_translator:av_read -> tx_eth_pad_inserter:csr_read
+ signal tx_eth_pad_inserter_csr_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- tx_eth_pad_inserter:csr_readdata -> tx_eth_pad_inserter_csr_translator:av_readdata
+ signal tx_eth_crc_inserter_csr_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- tx_eth_crc_inserter_csr_translator:av_writedata -> tx_eth_crc_inserter:csr_writedata
+ signal tx_eth_crc_inserter_csr_translator_avalon_anti_slave_0_address : std_logic; -- tx_eth_crc_inserter_csr_translator:av_address -> tx_eth_crc_inserter:csr_address
+ signal tx_eth_crc_inserter_csr_translator_avalon_anti_slave_0_write : std_logic; -- tx_eth_crc_inserter_csr_translator:av_write -> tx_eth_crc_inserter:csr_write
+ signal tx_eth_crc_inserter_csr_translator_avalon_anti_slave_0_read : std_logic; -- tx_eth_crc_inserter_csr_translator:av_read -> tx_eth_crc_inserter:csr_read
+ signal tx_eth_crc_inserter_csr_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- tx_eth_crc_inserter:csr_readdata -> tx_eth_crc_inserter_csr_translator:av_readdata
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- tx_eth_pause_ctrl_gen_csr_translator:av_writedata -> tx_eth_pause_ctrl_gen:csr_writedata
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_anti_slave_0_address : std_logic_vector(1 downto 0); -- tx_eth_pause_ctrl_gen_csr_translator:av_address -> tx_eth_pause_ctrl_gen:csr_address
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_anti_slave_0_write : std_logic; -- tx_eth_pause_ctrl_gen_csr_translator:av_write -> tx_eth_pause_ctrl_gen:csr_write
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_anti_slave_0_read : std_logic; -- tx_eth_pause_ctrl_gen_csr_translator:av_read -> tx_eth_pause_ctrl_gen:csr_read
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- tx_eth_pause_ctrl_gen:csr_readdata -> tx_eth_pause_ctrl_gen_csr_translator:av_readdata
+ signal tx_eth_address_inserter_csr_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- tx_eth_address_inserter_csr_translator:av_writedata -> tx_eth_address_inserter:csr_writedata
+ signal tx_eth_address_inserter_csr_translator_avalon_anti_slave_0_address : std_logic_vector(1 downto 0); -- tx_eth_address_inserter_csr_translator:av_address -> tx_eth_address_inserter:csr_address
+ signal tx_eth_address_inserter_csr_translator_avalon_anti_slave_0_write : std_logic; -- tx_eth_address_inserter_csr_translator:av_write -> tx_eth_address_inserter:csr_write
+ signal tx_eth_address_inserter_csr_translator_avalon_anti_slave_0_read : std_logic; -- tx_eth_address_inserter_csr_translator:av_read -> tx_eth_address_inserter:csr_read
+ signal tx_eth_address_inserter_csr_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- tx_eth_address_inserter:csr_readdata -> tx_eth_address_inserter_csr_translator:av_readdata
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_anti_slave_0_address : std_logic; -- tx_eth_packet_underflow_control_avalon_slave_0_translator:av_address -> tx_eth_packet_underflow_control:csr_address
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_anti_slave_0_read : std_logic; -- tx_eth_packet_underflow_control_avalon_slave_0_translator:av_read -> tx_eth_packet_underflow_control:csr_read
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- tx_eth_packet_underflow_control:csr_readdata -> tx_eth_packet_underflow_control_avalon_slave_0_translator:av_readdata
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- tx_eth_frame_decoder_avalom_mm_csr_translator:av_writedata -> tx_eth_frame_decoder:csr_writedata
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_address : std_logic_vector(4 downto 0); -- tx_eth_frame_decoder_avalom_mm_csr_translator:av_address -> tx_eth_frame_decoder:csr_address
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_write : std_logic; -- tx_eth_frame_decoder_avalom_mm_csr_translator:av_write -> tx_eth_frame_decoder:csr_write
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_read : std_logic; -- tx_eth_frame_decoder_avalom_mm_csr_translator:av_read -> tx_eth_frame_decoder:csr_read
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- tx_eth_frame_decoder:csr_readdata -> tx_eth_frame_decoder_avalom_mm_csr_translator:av_readdata
+ signal tx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- tx_eth_statistics_collector_csr_translator:av_writedata -> tx_eth_statistics_collector:csr_writedata
+ signal tx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_address : std_logic_vector(5 downto 0); -- tx_eth_statistics_collector_csr_translator:av_address -> tx_eth_statistics_collector:csr_address
+ signal tx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_write : std_logic; -- tx_eth_statistics_collector_csr_translator:av_write -> tx_eth_statistics_collector:csr_write
+ signal tx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_read : std_logic; -- tx_eth_statistics_collector_csr_translator:av_read -> tx_eth_statistics_collector:csr_read
+ signal tx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- tx_eth_statistics_collector:csr_readdata -> tx_eth_statistics_collector_csr_translator:av_readdata
+ signal rx_bridge_m0_burstcount : std_logic_vector(0 downto 0); -- rx_bridge:m0_burstcount -> rx_bridge_m0_translator:av_burstcount
+ signal rx_bridge_m0_waitrequest : std_logic; -- rx_bridge_m0_translator:av_waitrequest -> rx_bridge:m0_waitrequest
+ signal rx_bridge_m0_address : std_logic_vector(13 downto 0); -- rx_bridge:m0_address -> rx_bridge_m0_translator:av_address
+ signal rx_bridge_m0_writedata : std_logic_vector(31 downto 0); -- rx_bridge:m0_writedata -> rx_bridge_m0_translator:av_writedata
+ signal rx_bridge_m0_write : std_logic; -- rx_bridge:m0_write -> rx_bridge_m0_translator:av_write
+ signal rx_bridge_m0_read : std_logic; -- rx_bridge:m0_read -> rx_bridge_m0_translator:av_read
+ signal rx_bridge_m0_readdata : std_logic_vector(31 downto 0); -- rx_bridge_m0_translator:av_readdata -> rx_bridge:m0_readdata
+ signal rx_bridge_m0_debugaccess : std_logic; -- rx_bridge:m0_debugaccess -> rx_bridge_m0_translator:av_debugaccess
+ signal rx_bridge_m0_byteenable : std_logic_vector(3 downto 0); -- rx_bridge:m0_byteenable -> rx_bridge_m0_translator:av_byteenable
+ signal rx_bridge_m0_readdatavalid : std_logic; -- rx_bridge_m0_translator:av_readdatavalid -> rx_bridge:m0_readdatavalid
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- rx_eth_pkt_backpressure_control_csr_translator:av_writedata -> rx_eth_pkt_backpressure_control:csr_writedata
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_address : std_logic; -- rx_eth_pkt_backpressure_control_csr_translator:av_address -> rx_eth_pkt_backpressure_control:csr_address
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_write : std_logic; -- rx_eth_pkt_backpressure_control_csr_translator:av_write -> rx_eth_pkt_backpressure_control:csr_write
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_read : std_logic; -- rx_eth_pkt_backpressure_control_csr_translator:av_read -> rx_eth_pkt_backpressure_control:csr_read
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- rx_eth_pkt_backpressure_control:csr_readdata -> rx_eth_pkt_backpressure_control_csr_translator:av_readdata
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- rx_eth_crc_pad_rem_csr_translator:av_writedata -> rx_eth_crc_pad_rem:csr_writedata
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_anti_slave_0_address : std_logic_vector(1 downto 0); -- rx_eth_crc_pad_rem_csr_translator:av_address -> rx_eth_crc_pad_rem:csr_address
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_anti_slave_0_write : std_logic; -- rx_eth_crc_pad_rem_csr_translator:av_write -> rx_eth_crc_pad_rem:csr_write
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_anti_slave_0_read : std_logic; -- rx_eth_crc_pad_rem_csr_translator:av_read -> rx_eth_crc_pad_rem:csr_read
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- rx_eth_crc_pad_rem:csr_readdata -> rx_eth_crc_pad_rem_csr_translator:av_readdata
+ signal rx_eth_crc_checker_csr_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- rx_eth_crc_checker_csr_translator:av_writedata -> rx_eth_crc_checker:csr_writedata
+ signal rx_eth_crc_checker_csr_translator_avalon_anti_slave_0_address : std_logic; -- rx_eth_crc_checker_csr_translator:av_address -> rx_eth_crc_checker:csr_address
+ signal rx_eth_crc_checker_csr_translator_avalon_anti_slave_0_write : std_logic; -- rx_eth_crc_checker_csr_translator:av_write -> rx_eth_crc_checker:csr_write
+ signal rx_eth_crc_checker_csr_translator_avalon_anti_slave_0_read : std_logic; -- rx_eth_crc_checker_csr_translator:av_read -> rx_eth_crc_checker:csr_read
+ signal rx_eth_crc_checker_csr_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- rx_eth_crc_checker:csr_readdata -> rx_eth_crc_checker_csr_translator:av_readdata
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- rx_eth_frame_decoder_avalom_mm_csr_translator:av_writedata -> rx_eth_frame_decoder:csr_writedata
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_address : std_logic_vector(4 downto 0); -- rx_eth_frame_decoder_avalom_mm_csr_translator:av_address -> rx_eth_frame_decoder:csr_address
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_write : std_logic; -- rx_eth_frame_decoder_avalom_mm_csr_translator:av_write -> rx_eth_frame_decoder:csr_write
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_read : std_logic; -- rx_eth_frame_decoder_avalom_mm_csr_translator:av_read -> rx_eth_frame_decoder:csr_read
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- rx_eth_frame_decoder:csr_readdata -> rx_eth_frame_decoder_avalom_mm_csr_translator:av_readdata
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_anti_slave_0_address : std_logic_vector(1 downto 0); -- rx_eth_packet_overflow_control_csr_translator:av_address -> rx_eth_packet_overflow_control:csr_address
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_anti_slave_0_read : std_logic; -- rx_eth_packet_overflow_control_csr_translator:av_read -> rx_eth_packet_overflow_control:csr_read
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- rx_eth_packet_overflow_control:csr_readdata -> rx_eth_packet_overflow_control_csr_translator:av_readdata
+ signal rx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- rx_eth_statistics_collector_csr_translator:av_writedata -> rx_eth_statistics_collector:csr_writedata
+ signal rx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_address : std_logic_vector(5 downto 0); -- rx_eth_statistics_collector_csr_translator:av_address -> rx_eth_statistics_collector:csr_address
+ signal rx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_write : std_logic; -- rx_eth_statistics_collector_csr_translator:av_write -> rx_eth_statistics_collector:csr_write
+ signal rx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_read : std_logic; -- rx_eth_statistics_collector_csr_translator:av_read -> rx_eth_statistics_collector:csr_read
+ signal rx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- rx_eth_statistics_collector:csr_readdata -> rx_eth_statistics_collector_csr_translator:av_readdata
+ signal rx_eth_lane_decoder_csr_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- rx_eth_lane_decoder_csr_translator:av_writedata -> rx_eth_lane_decoder:csr_writedata
+ signal rx_eth_lane_decoder_csr_translator_avalon_anti_slave_0_address : std_logic; -- rx_eth_lane_decoder_csr_translator:av_address -> rx_eth_lane_decoder:csr_address
+ signal rx_eth_lane_decoder_csr_translator_avalon_anti_slave_0_write : std_logic; -- rx_eth_lane_decoder_csr_translator:av_write -> rx_eth_lane_decoder:csr_write
+ signal rx_eth_lane_decoder_csr_translator_avalon_anti_slave_0_read : std_logic; -- rx_eth_lane_decoder_csr_translator:av_read -> rx_eth_lane_decoder:csr_read
+ signal rx_eth_lane_decoder_csr_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- rx_eth_lane_decoder:csr_readdata -> rx_eth_lane_decoder_csr_translator:av_readdata
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- tx_bridge_s0_translator:uav_waitrequest -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- tx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_burstcount -> tx_bridge_s0_translator:uav_burstcount
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- tx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_writedata -> tx_bridge_s0_translator:uav_writedata
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(14 downto 0); -- tx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_address -> tx_bridge_s0_translator:uav_address
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- tx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_write -> tx_bridge_s0_translator:uav_write
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- tx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_lock -> tx_bridge_s0_translator:uav_lock
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- tx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_read -> tx_bridge_s0_translator:uav_read
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- tx_bridge_s0_translator:uav_readdata -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_readdata
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- tx_bridge_s0_translator:uav_readdatavalid -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- tx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> tx_bridge_s0_translator:uav_debugaccess
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- tx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_byteenable -> tx_bridge_s0_translator:uav_byteenable
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- tx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- tx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_source_valid -> tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- tx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(66 downto 0); -- tx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_source_data -> tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_source_ready
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(66 downto 0); -- tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_sink_data
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- tx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- tx_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- tx_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid : std_logic; -- tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data : std_logic_vector(31 downto 0); -- tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready : std_logic; -- tx_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
+ signal merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_waitrequest : std_logic; -- merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:av_waitrequest -> merlin_master_translator_avalon_universal_master_0_translator:uav_waitrequest
+ signal merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_burstcount : std_logic_vector(2 downto 0); -- merlin_master_translator_avalon_universal_master_0_translator:uav_burstcount -> merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:av_burstcount
+ signal merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_writedata : std_logic_vector(31 downto 0); -- merlin_master_translator_avalon_universal_master_0_translator:uav_writedata -> merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:av_writedata
+ signal merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_address : std_logic_vector(14 downto 0); -- merlin_master_translator_avalon_universal_master_0_translator:uav_address -> merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:av_address
+ signal merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_lock : std_logic; -- merlin_master_translator_avalon_universal_master_0_translator:uav_lock -> merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:av_lock
+ signal merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_write : std_logic; -- merlin_master_translator_avalon_universal_master_0_translator:uav_write -> merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:av_write
+ signal merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_read : std_logic; -- merlin_master_translator_avalon_universal_master_0_translator:uav_read -> merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:av_read
+ signal merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_readdata : std_logic_vector(31 downto 0); -- merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:av_readdata -> merlin_master_translator_avalon_universal_master_0_translator:uav_readdata
+ signal merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_debugaccess : std_logic; -- merlin_master_translator_avalon_universal_master_0_translator:uav_debugaccess -> merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:av_debugaccess
+ signal merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_byteenable : std_logic_vector(3 downto 0); -- merlin_master_translator_avalon_universal_master_0_translator:uav_byteenable -> merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:av_byteenable
+ signal merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_readdatavalid : std_logic; -- merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:av_readdatavalid -> merlin_master_translator_avalon_universal_master_0_translator:uav_readdatavalid
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- rx_bridge_s0_translator:uav_waitrequest -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- rx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_burstcount -> rx_bridge_s0_translator:uav_burstcount
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- rx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_writedata -> rx_bridge_s0_translator:uav_writedata
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(14 downto 0); -- rx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_address -> rx_bridge_s0_translator:uav_address
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- rx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_write -> rx_bridge_s0_translator:uav_write
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- rx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_lock -> rx_bridge_s0_translator:uav_lock
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- rx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_read -> rx_bridge_s0_translator:uav_read
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- rx_bridge_s0_translator:uav_readdata -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_readdata
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- rx_bridge_s0_translator:uav_readdatavalid -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- rx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> rx_bridge_s0_translator:uav_debugaccess
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- rx_bridge_s0_translator_avalon_universal_slave_0_agent:m0_byteenable -> rx_bridge_s0_translator:uav_byteenable
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- rx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- rx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_source_valid -> rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- rx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(66 downto 0); -- rx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_source_data -> rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_source_ready
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(66 downto 0); -- rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_sink_data
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- rx_bridge_s0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- rx_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- rx_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid : std_logic; -- rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data : std_logic_vector(31 downto 0); -- rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready : std_logic; -- rx_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
+ signal tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- tx_eth_statistics_collector_csr_translator:uav_waitrequest -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ signal tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_burstcount -> tx_eth_statistics_collector_csr_translator:uav_burstcount
+ signal tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_writedata -> tx_eth_statistics_collector_csr_translator:uav_writedata
+ signal tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(13 downto 0); -- tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_address -> tx_eth_statistics_collector_csr_translator:uav_address
+ signal tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_write -> tx_eth_statistics_collector_csr_translator:uav_write
+ signal tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_lock -> tx_eth_statistics_collector_csr_translator:uav_lock
+ signal tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_read -> tx_eth_statistics_collector_csr_translator:uav_read
+ signal tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- tx_eth_statistics_collector_csr_translator:uav_readdata -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_readdata
+ signal tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- tx_eth_statistics_collector_csr_translator:uav_readdatavalid -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ signal tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_debugaccess -> tx_eth_statistics_collector_csr_translator:uav_debugaccess
+ signal tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_byteenable -> tx_eth_statistics_collector_csr_translator:uav_byteenable
+ signal tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ signal tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_source_valid -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ signal tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ signal tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(69 downto 0); -- tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_source_data -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ signal tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_source_ready
+ signal tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ signal tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ signal tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ signal tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(69 downto 0); -- tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_sink_data
+ signal tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_sink_ready -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ signal tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ signal tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ signal tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ signal tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- tx_eth_pad_inserter_csr_translator:uav_waitrequest -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ signal tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:m0_burstcount -> tx_eth_pad_inserter_csr_translator:uav_burstcount
+ signal tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:m0_writedata -> tx_eth_pad_inserter_csr_translator:uav_writedata
+ signal tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(13 downto 0); -- tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:m0_address -> tx_eth_pad_inserter_csr_translator:uav_address
+ signal tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:m0_write -> tx_eth_pad_inserter_csr_translator:uav_write
+ signal tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:m0_lock -> tx_eth_pad_inserter_csr_translator:uav_lock
+ signal tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:m0_read -> tx_eth_pad_inserter_csr_translator:uav_read
+ signal tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- tx_eth_pad_inserter_csr_translator:uav_readdata -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:m0_readdata
+ signal tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- tx_eth_pad_inserter_csr_translator:uav_readdatavalid -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ signal tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:m0_debugaccess -> tx_eth_pad_inserter_csr_translator:uav_debugaccess
+ signal tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:m0_byteenable -> tx_eth_pad_inserter_csr_translator:uav_byteenable
+ signal tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ signal tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rf_source_valid -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ signal tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ signal tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(69 downto 0); -- tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rf_source_data -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ signal tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rf_source_ready
+ signal tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ signal tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ signal tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ signal tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(69 downto 0); -- tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rf_sink_data
+ signal tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rf_sink_ready -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ signal tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ signal tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ signal tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ signal tx_bridge_m0_translator_avalon_universal_master_0_waitrequest : std_logic; -- tx_bridge_m0_translator_avalon_universal_master_0_agent:av_waitrequest -> tx_bridge_m0_translator:uav_waitrequest
+ signal tx_bridge_m0_translator_avalon_universal_master_0_burstcount : std_logic_vector(2 downto 0); -- tx_bridge_m0_translator:uav_burstcount -> tx_bridge_m0_translator_avalon_universal_master_0_agent:av_burstcount
+ signal tx_bridge_m0_translator_avalon_universal_master_0_writedata : std_logic_vector(31 downto 0); -- tx_bridge_m0_translator:uav_writedata -> tx_bridge_m0_translator_avalon_universal_master_0_agent:av_writedata
+ signal tx_bridge_m0_translator_avalon_universal_master_0_address : std_logic_vector(13 downto 0); -- tx_bridge_m0_translator:uav_address -> tx_bridge_m0_translator_avalon_universal_master_0_agent:av_address
+ signal tx_bridge_m0_translator_avalon_universal_master_0_lock : std_logic; -- tx_bridge_m0_translator:uav_lock -> tx_bridge_m0_translator_avalon_universal_master_0_agent:av_lock
+ signal tx_bridge_m0_translator_avalon_universal_master_0_write : std_logic; -- tx_bridge_m0_translator:uav_write -> tx_bridge_m0_translator_avalon_universal_master_0_agent:av_write
+ signal tx_bridge_m0_translator_avalon_universal_master_0_read : std_logic; -- tx_bridge_m0_translator:uav_read -> tx_bridge_m0_translator_avalon_universal_master_0_agent:av_read
+ signal tx_bridge_m0_translator_avalon_universal_master_0_readdata : std_logic_vector(31 downto 0); -- tx_bridge_m0_translator_avalon_universal_master_0_agent:av_readdata -> tx_bridge_m0_translator:uav_readdata
+ signal tx_bridge_m0_translator_avalon_universal_master_0_debugaccess : std_logic; -- tx_bridge_m0_translator:uav_debugaccess -> tx_bridge_m0_translator_avalon_universal_master_0_agent:av_debugaccess
+ signal tx_bridge_m0_translator_avalon_universal_master_0_byteenable : std_logic_vector(3 downto 0); -- tx_bridge_m0_translator:uav_byteenable -> tx_bridge_m0_translator_avalon_universal_master_0_agent:av_byteenable
+ signal tx_bridge_m0_translator_avalon_universal_master_0_readdatavalid : std_logic; -- tx_bridge_m0_translator_avalon_universal_master_0_agent:av_readdatavalid -> tx_bridge_m0_translator:uav_readdatavalid
+ signal tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- tx_eth_crc_inserter_csr_translator:uav_waitrequest -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ signal tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:m0_burstcount -> tx_eth_crc_inserter_csr_translator:uav_burstcount
+ signal tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:m0_writedata -> tx_eth_crc_inserter_csr_translator:uav_writedata
+ signal tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(13 downto 0); -- tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:m0_address -> tx_eth_crc_inserter_csr_translator:uav_address
+ signal tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:m0_write -> tx_eth_crc_inserter_csr_translator:uav_write
+ signal tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:m0_lock -> tx_eth_crc_inserter_csr_translator:uav_lock
+ signal tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:m0_read -> tx_eth_crc_inserter_csr_translator:uav_read
+ signal tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- tx_eth_crc_inserter_csr_translator:uav_readdata -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:m0_readdata
+ signal tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- tx_eth_crc_inserter_csr_translator:uav_readdatavalid -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ signal tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:m0_debugaccess -> tx_eth_crc_inserter_csr_translator:uav_debugaccess
+ signal tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:m0_byteenable -> tx_eth_crc_inserter_csr_translator:uav_byteenable
+ signal tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ signal tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rf_source_valid -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ signal tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ signal tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(69 downto 0); -- tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rf_source_data -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ signal tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rf_source_ready
+ signal tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ signal tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ signal tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ signal tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(69 downto 0); -- tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rf_sink_data
+ signal tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rf_sink_ready -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ signal tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ signal tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ signal tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ signal tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- tx_eth_address_inserter_csr_translator:uav_waitrequest -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ signal tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:m0_burstcount -> tx_eth_address_inserter_csr_translator:uav_burstcount
+ signal tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:m0_writedata -> tx_eth_address_inserter_csr_translator:uav_writedata
+ signal tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(13 downto 0); -- tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:m0_address -> tx_eth_address_inserter_csr_translator:uav_address
+ signal tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:m0_write -> tx_eth_address_inserter_csr_translator:uav_write
+ signal tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:m0_lock -> tx_eth_address_inserter_csr_translator:uav_lock
+ signal tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:m0_read -> tx_eth_address_inserter_csr_translator:uav_read
+ signal tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- tx_eth_address_inserter_csr_translator:uav_readdata -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:m0_readdata
+ signal tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- tx_eth_address_inserter_csr_translator:uav_readdatavalid -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ signal tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:m0_debugaccess -> tx_eth_address_inserter_csr_translator:uav_debugaccess
+ signal tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:m0_byteenable -> tx_eth_address_inserter_csr_translator:uav_byteenable
+ signal tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ signal tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rf_source_valid -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ signal tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ signal tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(69 downto 0); -- tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rf_source_data -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ signal tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rf_source_ready
+ signal tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ signal tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ signal tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ signal tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(69 downto 0); -- tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rf_sink_data
+ signal tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rf_sink_ready -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ signal tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ signal tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ signal tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- tx_eth_frame_decoder_avalom_mm_csr_translator:uav_waitrequest -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_burstcount -> tx_eth_frame_decoder_avalom_mm_csr_translator:uav_burstcount
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_writedata -> tx_eth_frame_decoder_avalom_mm_csr_translator:uav_writedata
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(13 downto 0); -- tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_address -> tx_eth_frame_decoder_avalom_mm_csr_translator:uav_address
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_write -> tx_eth_frame_decoder_avalom_mm_csr_translator:uav_write
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_lock -> tx_eth_frame_decoder_avalom_mm_csr_translator:uav_lock
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_read -> tx_eth_frame_decoder_avalom_mm_csr_translator:uav_read
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- tx_eth_frame_decoder_avalom_mm_csr_translator:uav_readdata -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_readdata
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- tx_eth_frame_decoder_avalom_mm_csr_translator:uav_readdatavalid -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_debugaccess -> tx_eth_frame_decoder_avalom_mm_csr_translator:uav_debugaccess
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_byteenable -> tx_eth_frame_decoder_avalom_mm_csr_translator:uav_byteenable
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_source_valid -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(69 downto 0); -- tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_source_data -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_source_ready
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(69 downto 0); -- tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_sink_data
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_sink_ready -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- tx_eth_pkt_backpressure_control_csr_translator:uav_waitrequest -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_burstcount -> tx_eth_pkt_backpressure_control_csr_translator:uav_burstcount
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_writedata -> tx_eth_pkt_backpressure_control_csr_translator:uav_writedata
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(13 downto 0); -- tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_address -> tx_eth_pkt_backpressure_control_csr_translator:uav_address
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_write -> tx_eth_pkt_backpressure_control_csr_translator:uav_write
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_lock -> tx_eth_pkt_backpressure_control_csr_translator:uav_lock
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_read -> tx_eth_pkt_backpressure_control_csr_translator:uav_read
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- tx_eth_pkt_backpressure_control_csr_translator:uav_readdata -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_readdata
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- tx_eth_pkt_backpressure_control_csr_translator:uav_readdatavalid -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_debugaccess -> tx_eth_pkt_backpressure_control_csr_translator:uav_debugaccess
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_byteenable -> tx_eth_pkt_backpressure_control_csr_translator:uav_byteenable
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_source_valid -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(69 downto 0); -- tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_source_data -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_source_ready
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(69 downto 0); -- tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_sink_data
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_sink_ready -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- tx_eth_packet_underflow_control_avalon_slave_0_translator:uav_waitrequest -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> tx_eth_packet_underflow_control_avalon_slave_0_translator:uav_burstcount
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> tx_eth_packet_underflow_control_avalon_slave_0_translator:uav_writedata
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(13 downto 0); -- tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> tx_eth_packet_underflow_control_avalon_slave_0_translator:uav_address
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> tx_eth_packet_underflow_control_avalon_slave_0_translator:uav_write
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> tx_eth_packet_underflow_control_avalon_slave_0_translator:uav_lock
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> tx_eth_packet_underflow_control_avalon_slave_0_translator:uav_read
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- tx_eth_packet_underflow_control_avalon_slave_0_translator:uav_readdata -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- tx_eth_packet_underflow_control_avalon_slave_0_translator:uav_readdatavalid -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> tx_eth_packet_underflow_control_avalon_slave_0_translator:uav_debugaccess
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> tx_eth_packet_underflow_control_avalon_slave_0_translator:uav_byteenable
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(69 downto 0); -- tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(69 downto 0); -- tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- tx_eth_pause_ctrl_gen_csr_translator:uav_waitrequest -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:m0_burstcount -> tx_eth_pause_ctrl_gen_csr_translator:uav_burstcount
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:m0_writedata -> tx_eth_pause_ctrl_gen_csr_translator:uav_writedata
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(13 downto 0); -- tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:m0_address -> tx_eth_pause_ctrl_gen_csr_translator:uav_address
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:m0_write -> tx_eth_pause_ctrl_gen_csr_translator:uav_write
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:m0_lock -> tx_eth_pause_ctrl_gen_csr_translator:uav_lock
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:m0_read -> tx_eth_pause_ctrl_gen_csr_translator:uav_read
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- tx_eth_pause_ctrl_gen_csr_translator:uav_readdata -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:m0_readdata
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- tx_eth_pause_ctrl_gen_csr_translator:uav_readdatavalid -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:m0_debugaccess -> tx_eth_pause_ctrl_gen_csr_translator:uav_debugaccess
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:m0_byteenable -> tx_eth_pause_ctrl_gen_csr_translator:uav_byteenable
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rf_source_valid -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(69 downto 0); -- tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rf_source_data -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rf_source_ready
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(69 downto 0); -- tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rf_sink_data
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rf_sink_ready -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- rx_eth_crc_pad_rem_csr_translator:uav_waitrequest -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:m0_burstcount -> rx_eth_crc_pad_rem_csr_translator:uav_burstcount
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:m0_writedata -> rx_eth_crc_pad_rem_csr_translator:uav_writedata
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(13 downto 0); -- rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:m0_address -> rx_eth_crc_pad_rem_csr_translator:uav_address
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:m0_write -> rx_eth_crc_pad_rem_csr_translator:uav_write
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:m0_lock -> rx_eth_crc_pad_rem_csr_translator:uav_lock
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:m0_read -> rx_eth_crc_pad_rem_csr_translator:uav_read
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- rx_eth_crc_pad_rem_csr_translator:uav_readdata -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:m0_readdata
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- rx_eth_crc_pad_rem_csr_translator:uav_readdatavalid -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:m0_debugaccess -> rx_eth_crc_pad_rem_csr_translator:uav_debugaccess
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:m0_byteenable -> rx_eth_crc_pad_rem_csr_translator:uav_byteenable
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rf_source_valid -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(69 downto 0); -- rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rf_source_data -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rf_source_ready
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(69 downto 0); -- rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rf_sink_data
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rf_sink_ready -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- rx_eth_frame_decoder_avalom_mm_csr_translator:uav_waitrequest -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_burstcount -> rx_eth_frame_decoder_avalom_mm_csr_translator:uav_burstcount
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_writedata -> rx_eth_frame_decoder_avalom_mm_csr_translator:uav_writedata
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(13 downto 0); -- rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_address -> rx_eth_frame_decoder_avalom_mm_csr_translator:uav_address
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_write -> rx_eth_frame_decoder_avalom_mm_csr_translator:uav_write
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_lock -> rx_eth_frame_decoder_avalom_mm_csr_translator:uav_lock
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_read -> rx_eth_frame_decoder_avalom_mm_csr_translator:uav_read
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- rx_eth_frame_decoder_avalom_mm_csr_translator:uav_readdata -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_readdata
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- rx_eth_frame_decoder_avalom_mm_csr_translator:uav_readdatavalid -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_debugaccess -> rx_eth_frame_decoder_avalom_mm_csr_translator:uav_debugaccess
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:m0_byteenable -> rx_eth_frame_decoder_avalom_mm_csr_translator:uav_byteenable
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_source_valid -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(69 downto 0); -- rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_source_data -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_source_ready
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(69 downto 0); -- rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_sink_data
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rf_sink_ready -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ signal rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- rx_eth_crc_checker_csr_translator:uav_waitrequest -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ signal rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:m0_burstcount -> rx_eth_crc_checker_csr_translator:uav_burstcount
+ signal rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:m0_writedata -> rx_eth_crc_checker_csr_translator:uav_writedata
+ signal rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(13 downto 0); -- rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:m0_address -> rx_eth_crc_checker_csr_translator:uav_address
+ signal rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:m0_write -> rx_eth_crc_checker_csr_translator:uav_write
+ signal rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:m0_lock -> rx_eth_crc_checker_csr_translator:uav_lock
+ signal rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:m0_read -> rx_eth_crc_checker_csr_translator:uav_read
+ signal rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- rx_eth_crc_checker_csr_translator:uav_readdata -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:m0_readdata
+ signal rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- rx_eth_crc_checker_csr_translator:uav_readdatavalid -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ signal rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:m0_debugaccess -> rx_eth_crc_checker_csr_translator:uav_debugaccess
+ signal rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:m0_byteenable -> rx_eth_crc_checker_csr_translator:uav_byteenable
+ signal rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ signal rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rf_source_valid -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ signal rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ signal rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(69 downto 0); -- rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rf_source_data -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ signal rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rf_source_ready
+ signal rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ signal rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ signal rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ signal rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(69 downto 0); -- rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rf_sink_data
+ signal rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rf_sink_ready -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ signal rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ signal rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ signal rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ signal rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- rx_eth_lane_decoder_csr_translator:uav_waitrequest -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ signal rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:m0_burstcount -> rx_eth_lane_decoder_csr_translator:uav_burstcount
+ signal rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:m0_writedata -> rx_eth_lane_decoder_csr_translator:uav_writedata
+ signal rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(13 downto 0); -- rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:m0_address -> rx_eth_lane_decoder_csr_translator:uav_address
+ signal rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:m0_write -> rx_eth_lane_decoder_csr_translator:uav_write
+ signal rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:m0_lock -> rx_eth_lane_decoder_csr_translator:uav_lock
+ signal rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:m0_read -> rx_eth_lane_decoder_csr_translator:uav_read
+ signal rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- rx_eth_lane_decoder_csr_translator:uav_readdata -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:m0_readdata
+ signal rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- rx_eth_lane_decoder_csr_translator:uav_readdatavalid -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ signal rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:m0_debugaccess -> rx_eth_lane_decoder_csr_translator:uav_debugaccess
+ signal rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:m0_byteenable -> rx_eth_lane_decoder_csr_translator:uav_byteenable
+ signal rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ signal rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rf_source_valid -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ signal rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ signal rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(69 downto 0); -- rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rf_source_data -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ signal rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rf_source_ready
+ signal rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ signal rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ signal rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ signal rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(69 downto 0); -- rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rf_sink_data
+ signal rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rf_sink_ready -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ signal rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ signal rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ signal rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- rx_eth_packet_overflow_control_csr_translator:uav_waitrequest -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:m0_burstcount -> rx_eth_packet_overflow_control_csr_translator:uav_burstcount
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:m0_writedata -> rx_eth_packet_overflow_control_csr_translator:uav_writedata
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(13 downto 0); -- rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:m0_address -> rx_eth_packet_overflow_control_csr_translator:uav_address
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:m0_write -> rx_eth_packet_overflow_control_csr_translator:uav_write
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:m0_lock -> rx_eth_packet_overflow_control_csr_translator:uav_lock
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:m0_read -> rx_eth_packet_overflow_control_csr_translator:uav_read
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- rx_eth_packet_overflow_control_csr_translator:uav_readdata -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:m0_readdata
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- rx_eth_packet_overflow_control_csr_translator:uav_readdatavalid -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:m0_debugaccess -> rx_eth_packet_overflow_control_csr_translator:uav_debugaccess
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:m0_byteenable -> rx_eth_packet_overflow_control_csr_translator:uav_byteenable
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rf_source_valid -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(69 downto 0); -- rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rf_source_data -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rf_source_ready
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(69 downto 0); -- rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rf_sink_data
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rf_sink_ready -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- rx_eth_pkt_backpressure_control_csr_translator:uav_waitrequest -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_burstcount -> rx_eth_pkt_backpressure_control_csr_translator:uav_burstcount
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_writedata -> rx_eth_pkt_backpressure_control_csr_translator:uav_writedata
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(13 downto 0); -- rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_address -> rx_eth_pkt_backpressure_control_csr_translator:uav_address
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_write -> rx_eth_pkt_backpressure_control_csr_translator:uav_write
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_lock -> rx_eth_pkt_backpressure_control_csr_translator:uav_lock
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_read -> rx_eth_pkt_backpressure_control_csr_translator:uav_read
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- rx_eth_pkt_backpressure_control_csr_translator:uav_readdata -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_readdata
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- rx_eth_pkt_backpressure_control_csr_translator:uav_readdatavalid -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_debugaccess -> rx_eth_pkt_backpressure_control_csr_translator:uav_debugaccess
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:m0_byteenable -> rx_eth_pkt_backpressure_control_csr_translator:uav_byteenable
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_source_valid -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(69 downto 0); -- rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_source_data -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_source_ready
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(69 downto 0); -- rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_sink_data
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rf_sink_ready -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ signal rx_bridge_m0_translator_avalon_universal_master_0_waitrequest : std_logic; -- rx_bridge_m0_translator_avalon_universal_master_0_agent:av_waitrequest -> rx_bridge_m0_translator:uav_waitrequest
+ signal rx_bridge_m0_translator_avalon_universal_master_0_burstcount : std_logic_vector(2 downto 0); -- rx_bridge_m0_translator:uav_burstcount -> rx_bridge_m0_translator_avalon_universal_master_0_agent:av_burstcount
+ signal rx_bridge_m0_translator_avalon_universal_master_0_writedata : std_logic_vector(31 downto 0); -- rx_bridge_m0_translator:uav_writedata -> rx_bridge_m0_translator_avalon_universal_master_0_agent:av_writedata
+ signal rx_bridge_m0_translator_avalon_universal_master_0_address : std_logic_vector(13 downto 0); -- rx_bridge_m0_translator:uav_address -> rx_bridge_m0_translator_avalon_universal_master_0_agent:av_address
+ signal rx_bridge_m0_translator_avalon_universal_master_0_lock : std_logic; -- rx_bridge_m0_translator:uav_lock -> rx_bridge_m0_translator_avalon_universal_master_0_agent:av_lock
+ signal rx_bridge_m0_translator_avalon_universal_master_0_write : std_logic; -- rx_bridge_m0_translator:uav_write -> rx_bridge_m0_translator_avalon_universal_master_0_agent:av_write
+ signal rx_bridge_m0_translator_avalon_universal_master_0_read : std_logic; -- rx_bridge_m0_translator:uav_read -> rx_bridge_m0_translator_avalon_universal_master_0_agent:av_read
+ signal rx_bridge_m0_translator_avalon_universal_master_0_readdata : std_logic_vector(31 downto 0); -- rx_bridge_m0_translator_avalon_universal_master_0_agent:av_readdata -> rx_bridge_m0_translator:uav_readdata
+ signal rx_bridge_m0_translator_avalon_universal_master_0_debugaccess : std_logic; -- rx_bridge_m0_translator:uav_debugaccess -> rx_bridge_m0_translator_avalon_universal_master_0_agent:av_debugaccess
+ signal rx_bridge_m0_translator_avalon_universal_master_0_byteenable : std_logic_vector(3 downto 0); -- rx_bridge_m0_translator:uav_byteenable -> rx_bridge_m0_translator_avalon_universal_master_0_agent:av_byteenable
+ signal rx_bridge_m0_translator_avalon_universal_master_0_readdatavalid : std_logic; -- rx_bridge_m0_translator_avalon_universal_master_0_agent:av_readdatavalid -> rx_bridge_m0_translator:uav_readdatavalid
+ signal rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- rx_eth_statistics_collector_csr_translator:uav_waitrequest -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_waitrequest
+ signal rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_burstcount -> rx_eth_statistics_collector_csr_translator:uav_burstcount
+ signal rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_writedata -> rx_eth_statistics_collector_csr_translator:uav_writedata
+ signal rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(13 downto 0); -- rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_address -> rx_eth_statistics_collector_csr_translator:uav_address
+ signal rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_write -> rx_eth_statistics_collector_csr_translator:uav_write
+ signal rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_lock -> rx_eth_statistics_collector_csr_translator:uav_lock
+ signal rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_read -> rx_eth_statistics_collector_csr_translator:uav_read
+ signal rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- rx_eth_statistics_collector_csr_translator:uav_readdata -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_readdata
+ signal rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- rx_eth_statistics_collector_csr_translator:uav_readdatavalid -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_readdatavalid
+ signal rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_debugaccess -> rx_eth_statistics_collector_csr_translator:uav_debugaccess
+ signal rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:m0_byteenable -> rx_eth_statistics_collector_csr_translator:uav_byteenable
+ signal rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
+ signal rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_source_valid -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
+ signal rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
+ signal rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(69 downto 0); -- rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_source_data -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
+ signal rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_source_ready
+ signal rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
+ signal rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_sink_valid
+ signal rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
+ signal rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(69 downto 0); -- rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_sink_data
+ signal rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rf_sink_ready -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
+ signal rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
+ signal rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
+ signal rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
+ signal merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent_cp_endofpacket : std_logic; -- merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
+ signal merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent_cp_valid : std_logic; -- merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
+ signal merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent_cp_startofpacket : std_logic; -- merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
+ signal merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent_cp_data : std_logic_vector(65 downto 0); -- merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
+ signal merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent_cp_ready : std_logic; -- addr_router:sink_ready -> merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:cp_ready
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- tx_bridge_s0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- tx_bridge_s0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- tx_bridge_s0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(65 downto 0); -- tx_bridge_s0_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
+ signal tx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router:sink_ready -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:rp_ready
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- rx_bridge_s0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- rx_bridge_s0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- rx_bridge_s0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(65 downto 0); -- rx_bridge_s0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
+ signal rx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_001:sink_ready -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:rp_ready
+ signal tx_bridge_m0_translator_avalon_universal_master_0_agent_cp_endofpacket : std_logic; -- tx_bridge_m0_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket
+ signal tx_bridge_m0_translator_avalon_universal_master_0_agent_cp_valid : std_logic; -- tx_bridge_m0_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid
+ signal tx_bridge_m0_translator_avalon_universal_master_0_agent_cp_startofpacket : std_logic; -- tx_bridge_m0_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket
+ signal tx_bridge_m0_translator_avalon_universal_master_0_agent_cp_data : std_logic_vector(68 downto 0); -- tx_bridge_m0_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data
+ signal tx_bridge_m0_translator_avalon_universal_master_0_agent_cp_ready : std_logic; -- addr_router_001:sink_ready -> tx_bridge_m0_translator_avalon_universal_master_0_agent:cp_ready
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(68 downto 0); -- tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data
+ signal tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_002:sink_ready -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rp_ready
+ signal tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket
+ signal tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid
+ signal tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket
+ signal tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(68 downto 0); -- tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data
+ signal tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_003:sink_ready -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:rp_ready
+ signal tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket
+ signal tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid
+ signal tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket
+ signal tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(68 downto 0); -- tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data
+ signal tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_004:sink_ready -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:rp_ready
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(68 downto 0); -- tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data
+ signal tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_005:sink_ready -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:rp_ready
+ signal tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_006:sink_endofpacket
+ signal tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_006:sink_valid
+ signal tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_006:sink_startofpacket
+ signal tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(68 downto 0); -- tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rp_data -> id_router_006:sink_data
+ signal tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_006:sink_ready -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:rp_ready
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_007:sink_endofpacket
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_007:sink_valid
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_007:sink_startofpacket
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(68 downto 0); -- tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_007:sink_data
+ signal tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_007:sink_ready -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_008:sink_endofpacket
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_008:sink_valid
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_008:sink_startofpacket
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(68 downto 0); -- tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rp_data -> id_router_008:sink_data
+ signal tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_008:sink_ready -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rp_ready
+ signal tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_009:sink_endofpacket
+ signal tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_009:sink_valid
+ signal tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_009:sink_startofpacket
+ signal tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(68 downto 0); -- tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rp_data -> id_router_009:sink_data
+ signal tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_009:sink_ready -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rp_ready
+ signal rx_bridge_m0_translator_avalon_universal_master_0_agent_cp_endofpacket : std_logic; -- rx_bridge_m0_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_002:sink_endofpacket
+ signal rx_bridge_m0_translator_avalon_universal_master_0_agent_cp_valid : std_logic; -- rx_bridge_m0_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_002:sink_valid
+ signal rx_bridge_m0_translator_avalon_universal_master_0_agent_cp_startofpacket : std_logic; -- rx_bridge_m0_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_002:sink_startofpacket
+ signal rx_bridge_m0_translator_avalon_universal_master_0_agent_cp_data : std_logic_vector(68 downto 0); -- rx_bridge_m0_translator_avalon_universal_master_0_agent:cp_data -> addr_router_002:sink_data
+ signal rx_bridge_m0_translator_avalon_universal_master_0_agent_cp_ready : std_logic; -- addr_router_002:sink_ready -> rx_bridge_m0_translator_avalon_universal_master_0_agent:cp_ready
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_010:sink_endofpacket
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_010:sink_valid
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_010:sink_startofpacket
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(68 downto 0); -- rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rp_data -> id_router_010:sink_data
+ signal rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_010:sink_ready -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:rp_ready
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_011:sink_endofpacket
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_011:sink_valid
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_011:sink_startofpacket
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(68 downto 0); -- rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rp_data -> id_router_011:sink_data
+ signal rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_011:sink_ready -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:rp_ready
+ signal rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_012:sink_endofpacket
+ signal rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_012:sink_valid
+ signal rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_012:sink_startofpacket
+ signal rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(68 downto 0); -- rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rp_data -> id_router_012:sink_data
+ signal rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_012:sink_ready -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:rp_ready
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_013:sink_endofpacket
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_013:sink_valid
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_013:sink_startofpacket
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(68 downto 0); -- rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rp_data -> id_router_013:sink_data
+ signal rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_013:sink_ready -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:rp_ready
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_014:sink_endofpacket
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_014:sink_valid
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_014:sink_startofpacket
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(68 downto 0); -- rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rp_data -> id_router_014:sink_data
+ signal rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_014:sink_ready -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:rp_ready
+ signal rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_015:sink_endofpacket
+ signal rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_015:sink_valid
+ signal rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_015:sink_startofpacket
+ signal rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(68 downto 0); -- rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rp_data -> id_router_015:sink_data
+ signal rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_015:sink_ready -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:rp_ready
+ signal rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_016:sink_endofpacket
+ signal rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_016:sink_valid
+ signal rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_016:sink_startofpacket
+ signal rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(68 downto 0); -- rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rp_data -> id_router_016:sink_data
+ signal rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_016:sink_ready -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:rp_ready
+ signal addr_router_src_endofpacket : std_logic; -- addr_router:src_endofpacket -> limiter:cmd_sink_endofpacket
+ signal addr_router_src_valid : std_logic; -- addr_router:src_valid -> limiter:cmd_sink_valid
+ signal addr_router_src_startofpacket : std_logic; -- addr_router:src_startofpacket -> limiter:cmd_sink_startofpacket
+ signal addr_router_src_data : std_logic_vector(65 downto 0); -- addr_router:src_data -> limiter:cmd_sink_data
+ signal addr_router_src_channel : std_logic_vector(1 downto 0); -- addr_router:src_channel -> limiter:cmd_sink_channel
+ signal addr_router_src_ready : std_logic; -- limiter:cmd_sink_ready -> addr_router:src_ready
+ signal limiter_rsp_src_endofpacket : std_logic; -- limiter:rsp_src_endofpacket -> merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:rp_endofpacket
+ signal limiter_rsp_src_valid : std_logic; -- limiter:rsp_src_valid -> merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:rp_valid
+ signal limiter_rsp_src_startofpacket : std_logic; -- limiter:rsp_src_startofpacket -> merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:rp_startofpacket
+ signal limiter_rsp_src_data : std_logic_vector(65 downto 0); -- limiter:rsp_src_data -> merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:rp_data
+ signal limiter_rsp_src_channel : std_logic_vector(1 downto 0); -- limiter:rsp_src_channel -> merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:rp_channel
+ signal limiter_rsp_src_ready : std_logic; -- merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:rp_ready -> limiter:rsp_src_ready
+ signal addr_router_001_src_endofpacket : std_logic; -- addr_router_001:src_endofpacket -> limiter_001:cmd_sink_endofpacket
+ signal addr_router_001_src_valid : std_logic; -- addr_router_001:src_valid -> limiter_001:cmd_sink_valid
+ signal addr_router_001_src_startofpacket : std_logic; -- addr_router_001:src_startofpacket -> limiter_001:cmd_sink_startofpacket
+ signal addr_router_001_src_data : std_logic_vector(68 downto 0); -- addr_router_001:src_data -> limiter_001:cmd_sink_data
+ signal addr_router_001_src_channel : std_logic_vector(7 downto 0); -- addr_router_001:src_channel -> limiter_001:cmd_sink_channel
+ signal addr_router_001_src_ready : std_logic; -- limiter_001:cmd_sink_ready -> addr_router_001:src_ready
+ signal limiter_001_rsp_src_endofpacket : std_logic; -- limiter_001:rsp_src_endofpacket -> tx_bridge_m0_translator_avalon_universal_master_0_agent:rp_endofpacket
+ signal limiter_001_rsp_src_valid : std_logic; -- limiter_001:rsp_src_valid -> tx_bridge_m0_translator_avalon_universal_master_0_agent:rp_valid
+ signal limiter_001_rsp_src_startofpacket : std_logic; -- limiter_001:rsp_src_startofpacket -> tx_bridge_m0_translator_avalon_universal_master_0_agent:rp_startofpacket
+ signal limiter_001_rsp_src_data : std_logic_vector(68 downto 0); -- limiter_001:rsp_src_data -> tx_bridge_m0_translator_avalon_universal_master_0_agent:rp_data
+ signal limiter_001_rsp_src_channel : std_logic_vector(7 downto 0); -- limiter_001:rsp_src_channel -> tx_bridge_m0_translator_avalon_universal_master_0_agent:rp_channel
+ signal limiter_001_rsp_src_ready : std_logic; -- tx_bridge_m0_translator_avalon_universal_master_0_agent:rp_ready -> limiter_001:rsp_src_ready
+ signal addr_router_002_src_endofpacket : std_logic; -- addr_router_002:src_endofpacket -> limiter_002:cmd_sink_endofpacket
+ signal addr_router_002_src_valid : std_logic; -- addr_router_002:src_valid -> limiter_002:cmd_sink_valid
+ signal addr_router_002_src_startofpacket : std_logic; -- addr_router_002:src_startofpacket -> limiter_002:cmd_sink_startofpacket
+ signal addr_router_002_src_data : std_logic_vector(68 downto 0); -- addr_router_002:src_data -> limiter_002:cmd_sink_data
+ signal addr_router_002_src_channel : std_logic_vector(6 downto 0); -- addr_router_002:src_channel -> limiter_002:cmd_sink_channel
+ signal addr_router_002_src_ready : std_logic; -- limiter_002:cmd_sink_ready -> addr_router_002:src_ready
+ signal limiter_002_rsp_src_endofpacket : std_logic; -- limiter_002:rsp_src_endofpacket -> rx_bridge_m0_translator_avalon_universal_master_0_agent:rp_endofpacket
+ signal limiter_002_rsp_src_valid : std_logic; -- limiter_002:rsp_src_valid -> rx_bridge_m0_translator_avalon_universal_master_0_agent:rp_valid
+ signal limiter_002_rsp_src_startofpacket : std_logic; -- limiter_002:rsp_src_startofpacket -> rx_bridge_m0_translator_avalon_universal_master_0_agent:rp_startofpacket
+ signal limiter_002_rsp_src_data : std_logic_vector(68 downto 0); -- limiter_002:rsp_src_data -> rx_bridge_m0_translator_avalon_universal_master_0_agent:rp_data
+ signal limiter_002_rsp_src_channel : std_logic_vector(6 downto 0); -- limiter_002:rsp_src_channel -> rx_bridge_m0_translator_avalon_universal_master_0_agent:rp_channel
+ signal limiter_002_rsp_src_ready : std_logic; -- rx_bridge_m0_translator_avalon_universal_master_0_agent:rp_ready -> limiter_002:rsp_src_ready
+ signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [addr_router:reset, cmd_xbar_demux:reset, crosser:in_reset, crosser_001:in_reset, crosser_002:out_reset, crosser_003:out_reset, limiter:reset, merlin_master_translator:reset, merlin_master_translator_avalon_universal_master_0_translator:reset, merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent:reset, rsp_xbar_mux:reset]
+ signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [addr_router_001:reset, cmd_xbar_demux_001:reset, crosser:out_reset, crosser_002:in_reset, id_router:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, id_router_006:reset, id_router_007:reset, id_router_008:reset, id_router_009:reset, limiter_001:reset, rsp_xbar_demux:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_demux_006:reset, rsp_xbar_demux_007:reset, rsp_xbar_demux_008:reset, rsp_xbar_demux_009:reset, rsp_xbar_mux_001:reset, rst_controller_001_reset_out_reset:in, tx_bridge:reset, tx_bridge_m0_translator:reset, tx_bridge_m0_translator_avalon_universal_master_0_agent:reset, tx_bridge_s0_translator:reset, tx_bridge_s0_translator_avalon_universal_slave_0_agent:reset, tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo:reset, tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, tx_eth_address_inserter:reset, tx_eth_address_inserter_csr_translator:reset, tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:reset, tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, tx_eth_crc_inserter:reset, tx_eth_crc_inserter_csr_translator:reset, tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:reset, tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, tx_eth_frame_decoder:reset, tx_eth_frame_decoder_avalom_mm_csr_translator:reset, tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:reset, tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, tx_eth_link_fault_generation:reset, tx_eth_packet_formatter:reset, tx_eth_packet_underflow_control:reset, tx_eth_packet_underflow_control_avalon_slave_0_translator:reset, tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:reset, tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, tx_eth_pad_inserter:reset, tx_eth_pad_inserter_csr_translator:reset, tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:reset, tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, tx_eth_pause_beat_conversion:reset, tx_eth_pause_ctrl_gen:reset, tx_eth_pause_ctrl_gen_csr_translator:reset, tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:reset, tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, tx_eth_pkt_backpressure_control:reset, tx_eth_pkt_backpressure_control_csr_translator:reset, tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:reset, tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, tx_eth_statistics_collector:reset, tx_eth_statistics_collector_csr_translator:reset, tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:reset, tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, tx_eth_xgmii_termination:reset, tx_st_pipeline_stage_rs:reset]
+ signal rst_controller_002_reset_out_reset : std_logic; -- rst_controller_002:reset_out -> [addr_router_002:reset, cmd_xbar_demux_002:reset, crosser_001:out_reset, crosser_003:in_reset, id_router_001:reset, id_router_010:reset, id_router_011:reset, id_router_012:reset, id_router_013:reset, id_router_014:reset, id_router_015:reset, id_router_016:reset, limiter_002:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_010:reset, rsp_xbar_demux_011:reset, rsp_xbar_demux_012:reset, rsp_xbar_demux_013:reset, rsp_xbar_demux_014:reset, rsp_xbar_demux_015:reset, rsp_xbar_demux_016:reset, rsp_xbar_mux_002:reset, rst_controller_002_reset_out_reset:in, rx_bridge:reset, rx_bridge_m0_translator:reset, rx_bridge_m0_translator_avalon_universal_master_0_agent:reset, rx_bridge_s0_translator:reset, rx_bridge_s0_translator_avalon_universal_slave_0_agent:reset, rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo:reset, rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rx_eth_crc_checker:reset, rx_eth_crc_checker_csr_translator:reset, rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:reset, rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rx_eth_crc_pad_rem:reset, rx_eth_crc_pad_rem_csr_translator:reset, rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:reset, rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rx_eth_frame_decoder:reset, rx_eth_frame_decoder_avalom_mm_csr_translator:reset, rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:reset, rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rx_eth_frame_status_merger:reset, rx_eth_lane_decoder:reset, rx_eth_lane_decoder_csr_translator:reset, rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:reset, rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rx_eth_link_fault_detection:reset, rx_eth_packet_overflow_control:reset, rx_eth_packet_overflow_control_csr_translator:reset, rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:reset, rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rx_eth_pkt_backpressure_control:reset, rx_eth_pkt_backpressure_control_csr_translator:reset, rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:reset, rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rx_eth_statistics_collector:reset, rx_eth_statistics_collector_csr_translator:reset, rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:reset, rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:reset]
+ signal limiter_cmd_src_endofpacket : std_logic; -- limiter:cmd_src_endofpacket -> cmd_xbar_demux:sink_endofpacket
+ signal limiter_cmd_src_startofpacket : std_logic; -- limiter:cmd_src_startofpacket -> cmd_xbar_demux:sink_startofpacket
+ signal limiter_cmd_src_data : std_logic_vector(65 downto 0); -- limiter:cmd_src_data -> cmd_xbar_demux:sink_data
+ signal limiter_cmd_src_channel : std_logic_vector(1 downto 0); -- limiter:cmd_src_channel -> cmd_xbar_demux:sink_channel
+ signal limiter_cmd_src_ready : std_logic; -- cmd_xbar_demux:sink_ready -> limiter:cmd_src_ready
+ signal rsp_xbar_mux_src_endofpacket : std_logic; -- rsp_xbar_mux:src_endofpacket -> limiter:rsp_sink_endofpacket
+ signal rsp_xbar_mux_src_valid : std_logic; -- rsp_xbar_mux:src_valid -> limiter:rsp_sink_valid
+ signal rsp_xbar_mux_src_startofpacket : std_logic; -- rsp_xbar_mux:src_startofpacket -> limiter:rsp_sink_startofpacket
+ signal rsp_xbar_mux_src_data : std_logic_vector(65 downto 0); -- rsp_xbar_mux:src_data -> limiter:rsp_sink_data
+ signal rsp_xbar_mux_src_channel : std_logic_vector(1 downto 0); -- rsp_xbar_mux:src_channel -> limiter:rsp_sink_channel
+ signal rsp_xbar_mux_src_ready : std_logic; -- limiter:rsp_sink_ready -> rsp_xbar_mux:src_ready
+ signal crosser_out_ready : std_logic; -- tx_bridge_s0_translator_avalon_universal_slave_0_agent:cp_ready -> crosser:out_ready
+ signal id_router_src_endofpacket : std_logic; -- id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
+ signal id_router_src_valid : std_logic; -- id_router:src_valid -> rsp_xbar_demux:sink_valid
+ signal id_router_src_startofpacket : std_logic; -- id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
+ signal id_router_src_data : std_logic_vector(65 downto 0); -- id_router:src_data -> rsp_xbar_demux:sink_data
+ signal id_router_src_channel : std_logic_vector(1 downto 0); -- id_router:src_channel -> rsp_xbar_demux:sink_channel
+ signal id_router_src_ready : std_logic; -- rsp_xbar_demux:sink_ready -> id_router:src_ready
+ signal crosser_001_out_ready : std_logic; -- rx_bridge_s0_translator_avalon_universal_slave_0_agent:cp_ready -> crosser_001:out_ready
+ signal id_router_001_src_endofpacket : std_logic; -- id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
+ signal id_router_001_src_valid : std_logic; -- id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid
+ signal id_router_001_src_startofpacket : std_logic; -- id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
+ signal id_router_001_src_data : std_logic_vector(65 downto 0); -- id_router_001:src_data -> rsp_xbar_demux_001:sink_data
+ signal id_router_001_src_channel : std_logic_vector(1 downto 0); -- id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel
+ signal id_router_001_src_ready : std_logic; -- rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready
+ signal cmd_xbar_demux_001_src0_endofpacket : std_logic; -- cmd_xbar_demux_001:src0_endofpacket -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ signal cmd_xbar_demux_001_src0_valid : std_logic; -- cmd_xbar_demux_001:src0_valid -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:cp_valid
+ signal cmd_xbar_demux_001_src0_startofpacket : std_logic; -- cmd_xbar_demux_001:src0_startofpacket -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ signal cmd_xbar_demux_001_src0_data : std_logic_vector(68 downto 0); -- cmd_xbar_demux_001:src0_data -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:cp_data
+ signal cmd_xbar_demux_001_src0_channel : std_logic_vector(7 downto 0); -- cmd_xbar_demux_001:src0_channel -> tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:cp_channel
+ signal cmd_xbar_demux_001_src1_endofpacket : std_logic; -- cmd_xbar_demux_001:src1_endofpacket -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ signal cmd_xbar_demux_001_src1_valid : std_logic; -- cmd_xbar_demux_001:src1_valid -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:cp_valid
+ signal cmd_xbar_demux_001_src1_startofpacket : std_logic; -- cmd_xbar_demux_001:src1_startofpacket -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ signal cmd_xbar_demux_001_src1_data : std_logic_vector(68 downto 0); -- cmd_xbar_demux_001:src1_data -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:cp_data
+ signal cmd_xbar_demux_001_src1_channel : std_logic_vector(7 downto 0); -- cmd_xbar_demux_001:src1_channel -> tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:cp_channel
+ signal cmd_xbar_demux_001_src2_endofpacket : std_logic; -- cmd_xbar_demux_001:src2_endofpacket -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ signal cmd_xbar_demux_001_src2_valid : std_logic; -- cmd_xbar_demux_001:src2_valid -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:cp_valid
+ signal cmd_xbar_demux_001_src2_startofpacket : std_logic; -- cmd_xbar_demux_001:src2_startofpacket -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ signal cmd_xbar_demux_001_src2_data : std_logic_vector(68 downto 0); -- cmd_xbar_demux_001:src2_data -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:cp_data
+ signal cmd_xbar_demux_001_src2_channel : std_logic_vector(7 downto 0); -- cmd_xbar_demux_001:src2_channel -> tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:cp_channel
+ signal cmd_xbar_demux_001_src3_endofpacket : std_logic; -- cmd_xbar_demux_001:src3_endofpacket -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ signal cmd_xbar_demux_001_src3_valid : std_logic; -- cmd_xbar_demux_001:src3_valid -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:cp_valid
+ signal cmd_xbar_demux_001_src3_startofpacket : std_logic; -- cmd_xbar_demux_001:src3_startofpacket -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ signal cmd_xbar_demux_001_src3_data : std_logic_vector(68 downto 0); -- cmd_xbar_demux_001:src3_data -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:cp_data
+ signal cmd_xbar_demux_001_src3_channel : std_logic_vector(7 downto 0); -- cmd_xbar_demux_001:src3_channel -> tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:cp_channel
+ signal cmd_xbar_demux_001_src4_endofpacket : std_logic; -- cmd_xbar_demux_001:src4_endofpacket -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ signal cmd_xbar_demux_001_src4_valid : std_logic; -- cmd_xbar_demux_001:src4_valid -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:cp_valid
+ signal cmd_xbar_demux_001_src4_startofpacket : std_logic; -- cmd_xbar_demux_001:src4_startofpacket -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ signal cmd_xbar_demux_001_src4_data : std_logic_vector(68 downto 0); -- cmd_xbar_demux_001:src4_data -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:cp_data
+ signal cmd_xbar_demux_001_src4_channel : std_logic_vector(7 downto 0); -- cmd_xbar_demux_001:src4_channel -> tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:cp_channel
+ signal cmd_xbar_demux_001_src5_endofpacket : std_logic; -- cmd_xbar_demux_001:src5_endofpacket -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ signal cmd_xbar_demux_001_src5_valid : std_logic; -- cmd_xbar_demux_001:src5_valid -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
+ signal cmd_xbar_demux_001_src5_startofpacket : std_logic; -- cmd_xbar_demux_001:src5_startofpacket -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ signal cmd_xbar_demux_001_src5_data : std_logic_vector(68 downto 0); -- cmd_xbar_demux_001:src5_data -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
+ signal cmd_xbar_demux_001_src5_channel : std_logic_vector(7 downto 0); -- cmd_xbar_demux_001:src5_channel -> tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
+ signal cmd_xbar_demux_001_src6_endofpacket : std_logic; -- cmd_xbar_demux_001:src6_endofpacket -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ signal cmd_xbar_demux_001_src6_valid : std_logic; -- cmd_xbar_demux_001:src6_valid -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:cp_valid
+ signal cmd_xbar_demux_001_src6_startofpacket : std_logic; -- cmd_xbar_demux_001:src6_startofpacket -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ signal cmd_xbar_demux_001_src6_data : std_logic_vector(68 downto 0); -- cmd_xbar_demux_001:src6_data -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:cp_data
+ signal cmd_xbar_demux_001_src6_channel : std_logic_vector(7 downto 0); -- cmd_xbar_demux_001:src6_channel -> tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:cp_channel
+ signal cmd_xbar_demux_001_src7_endofpacket : std_logic; -- cmd_xbar_demux_001:src7_endofpacket -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ signal cmd_xbar_demux_001_src7_valid : std_logic; -- cmd_xbar_demux_001:src7_valid -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:cp_valid
+ signal cmd_xbar_demux_001_src7_startofpacket : std_logic; -- cmd_xbar_demux_001:src7_startofpacket -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ signal cmd_xbar_demux_001_src7_data : std_logic_vector(68 downto 0); -- cmd_xbar_demux_001:src7_data -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:cp_data
+ signal cmd_xbar_demux_001_src7_channel : std_logic_vector(7 downto 0); -- cmd_xbar_demux_001:src7_channel -> tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:cp_channel
+ signal rsp_xbar_demux_002_src0_endofpacket : std_logic; -- rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket
+ signal rsp_xbar_demux_002_src0_valid : std_logic; -- rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux_001:sink0_valid
+ signal rsp_xbar_demux_002_src0_startofpacket : std_logic; -- rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket
+ signal rsp_xbar_demux_002_src0_data : std_logic_vector(68 downto 0); -- rsp_xbar_demux_002:src0_data -> rsp_xbar_mux_001:sink0_data
+ signal rsp_xbar_demux_002_src0_channel : std_logic_vector(7 downto 0); -- rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux_001:sink0_channel
+ signal rsp_xbar_demux_002_src0_ready : std_logic; -- rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux_002:src0_ready
+ signal rsp_xbar_demux_003_src0_endofpacket : std_logic; -- rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket
+ signal rsp_xbar_demux_003_src0_valid : std_logic; -- rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux_001:sink1_valid
+ signal rsp_xbar_demux_003_src0_startofpacket : std_logic; -- rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket
+ signal rsp_xbar_demux_003_src0_data : std_logic_vector(68 downto 0); -- rsp_xbar_demux_003:src0_data -> rsp_xbar_mux_001:sink1_data
+ signal rsp_xbar_demux_003_src0_channel : std_logic_vector(7 downto 0); -- rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux_001:sink1_channel
+ signal rsp_xbar_demux_003_src0_ready : std_logic; -- rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_003:src0_ready
+ signal rsp_xbar_demux_004_src0_endofpacket : std_logic; -- rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket
+ signal rsp_xbar_demux_004_src0_valid : std_logic; -- rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux_001:sink2_valid
+ signal rsp_xbar_demux_004_src0_startofpacket : std_logic; -- rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket
+ signal rsp_xbar_demux_004_src0_data : std_logic_vector(68 downto 0); -- rsp_xbar_demux_004:src0_data -> rsp_xbar_mux_001:sink2_data
+ signal rsp_xbar_demux_004_src0_channel : std_logic_vector(7 downto 0); -- rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux_001:sink2_channel
+ signal rsp_xbar_demux_004_src0_ready : std_logic; -- rsp_xbar_mux_001:sink2_ready -> rsp_xbar_demux_004:src0_ready
+ signal rsp_xbar_demux_005_src0_endofpacket : std_logic; -- rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket
+ signal rsp_xbar_demux_005_src0_valid : std_logic; -- rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink3_valid
+ signal rsp_xbar_demux_005_src0_startofpacket : std_logic; -- rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket
+ signal rsp_xbar_demux_005_src0_data : std_logic_vector(68 downto 0); -- rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink3_data
+ signal rsp_xbar_demux_005_src0_channel : std_logic_vector(7 downto 0); -- rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink3_channel
+ signal rsp_xbar_demux_005_src0_ready : std_logic; -- rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_005:src0_ready
+ signal rsp_xbar_demux_006_src0_endofpacket : std_logic; -- rsp_xbar_demux_006:src0_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket
+ signal rsp_xbar_demux_006_src0_valid : std_logic; -- rsp_xbar_demux_006:src0_valid -> rsp_xbar_mux_001:sink4_valid
+ signal rsp_xbar_demux_006_src0_startofpacket : std_logic; -- rsp_xbar_demux_006:src0_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket
+ signal rsp_xbar_demux_006_src0_data : std_logic_vector(68 downto 0); -- rsp_xbar_demux_006:src0_data -> rsp_xbar_mux_001:sink4_data
+ signal rsp_xbar_demux_006_src0_channel : std_logic_vector(7 downto 0); -- rsp_xbar_demux_006:src0_channel -> rsp_xbar_mux_001:sink4_channel
+ signal rsp_xbar_demux_006_src0_ready : std_logic; -- rsp_xbar_mux_001:sink4_ready -> rsp_xbar_demux_006:src0_ready
+ signal rsp_xbar_demux_007_src0_endofpacket : std_logic; -- rsp_xbar_demux_007:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket
+ signal rsp_xbar_demux_007_src0_valid : std_logic; -- rsp_xbar_demux_007:src0_valid -> rsp_xbar_mux_001:sink5_valid
+ signal rsp_xbar_demux_007_src0_startofpacket : std_logic; -- rsp_xbar_demux_007:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket
+ signal rsp_xbar_demux_007_src0_data : std_logic_vector(68 downto 0); -- rsp_xbar_demux_007:src0_data -> rsp_xbar_mux_001:sink5_data
+ signal rsp_xbar_demux_007_src0_channel : std_logic_vector(7 downto 0); -- rsp_xbar_demux_007:src0_channel -> rsp_xbar_mux_001:sink5_channel
+ signal rsp_xbar_demux_007_src0_ready : std_logic; -- rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_007:src0_ready
+ signal rsp_xbar_demux_008_src0_endofpacket : std_logic; -- rsp_xbar_demux_008:src0_endofpacket -> rsp_xbar_mux_001:sink6_endofpacket
+ signal rsp_xbar_demux_008_src0_valid : std_logic; -- rsp_xbar_demux_008:src0_valid -> rsp_xbar_mux_001:sink6_valid
+ signal rsp_xbar_demux_008_src0_startofpacket : std_logic; -- rsp_xbar_demux_008:src0_startofpacket -> rsp_xbar_mux_001:sink6_startofpacket
+ signal rsp_xbar_demux_008_src0_data : std_logic_vector(68 downto 0); -- rsp_xbar_demux_008:src0_data -> rsp_xbar_mux_001:sink6_data
+ signal rsp_xbar_demux_008_src0_channel : std_logic_vector(7 downto 0); -- rsp_xbar_demux_008:src0_channel -> rsp_xbar_mux_001:sink6_channel
+ signal rsp_xbar_demux_008_src0_ready : std_logic; -- rsp_xbar_mux_001:sink6_ready -> rsp_xbar_demux_008:src0_ready
+ signal rsp_xbar_demux_009_src0_endofpacket : std_logic; -- rsp_xbar_demux_009:src0_endofpacket -> rsp_xbar_mux_001:sink7_endofpacket
+ signal rsp_xbar_demux_009_src0_valid : std_logic; -- rsp_xbar_demux_009:src0_valid -> rsp_xbar_mux_001:sink7_valid
+ signal rsp_xbar_demux_009_src0_startofpacket : std_logic; -- rsp_xbar_demux_009:src0_startofpacket -> rsp_xbar_mux_001:sink7_startofpacket
+ signal rsp_xbar_demux_009_src0_data : std_logic_vector(68 downto 0); -- rsp_xbar_demux_009:src0_data -> rsp_xbar_mux_001:sink7_data
+ signal rsp_xbar_demux_009_src0_channel : std_logic_vector(7 downto 0); -- rsp_xbar_demux_009:src0_channel -> rsp_xbar_mux_001:sink7_channel
+ signal rsp_xbar_demux_009_src0_ready : std_logic; -- rsp_xbar_mux_001:sink7_ready -> rsp_xbar_demux_009:src0_ready
+ signal limiter_001_cmd_src_endofpacket : std_logic; -- limiter_001:cmd_src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
+ signal limiter_001_cmd_src_startofpacket : std_logic; -- limiter_001:cmd_src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
+ signal limiter_001_cmd_src_data : std_logic_vector(68 downto 0); -- limiter_001:cmd_src_data -> cmd_xbar_demux_001:sink_data
+ signal limiter_001_cmd_src_channel : std_logic_vector(7 downto 0); -- limiter_001:cmd_src_channel -> cmd_xbar_demux_001:sink_channel
+ signal limiter_001_cmd_src_ready : std_logic; -- cmd_xbar_demux_001:sink_ready -> limiter_001:cmd_src_ready
+ signal rsp_xbar_mux_001_src_endofpacket : std_logic; -- rsp_xbar_mux_001:src_endofpacket -> limiter_001:rsp_sink_endofpacket
+ signal rsp_xbar_mux_001_src_valid : std_logic; -- rsp_xbar_mux_001:src_valid -> limiter_001:rsp_sink_valid
+ signal rsp_xbar_mux_001_src_startofpacket : std_logic; -- rsp_xbar_mux_001:src_startofpacket -> limiter_001:rsp_sink_startofpacket
+ signal rsp_xbar_mux_001_src_data : std_logic_vector(68 downto 0); -- rsp_xbar_mux_001:src_data -> limiter_001:rsp_sink_data
+ signal rsp_xbar_mux_001_src_channel : std_logic_vector(7 downto 0); -- rsp_xbar_mux_001:src_channel -> limiter_001:rsp_sink_channel
+ signal rsp_xbar_mux_001_src_ready : std_logic; -- limiter_001:rsp_sink_ready -> rsp_xbar_mux_001:src_ready
+ signal cmd_xbar_demux_001_src0_ready : std_logic; -- tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src0_ready
+ signal id_router_002_src_endofpacket : std_logic; -- id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket
+ signal id_router_002_src_valid : std_logic; -- id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid
+ signal id_router_002_src_startofpacket : std_logic; -- id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket
+ signal id_router_002_src_data : std_logic_vector(68 downto 0); -- id_router_002:src_data -> rsp_xbar_demux_002:sink_data
+ signal id_router_002_src_channel : std_logic_vector(7 downto 0); -- id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel
+ signal id_router_002_src_ready : std_logic; -- rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready
+ signal cmd_xbar_demux_001_src1_ready : std_logic; -- tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src1_ready
+ signal id_router_003_src_endofpacket : std_logic; -- id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket
+ signal id_router_003_src_valid : std_logic; -- id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid
+ signal id_router_003_src_startofpacket : std_logic; -- id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket
+ signal id_router_003_src_data : std_logic_vector(68 downto 0); -- id_router_003:src_data -> rsp_xbar_demux_003:sink_data
+ signal id_router_003_src_channel : std_logic_vector(7 downto 0); -- id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel
+ signal id_router_003_src_ready : std_logic; -- rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready
+ signal cmd_xbar_demux_001_src2_ready : std_logic; -- tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src2_ready
+ signal id_router_004_src_endofpacket : std_logic; -- id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket
+ signal id_router_004_src_valid : std_logic; -- id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid
+ signal id_router_004_src_startofpacket : std_logic; -- id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket
+ signal id_router_004_src_data : std_logic_vector(68 downto 0); -- id_router_004:src_data -> rsp_xbar_demux_004:sink_data
+ signal id_router_004_src_channel : std_logic_vector(7 downto 0); -- id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel
+ signal id_router_004_src_ready : std_logic; -- rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready
+ signal cmd_xbar_demux_001_src3_ready : std_logic; -- tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src3_ready
+ signal id_router_005_src_endofpacket : std_logic; -- id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket
+ signal id_router_005_src_valid : std_logic; -- id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid
+ signal id_router_005_src_startofpacket : std_logic; -- id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket
+ signal id_router_005_src_data : std_logic_vector(68 downto 0); -- id_router_005:src_data -> rsp_xbar_demux_005:sink_data
+ signal id_router_005_src_channel : std_logic_vector(7 downto 0); -- id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel
+ signal id_router_005_src_ready : std_logic; -- rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready
+ signal cmd_xbar_demux_001_src4_ready : std_logic; -- tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src4_ready
+ signal id_router_006_src_endofpacket : std_logic; -- id_router_006:src_endofpacket -> rsp_xbar_demux_006:sink_endofpacket
+ signal id_router_006_src_valid : std_logic; -- id_router_006:src_valid -> rsp_xbar_demux_006:sink_valid
+ signal id_router_006_src_startofpacket : std_logic; -- id_router_006:src_startofpacket -> rsp_xbar_demux_006:sink_startofpacket
+ signal id_router_006_src_data : std_logic_vector(68 downto 0); -- id_router_006:src_data -> rsp_xbar_demux_006:sink_data
+ signal id_router_006_src_channel : std_logic_vector(7 downto 0); -- id_router_006:src_channel -> rsp_xbar_demux_006:sink_channel
+ signal id_router_006_src_ready : std_logic; -- rsp_xbar_demux_006:sink_ready -> id_router_006:src_ready
+ signal cmd_xbar_demux_001_src5_ready : std_logic; -- tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready
+ signal id_router_007_src_endofpacket : std_logic; -- id_router_007:src_endofpacket -> rsp_xbar_demux_007:sink_endofpacket
+ signal id_router_007_src_valid : std_logic; -- id_router_007:src_valid -> rsp_xbar_demux_007:sink_valid
+ signal id_router_007_src_startofpacket : std_logic; -- id_router_007:src_startofpacket -> rsp_xbar_demux_007:sink_startofpacket
+ signal id_router_007_src_data : std_logic_vector(68 downto 0); -- id_router_007:src_data -> rsp_xbar_demux_007:sink_data
+ signal id_router_007_src_channel : std_logic_vector(7 downto 0); -- id_router_007:src_channel -> rsp_xbar_demux_007:sink_channel
+ signal id_router_007_src_ready : std_logic; -- rsp_xbar_demux_007:sink_ready -> id_router_007:src_ready
+ signal cmd_xbar_demux_001_src6_ready : std_logic; -- tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src6_ready
+ signal id_router_008_src_endofpacket : std_logic; -- id_router_008:src_endofpacket -> rsp_xbar_demux_008:sink_endofpacket
+ signal id_router_008_src_valid : std_logic; -- id_router_008:src_valid -> rsp_xbar_demux_008:sink_valid
+ signal id_router_008_src_startofpacket : std_logic; -- id_router_008:src_startofpacket -> rsp_xbar_demux_008:sink_startofpacket
+ signal id_router_008_src_data : std_logic_vector(68 downto 0); -- id_router_008:src_data -> rsp_xbar_demux_008:sink_data
+ signal id_router_008_src_channel : std_logic_vector(7 downto 0); -- id_router_008:src_channel -> rsp_xbar_demux_008:sink_channel
+ signal id_router_008_src_ready : std_logic; -- rsp_xbar_demux_008:sink_ready -> id_router_008:src_ready
+ signal cmd_xbar_demux_001_src7_ready : std_logic; -- tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src7_ready
+ signal id_router_009_src_endofpacket : std_logic; -- id_router_009:src_endofpacket -> rsp_xbar_demux_009:sink_endofpacket
+ signal id_router_009_src_valid : std_logic; -- id_router_009:src_valid -> rsp_xbar_demux_009:sink_valid
+ signal id_router_009_src_startofpacket : std_logic; -- id_router_009:src_startofpacket -> rsp_xbar_demux_009:sink_startofpacket
+ signal id_router_009_src_data : std_logic_vector(68 downto 0); -- id_router_009:src_data -> rsp_xbar_demux_009:sink_data
+ signal id_router_009_src_channel : std_logic_vector(7 downto 0); -- id_router_009:src_channel -> rsp_xbar_demux_009:sink_channel
+ signal id_router_009_src_ready : std_logic; -- rsp_xbar_demux_009:sink_ready -> id_router_009:src_ready
+ signal cmd_xbar_demux_002_src0_endofpacket : std_logic; -- cmd_xbar_demux_002:src0_endofpacket -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ signal cmd_xbar_demux_002_src0_valid : std_logic; -- cmd_xbar_demux_002:src0_valid -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:cp_valid
+ signal cmd_xbar_demux_002_src0_startofpacket : std_logic; -- cmd_xbar_demux_002:src0_startofpacket -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ signal cmd_xbar_demux_002_src0_data : std_logic_vector(68 downto 0); -- cmd_xbar_demux_002:src0_data -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:cp_data
+ signal cmd_xbar_demux_002_src0_channel : std_logic_vector(6 downto 0); -- cmd_xbar_demux_002:src0_channel -> rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:cp_channel
+ signal cmd_xbar_demux_002_src1_endofpacket : std_logic; -- cmd_xbar_demux_002:src1_endofpacket -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ signal cmd_xbar_demux_002_src1_valid : std_logic; -- cmd_xbar_demux_002:src1_valid -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:cp_valid
+ signal cmd_xbar_demux_002_src1_startofpacket : std_logic; -- cmd_xbar_demux_002:src1_startofpacket -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ signal cmd_xbar_demux_002_src1_data : std_logic_vector(68 downto 0); -- cmd_xbar_demux_002:src1_data -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:cp_data
+ signal cmd_xbar_demux_002_src1_channel : std_logic_vector(6 downto 0); -- cmd_xbar_demux_002:src1_channel -> rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:cp_channel
+ signal cmd_xbar_demux_002_src2_endofpacket : std_logic; -- cmd_xbar_demux_002:src2_endofpacket -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ signal cmd_xbar_demux_002_src2_valid : std_logic; -- cmd_xbar_demux_002:src2_valid -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:cp_valid
+ signal cmd_xbar_demux_002_src2_startofpacket : std_logic; -- cmd_xbar_demux_002:src2_startofpacket -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ signal cmd_xbar_demux_002_src2_data : std_logic_vector(68 downto 0); -- cmd_xbar_demux_002:src2_data -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:cp_data
+ signal cmd_xbar_demux_002_src2_channel : std_logic_vector(6 downto 0); -- cmd_xbar_demux_002:src2_channel -> rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:cp_channel
+ signal cmd_xbar_demux_002_src3_endofpacket : std_logic; -- cmd_xbar_demux_002:src3_endofpacket -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ signal cmd_xbar_demux_002_src3_valid : std_logic; -- cmd_xbar_demux_002:src3_valid -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:cp_valid
+ signal cmd_xbar_demux_002_src3_startofpacket : std_logic; -- cmd_xbar_demux_002:src3_startofpacket -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ signal cmd_xbar_demux_002_src3_data : std_logic_vector(68 downto 0); -- cmd_xbar_demux_002:src3_data -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:cp_data
+ signal cmd_xbar_demux_002_src3_channel : std_logic_vector(6 downto 0); -- cmd_xbar_demux_002:src3_channel -> rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:cp_channel
+ signal cmd_xbar_demux_002_src4_endofpacket : std_logic; -- cmd_xbar_demux_002:src4_endofpacket -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ signal cmd_xbar_demux_002_src4_valid : std_logic; -- cmd_xbar_demux_002:src4_valid -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:cp_valid
+ signal cmd_xbar_demux_002_src4_startofpacket : std_logic; -- cmd_xbar_demux_002:src4_startofpacket -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ signal cmd_xbar_demux_002_src4_data : std_logic_vector(68 downto 0); -- cmd_xbar_demux_002:src4_data -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:cp_data
+ signal cmd_xbar_demux_002_src4_channel : std_logic_vector(6 downto 0); -- cmd_xbar_demux_002:src4_channel -> rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:cp_channel
+ signal cmd_xbar_demux_002_src5_endofpacket : std_logic; -- cmd_xbar_demux_002:src5_endofpacket -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ signal cmd_xbar_demux_002_src5_valid : std_logic; -- cmd_xbar_demux_002:src5_valid -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:cp_valid
+ signal cmd_xbar_demux_002_src5_startofpacket : std_logic; -- cmd_xbar_demux_002:src5_startofpacket -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ signal cmd_xbar_demux_002_src5_data : std_logic_vector(68 downto 0); -- cmd_xbar_demux_002:src5_data -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:cp_data
+ signal cmd_xbar_demux_002_src5_channel : std_logic_vector(6 downto 0); -- cmd_xbar_demux_002:src5_channel -> rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:cp_channel
+ signal cmd_xbar_demux_002_src6_endofpacket : std_logic; -- cmd_xbar_demux_002:src6_endofpacket -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ signal cmd_xbar_demux_002_src6_valid : std_logic; -- cmd_xbar_demux_002:src6_valid -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:cp_valid
+ signal cmd_xbar_demux_002_src6_startofpacket : std_logic; -- cmd_xbar_demux_002:src6_startofpacket -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ signal cmd_xbar_demux_002_src6_data : std_logic_vector(68 downto 0); -- cmd_xbar_demux_002:src6_data -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:cp_data
+ signal cmd_xbar_demux_002_src6_channel : std_logic_vector(6 downto 0); -- cmd_xbar_demux_002:src6_channel -> rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:cp_channel
+ signal rsp_xbar_demux_010_src0_endofpacket : std_logic; -- rsp_xbar_demux_010:src0_endofpacket -> rsp_xbar_mux_002:sink0_endofpacket
+ signal rsp_xbar_demux_010_src0_valid : std_logic; -- rsp_xbar_demux_010:src0_valid -> rsp_xbar_mux_002:sink0_valid
+ signal rsp_xbar_demux_010_src0_startofpacket : std_logic; -- rsp_xbar_demux_010:src0_startofpacket -> rsp_xbar_mux_002:sink0_startofpacket
+ signal rsp_xbar_demux_010_src0_data : std_logic_vector(68 downto 0); -- rsp_xbar_demux_010:src0_data -> rsp_xbar_mux_002:sink0_data
+ signal rsp_xbar_demux_010_src0_channel : std_logic_vector(6 downto 0); -- rsp_xbar_demux_010:src0_channel -> rsp_xbar_mux_002:sink0_channel
+ signal rsp_xbar_demux_010_src0_ready : std_logic; -- rsp_xbar_mux_002:sink0_ready -> rsp_xbar_demux_010:src0_ready
+ signal rsp_xbar_demux_011_src0_endofpacket : std_logic; -- rsp_xbar_demux_011:src0_endofpacket -> rsp_xbar_mux_002:sink1_endofpacket
+ signal rsp_xbar_demux_011_src0_valid : std_logic; -- rsp_xbar_demux_011:src0_valid -> rsp_xbar_mux_002:sink1_valid
+ signal rsp_xbar_demux_011_src0_startofpacket : std_logic; -- rsp_xbar_demux_011:src0_startofpacket -> rsp_xbar_mux_002:sink1_startofpacket
+ signal rsp_xbar_demux_011_src0_data : std_logic_vector(68 downto 0); -- rsp_xbar_demux_011:src0_data -> rsp_xbar_mux_002:sink1_data
+ signal rsp_xbar_demux_011_src0_channel : std_logic_vector(6 downto 0); -- rsp_xbar_demux_011:src0_channel -> rsp_xbar_mux_002:sink1_channel
+ signal rsp_xbar_demux_011_src0_ready : std_logic; -- rsp_xbar_mux_002:sink1_ready -> rsp_xbar_demux_011:src0_ready
+ signal rsp_xbar_demux_012_src0_endofpacket : std_logic; -- rsp_xbar_demux_012:src0_endofpacket -> rsp_xbar_mux_002:sink2_endofpacket
+ signal rsp_xbar_demux_012_src0_valid : std_logic; -- rsp_xbar_demux_012:src0_valid -> rsp_xbar_mux_002:sink2_valid
+ signal rsp_xbar_demux_012_src0_startofpacket : std_logic; -- rsp_xbar_demux_012:src0_startofpacket -> rsp_xbar_mux_002:sink2_startofpacket
+ signal rsp_xbar_demux_012_src0_data : std_logic_vector(68 downto 0); -- rsp_xbar_demux_012:src0_data -> rsp_xbar_mux_002:sink2_data
+ signal rsp_xbar_demux_012_src0_channel : std_logic_vector(6 downto 0); -- rsp_xbar_demux_012:src0_channel -> rsp_xbar_mux_002:sink2_channel
+ signal rsp_xbar_demux_012_src0_ready : std_logic; -- rsp_xbar_mux_002:sink2_ready -> rsp_xbar_demux_012:src0_ready
+ signal rsp_xbar_demux_013_src0_endofpacket : std_logic; -- rsp_xbar_demux_013:src0_endofpacket -> rsp_xbar_mux_002:sink3_endofpacket
+ signal rsp_xbar_demux_013_src0_valid : std_logic; -- rsp_xbar_demux_013:src0_valid -> rsp_xbar_mux_002:sink3_valid
+ signal rsp_xbar_demux_013_src0_startofpacket : std_logic; -- rsp_xbar_demux_013:src0_startofpacket -> rsp_xbar_mux_002:sink3_startofpacket
+ signal rsp_xbar_demux_013_src0_data : std_logic_vector(68 downto 0); -- rsp_xbar_demux_013:src0_data -> rsp_xbar_mux_002:sink3_data
+ signal rsp_xbar_demux_013_src0_channel : std_logic_vector(6 downto 0); -- rsp_xbar_demux_013:src0_channel -> rsp_xbar_mux_002:sink3_channel
+ signal rsp_xbar_demux_013_src0_ready : std_logic; -- rsp_xbar_mux_002:sink3_ready -> rsp_xbar_demux_013:src0_ready
+ signal rsp_xbar_demux_014_src0_endofpacket : std_logic; -- rsp_xbar_demux_014:src0_endofpacket -> rsp_xbar_mux_002:sink4_endofpacket
+ signal rsp_xbar_demux_014_src0_valid : std_logic; -- rsp_xbar_demux_014:src0_valid -> rsp_xbar_mux_002:sink4_valid
+ signal rsp_xbar_demux_014_src0_startofpacket : std_logic; -- rsp_xbar_demux_014:src0_startofpacket -> rsp_xbar_mux_002:sink4_startofpacket
+ signal rsp_xbar_demux_014_src0_data : std_logic_vector(68 downto 0); -- rsp_xbar_demux_014:src0_data -> rsp_xbar_mux_002:sink4_data
+ signal rsp_xbar_demux_014_src0_channel : std_logic_vector(6 downto 0); -- rsp_xbar_demux_014:src0_channel -> rsp_xbar_mux_002:sink4_channel
+ signal rsp_xbar_demux_014_src0_ready : std_logic; -- rsp_xbar_mux_002:sink4_ready -> rsp_xbar_demux_014:src0_ready
+ signal rsp_xbar_demux_015_src0_endofpacket : std_logic; -- rsp_xbar_demux_015:src0_endofpacket -> rsp_xbar_mux_002:sink5_endofpacket
+ signal rsp_xbar_demux_015_src0_valid : std_logic; -- rsp_xbar_demux_015:src0_valid -> rsp_xbar_mux_002:sink5_valid
+ signal rsp_xbar_demux_015_src0_startofpacket : std_logic; -- rsp_xbar_demux_015:src0_startofpacket -> rsp_xbar_mux_002:sink5_startofpacket
+ signal rsp_xbar_demux_015_src0_data : std_logic_vector(68 downto 0); -- rsp_xbar_demux_015:src0_data -> rsp_xbar_mux_002:sink5_data
+ signal rsp_xbar_demux_015_src0_channel : std_logic_vector(6 downto 0); -- rsp_xbar_demux_015:src0_channel -> rsp_xbar_mux_002:sink5_channel
+ signal rsp_xbar_demux_015_src0_ready : std_logic; -- rsp_xbar_mux_002:sink5_ready -> rsp_xbar_demux_015:src0_ready
+ signal rsp_xbar_demux_016_src0_endofpacket : std_logic; -- rsp_xbar_demux_016:src0_endofpacket -> rsp_xbar_mux_002:sink6_endofpacket
+ signal rsp_xbar_demux_016_src0_valid : std_logic; -- rsp_xbar_demux_016:src0_valid -> rsp_xbar_mux_002:sink6_valid
+ signal rsp_xbar_demux_016_src0_startofpacket : std_logic; -- rsp_xbar_demux_016:src0_startofpacket -> rsp_xbar_mux_002:sink6_startofpacket
+ signal rsp_xbar_demux_016_src0_data : std_logic_vector(68 downto 0); -- rsp_xbar_demux_016:src0_data -> rsp_xbar_mux_002:sink6_data
+ signal rsp_xbar_demux_016_src0_channel : std_logic_vector(6 downto 0); -- rsp_xbar_demux_016:src0_channel -> rsp_xbar_mux_002:sink6_channel
+ signal rsp_xbar_demux_016_src0_ready : std_logic; -- rsp_xbar_mux_002:sink6_ready -> rsp_xbar_demux_016:src0_ready
+ signal limiter_002_cmd_src_endofpacket : std_logic; -- limiter_002:cmd_src_endofpacket -> cmd_xbar_demux_002:sink_endofpacket
+ signal limiter_002_cmd_src_startofpacket : std_logic; -- limiter_002:cmd_src_startofpacket -> cmd_xbar_demux_002:sink_startofpacket
+ signal limiter_002_cmd_src_data : std_logic_vector(68 downto 0); -- limiter_002:cmd_src_data -> cmd_xbar_demux_002:sink_data
+ signal limiter_002_cmd_src_channel : std_logic_vector(6 downto 0); -- limiter_002:cmd_src_channel -> cmd_xbar_demux_002:sink_channel
+ signal limiter_002_cmd_src_ready : std_logic; -- cmd_xbar_demux_002:sink_ready -> limiter_002:cmd_src_ready
+ signal rsp_xbar_mux_002_src_endofpacket : std_logic; -- rsp_xbar_mux_002:src_endofpacket -> limiter_002:rsp_sink_endofpacket
+ signal rsp_xbar_mux_002_src_valid : std_logic; -- rsp_xbar_mux_002:src_valid -> limiter_002:rsp_sink_valid
+ signal rsp_xbar_mux_002_src_startofpacket : std_logic; -- rsp_xbar_mux_002:src_startofpacket -> limiter_002:rsp_sink_startofpacket
+ signal rsp_xbar_mux_002_src_data : std_logic_vector(68 downto 0); -- rsp_xbar_mux_002:src_data -> limiter_002:rsp_sink_data
+ signal rsp_xbar_mux_002_src_channel : std_logic_vector(6 downto 0); -- rsp_xbar_mux_002:src_channel -> limiter_002:rsp_sink_channel
+ signal rsp_xbar_mux_002_src_ready : std_logic; -- limiter_002:rsp_sink_ready -> rsp_xbar_mux_002:src_ready
+ signal cmd_xbar_demux_002_src0_ready : std_logic; -- rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src0_ready
+ signal id_router_010_src_endofpacket : std_logic; -- id_router_010:src_endofpacket -> rsp_xbar_demux_010:sink_endofpacket
+ signal id_router_010_src_valid : std_logic; -- id_router_010:src_valid -> rsp_xbar_demux_010:sink_valid
+ signal id_router_010_src_startofpacket : std_logic; -- id_router_010:src_startofpacket -> rsp_xbar_demux_010:sink_startofpacket
+ signal id_router_010_src_data : std_logic_vector(68 downto 0); -- id_router_010:src_data -> rsp_xbar_demux_010:sink_data
+ signal id_router_010_src_channel : std_logic_vector(6 downto 0); -- id_router_010:src_channel -> rsp_xbar_demux_010:sink_channel
+ signal id_router_010_src_ready : std_logic; -- rsp_xbar_demux_010:sink_ready -> id_router_010:src_ready
+ signal cmd_xbar_demux_002_src1_ready : std_logic; -- rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src1_ready
+ signal id_router_011_src_endofpacket : std_logic; -- id_router_011:src_endofpacket -> rsp_xbar_demux_011:sink_endofpacket
+ signal id_router_011_src_valid : std_logic; -- id_router_011:src_valid -> rsp_xbar_demux_011:sink_valid
+ signal id_router_011_src_startofpacket : std_logic; -- id_router_011:src_startofpacket -> rsp_xbar_demux_011:sink_startofpacket
+ signal id_router_011_src_data : std_logic_vector(68 downto 0); -- id_router_011:src_data -> rsp_xbar_demux_011:sink_data
+ signal id_router_011_src_channel : std_logic_vector(6 downto 0); -- id_router_011:src_channel -> rsp_xbar_demux_011:sink_channel
+ signal id_router_011_src_ready : std_logic; -- rsp_xbar_demux_011:sink_ready -> id_router_011:src_ready
+ signal cmd_xbar_demux_002_src2_ready : std_logic; -- rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src2_ready
+ signal id_router_012_src_endofpacket : std_logic; -- id_router_012:src_endofpacket -> rsp_xbar_demux_012:sink_endofpacket
+ signal id_router_012_src_valid : std_logic; -- id_router_012:src_valid -> rsp_xbar_demux_012:sink_valid
+ signal id_router_012_src_startofpacket : std_logic; -- id_router_012:src_startofpacket -> rsp_xbar_demux_012:sink_startofpacket
+ signal id_router_012_src_data : std_logic_vector(68 downto 0); -- id_router_012:src_data -> rsp_xbar_demux_012:sink_data
+ signal id_router_012_src_channel : std_logic_vector(6 downto 0); -- id_router_012:src_channel -> rsp_xbar_demux_012:sink_channel
+ signal id_router_012_src_ready : std_logic; -- rsp_xbar_demux_012:sink_ready -> id_router_012:src_ready
+ signal cmd_xbar_demux_002_src3_ready : std_logic; -- rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src3_ready
+ signal id_router_013_src_endofpacket : std_logic; -- id_router_013:src_endofpacket -> rsp_xbar_demux_013:sink_endofpacket
+ signal id_router_013_src_valid : std_logic; -- id_router_013:src_valid -> rsp_xbar_demux_013:sink_valid
+ signal id_router_013_src_startofpacket : std_logic; -- id_router_013:src_startofpacket -> rsp_xbar_demux_013:sink_startofpacket
+ signal id_router_013_src_data : std_logic_vector(68 downto 0); -- id_router_013:src_data -> rsp_xbar_demux_013:sink_data
+ signal id_router_013_src_channel : std_logic_vector(6 downto 0); -- id_router_013:src_channel -> rsp_xbar_demux_013:sink_channel
+ signal id_router_013_src_ready : std_logic; -- rsp_xbar_demux_013:sink_ready -> id_router_013:src_ready
+ signal cmd_xbar_demux_002_src4_ready : std_logic; -- rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src4_ready
+ signal id_router_014_src_endofpacket : std_logic; -- id_router_014:src_endofpacket -> rsp_xbar_demux_014:sink_endofpacket
+ signal id_router_014_src_valid : std_logic; -- id_router_014:src_valid -> rsp_xbar_demux_014:sink_valid
+ signal id_router_014_src_startofpacket : std_logic; -- id_router_014:src_startofpacket -> rsp_xbar_demux_014:sink_startofpacket
+ signal id_router_014_src_data : std_logic_vector(68 downto 0); -- id_router_014:src_data -> rsp_xbar_demux_014:sink_data
+ signal id_router_014_src_channel : std_logic_vector(6 downto 0); -- id_router_014:src_channel -> rsp_xbar_demux_014:sink_channel
+ signal id_router_014_src_ready : std_logic; -- rsp_xbar_demux_014:sink_ready -> id_router_014:src_ready
+ signal cmd_xbar_demux_002_src5_ready : std_logic; -- rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src5_ready
+ signal id_router_015_src_endofpacket : std_logic; -- id_router_015:src_endofpacket -> rsp_xbar_demux_015:sink_endofpacket
+ signal id_router_015_src_valid : std_logic; -- id_router_015:src_valid -> rsp_xbar_demux_015:sink_valid
+ signal id_router_015_src_startofpacket : std_logic; -- id_router_015:src_startofpacket -> rsp_xbar_demux_015:sink_startofpacket
+ signal id_router_015_src_data : std_logic_vector(68 downto 0); -- id_router_015:src_data -> rsp_xbar_demux_015:sink_data
+ signal id_router_015_src_channel : std_logic_vector(6 downto 0); -- id_router_015:src_channel -> rsp_xbar_demux_015:sink_channel
+ signal id_router_015_src_ready : std_logic; -- rsp_xbar_demux_015:sink_ready -> id_router_015:src_ready
+ signal cmd_xbar_demux_002_src6_ready : std_logic; -- rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src6_ready
+ signal id_router_016_src_endofpacket : std_logic; -- id_router_016:src_endofpacket -> rsp_xbar_demux_016:sink_endofpacket
+ signal id_router_016_src_valid : std_logic; -- id_router_016:src_valid -> rsp_xbar_demux_016:sink_valid
+ signal id_router_016_src_startofpacket : std_logic; -- id_router_016:src_startofpacket -> rsp_xbar_demux_016:sink_startofpacket
+ signal id_router_016_src_data : std_logic_vector(68 downto 0); -- id_router_016:src_data -> rsp_xbar_demux_016:sink_data
+ signal id_router_016_src_channel : std_logic_vector(6 downto 0); -- id_router_016:src_channel -> rsp_xbar_demux_016:sink_channel
+ signal id_router_016_src_ready : std_logic; -- rsp_xbar_demux_016:sink_ready -> id_router_016:src_ready
+ signal crosser_out_endofpacket : std_logic; -- crosser:out_endofpacket -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ signal crosser_out_valid : std_logic; -- crosser:out_valid -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:cp_valid
+ signal crosser_out_startofpacket : std_logic; -- crosser:out_startofpacket -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ signal crosser_out_data : std_logic_vector(65 downto 0); -- crosser:out_data -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:cp_data
+ signal crosser_out_channel : std_logic_vector(1 downto 0); -- crosser:out_channel -> tx_bridge_s0_translator_avalon_universal_slave_0_agent:cp_channel
+ signal cmd_xbar_demux_src0_endofpacket : std_logic; -- cmd_xbar_demux:src0_endofpacket -> crosser:in_endofpacket
+ signal cmd_xbar_demux_src0_valid : std_logic; -- cmd_xbar_demux:src0_valid -> crosser:in_valid
+ signal cmd_xbar_demux_src0_startofpacket : std_logic; -- cmd_xbar_demux:src0_startofpacket -> crosser:in_startofpacket
+ signal cmd_xbar_demux_src0_data : std_logic_vector(65 downto 0); -- cmd_xbar_demux:src0_data -> crosser:in_data
+ signal cmd_xbar_demux_src0_channel : std_logic_vector(1 downto 0); -- cmd_xbar_demux:src0_channel -> crosser:in_channel
+ signal cmd_xbar_demux_src0_ready : std_logic; -- crosser:in_ready -> cmd_xbar_demux:src0_ready
+ signal crosser_001_out_endofpacket : std_logic; -- crosser_001:out_endofpacket -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:cp_endofpacket
+ signal crosser_001_out_valid : std_logic; -- crosser_001:out_valid -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:cp_valid
+ signal crosser_001_out_startofpacket : std_logic; -- crosser_001:out_startofpacket -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:cp_startofpacket
+ signal crosser_001_out_data : std_logic_vector(65 downto 0); -- crosser_001:out_data -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:cp_data
+ signal crosser_001_out_channel : std_logic_vector(1 downto 0); -- crosser_001:out_channel -> rx_bridge_s0_translator_avalon_universal_slave_0_agent:cp_channel
+ signal cmd_xbar_demux_src1_endofpacket : std_logic; -- cmd_xbar_demux:src1_endofpacket -> crosser_001:in_endofpacket
+ signal cmd_xbar_demux_src1_valid : std_logic; -- cmd_xbar_demux:src1_valid -> crosser_001:in_valid
+ signal cmd_xbar_demux_src1_startofpacket : std_logic; -- cmd_xbar_demux:src1_startofpacket -> crosser_001:in_startofpacket
+ signal cmd_xbar_demux_src1_data : std_logic_vector(65 downto 0); -- cmd_xbar_demux:src1_data -> crosser_001:in_data
+ signal cmd_xbar_demux_src1_channel : std_logic_vector(1 downto 0); -- cmd_xbar_demux:src1_channel -> crosser_001:in_channel
+ signal cmd_xbar_demux_src1_ready : std_logic; -- crosser_001:in_ready -> cmd_xbar_demux:src1_ready
+ signal crosser_002_out_endofpacket : std_logic; -- crosser_002:out_endofpacket -> rsp_xbar_mux:sink0_endofpacket
+ signal crosser_002_out_valid : std_logic; -- crosser_002:out_valid -> rsp_xbar_mux:sink0_valid
+ signal crosser_002_out_startofpacket : std_logic; -- crosser_002:out_startofpacket -> rsp_xbar_mux:sink0_startofpacket
+ signal crosser_002_out_data : std_logic_vector(65 downto 0); -- crosser_002:out_data -> rsp_xbar_mux:sink0_data
+ signal crosser_002_out_channel : std_logic_vector(1 downto 0); -- crosser_002:out_channel -> rsp_xbar_mux:sink0_channel
+ signal crosser_002_out_ready : std_logic; -- rsp_xbar_mux:sink0_ready -> crosser_002:out_ready
+ signal rsp_xbar_demux_src0_endofpacket : std_logic; -- rsp_xbar_demux:src0_endofpacket -> crosser_002:in_endofpacket
+ signal rsp_xbar_demux_src0_valid : std_logic; -- rsp_xbar_demux:src0_valid -> crosser_002:in_valid
+ signal rsp_xbar_demux_src0_startofpacket : std_logic; -- rsp_xbar_demux:src0_startofpacket -> crosser_002:in_startofpacket
+ signal rsp_xbar_demux_src0_data : std_logic_vector(65 downto 0); -- rsp_xbar_demux:src0_data -> crosser_002:in_data
+ signal rsp_xbar_demux_src0_channel : std_logic_vector(1 downto 0); -- rsp_xbar_demux:src0_channel -> crosser_002:in_channel
+ signal rsp_xbar_demux_src0_ready : std_logic; -- crosser_002:in_ready -> rsp_xbar_demux:src0_ready
+ signal crosser_003_out_endofpacket : std_logic; -- crosser_003:out_endofpacket -> rsp_xbar_mux:sink1_endofpacket
+ signal crosser_003_out_valid : std_logic; -- crosser_003:out_valid -> rsp_xbar_mux:sink1_valid
+ signal crosser_003_out_startofpacket : std_logic; -- crosser_003:out_startofpacket -> rsp_xbar_mux:sink1_startofpacket
+ signal crosser_003_out_data : std_logic_vector(65 downto 0); -- crosser_003:out_data -> rsp_xbar_mux:sink1_data
+ signal crosser_003_out_channel : std_logic_vector(1 downto 0); -- crosser_003:out_channel -> rsp_xbar_mux:sink1_channel
+ signal crosser_003_out_ready : std_logic; -- rsp_xbar_mux:sink1_ready -> crosser_003:out_ready
+ signal rsp_xbar_demux_001_src0_endofpacket : std_logic; -- rsp_xbar_demux_001:src0_endofpacket -> crosser_003:in_endofpacket
+ signal rsp_xbar_demux_001_src0_valid : std_logic; -- rsp_xbar_demux_001:src0_valid -> crosser_003:in_valid
+ signal rsp_xbar_demux_001_src0_startofpacket : std_logic; -- rsp_xbar_demux_001:src0_startofpacket -> crosser_003:in_startofpacket
+ signal rsp_xbar_demux_001_src0_data : std_logic_vector(65 downto 0); -- rsp_xbar_demux_001:src0_data -> crosser_003:in_data
+ signal rsp_xbar_demux_001_src0_channel : std_logic_vector(1 downto 0); -- rsp_xbar_demux_001:src0_channel -> crosser_003:in_channel
+ signal rsp_xbar_demux_001_src0_ready : std_logic; -- crosser_003:in_ready -> rsp_xbar_demux_001:src0_ready
+ signal limiter_cmd_valid_data : std_logic_vector(1 downto 0); -- limiter:cmd_src_valid -> cmd_xbar_demux:sink_valid
+ signal limiter_001_cmd_valid_data : std_logic_vector(7 downto 0); -- limiter_001:cmd_src_valid -> cmd_xbar_demux_001:sink_valid
+ signal limiter_002_cmd_valid_data : std_logic_vector(6 downto 0); -- limiter_002:cmd_src_valid -> cmd_xbar_demux_002:sink_valid
+ signal rx_reset_reset_n_ports_inv : std_logic; -- rx_reset_reset_n:inv -> rst_controller_002:reset_in0
+ signal csr_reset_reset_n_ports_inv : std_logic; -- csr_reset_reset_n:inv -> rst_controller:reset_in0
+ signal tx_reset_reset_n_ports_inv : std_logic; -- tx_reset_reset_n:inv -> rst_controller_001:reset_in0
+ signal rst_controller_001_reset_out_reset_ports_inv : std_logic; -- rst_controller_001_reset_out_reset:inv -> [rxtx_dc_fifo_link_fault_status:out_reset_n, rxtx_dc_fifo_pauselen:out_reset_n, rxtx_timing_adapter_link_fault_status_tx:reset_n, rxtx_timing_adapter_pauselen_tx:reset_n, tx_st_error_adapter_stat:reset_n, tx_st_mux_flow_control_user_frame:reset_n, tx_st_pause_ctrl_error_adapter:reset_n, tx_st_timing_adapter_frame_decoder:reset_n, tx_st_timing_adapter_splitter_status_in:reset_n, tx_st_timing_adapter_splitter_status_output:reset_n, tx_st_timing_adapter_splitter_status_statistics:reset_n]
+ signal rst_controller_002_reset_out_reset_ports_inv : std_logic; -- rst_controller_002_reset_out_reset:inv -> [rx_st_error_adapter_stat:reset_n, rx_st_status_output_delay:reset_n, rx_st_status_statistics_delay:reset_n, rx_st_timing_adapter_frame_status_in:reset_n, rx_st_timing_adapter_interface_conversion:reset_n, rx_st_timing_adapter_lane_decoder:reset_n, rx_st_timing_adapter_link_fault_detection:reset_n, rx_st_timing_adapter_splitter_status_in:reset_n, rx_st_timing_adapter_splitter_status_output:reset_n, rx_st_timing_adapter_splitter_status_statistics:reset_n, rx_timing_adapter_frame_status_out_crc_checker:reset_n, rx_timing_adapter_frame_status_out_frame_decoder:reset_n, rxtx_dc_fifo_link_fault_status:in_reset_n, rxtx_dc_fifo_pauselen:in_reset_n, rxtx_timing_adapter_pauselen_rx:reset_n, txrx_timing_adapter_link_fault_status_export:reset_n, txrx_timing_adapter_link_fault_status_rx:reset_n]
+
+begin
+
+ merlin_master_translator : component altera_merlin_master_translator_0001
+ port map (
+ clk => csr_clk_clk, -- clk.clk
+ reset => rst_controller_reset_out_reset, -- reset.reset
+ uav_address => merlin_master_translator_avalon_universal_master_0_address, -- avalon_universal_master_0.address
+ uav_burstcount => merlin_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
+ uav_read => merlin_master_translator_avalon_universal_master_0_read, -- .read
+ uav_write => merlin_master_translator_avalon_universal_master_0_write, -- .write
+ uav_waitrequest => merlin_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
+ uav_readdatavalid => merlin_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
+ uav_byteenable => merlin_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
+ uav_readdata => merlin_master_translator_avalon_universal_master_0_readdata, -- .readdata
+ uav_writedata => merlin_master_translator_avalon_universal_master_0_writedata, -- .writedata
+ uav_lock => merlin_master_translator_avalon_universal_master_0_lock, -- .lock
+ uav_debugaccess => merlin_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
+ av_address => csr_address, -- avalon_anti_master_0.address
+ av_waitrequest => csr_waitrequest, -- .waitrequest
+ av_read => csr_read, -- .read
+ av_readdata => csr_readdata, -- .readdata
+ av_write => csr_write, -- .write
+ av_writedata => csr_writedata -- .writedata
+ );
+
+ tx_bridge : component altera_avalon_mm_bridge_0001
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- reset.reset
+ s0_waitrequest => tx_bridge_s0_translator_avalon_anti_slave_0_waitrequest, -- s0.waitrequest
+ s0_readdata => tx_bridge_s0_translator_avalon_anti_slave_0_readdata, -- .readdata
+ s0_readdatavalid => tx_bridge_s0_translator_avalon_anti_slave_0_readdatavalid, -- .readdatavalid
+ s0_burstcount(0) => tx_bridge_s0_translator_avalon_anti_slave_0_burstcount, -- .burstcount
+ s0_writedata => tx_bridge_s0_translator_avalon_anti_slave_0_writedata, -- .writedata
+ s0_address => tx_bridge_s0_translator_avalon_anti_slave_0_address, -- .address
+ s0_write => tx_bridge_s0_translator_avalon_anti_slave_0_write, -- .write
+ s0_read => tx_bridge_s0_translator_avalon_anti_slave_0_read, -- .read
+ s0_byteenable => tx_bridge_s0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
+ s0_debugaccess => tx_bridge_s0_translator_avalon_anti_slave_0_debugaccess, -- .debugaccess
+ m0_waitrequest => tx_bridge_m0_waitrequest, -- m0.waitrequest
+ m0_readdata => tx_bridge_m0_readdata, -- .readdata
+ m0_readdatavalid => tx_bridge_m0_readdatavalid, -- .readdatavalid
+ m0_burstcount => tx_bridge_m0_burstcount, -- .burstcount
+ m0_writedata => tx_bridge_m0_writedata, -- .writedata
+ m0_address => tx_bridge_m0_address, -- .address
+ m0_write => tx_bridge_m0_write, -- .write
+ m0_read => tx_bridge_m0_read, -- .read
+ m0_byteenable => tx_bridge_m0_byteenable, -- .byteenable
+ m0_debugaccess => tx_bridge_m0_debugaccess -- .debugaccess
+ );
+
+ tx_eth_packet_underflow_control : component altera_eth_packet_underflow_control
+ generic map (
+ BITSPERSYMBOL => 8,
+ SYMBOLSPERBEAT => 8,
+ ERROR_WIDTH => 1
+ )
+ port map (
+ clk => tx_clk_clk, -- clock_reset.clk
+ reset => rst_controller_001_reset_out_reset, -- clock_reset_reset.reset
+ csr_readdata => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- avalon_slave_0.readdata
+ csr_read => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
+ csr_address => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_anti_slave_0_address, -- .address
+ data_sink_sop => avalon_st_tx_startofpacket, -- avalon_streaming_sink.startofpacket
+ data_sink_valid => avalon_st_tx_valid, -- .valid
+ data_sink_data => avalon_st_tx_data, -- .data
+ data_sink_empty => avalon_st_tx_empty, -- .empty
+ data_sink_ready => avalon_st_tx_ready, -- .ready
+ data_sink_error => avalon_st_tx_error, -- .error
+ data_sink_eop => avalon_st_tx_endofpacket, -- .endofpacket
+ data_src_sop => tx_eth_packet_underflow_control_avalon_streaming_source_startofpacket, -- avalon_streaming_source.startofpacket
+ data_src_eop => tx_eth_packet_underflow_control_avalon_streaming_source_endofpacket, -- .endofpacket
+ data_src_valid => tx_eth_packet_underflow_control_avalon_streaming_source_valid, -- .valid
+ data_src_data => tx_eth_packet_underflow_control_avalon_streaming_source_data, -- .data
+ data_src_empty => tx_eth_packet_underflow_control_avalon_streaming_source_empty, -- .empty
+ data_src_ready => tx_eth_packet_underflow_control_avalon_streaming_source_ready, -- .ready
+ data_src_error => tx_eth_packet_underflow_control_avalon_streaming_source_error -- .error
+ );
+
+ tx_eth_pad_inserter : component altera_eth_pad_inserter
+ generic map (
+ SYMBOLSPERBEAT => 8,
+ ERROR_WIDTH => 2
+ )
+ port map (
+ clk => tx_clk_clk, -- clock_reset.clk
+ reset => rst_controller_001_reset_out_reset, -- clock_reset_reset.reset
+ csr_write => tx_eth_pad_inserter_csr_translator_avalon_anti_slave_0_write, -- csr.write
+ csr_read => tx_eth_pad_inserter_csr_translator_avalon_anti_slave_0_read, -- .read
+ csr_address(0) => tx_eth_pad_inserter_csr_translator_avalon_anti_slave_0_address, -- .address
+ csr_writedata => tx_eth_pad_inserter_csr_translator_avalon_anti_slave_0_writedata, -- .writedata
+ csr_readdata => tx_eth_pad_inserter_csr_translator_avalon_anti_slave_0_readdata, -- .readdata
+ data_src_sop => tx_eth_pad_inserter_avalon_st_source_data_startofpacket, -- avalon_st_source_data.startofpacket
+ data_src_eop => tx_eth_pad_inserter_avalon_st_source_data_endofpacket, -- .endofpacket
+ data_src_valid => tx_eth_pad_inserter_avalon_st_source_data_valid, -- .valid
+ data_src_ready => tx_eth_pad_inserter_avalon_st_source_data_ready, -- .ready
+ data_src_data => tx_eth_pad_inserter_avalon_st_source_data_data, -- .data
+ data_src_empty => tx_eth_pad_inserter_avalon_st_source_data_empty, -- .empty
+ data_src_error => tx_eth_pad_inserter_avalon_st_source_data_error, -- .error
+ data_sink_sop => tx_eth_packet_underflow_control_avalon_streaming_source_startofpacket, -- avalon_st_sink_data.startofpacket
+ data_sink_eop => tx_eth_packet_underflow_control_avalon_streaming_source_endofpacket, -- .endofpacket
+ data_sink_valid => tx_eth_packet_underflow_control_avalon_streaming_source_valid, -- .valid
+ data_sink_ready => tx_eth_packet_underflow_control_avalon_streaming_source_ready, -- .ready
+ data_sink_data => tx_eth_packet_underflow_control_avalon_streaming_source_data, -- .data
+ data_sink_empty => tx_eth_packet_underflow_control_avalon_streaming_source_empty, -- .empty
+ data_sink_error => tx_eth_packet_underflow_control_avalon_streaming_source_error -- .error
+ );
+
+ tx_eth_pkt_backpressure_control : component ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control
+ generic map (
+ BITSPERSYMBOL => 8,
+ SYMBOLSPERBEAT => 8,
+ ERROR_WIDTH => 2,
+ USE_READY => 1
+ )
+ port map (
+ clk => tx_clk_clk, -- clock_reset.clk
+ reset => rst_controller_001_reset_out_reset, -- clock_reset_reset.reset
+ csr_write => tx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_write, -- csr.write
+ csr_read => tx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_read, -- .read
+ csr_address(0) => tx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_address, -- .address
+ csr_writedata => tx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_writedata, -- .writedata
+ csr_readdata => tx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_readdata, -- .readdata
+ data_src_sop => tx_eth_pkt_backpressure_control_avalon_st_source_data_startofpacket, -- avalon_st_source_data.startofpacket
+ data_src_eop => tx_eth_pkt_backpressure_control_avalon_st_source_data_endofpacket, -- .endofpacket
+ data_src_valid => tx_eth_pkt_backpressure_control_avalon_st_source_data_valid, -- .valid
+ data_src_ready => tx_eth_pkt_backpressure_control_avalon_st_source_data_ready, -- .ready
+ data_src_data => tx_eth_pkt_backpressure_control_avalon_st_source_data_data, -- .data
+ data_src_empty => tx_eth_pkt_backpressure_control_avalon_st_source_data_empty, -- .empty
+ data_src_error => tx_eth_pkt_backpressure_control_avalon_st_source_data_error, -- .error
+ data_sink_sop => tx_eth_pad_inserter_avalon_st_source_data_startofpacket, -- avalon_st_sink_data.startofpacket
+ data_sink_eop => tx_eth_pad_inserter_avalon_st_source_data_endofpacket, -- .endofpacket
+ data_sink_valid => tx_eth_pad_inserter_avalon_st_source_data_valid, -- .valid
+ data_sink_ready => tx_eth_pad_inserter_avalon_st_source_data_ready, -- .ready
+ data_sink_data => tx_eth_pad_inserter_avalon_st_source_data_data, -- .data
+ data_sink_empty => tx_eth_pad_inserter_avalon_st_source_data_empty, -- .empty
+ data_sink_error => tx_eth_pad_inserter_avalon_st_source_data_error, -- .error
+ pausebeats_sink_valid => tx_eth_pause_beat_conversion_pause_beat_src_valid, -- avalon_st_pause.valid
+ pausebeats_sink_data => tx_eth_pause_beat_conversion_pause_beat_src_data -- .data
+ );
+
+ tx_eth_pause_beat_conversion : component altera_eth_pause_beat_conversion
+ port map (
+ clk => tx_clk_clk, -- clock_reset.clk
+ reset => rst_controller_001_reset_out_reset, -- clock_reset_reset.reset
+ pause_quanta_sink_valid => rxtx_timing_adapter_pauselen_tx_out_valid, -- pause_quanta_sink.valid
+ pause_quanta_sink_data => rxtx_timing_adapter_pauselen_tx_out_data, -- .data
+ pause_beat_src_valid => tx_eth_pause_beat_conversion_pause_beat_src_valid, -- pause_beat_src.valid
+ pause_beat_src_data => tx_eth_pause_beat_conversion_pause_beat_src_data -- .data
+ );
+
+ tx_eth_pause_ctrl_gen : component altera_eth_pause_ctrl_gen
+ generic map (
+ BITSPERSYMBOL => 8,
+ SYMBOLSPERBEAT => 8,
+ ERROR_WIDTH => 1
+ )
+ port map (
+ clk => tx_clk_clk, -- clock_reset.clk
+ reset => rst_controller_001_reset_out_reset, -- clock_reset_reset.reset
+ csr_address => tx_eth_pause_ctrl_gen_csr_translator_avalon_anti_slave_0_address, -- csr.address
+ csr_read => tx_eth_pause_ctrl_gen_csr_translator_avalon_anti_slave_0_read, -- .read
+ csr_readdata => tx_eth_pause_ctrl_gen_csr_translator_avalon_anti_slave_0_readdata, -- .readdata
+ csr_write => tx_eth_pause_ctrl_gen_csr_translator_avalon_anti_slave_0_write, -- .write
+ csr_writedata => tx_eth_pause_ctrl_gen_csr_translator_avalon_anti_slave_0_writedata, -- .writedata
+ pause_ctrl_sink_data => avalon_st_pause_data, -- pause_control.data
+ pause_source_sop => tx_eth_pause_ctrl_gen_pause_packet_startofpacket, -- pause_packet.startofpacket
+ pause_source_eop => tx_eth_pause_ctrl_gen_pause_packet_endofpacket, -- .endofpacket
+ pause_source_valid => tx_eth_pause_ctrl_gen_pause_packet_valid, -- .valid
+ pause_source_data => tx_eth_pause_ctrl_gen_pause_packet_data, -- .data
+ pause_source_empty => tx_eth_pause_ctrl_gen_pause_packet_empty, -- .empty
+ pause_source_error => tx_eth_pause_ctrl_gen_pause_packet_error, -- .error
+ pause_source_ready => tx_eth_pause_ctrl_gen_pause_packet_ready -- .ready
+ );
+
+ tx_st_pause_ctrl_error_adapter : component error_adapter_0001
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
+ in_ready => tx_eth_pause_ctrl_gen_pause_packet_ready, -- in.ready
+ in_valid => tx_eth_pause_ctrl_gen_pause_packet_valid, -- .valid
+ in_data => tx_eth_pause_ctrl_gen_pause_packet_data, -- .data
+ in_error => tx_eth_pause_ctrl_gen_pause_packet_error, -- .error
+ in_startofpacket => tx_eth_pause_ctrl_gen_pause_packet_startofpacket, -- .startofpacket
+ in_endofpacket => tx_eth_pause_ctrl_gen_pause_packet_endofpacket, -- .endofpacket
+ in_empty => tx_eth_pause_ctrl_gen_pause_packet_empty, -- .empty
+ out_ready => tx_st_pause_ctrl_error_adapter_out_ready, -- out.ready
+ out_valid => tx_st_pause_ctrl_error_adapter_out_valid, -- .valid
+ out_data => tx_st_pause_ctrl_error_adapter_out_data, -- .data
+ out_error => tx_st_pause_ctrl_error_adapter_out_error, -- .error
+ out_startofpacket => tx_st_pause_ctrl_error_adapter_out_startofpacket, -- .startofpacket
+ out_endofpacket => tx_st_pause_ctrl_error_adapter_out_endofpacket, -- .endofpacket
+ out_empty => tx_st_pause_ctrl_error_adapter_out_empty -- .empty
+ );
+
+ tx_st_mux_flow_control_user_frame : component multiplexer_0001
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
+ in0_valid => tx_eth_pkt_backpressure_control_avalon_st_source_data_valid, -- in0.valid
+ in0_ready => tx_eth_pkt_backpressure_control_avalon_st_source_data_ready, -- .ready
+ in0_data => tx_eth_pkt_backpressure_control_avalon_st_source_data_data, -- .data
+ in0_error => tx_eth_pkt_backpressure_control_avalon_st_source_data_error, -- .error
+ in0_startofpacket => tx_eth_pkt_backpressure_control_avalon_st_source_data_startofpacket, -- .startofpacket
+ in0_endofpacket => tx_eth_pkt_backpressure_control_avalon_st_source_data_endofpacket, -- .endofpacket
+ in0_empty => tx_eth_pkt_backpressure_control_avalon_st_source_data_empty, -- .empty
+ in1_valid => tx_st_pause_ctrl_error_adapter_out_valid, -- in1.valid
+ in1_ready => tx_st_pause_ctrl_error_adapter_out_ready, -- .ready
+ in1_data => tx_st_pause_ctrl_error_adapter_out_data, -- .data
+ in1_error => tx_st_pause_ctrl_error_adapter_out_error, -- .error
+ in1_startofpacket => tx_st_pause_ctrl_error_adapter_out_startofpacket, -- .startofpacket
+ in1_endofpacket => tx_st_pause_ctrl_error_adapter_out_endofpacket, -- .endofpacket
+ in1_empty => tx_st_pause_ctrl_error_adapter_out_empty, -- .empty
+ out_channel => open, -- out.channel
+ out_valid => tx_st_mux_flow_control_user_frame_out_valid, -- .valid
+ out_ready => tx_st_mux_flow_control_user_frame_out_ready, -- .ready
+ out_data => tx_st_mux_flow_control_user_frame_out_data, -- .data
+ out_error => tx_st_mux_flow_control_user_frame_out_error, -- .error
+ out_startofpacket => tx_st_mux_flow_control_user_frame_out_startofpacket, -- .startofpacket
+ out_endofpacket => tx_st_mux_flow_control_user_frame_out_endofpacket, -- .endofpacket
+ out_empty => tx_st_mux_flow_control_user_frame_out_empty -- .empty
+ );
+
+ tx_eth_address_inserter : component altera_eth_address_inserter
+ generic map (
+ BITSPERSYMBOL => 8,
+ SYMBOLSPERBEAT => 8,
+ ERROR_WIDTH => 2
+ )
+ port map (
+ clk => tx_clk_clk, -- clock_reset.clk
+ reset => rst_controller_001_reset_out_reset, -- clock_reset_reset.reset
+ csr_write => tx_eth_address_inserter_csr_translator_avalon_anti_slave_0_write, -- csr.write
+ csr_read => tx_eth_address_inserter_csr_translator_avalon_anti_slave_0_read, -- .read
+ csr_address => tx_eth_address_inserter_csr_translator_avalon_anti_slave_0_address, -- .address
+ csr_writedata => tx_eth_address_inserter_csr_translator_avalon_anti_slave_0_writedata, -- .writedata
+ csr_readdata => tx_eth_address_inserter_csr_translator_avalon_anti_slave_0_readdata, -- .readdata
+ data_sink_sop => tx_st_mux_flow_control_user_frame_out_startofpacket, -- avalon_streaming_sink.startofpacket
+ data_sink_eop => tx_st_mux_flow_control_user_frame_out_endofpacket, -- .endofpacket
+ data_sink_valid => tx_st_mux_flow_control_user_frame_out_valid, -- .valid
+ data_sink_ready => tx_st_mux_flow_control_user_frame_out_ready, -- .ready
+ data_sink_data => tx_st_mux_flow_control_user_frame_out_data, -- .data
+ data_sink_empty => tx_st_mux_flow_control_user_frame_out_empty, -- .empty
+ data_sink_error => tx_st_mux_flow_control_user_frame_out_error, -- .error
+ data_src_sop => tx_eth_address_inserter_avalon_streaming_source_startofpacket, -- avalon_streaming_source.startofpacket
+ data_src_eop => tx_eth_address_inserter_avalon_streaming_source_endofpacket, -- .endofpacket
+ data_src_valid => tx_eth_address_inserter_avalon_streaming_source_valid, -- .valid
+ data_src_ready => tx_eth_address_inserter_avalon_streaming_source_ready, -- .ready
+ data_src_data => tx_eth_address_inserter_avalon_streaming_source_data, -- .data
+ data_src_empty => tx_eth_address_inserter_avalon_streaming_source_empty, -- .empty
+ data_src_error => tx_eth_address_inserter_avalon_streaming_source_error -- .error
+ );
+
+ tx_eth_crc_inserter : component ip_stratixiv_mac_10g_tx_eth_crc_inserter
+ generic map (
+ BITSPERSYMBOL => 8,
+ SYMBOLSPERBEAT => 8,
+ ERROR_WIDTH => 2,
+ MODE_CHECKER_0_INSERTER_1 => 1
+ )
+ port map (
+ clk => tx_clk_clk, -- clock_reset.clk
+ reset => rst_controller_001_reset_out_reset, -- clock_reset_reset.reset
+ csr_write => tx_eth_crc_inserter_csr_translator_avalon_anti_slave_0_write, -- csr.write
+ csr_read => tx_eth_crc_inserter_csr_translator_avalon_anti_slave_0_read, -- .read
+ csr_address => tx_eth_crc_inserter_csr_translator_avalon_anti_slave_0_address, -- .address
+ csr_writedata => tx_eth_crc_inserter_csr_translator_avalon_anti_slave_0_writedata, -- .writedata
+ csr_readdata => tx_eth_crc_inserter_csr_translator_avalon_anti_slave_0_readdata, -- .readdata
+ data_sink_sop => tx_eth_address_inserter_avalon_streaming_source_startofpacket, -- avalon_streaming_sink.startofpacket
+ data_sink_eop => tx_eth_address_inserter_avalon_streaming_source_endofpacket, -- .endofpacket
+ data_sink_valid => tx_eth_address_inserter_avalon_streaming_source_valid, -- .valid
+ data_sink_ready => tx_eth_address_inserter_avalon_streaming_source_ready, -- .ready
+ data_sink_data => tx_eth_address_inserter_avalon_streaming_source_data, -- .data
+ data_sink_empty => tx_eth_address_inserter_avalon_streaming_source_empty, -- .empty
+ data_sink_error => tx_eth_address_inserter_avalon_streaming_source_error, -- .error
+ data_src_sop => tx_eth_crc_inserter_avalon_streaming_source_startofpacket, -- avalon_streaming_source.startofpacket
+ data_src_eop => tx_eth_crc_inserter_avalon_streaming_source_endofpacket, -- .endofpacket
+ data_src_valid => tx_eth_crc_inserter_avalon_streaming_source_valid, -- .valid
+ data_src_ready => tx_eth_crc_inserter_avalon_streaming_source_ready, -- .ready
+ data_src_data => tx_eth_crc_inserter_avalon_streaming_source_data, -- .data
+ data_src_empty => tx_eth_crc_inserter_avalon_streaming_source_empty, -- .empty
+ data_src_error => tx_eth_crc_inserter_avalon_streaming_source_error -- .error
+ );
+
+ tx_st_pipeline_stage_rs : component altera_avalon_st_pipeline_stage_0001
+ port map (
+ clk => tx_clk_clk, -- cr0.clk
+ reset => rst_controller_001_reset_out_reset, -- cr0_reset.reset
+ in_ready => tx_eth_crc_inserter_avalon_streaming_source_ready, -- sink0.ready
+ in_valid => tx_eth_crc_inserter_avalon_streaming_source_valid, -- .valid
+ in_startofpacket => tx_eth_crc_inserter_avalon_streaming_source_startofpacket, -- .startofpacket
+ in_endofpacket => tx_eth_crc_inserter_avalon_streaming_source_endofpacket, -- .endofpacket
+ in_empty => tx_eth_crc_inserter_avalon_streaming_source_empty, -- .empty
+ in_error => tx_eth_crc_inserter_avalon_streaming_source_error, -- .error
+ in_data => tx_eth_crc_inserter_avalon_streaming_source_data, -- .data
+ out_ready => tx_st_pipeline_stage_rs_source0_ready, -- source0.ready
+ out_valid => tx_st_pipeline_stage_rs_source0_valid, -- .valid
+ out_startofpacket => tx_st_pipeline_stage_rs_source0_startofpacket, -- .startofpacket
+ out_endofpacket => tx_st_pipeline_stage_rs_source0_endofpacket, -- .endofpacket
+ out_empty => tx_st_pipeline_stage_rs_source0_empty, -- .empty
+ out_error => tx_st_pipeline_stage_rs_source0_error, -- .error
+ out_data => tx_st_pipeline_stage_rs_source0_data -- .data
+ );
+
+ tx_st_splitter_1 : component altera_avalon_st_splitter_0001
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ in0_ready => tx_st_pipeline_stage_rs_source0_ready, -- in.ready
+ in0_valid => tx_st_pipeline_stage_rs_source0_valid, -- .valid
+ in0_startofpacket => tx_st_pipeline_stage_rs_source0_startofpacket, -- .startofpacket
+ in0_endofpacket => tx_st_pipeline_stage_rs_source0_endofpacket, -- .endofpacket
+ in0_empty => tx_st_pipeline_stage_rs_source0_empty, -- .empty
+ in0_error => tx_st_pipeline_stage_rs_source0_error, -- .error
+ in0_data => tx_st_pipeline_stage_rs_source0_data, -- .data
+ out0_ready => tx_st_splitter_1_out0_ready, -- out0.ready
+ out0_valid => tx_st_splitter_1_out0_valid, -- .valid
+ out0_startofpacket => tx_st_splitter_1_out0_startofpacket, -- .startofpacket
+ out0_endofpacket => tx_st_splitter_1_out0_endofpacket, -- .endofpacket
+ out0_empty => tx_st_splitter_1_out0_empty, -- .empty
+ out0_error => tx_st_splitter_1_out0_error, -- .error
+ out0_data => tx_st_splitter_1_out0_data, -- .data
+ out1_ready => tx_st_splitter_1_out1_ready, -- out1.ready
+ out1_valid => tx_st_splitter_1_out1_valid, -- .valid
+ out1_startofpacket => tx_st_splitter_1_out1_startofpacket, -- .startofpacket
+ out1_endofpacket => tx_st_splitter_1_out1_endofpacket, -- .endofpacket
+ out1_empty => tx_st_splitter_1_out1_empty, -- .empty
+ out1_error => tx_st_splitter_1_out1_error, -- .error
+ out1_data => tx_st_splitter_1_out1_data -- .data
+ );
+
+ tx_st_timing_adapter_frame_decoder : component timing_adapter_0001
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
+ in_ready => tx_st_splitter_1_out0_ready, -- in.ready
+ in_valid => tx_st_splitter_1_out0_valid, -- .valid
+ in_data => tx_st_splitter_1_out0_data, -- .data
+ in_error => tx_st_splitter_1_out0_error, -- .error
+ in_startofpacket => tx_st_splitter_1_out0_startofpacket, -- .startofpacket
+ in_endofpacket => tx_st_splitter_1_out0_endofpacket, -- .endofpacket
+ in_empty => tx_st_splitter_1_out0_empty, -- .empty
+ out_valid => tx_st_timing_adapter_frame_decoder_out_valid, -- out.valid
+ out_data => tx_st_timing_adapter_frame_decoder_out_data, -- .data
+ out_error => tx_st_timing_adapter_frame_decoder_out_error, -- .error
+ out_startofpacket => tx_st_timing_adapter_frame_decoder_out_startofpacket, -- .startofpacket
+ out_endofpacket => tx_st_timing_adapter_frame_decoder_out_endofpacket, -- .endofpacket
+ out_empty => tx_st_timing_adapter_frame_decoder_out_empty -- .empty
+ );
+
+ tx_eth_frame_decoder : component ip_stratixiv_mac_10g_tx_eth_frame_decoder
+ generic map (
+ BITSPERSYMBOL => 8,
+ SYMBOLSPERBEAT => 8,
+ ERROR_WIDTH => 3,
+ ENABLE_SUPP_ADDR => 0,
+ ENABLE_PFC => 0,
+ PFC_PRIORITY_NUM => 8
+ )
+ port map (
+ clk => tx_clk_clk, -- clock_reset.clk
+ reset => rst_controller_001_reset_out_reset, -- clock_reset_reset.reset
+ csr_readdata => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_readdata, -- avalom_mm_csr.readdata
+ csr_write => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_write, -- .write
+ csr_read => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_read, -- .read
+ csr_address => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_address, -- .address
+ csr_writedata => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_writedata, -- .writedata
+ data_sink_sop => tx_st_timing_adapter_frame_decoder_out_startofpacket, -- avalon_st_data_sink.startofpacket
+ data_sink_eop => tx_st_timing_adapter_frame_decoder_out_endofpacket, -- .endofpacket
+ data_sink_valid => tx_st_timing_adapter_frame_decoder_out_valid, -- .valid
+ data_sink_data => tx_st_timing_adapter_frame_decoder_out_data, -- .data
+ data_sink_empty => tx_st_timing_adapter_frame_decoder_out_empty, -- .empty
+ data_sink_error => tx_st_timing_adapter_frame_decoder_out_error, -- .error
+ rxstatus_src_valid => tx_eth_frame_decoder_avalon_st_rxstatus_src_valid, -- avalon_st_rxstatus_src.valid
+ rxstatus_src_data => tx_eth_frame_decoder_avalon_st_rxstatus_src_data, -- .data
+ rxstatus_src_error => tx_eth_frame_decoder_avalon_st_rxstatus_src_error, -- .error
+ data_sink_ready => open, -- (terminated)
+ data_src_sop => open, -- (terminated)
+ data_src_eop => open, -- (terminated)
+ data_src_valid => open, -- (terminated)
+ data_src_ready => '1', -- (terminated)
+ data_src_data => open, -- (terminated)
+ data_src_empty => open, -- (terminated)
+ data_src_error => open, -- (terminated)
+ pauselen_src_valid => open, -- (terminated)
+ pauselen_src_data => open, -- (terminated)
+ pfc_pause_quanta_src_valid => open, -- (terminated)
+ pfc_pause_quanta_src_data => open, -- (terminated)
+ pfc_status_src_valid => open, -- (terminated)
+ pfc_status_src_data => open, -- (terminated)
+ pktinfo_src_valid => open, -- (terminated)
+ pktinfo_src_data => open -- (terminated)
+ );
+
+ tx_st_error_adapter_stat : component error_adapter_0002
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
+ in_valid => tx_eth_frame_decoder_avalon_st_rxstatus_src_valid, -- in.valid
+ in_data => tx_eth_frame_decoder_avalon_st_rxstatus_src_data, -- .data
+ in_error => tx_eth_frame_decoder_avalon_st_rxstatus_src_error, -- .error
+ out_valid => tx_st_error_adapter_stat_out_valid, -- out.valid
+ out_data => tx_st_error_adapter_stat_out_data, -- .data
+ out_error => tx_st_error_adapter_stat_out_error -- .error
+ );
+
+ tx_st_timing_adapter_splitter_status_in : component timing_adapter_0002
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
+ in_valid => tx_st_error_adapter_stat_out_valid, -- in.valid
+ in_data => tx_st_error_adapter_stat_out_data, -- .data
+ in_error => tx_st_error_adapter_stat_out_error, -- .error
+ out_valid => tx_st_timing_adapter_splitter_status_in_out_valid, -- out.valid
+ out_data => tx_st_timing_adapter_splitter_status_in_out_data, -- .data
+ out_error => tx_st_timing_adapter_splitter_status_in_out_error, -- .error
+ out_ready => tx_st_timing_adapter_splitter_status_in_out_ready -- .ready
+ );
+
+ tx_st_timing_adapter_splitter_status_output : component timing_adapter_0003
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
+ in_ready => tx_st_status_splitter_out1_ready, -- in.ready
+ in_valid => tx_st_status_splitter_out1_valid, -- .valid
+ in_data => tx_st_status_splitter_out1_data, -- .data
+ in_error => tx_st_status_splitter_out1_error, -- .error
+ out_valid => avalon_st_txstatus_valid, -- out.valid
+ out_data => avalon_st_txstatus_data, -- .data
+ out_error => avalon_st_txstatus_error -- .error
+ );
+
+ tx_st_status_splitter : component altera_avalon_st_splitter_0002
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ in0_ready => tx_st_timing_adapter_splitter_status_in_out_ready, -- in.ready
+ in0_valid => tx_st_timing_adapter_splitter_status_in_out_valid, -- .valid
+ in0_error => tx_st_timing_adapter_splitter_status_in_out_error, -- .error
+ in0_data => tx_st_timing_adapter_splitter_status_in_out_data, -- .data
+ out0_ready => tx_st_status_splitter_out0_ready, -- out0.ready
+ out0_valid => tx_st_status_splitter_out0_valid, -- .valid
+ out0_error => tx_st_status_splitter_out0_error, -- .error
+ out0_data => tx_st_status_splitter_out0_data, -- .data
+ out1_ready => tx_st_status_splitter_out1_ready, -- out1.ready
+ out1_valid => tx_st_status_splitter_out1_valid, -- .valid
+ out1_error => tx_st_status_splitter_out1_error, -- .error
+ out1_data => tx_st_status_splitter_out1_data -- .data
+ );
+
+ tx_st_timing_adapter_splitter_status_statistics : component timing_adapter_0003
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
+ in_ready => tx_st_status_splitter_out0_ready, -- in.ready
+ in_valid => tx_st_status_splitter_out0_valid, -- .valid
+ in_data => tx_st_status_splitter_out0_data, -- .data
+ in_error => tx_st_status_splitter_out0_error, -- .error
+ out_valid => tx_st_timing_adapter_splitter_status_statistics_out_valid, -- out.valid
+ out_data => tx_st_timing_adapter_splitter_status_statistics_out_data, -- .data
+ out_error => tx_st_timing_adapter_splitter_status_statistics_out_error -- .error
+ );
+
+ tx_eth_statistics_collector : component altera_eth_10gmem_statistics_collector
+ generic map (
+ ENABLE_PFC => 0
+ )
+ port map (
+ clk => tx_clk_clk, -- clock_reset.clk
+ reset => rst_controller_001_reset_out_reset, -- clock_reset_reset.reset
+ csr_read => tx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_read, -- csr.read
+ csr_address => tx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_address, -- .address
+ csr_readdata => tx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_readdata, -- .readdata
+ csr_write => tx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_write, -- .write
+ csr_writedata => tx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_writedata, -- .writedata
+ stat_sink_valid => tx_st_timing_adapter_splitter_status_statistics_out_valid, -- avalon_st_sink_data.valid
+ stat_sink_data => tx_st_timing_adapter_splitter_status_statistics_out_data, -- .data
+ stat_sink_error => tx_st_timing_adapter_splitter_status_statistics_out_error -- .error
+ );
+
+ tx_eth_packet_formatter : component altera_eth_packet_formatter
+ generic map (
+ ERROR_WIDTH => 3
+ )
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ data_sink_data => tx_st_splitter_1_out1_data, -- data_sink.data
+ data_sink_sop => tx_st_splitter_1_out1_startofpacket, -- .startofpacket
+ data_sink_eop => tx_st_splitter_1_out1_endofpacket, -- .endofpacket
+ data_sink_empty => tx_st_splitter_1_out1_empty, -- .empty
+ data_sink_error => tx_st_splitter_1_out1_error, -- .error
+ data_sink_valid => tx_st_splitter_1_out1_valid, -- .valid
+ data_sink_ready => tx_st_splitter_1_out1_ready, -- .ready
+ data_src_data => tx_eth_packet_formatter_data_src_data, -- data_src.data
+ data_src_sop => tx_eth_packet_formatter_data_src_startofpacket, -- .startofpacket
+ data_src_eop => tx_eth_packet_formatter_data_src_endofpacket, -- .endofpacket
+ data_src_empty => tx_eth_packet_formatter_data_src_empty, -- .empty
+ data_src_valid => tx_eth_packet_formatter_data_src_valid, -- .valid
+ data_src_ready => tx_eth_packet_formatter_data_src_ready, -- .ready
+ data_sink_data_preamble => "0000000000000000000000000000000000000000000000000000000000000000", -- (terminated)
+ data_sink_valid_preamble => '0', -- (terminated)
+ data_sink_ready_preamble => open -- (terminated)
+ );
+
+ tx_eth_xgmii_termination : component altera_eth_xgmii_termination
+ port map (
+ clk => tx_clk_clk, -- clock_reset.clk
+ reset => rst_controller_001_reset_out_reset, -- clock_reset_reset.reset
+ xgmii_src_data => tx_eth_xgmii_termination_avalon_streaming_source_data, -- avalon_streaming_source.data
+ data_sink_sop => tx_eth_packet_formatter_data_src_startofpacket, -- avalon_streaming_sink.startofpacket
+ data_sink_eop => tx_eth_packet_formatter_data_src_endofpacket, -- .endofpacket
+ data_sink_valid => tx_eth_packet_formatter_data_src_valid, -- .valid
+ data_sink_data => tx_eth_packet_formatter_data_src_data, -- .data
+ data_sink_empty => tx_eth_packet_formatter_data_src_empty, -- .empty
+ data_sink_ready => tx_eth_packet_formatter_data_src_ready -- .ready
+ );
+
+ tx_eth_link_fault_generation : component altera_eth_link_fault_generation
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ mii_sink_data => tx_eth_xgmii_termination_avalon_streaming_source_data, -- mii_sink.data
+ mii_src_data => xgmii_tx_data, -- mii_src.data
+ link_fault_sink_data => rxtx_timing_adapter_link_fault_status_tx_out_data -- link_fault_sink.data
+ );
+
+ rx_bridge : component altera_avalon_mm_bridge_0001
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- reset.reset
+ s0_waitrequest => rx_bridge_s0_translator_avalon_anti_slave_0_waitrequest, -- s0.waitrequest
+ s0_readdata => rx_bridge_s0_translator_avalon_anti_slave_0_readdata, -- .readdata
+ s0_readdatavalid => rx_bridge_s0_translator_avalon_anti_slave_0_readdatavalid, -- .readdatavalid
+ s0_burstcount(0) => rx_bridge_s0_translator_avalon_anti_slave_0_burstcount, -- .burstcount
+ s0_writedata => rx_bridge_s0_translator_avalon_anti_slave_0_writedata, -- .writedata
+ s0_address => rx_bridge_s0_translator_avalon_anti_slave_0_address, -- .address
+ s0_write => rx_bridge_s0_translator_avalon_anti_slave_0_write, -- .write
+ s0_read => rx_bridge_s0_translator_avalon_anti_slave_0_read, -- .read
+ s0_byteenable => rx_bridge_s0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
+ s0_debugaccess => rx_bridge_s0_translator_avalon_anti_slave_0_debugaccess, -- .debugaccess
+ m0_waitrequest => rx_bridge_m0_waitrequest, -- m0.waitrequest
+ m0_readdata => rx_bridge_m0_readdata, -- .readdata
+ m0_readdatavalid => rx_bridge_m0_readdatavalid, -- .readdatavalid
+ m0_burstcount => rx_bridge_m0_burstcount, -- .burstcount
+ m0_writedata => rx_bridge_m0_writedata, -- .writedata
+ m0_address => rx_bridge_m0_address, -- .address
+ m0_write => rx_bridge_m0_write, -- .write
+ m0_read => rx_bridge_m0_read, -- .read
+ m0_byteenable => rx_bridge_m0_byteenable, -- .byteenable
+ m0_debugaccess => rx_bridge_m0_debugaccess -- .debugaccess
+ );
+
+ rx_st_timing_adapter_interface_conversion : component timing_adapter_0004
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset_n => rst_controller_002_reset_out_reset_ports_inv, -- reset.reset_n
+ in_data => xgmii_rx_data, -- in.data
+ out_data => rx_st_timing_adapter_interface_conversion_out_data, -- out.data
+ out_ready => rx_st_timing_adapter_interface_conversion_out_ready, -- .ready
+ out_valid => rx_st_timing_adapter_interface_conversion_out_valid -- .valid
+ );
+
+ rx_st_splitter_xgmii : component altera_avalon_st_splitter_0003
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ in0_ready => rx_st_timing_adapter_interface_conversion_out_ready, -- in.ready
+ in0_valid => rx_st_timing_adapter_interface_conversion_out_valid, -- .valid
+ in0_data => rx_st_timing_adapter_interface_conversion_out_data, -- .data
+ out0_ready => rx_st_splitter_xgmii_out0_ready, -- out0.ready
+ out0_valid => rx_st_splitter_xgmii_out0_valid, -- .valid
+ out0_data => rx_st_splitter_xgmii_out0_data, -- .data
+ out1_ready => rx_st_splitter_xgmii_out1_ready, -- out1.ready
+ out1_valid => rx_st_splitter_xgmii_out1_valid, -- .valid
+ out1_data => rx_st_splitter_xgmii_out1_data -- .data
+ );
+
+ rx_st_timing_adapter_lane_decoder : component timing_adapter_0005
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset_n => rst_controller_002_reset_out_reset_ports_inv, -- reset.reset_n
+ in_ready => rx_st_splitter_xgmii_out0_ready, -- in.ready
+ in_valid => rx_st_splitter_xgmii_out0_valid, -- .valid
+ in_data => rx_st_splitter_xgmii_out0_data, -- .data
+ out_data => rx_st_timing_adapter_lane_decoder_out_data -- out.data
+ );
+
+ rx_st_timing_adapter_link_fault_detection : component timing_adapter_0005
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset_n => rst_controller_002_reset_out_reset_ports_inv, -- reset.reset_n
+ in_ready => rx_st_splitter_xgmii_out1_ready, -- in.ready
+ in_valid => rx_st_splitter_xgmii_out1_valid, -- .valid
+ in_data => rx_st_splitter_xgmii_out1_data, -- .data
+ out_data => rx_st_timing_adapter_link_fault_detection_out_data -- out.data
+ );
+
+ rx_eth_link_fault_detection : component altera_eth_link_fault_detection
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ mii_sink_data => rx_st_timing_adapter_link_fault_detection_out_data, -- mii_sink.data
+ link_fault_src_data => rx_eth_link_fault_detection_link_fault_src_data -- link_fault_src.data
+ );
+
+ rx_eth_lane_decoder : component altera_eth_lane_decoder
+ port map (
+ clk => rx_clk_clk, -- clock_reset.clk
+ reset => rst_controller_002_reset_out_reset, -- clock_reset_reset.reset
+ xgmii_sink_data => rx_st_timing_adapter_lane_decoder_out_data, -- avalon_streaming_sink.data
+ rxdata_src_eop => rx_eth_lane_decoder_avalon_streaming_source_endofpacket, -- avalon_streaming_source.endofpacket
+ rxdata_src_sop => rx_eth_lane_decoder_avalon_streaming_source_startofpacket, -- .startofpacket
+ rxdata_src_valid => rx_eth_lane_decoder_avalon_streaming_source_valid, -- .valid
+ rxdata_src_data => rx_eth_lane_decoder_avalon_streaming_source_data, -- .data
+ rxdata_src_empty => rx_eth_lane_decoder_avalon_streaming_source_empty, -- .empty
+ rxdata_src_error => rx_eth_lane_decoder_avalon_streaming_source_error, -- .error
+ csr_read => rx_eth_lane_decoder_csr_translator_avalon_anti_slave_0_read, -- csr.read
+ csr_write => rx_eth_lane_decoder_csr_translator_avalon_anti_slave_0_write, -- .write
+ csr_address => rx_eth_lane_decoder_csr_translator_avalon_anti_slave_0_address, -- .address
+ csr_writedata => rx_eth_lane_decoder_csr_translator_avalon_anti_slave_0_writedata, -- .writedata
+ csr_readdata => rx_eth_lane_decoder_csr_translator_avalon_anti_slave_0_readdata, -- .readdata
+ preamble_valid => open, -- (terminated)
+ preamble_bytes => open -- (terminated)
+ );
+
+ rx_eth_pkt_backpressure_control : component ip_stratixiv_mac_10g_rx_eth_pkt_backpressure_control
+ generic map (
+ BITSPERSYMBOL => 8,
+ SYMBOLSPERBEAT => 8,
+ ERROR_WIDTH => 1,
+ USE_READY => 0
+ )
+ port map (
+ clk => rx_clk_clk, -- clock_reset.clk
+ reset => rst_controller_002_reset_out_reset, -- clock_reset_reset.reset
+ csr_write => rx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_write, -- csr.write
+ csr_read => rx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_read, -- .read
+ csr_address(0) => rx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_address, -- .address
+ csr_writedata => rx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_writedata, -- .writedata
+ csr_readdata => rx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_readdata, -- .readdata
+ data_src_sop => rx_eth_pkt_backpressure_control_avalon_st_source_data_startofpacket, -- avalon_st_source_data.startofpacket
+ data_src_eop => rx_eth_pkt_backpressure_control_avalon_st_source_data_endofpacket, -- .endofpacket
+ data_src_valid => rx_eth_pkt_backpressure_control_avalon_st_source_data_valid, -- .valid
+ data_src_data => rx_eth_pkt_backpressure_control_avalon_st_source_data_data, -- .data
+ data_src_empty => rx_eth_pkt_backpressure_control_avalon_st_source_data_empty, -- .empty
+ data_src_error => rx_eth_pkt_backpressure_control_avalon_st_source_data_error, -- .error
+ data_sink_sop => rx_eth_lane_decoder_avalon_streaming_source_startofpacket, -- avalon_st_sink_data.startofpacket
+ data_sink_eop => rx_eth_lane_decoder_avalon_streaming_source_endofpacket, -- .endofpacket
+ data_sink_valid => rx_eth_lane_decoder_avalon_streaming_source_valid, -- .valid
+ data_sink_data => rx_eth_lane_decoder_avalon_streaming_source_data, -- .data
+ data_sink_empty => rx_eth_lane_decoder_avalon_streaming_source_empty, -- .empty
+ data_sink_error => rx_eth_lane_decoder_avalon_streaming_source_error, -- .error
+ data_src_ready => '1', -- (terminated)
+ data_sink_ready => open, -- (terminated)
+ pausebeats_sink_valid => '0', -- (terminated)
+ pausebeats_sink_data => "00000000000000000000000000000000" -- (terminated)
+ );
+
+ rx_st_timing_adapter_frame_status_in : component timing_adapter_0006
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset_n => rst_controller_002_reset_out_reset_ports_inv, -- reset.reset_n
+ in_valid => rx_eth_pkt_backpressure_control_avalon_st_source_data_valid, -- in.valid
+ in_data => rx_eth_pkt_backpressure_control_avalon_st_source_data_data, -- .data
+ in_error => rx_eth_pkt_backpressure_control_avalon_st_source_data_error(0), -- .error
+ in_startofpacket => rx_eth_pkt_backpressure_control_avalon_st_source_data_startofpacket, -- .startofpacket
+ in_endofpacket => rx_eth_pkt_backpressure_control_avalon_st_source_data_endofpacket, -- .endofpacket
+ in_empty => rx_eth_pkt_backpressure_control_avalon_st_source_data_empty, -- .empty
+ out_valid => rx_st_timing_adapter_frame_status_in_out_valid, -- out.valid
+ out_data => rx_st_timing_adapter_frame_status_in_out_data, -- .data
+ out_error => rx_st_timing_adapter_frame_status_in_out_error, -- .error
+ out_startofpacket => rx_st_timing_adapter_frame_status_in_out_startofpacket, -- .startofpacket
+ out_endofpacket => rx_st_timing_adapter_frame_status_in_out_endofpacket, -- .endofpacket
+ out_empty => rx_st_timing_adapter_frame_status_in_out_empty, -- .empty
+ out_ready => rx_st_timing_adapter_frame_status_in_out_ready -- .ready
+ );
+
+ rx_st_frame_status_splitter : component altera_avalon_st_splitter_0004
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ in0_ready => rx_st_timing_adapter_frame_status_in_out_ready, -- in.ready
+ in0_valid => rx_st_timing_adapter_frame_status_in_out_valid, -- .valid
+ in0_startofpacket => rx_st_timing_adapter_frame_status_in_out_startofpacket, -- .startofpacket
+ in0_endofpacket => rx_st_timing_adapter_frame_status_in_out_endofpacket, -- .endofpacket
+ in0_empty => rx_st_timing_adapter_frame_status_in_out_empty, -- .empty
+ in0_error => rx_st_timing_adapter_frame_status_in_out_error, -- .error
+ in0_data => rx_st_timing_adapter_frame_status_in_out_data, -- .data
+ out0_ready => rx_st_frame_status_splitter_out0_ready, -- out0.ready
+ out0_valid => rx_st_frame_status_splitter_out0_valid, -- .valid
+ out0_startofpacket => rx_st_frame_status_splitter_out0_startofpacket, -- .startofpacket
+ out0_endofpacket => rx_st_frame_status_splitter_out0_endofpacket, -- .endofpacket
+ out0_empty => rx_st_frame_status_splitter_out0_empty, -- .empty
+ out0_error => rx_st_frame_status_splitter_out0_error, -- .error
+ out0_data => rx_st_frame_status_splitter_out0_data, -- .data
+ out1_ready => rx_st_frame_status_splitter_out1_ready, -- out1.ready
+ out1_valid => rx_st_frame_status_splitter_out1_valid, -- .valid
+ out1_startofpacket => rx_st_frame_status_splitter_out1_startofpacket, -- .startofpacket
+ out1_endofpacket => rx_st_frame_status_splitter_out1_endofpacket, -- .endofpacket
+ out1_empty => rx_st_frame_status_splitter_out1_empty, -- .empty
+ out1_error => rx_st_frame_status_splitter_out1_error, -- .error
+ out1_data => rx_st_frame_status_splitter_out1_data -- .data
+ );
+
+ rx_eth_frame_decoder : component ip_stratixiv_mac_10g_rx_eth_frame_decoder
+ generic map (
+ BITSPERSYMBOL => 8,
+ SYMBOLSPERBEAT => 8,
+ ERROR_WIDTH => 1,
+ ENABLE_SUPP_ADDR => 1,
+ ENABLE_PFC => 0,
+ PFC_PRIORITY_NUM => 8
+ )
+ port map (
+ clk => rx_clk_clk, -- clock_reset.clk
+ reset => rst_controller_002_reset_out_reset, -- clock_reset_reset.reset
+ csr_readdata => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_readdata, -- avalom_mm_csr.readdata
+ csr_write => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_write, -- .write
+ csr_read => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_read, -- .read
+ csr_address => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_address, -- .address
+ csr_writedata => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_writedata, -- .writedata
+ data_sink_sop => rx_timing_adapter_frame_status_out_frame_decoder_out_startofpacket, -- avalon_st_data_sink.startofpacket
+ data_sink_eop => rx_timing_adapter_frame_status_out_frame_decoder_out_endofpacket, -- .endofpacket
+ data_sink_valid => rx_timing_adapter_frame_status_out_frame_decoder_out_valid, -- .valid
+ data_sink_data => rx_timing_adapter_frame_status_out_frame_decoder_out_data, -- .data
+ data_sink_empty => rx_timing_adapter_frame_status_out_frame_decoder_out_empty, -- .empty
+ data_sink_error(0) => rx_timing_adapter_frame_status_out_frame_decoder_out_error, -- .error
+ data_src_sop => rx_eth_frame_decoder_avalon_st_data_src_startofpacket, -- avalon_st_data_src.startofpacket
+ data_src_eop => rx_eth_frame_decoder_avalon_st_data_src_endofpacket, -- .endofpacket
+ data_src_valid => rx_eth_frame_decoder_avalon_st_data_src_valid, -- .valid
+ data_src_data => rx_eth_frame_decoder_avalon_st_data_src_data, -- .data
+ data_src_empty => rx_eth_frame_decoder_avalon_st_data_src_empty, -- .empty
+ data_src_error => rx_eth_frame_decoder_avalon_st_data_src_error, -- .error
+ pauselen_src_valid => rx_eth_frame_decoder_avalon_st_pauselen_src_valid, -- avalon_st_pauselen_src.valid
+ pauselen_src_data => rx_eth_frame_decoder_avalon_st_pauselen_src_data, -- .data
+ rxstatus_src_valid => rx_eth_frame_decoder_avalon_st_rxstatus_src_valid, -- avalon_st_rxstatus_src.valid
+ rxstatus_src_data => rx_eth_frame_decoder_avalon_st_rxstatus_src_data, -- .data
+ rxstatus_src_error => rx_eth_frame_decoder_avalon_st_rxstatus_src_error, -- .error
+ pktinfo_src_valid => rx_eth_frame_decoder_avalon_st_pktinfo_src_valid, -- avalon_st_pktinfo_src.valid
+ pktinfo_src_data => rx_eth_frame_decoder_avalon_st_pktinfo_src_data, -- .data
+ data_sink_ready => open, -- (terminated)
+ data_src_ready => '1', -- (terminated)
+ pfc_pause_quanta_src_valid => open, -- (terminated)
+ pfc_pause_quanta_src_data => open, -- (terminated)
+ pfc_status_src_valid => open, -- (terminated)
+ pfc_status_src_data => open -- (terminated)
+ );
+
+ rx_eth_crc_checker : component ip_stratixiv_mac_10g_rx_eth_crc_checker
+ generic map (
+ BITSPERSYMBOL => 8,
+ SYMBOLSPERBEAT => 8,
+ ERROR_WIDTH => 1,
+ MODE_CHECKER_0_INSERTER_1 => 0
+ )
+ port map (
+ clk => rx_clk_clk, -- clock_reset.clk
+ reset => rst_controller_002_reset_out_reset, -- clock_reset_reset.reset
+ csr_write => rx_eth_crc_checker_csr_translator_avalon_anti_slave_0_write, -- csr.write
+ csr_read => rx_eth_crc_checker_csr_translator_avalon_anti_slave_0_read, -- .read
+ csr_address => rx_eth_crc_checker_csr_translator_avalon_anti_slave_0_address, -- .address
+ csr_writedata => rx_eth_crc_checker_csr_translator_avalon_anti_slave_0_writedata, -- .writedata
+ csr_readdata => rx_eth_crc_checker_csr_translator_avalon_anti_slave_0_readdata, -- .readdata
+ data_sink_sop => rx_timing_adapter_frame_status_out_crc_checker_out_startofpacket, -- avalon_streaming_sink.startofpacket
+ data_sink_eop => rx_timing_adapter_frame_status_out_crc_checker_out_endofpacket, -- .endofpacket
+ data_sink_valid => rx_timing_adapter_frame_status_out_crc_checker_out_valid, -- .valid
+ data_sink_data => rx_timing_adapter_frame_status_out_crc_checker_out_data, -- .data
+ data_sink_empty => rx_timing_adapter_frame_status_out_crc_checker_out_empty, -- .empty
+ data_sink_error(0) => rx_timing_adapter_frame_status_out_crc_checker_out_error, -- .error
+ data_src_sop => rx_eth_crc_checker_avalon_streaming_source_startofpacket, -- avalon_streaming_source.startofpacket
+ data_src_eop => rx_eth_crc_checker_avalon_streaming_source_endofpacket, -- .endofpacket
+ data_src_valid => rx_eth_crc_checker_avalon_streaming_source_valid, -- .valid
+ data_src_data => rx_eth_crc_checker_avalon_streaming_source_data, -- .data
+ data_src_empty => rx_eth_crc_checker_avalon_streaming_source_empty, -- .empty
+ data_src_error => rx_eth_crc_checker_avalon_streaming_source_error, -- .error
+ data_sink_ready => open, -- (terminated)
+ data_src_ready => '1' -- (terminated)
+ );
+
+ rx_timing_adapter_frame_status_out_frame_decoder : component timing_adapter_0007
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset_n => rst_controller_002_reset_out_reset_ports_inv, -- reset.reset_n
+ in_ready => rx_st_frame_status_splitter_out0_ready, -- in.ready
+ in_valid => rx_st_frame_status_splitter_out0_valid, -- .valid
+ in_data => rx_st_frame_status_splitter_out0_data, -- .data
+ in_error => rx_st_frame_status_splitter_out0_error, -- .error
+ in_startofpacket => rx_st_frame_status_splitter_out0_startofpacket, -- .startofpacket
+ in_endofpacket => rx_st_frame_status_splitter_out0_endofpacket, -- .endofpacket
+ in_empty => rx_st_frame_status_splitter_out0_empty, -- .empty
+ out_valid => rx_timing_adapter_frame_status_out_frame_decoder_out_valid, -- out.valid
+ out_data => rx_timing_adapter_frame_status_out_frame_decoder_out_data, -- .data
+ out_error => rx_timing_adapter_frame_status_out_frame_decoder_out_error, -- .error
+ out_startofpacket => rx_timing_adapter_frame_status_out_frame_decoder_out_startofpacket, -- .startofpacket
+ out_endofpacket => rx_timing_adapter_frame_status_out_frame_decoder_out_endofpacket, -- .endofpacket
+ out_empty => rx_timing_adapter_frame_status_out_frame_decoder_out_empty -- .empty
+ );
+
+ rx_timing_adapter_frame_status_out_crc_checker : component timing_adapter_0007
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset_n => rst_controller_002_reset_out_reset_ports_inv, -- reset.reset_n
+ in_ready => rx_st_frame_status_splitter_out1_ready, -- in.ready
+ in_valid => rx_st_frame_status_splitter_out1_valid, -- .valid
+ in_data => rx_st_frame_status_splitter_out1_data, -- .data
+ in_error => rx_st_frame_status_splitter_out1_error, -- .error
+ in_startofpacket => rx_st_frame_status_splitter_out1_startofpacket, -- .startofpacket
+ in_endofpacket => rx_st_frame_status_splitter_out1_endofpacket, -- .endofpacket
+ in_empty => rx_st_frame_status_splitter_out1_empty, -- .empty
+ out_valid => rx_timing_adapter_frame_status_out_crc_checker_out_valid, -- out.valid
+ out_data => rx_timing_adapter_frame_status_out_crc_checker_out_data, -- .data
+ out_error => rx_timing_adapter_frame_status_out_crc_checker_out_error, -- .error
+ out_startofpacket => rx_timing_adapter_frame_status_out_crc_checker_out_startofpacket, -- .startofpacket
+ out_endofpacket => rx_timing_adapter_frame_status_out_crc_checker_out_endofpacket, -- .endofpacket
+ out_empty => rx_timing_adapter_frame_status_out_crc_checker_out_empty -- .empty
+ );
+
+ rx_eth_frame_status_merger : component altera_eth_frame_status_merger
+ port map (
+ clk => rx_clk_clk, -- clock_reset.clk
+ reset => rst_controller_002_reset_out_reset, -- clock_reset_reset.reset
+ frame_decoder_data_sink_sop => rx_eth_frame_decoder_avalon_st_data_src_startofpacket, -- frame_decoder_data_sink.startofpacket
+ frame_decoder_data_sink_eop => rx_eth_frame_decoder_avalon_st_data_src_endofpacket, -- .endofpacket
+ frame_decoder_data_sink_valid => rx_eth_frame_decoder_avalon_st_data_src_valid, -- .valid
+ frame_decoder_data_sink_data => rx_eth_frame_decoder_avalon_st_data_src_data, -- .data
+ frame_decoder_data_sink_empty => rx_eth_frame_decoder_avalon_st_data_src_empty, -- .empty
+ frame_decoder_data_sink_error => rx_eth_frame_decoder_avalon_st_data_src_error, -- .error
+ crc_checker_data_sink_sop => rx_eth_crc_checker_avalon_streaming_source_startofpacket, -- crc_checker_data_sink.startofpacket
+ crc_checker_data_sink_eop => rx_eth_crc_checker_avalon_streaming_source_endofpacket, -- .endofpacket
+ crc_checker_data_sink_valid => rx_eth_crc_checker_avalon_streaming_source_valid, -- .valid
+ crc_checker_data_sink_data => rx_eth_crc_checker_avalon_streaming_source_data, -- .data
+ crc_checker_data_sink_empty => rx_eth_crc_checker_avalon_streaming_source_empty, -- .empty
+ crc_checker_data_sink_error => rx_eth_crc_checker_avalon_streaming_source_error, -- .error
+ data_src_sop => rx_eth_frame_status_merger_data_src_startofpacket, -- data_src.startofpacket
+ data_src_eop => rx_eth_frame_status_merger_data_src_endofpacket, -- .endofpacket
+ data_src_valid => rx_eth_frame_status_merger_data_src_valid, -- .valid
+ data_src_data => rx_eth_frame_status_merger_data_src_data, -- .data
+ data_src_empty => rx_eth_frame_status_merger_data_src_empty, -- .empty
+ data_src_error => rx_eth_frame_status_merger_data_src_error, -- .error
+ pauselen_sink_valid => rx_eth_frame_decoder_avalon_st_pauselen_src_valid, -- pauselen_sink.valid
+ pauselen_sink_data => rx_eth_frame_decoder_avalon_st_pauselen_src_data, -- .data
+ pauselen_src_valid => rx_eth_frame_status_merger_pauselen_src_valid, -- pauselen_src.valid
+ pauselen_src_data => rx_eth_frame_status_merger_pauselen_src_data, -- .data
+ rxstatus_sink_valid => rx_eth_frame_decoder_avalon_st_rxstatus_src_valid, -- rxstatus_sink.valid
+ rxstatus_sink_data => rx_eth_frame_decoder_avalon_st_rxstatus_src_data, -- .data
+ rxstatus_sink_error => rx_eth_frame_decoder_avalon_st_rxstatus_src_error, -- .error
+ rxstatus_src_valid => rx_eth_frame_status_merger_rxstatus_src_valid, -- rxstatus_src.valid
+ rxstatus_src_data => rx_eth_frame_status_merger_rxstatus_src_data, -- .data
+ rxstatus_src_error => rx_eth_frame_status_merger_rxstatus_src_error, -- .error
+ pfc_pause_quanta_sink_valid => '0', -- (terminated)
+ pfc_pause_quanta_sink_data => "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", -- (terminated)
+ pfc_pause_quanta_src_valid => open, -- (terminated)
+ pfc_pause_quanta_src_data => open -- (terminated)
+ );
+
+ rx_eth_crc_pad_rem : component altera_eth_crc_pad_rem
+ generic map (
+ BITSPERSYMBOL => 8,
+ SYMBOLSPERBEAT => 8,
+ ERRORWIDTH => 5
+ )
+ port map (
+ clk => rx_clk_clk, -- clock_reset.clk
+ reset => rst_controller_002_reset_out_reset, -- clock_reset_reset.reset
+ csr_read => rx_eth_crc_pad_rem_csr_translator_avalon_anti_slave_0_read, -- csr.read
+ csr_write => rx_eth_crc_pad_rem_csr_translator_avalon_anti_slave_0_write, -- .write
+ csr_address => rx_eth_crc_pad_rem_csr_translator_avalon_anti_slave_0_address, -- .address
+ csr_writedata => rx_eth_crc_pad_rem_csr_translator_avalon_anti_slave_0_writedata, -- .writedata
+ csr_readdata => rx_eth_crc_pad_rem_csr_translator_avalon_anti_slave_0_readdata, -- .readdata
+ data_sink_sop => rx_eth_frame_status_merger_data_src_startofpacket, -- avalon_streaming_sink_data.startofpacket
+ data_sink_eop => rx_eth_frame_status_merger_data_src_endofpacket, -- .endofpacket
+ data_sink_valid => rx_eth_frame_status_merger_data_src_valid, -- .valid
+ data_sink_data => rx_eth_frame_status_merger_data_src_data, -- .data
+ data_sink_empty => rx_eth_frame_status_merger_data_src_empty, -- .empty
+ data_sink_error => rx_eth_frame_status_merger_data_src_error, -- .error
+ status_sink_valid => rx_eth_frame_decoder_avalon_st_pktinfo_src_valid, -- avalon_streaming_sink_status.valid
+ status_sink_data => rx_eth_frame_decoder_avalon_st_pktinfo_src_data, -- .data
+ data_source_sop => rx_eth_crc_pad_rem_avalon_streaming_source_data_startofpacket, -- avalon_streaming_source_data.startofpacket
+ data_source_eop => rx_eth_crc_pad_rem_avalon_streaming_source_data_endofpacket, -- .endofpacket
+ data_source_valid => rx_eth_crc_pad_rem_avalon_streaming_source_data_valid, -- .valid
+ data_source_data => rx_eth_crc_pad_rem_avalon_streaming_source_data_data, -- .data
+ data_source_empty => rx_eth_crc_pad_rem_avalon_streaming_source_data_empty, -- .empty
+ data_source_error => rx_eth_crc_pad_rem_avalon_streaming_source_data_error -- .error
+ );
+
+ rx_eth_packet_overflow_control : component altera_eth_packet_overflow_control
+ generic map (
+ BITSPERSYMBOL => 8,
+ SYMBOLSPERBEAT => 8,
+ ERROR_WIDTH => 5
+ )
+ port map (
+ clk => rx_clk_clk, -- clock_reset.clk
+ reset => rst_controller_002_reset_out_reset, -- clock_reset_reset.reset
+ data_sink_sop => rx_eth_crc_pad_rem_avalon_streaming_source_data_startofpacket, -- avalon_streaming_sink.startofpacket
+ data_sink_eop => rx_eth_crc_pad_rem_avalon_streaming_source_data_endofpacket, -- .endofpacket
+ data_sink_valid => rx_eth_crc_pad_rem_avalon_streaming_source_data_valid, -- .valid
+ data_sink_empty => rx_eth_crc_pad_rem_avalon_streaming_source_data_empty, -- .empty
+ data_sink_error => rx_eth_crc_pad_rem_avalon_streaming_source_data_error, -- .error
+ data_sink_data => rx_eth_crc_pad_rem_avalon_streaming_source_data_data, -- .data
+ data_src_sop => avalon_st_rx_startofpacket, -- avalon_streaming_source.startofpacket
+ data_src_eop => avalon_st_rx_endofpacket, -- .endofpacket
+ data_src_valid => avalon_st_rx_valid, -- .valid
+ data_src_ready => avalon_st_rx_ready, -- .ready
+ data_src_data => avalon_st_rx_data, -- .data
+ data_src_empty => avalon_st_rx_empty, -- .empty
+ data_src_error => avalon_st_rx_error, -- .error
+ csr_address => rx_eth_packet_overflow_control_csr_translator_avalon_anti_slave_0_address, -- csr.address
+ csr_read => rx_eth_packet_overflow_control_csr_translator_avalon_anti_slave_0_read, -- .read
+ csr_readdata => rx_eth_packet_overflow_control_csr_translator_avalon_anti_slave_0_readdata -- .readdata
+ );
+
+ rx_st_status_output_delay : component altera_avalon_st_delay_0001
+ port map (
+ in0_valid => rx_st_timing_adapter_splitter_status_output_out_valid, -- in.valid
+ in0_data => rx_st_timing_adapter_splitter_status_output_out_data, -- .data
+ in0_error => rx_st_timing_adapter_splitter_status_output_out_error, -- .error
+ out0_valid => avalon_st_rxstatus_valid, -- out.valid
+ out0_data => avalon_st_rxstatus_data, -- .data
+ out0_error => avalon_st_rxstatus_error, -- .error
+ clk => rx_clk_clk, -- clk.clk
+ reset_n => rst_controller_002_reset_out_reset_ports_inv -- clk_reset.reset_n
+ );
+
+ rx_st_error_adapter_stat : component error_adapter_0003
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset_n => rst_controller_002_reset_out_reset_ports_inv, -- reset.reset_n
+ in_valid => rx_eth_frame_status_merger_rxstatus_src_valid, -- in.valid
+ in_data => rx_eth_frame_status_merger_rxstatus_src_data, -- .data
+ in_error => rx_eth_frame_status_merger_rxstatus_src_error, -- .error
+ out_valid => rx_st_error_adapter_stat_out_valid, -- out.valid
+ out_data => rx_st_error_adapter_stat_out_data, -- .data
+ out_error => rx_st_error_adapter_stat_out_error -- .error
+ );
+
+ rx_st_timing_adapter_splitter_status_in : component timing_adapter_0002
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset_n => rst_controller_002_reset_out_reset_ports_inv, -- reset.reset_n
+ in_valid => rx_st_error_adapter_stat_out_valid, -- in.valid
+ in_data => rx_st_error_adapter_stat_out_data, -- .data
+ in_error => rx_st_error_adapter_stat_out_error, -- .error
+ out_valid => rx_st_timing_adapter_splitter_status_in_out_valid, -- out.valid
+ out_data => rx_st_timing_adapter_splitter_status_in_out_data, -- .data
+ out_error => rx_st_timing_adapter_splitter_status_in_out_error, -- .error
+ out_ready => rx_st_timing_adapter_splitter_status_in_out_ready -- .ready
+ );
+
+ rx_st_status_splitter : component altera_avalon_st_splitter_0002
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ in0_ready => rx_st_timing_adapter_splitter_status_in_out_ready, -- in.ready
+ in0_valid => rx_st_timing_adapter_splitter_status_in_out_valid, -- .valid
+ in0_error => rx_st_timing_adapter_splitter_status_in_out_error, -- .error
+ in0_data => rx_st_timing_adapter_splitter_status_in_out_data, -- .data
+ out0_ready => rx_st_status_splitter_out0_ready, -- out0.ready
+ out0_valid => rx_st_status_splitter_out0_valid, -- .valid
+ out0_error => rx_st_status_splitter_out0_error, -- .error
+ out0_data => rx_st_status_splitter_out0_data, -- .data
+ out1_ready => rx_st_status_splitter_out1_ready, -- out1.ready
+ out1_valid => rx_st_status_splitter_out1_valid, -- .valid
+ out1_error => rx_st_status_splitter_out1_error, -- .error
+ out1_data => rx_st_status_splitter_out1_data -- .data
+ );
+
+ rx_st_timing_adapter_splitter_status_statistics : component timing_adapter_0003
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset_n => rst_controller_002_reset_out_reset_ports_inv, -- reset.reset_n
+ in_ready => rx_st_status_splitter_out0_ready, -- in.ready
+ in_valid => rx_st_status_splitter_out0_valid, -- .valid
+ in_data => rx_st_status_splitter_out0_data, -- .data
+ in_error => rx_st_status_splitter_out0_error, -- .error
+ out_valid => rx_st_timing_adapter_splitter_status_statistics_out_valid, -- out.valid
+ out_data => rx_st_timing_adapter_splitter_status_statistics_out_data, -- .data
+ out_error => rx_st_timing_adapter_splitter_status_statistics_out_error -- .error
+ );
+
+ rx_st_timing_adapter_splitter_status_output : component timing_adapter_0003
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset_n => rst_controller_002_reset_out_reset_ports_inv, -- reset.reset_n
+ in_ready => rx_st_status_splitter_out1_ready, -- in.ready
+ in_valid => rx_st_status_splitter_out1_valid, -- .valid
+ in_data => rx_st_status_splitter_out1_data, -- .data
+ in_error => rx_st_status_splitter_out1_error, -- .error
+ out_valid => rx_st_timing_adapter_splitter_status_output_out_valid, -- out.valid
+ out_data => rx_st_timing_adapter_splitter_status_output_out_data, -- .data
+ out_error => rx_st_timing_adapter_splitter_status_output_out_error -- .error
+ );
+
+ rx_st_status_statistics_delay : component altera_avalon_st_delay_0002
+ port map (
+ in0_valid => rx_st_timing_adapter_splitter_status_statistics_out_valid, -- in.valid
+ in0_data => rx_st_timing_adapter_splitter_status_statistics_out_data, -- .data
+ in0_error => rx_st_timing_adapter_splitter_status_statistics_out_error, -- .error
+ out0_valid => rx_st_status_statistics_delay_out_valid, -- out.valid
+ out0_data => rx_st_status_statistics_delay_out_data, -- .data
+ out0_error => rx_st_status_statistics_delay_out_error, -- .error
+ clk => rx_clk_clk, -- clk.clk
+ reset_n => rst_controller_002_reset_out_reset_ports_inv -- clk_reset.reset_n
+ );
+
+ rx_eth_statistics_collector : component altera_eth_10gmem_statistics_collector
+ generic map (
+ ENABLE_PFC => 0
+ )
+ port map (
+ clk => rx_clk_clk, -- clock_reset.clk
+ reset => rst_controller_002_reset_out_reset, -- clock_reset_reset.reset
+ csr_read => rx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_read, -- csr.read
+ csr_address => rx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_address, -- .address
+ csr_readdata => rx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_readdata, -- .readdata
+ csr_write => rx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_write, -- .write
+ csr_writedata => rx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_writedata, -- .writedata
+ stat_sink_valid => rx_st_status_statistics_delay_out_valid, -- avalon_st_sink_data.valid
+ stat_sink_data => rx_st_status_statistics_delay_out_data, -- .data
+ stat_sink_error => rx_st_status_statistics_delay_out_error -- .error
+ );
+
+ txrx_timing_adapter_link_fault_status_rx : component timing_adapter_0008
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset_n => rst_controller_002_reset_out_reset_ports_inv, -- reset.reset_n
+ in_data => rx_eth_link_fault_detection_link_fault_src_data, -- in.data
+ out_data => txrx_timing_adapter_link_fault_status_rx_out_data, -- out.data
+ out_ready => txrx_timing_adapter_link_fault_status_rx_out_ready, -- .ready
+ out_valid => txrx_timing_adapter_link_fault_status_rx_out_valid -- .valid
+ );
+
+ txrx_st_splitter_link_fault_status : component altera_avalon_st_splitter_0005
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ in0_ready => txrx_timing_adapter_link_fault_status_rx_out_ready, -- in.ready
+ in0_valid => txrx_timing_adapter_link_fault_status_rx_out_valid, -- .valid
+ in0_data => txrx_timing_adapter_link_fault_status_rx_out_data, -- .data
+ out0_ready => txrx_st_splitter_link_fault_status_out0_ready, -- out0.ready
+ out0_valid => txrx_st_splitter_link_fault_status_out0_valid, -- .valid
+ out0_data => txrx_st_splitter_link_fault_status_out0_data, -- .data
+ out1_ready => txrx_st_splitter_link_fault_status_out1_ready, -- out1.ready
+ out1_valid => txrx_st_splitter_link_fault_status_out1_valid, -- .valid
+ out1_data => txrx_st_splitter_link_fault_status_out1_data -- .data
+ );
+
+ txrx_timing_adapter_link_fault_status_export : component timing_adapter_0009
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset_n => rst_controller_002_reset_out_reset_ports_inv, -- reset.reset_n
+ in_ready => txrx_st_splitter_link_fault_status_out0_ready, -- in.ready
+ in_valid => txrx_st_splitter_link_fault_status_out0_valid, -- .valid
+ in_data => txrx_st_splitter_link_fault_status_out0_data, -- .data
+ out_data => link_fault_status_xgmii_rx_data -- out.data
+ );
+
+ rxtx_dc_fifo_link_fault_status : component altera_avalon_dc_fifo_0001
+ port map (
+ in_clk => rx_clk_clk, -- in_clk.clk
+ in_reset_n => rst_controller_002_reset_out_reset_ports_inv, -- in_clk_reset.reset_n
+ out_clk => tx_clk_clk, -- out_clk.clk
+ out_reset_n => rst_controller_001_reset_out_reset_ports_inv, -- out_clk_reset.reset_n
+ in_data => txrx_st_splitter_link_fault_status_out1_data, -- in.data
+ in_valid => txrx_st_splitter_link_fault_status_out1_valid, -- .valid
+ in_ready => txrx_st_splitter_link_fault_status_out1_ready, -- .ready
+ out_data => rxtx_dc_fifo_link_fault_status_out_data, -- out.data
+ out_valid => rxtx_dc_fifo_link_fault_status_out_valid, -- .valid
+ out_ready => rxtx_dc_fifo_link_fault_status_out_ready -- .ready
+ );
+
+ rxtx_timing_adapter_link_fault_status_tx : component timing_adapter_0009
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
+ in_ready => rxtx_dc_fifo_link_fault_status_out_ready, -- in.ready
+ in_valid => rxtx_dc_fifo_link_fault_status_out_valid, -- .valid
+ in_data => rxtx_dc_fifo_link_fault_status_out_data, -- .data
+ out_data => rxtx_timing_adapter_link_fault_status_tx_out_data -- out.data
+ );
+
+ rxtx_timing_adapter_pauselen_rx : component timing_adapter_0010
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset_n => rst_controller_002_reset_out_reset_ports_inv, -- reset.reset_n
+ in_valid => rx_eth_frame_status_merger_pauselen_src_valid, -- in.valid
+ in_data => rx_eth_frame_status_merger_pauselen_src_data, -- .data
+ out_valid => rxtx_timing_adapter_pauselen_rx_out_valid, -- out.valid
+ out_data => rxtx_timing_adapter_pauselen_rx_out_data, -- .data
+ out_ready => rxtx_timing_adapter_pauselen_rx_out_ready -- .ready
+ );
+
+ rxtx_dc_fifo_pauselen : component altera_avalon_dc_fifo_0002
+ port map (
+ in_clk => rx_clk_clk, -- in_clk.clk
+ in_reset_n => rst_controller_002_reset_out_reset_ports_inv, -- in_clk_reset.reset_n
+ out_clk => tx_clk_clk, -- out_clk.clk
+ out_reset_n => rst_controller_001_reset_out_reset_ports_inv, -- out_clk_reset.reset_n
+ in_data => rxtx_timing_adapter_pauselen_rx_out_data, -- in.data
+ in_valid => rxtx_timing_adapter_pauselen_rx_out_valid, -- .valid
+ in_ready => rxtx_timing_adapter_pauselen_rx_out_ready, -- .ready
+ out_data => rxtx_dc_fifo_pauselen_out_data, -- out.data
+ out_valid => rxtx_dc_fifo_pauselen_out_valid, -- .valid
+ out_ready => rxtx_dc_fifo_pauselen_out_ready -- .ready
+ );
+
+ rxtx_timing_adapter_pauselen_tx : component timing_adapter_0011
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
+ in_ready => rxtx_dc_fifo_pauselen_out_ready, -- in.ready
+ in_valid => rxtx_dc_fifo_pauselen_out_valid, -- .valid
+ in_data => rxtx_dc_fifo_pauselen_out_data, -- .data
+ out_valid => rxtx_timing_adapter_pauselen_tx_out_valid, -- out.valid
+ out_data => rxtx_timing_adapter_pauselen_tx_out_data -- .data
+ );
+
+ merlin_master_translator_avalon_universal_master_0_translator : component altera_merlin_master_translator_0002
+ port map (
+ clk => csr_clk_clk, -- clk.clk
+ reset => rst_controller_reset_out_reset, -- reset.reset
+ uav_address => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_address, -- avalon_universal_master_0.address
+ uav_burstcount => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_burstcount, -- .burstcount
+ uav_read => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_read, -- .read
+ uav_write => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_write, -- .write
+ uav_waitrequest => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
+ uav_readdatavalid => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
+ uav_byteenable => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_byteenable, -- .byteenable
+ uav_readdata => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_readdata, -- .readdata
+ uav_writedata => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_writedata, -- .writedata
+ uav_lock => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_lock, -- .lock
+ uav_debugaccess => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
+ av_address => merlin_master_translator_avalon_universal_master_0_address, -- avalon_anti_master_0.address
+ av_waitrequest => merlin_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
+ av_burstcount => merlin_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
+ av_byteenable => merlin_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
+ av_read => merlin_master_translator_avalon_universal_master_0_read, -- .read
+ av_readdata => merlin_master_translator_avalon_universal_master_0_readdata, -- .readdata
+ av_readdatavalid => merlin_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
+ av_write => merlin_master_translator_avalon_universal_master_0_write, -- .write
+ av_writedata => merlin_master_translator_avalon_universal_master_0_writedata, -- .writedata
+ av_lock => merlin_master_translator_avalon_universal_master_0_lock, -- .lock
+ av_debugaccess => merlin_master_translator_avalon_universal_master_0_debugaccess -- .debugaccess
+ );
+
+ tx_bridge_s0_translator : component altera_merlin_slave_translator_0001
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- reset.reset
+ uav_address => tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
+ uav_burstcount => tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ uav_read => tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ uav_write => tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ uav_waitrequest => tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ uav_readdatavalid => tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ uav_byteenable => tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ uav_readdata => tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ uav_writedata => tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ uav_lock => tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ uav_debugaccess => tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ av_address => tx_bridge_s0_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
+ av_write => tx_bridge_s0_translator_avalon_anti_slave_0_write, -- .write
+ av_read => tx_bridge_s0_translator_avalon_anti_slave_0_read, -- .read
+ av_readdata => tx_bridge_s0_translator_avalon_anti_slave_0_readdata, -- .readdata
+ av_writedata => tx_bridge_s0_translator_avalon_anti_slave_0_writedata, -- .writedata
+ av_burstcount => tx_bridge_s0_translator_avalon_anti_slave_0_burstcount, -- .burstcount
+ av_byteenable => tx_bridge_s0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
+ av_readdatavalid => tx_bridge_s0_translator_avalon_anti_slave_0_readdatavalid, -- .readdatavalid
+ av_waitrequest => tx_bridge_s0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
+ av_debugaccess => tx_bridge_s0_translator_avalon_anti_slave_0_debugaccess -- .debugaccess
+ );
+
+ rx_bridge_s0_translator : component altera_merlin_slave_translator_0001
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- reset.reset
+ uav_address => rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
+ uav_burstcount => rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ uav_read => rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ uav_write => rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ uav_waitrequest => rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ uav_readdatavalid => rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ uav_byteenable => rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ uav_readdata => rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ uav_writedata => rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ uav_lock => rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ uav_debugaccess => rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ av_address => rx_bridge_s0_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
+ av_write => rx_bridge_s0_translator_avalon_anti_slave_0_write, -- .write
+ av_read => rx_bridge_s0_translator_avalon_anti_slave_0_read, -- .read
+ av_readdata => rx_bridge_s0_translator_avalon_anti_slave_0_readdata, -- .readdata
+ av_writedata => rx_bridge_s0_translator_avalon_anti_slave_0_writedata, -- .writedata
+ av_burstcount => rx_bridge_s0_translator_avalon_anti_slave_0_burstcount, -- .burstcount
+ av_byteenable => rx_bridge_s0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
+ av_readdatavalid => rx_bridge_s0_translator_avalon_anti_slave_0_readdatavalid, -- .readdatavalid
+ av_waitrequest => rx_bridge_s0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
+ av_debugaccess => rx_bridge_s0_translator_avalon_anti_slave_0_debugaccess -- .debugaccess
+ );
+
+ tx_bridge_m0_translator : component altera_merlin_master_translator_0003
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- reset.reset
+ uav_address => tx_bridge_m0_translator_avalon_universal_master_0_address, -- avalon_universal_master_0.address
+ uav_burstcount => tx_bridge_m0_translator_avalon_universal_master_0_burstcount, -- .burstcount
+ uav_read => tx_bridge_m0_translator_avalon_universal_master_0_read, -- .read
+ uav_write => tx_bridge_m0_translator_avalon_universal_master_0_write, -- .write
+ uav_waitrequest => tx_bridge_m0_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
+ uav_readdatavalid => tx_bridge_m0_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
+ uav_byteenable => tx_bridge_m0_translator_avalon_universal_master_0_byteenable, -- .byteenable
+ uav_readdata => tx_bridge_m0_translator_avalon_universal_master_0_readdata, -- .readdata
+ uav_writedata => tx_bridge_m0_translator_avalon_universal_master_0_writedata, -- .writedata
+ uav_lock => tx_bridge_m0_translator_avalon_universal_master_0_lock, -- .lock
+ uav_debugaccess => tx_bridge_m0_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
+ av_address => tx_bridge_m0_address, -- avalon_anti_master_0.address
+ av_waitrequest => tx_bridge_m0_waitrequest, -- .waitrequest
+ av_burstcount => tx_bridge_m0_burstcount(0), -- .burstcount
+ av_byteenable => tx_bridge_m0_byteenable, -- .byteenable
+ av_read => tx_bridge_m0_read, -- .read
+ av_readdata => tx_bridge_m0_readdata, -- .readdata
+ av_readdatavalid => tx_bridge_m0_readdatavalid, -- .readdatavalid
+ av_write => tx_bridge_m0_write, -- .write
+ av_writedata => tx_bridge_m0_writedata, -- .writedata
+ av_debugaccess => tx_bridge_m0_debugaccess -- .debugaccess
+ );
+
+ tx_eth_pkt_backpressure_control_csr_translator : component altera_merlin_slave_translator_0002
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- reset.reset
+ uav_address => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
+ uav_burstcount => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ uav_read => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ uav_write => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ uav_waitrequest => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ uav_readdatavalid => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ uav_byteenable => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ uav_readdata => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ uav_writedata => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ uav_lock => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ uav_debugaccess => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ av_address => tx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
+ av_write => tx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_write, -- .write
+ av_read => tx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_read, -- .read
+ av_readdata => tx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_readdata, -- .readdata
+ av_writedata => tx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_writedata -- .writedata
+ );
+
+ tx_eth_pad_inserter_csr_translator : component altera_merlin_slave_translator_0002
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- reset.reset
+ uav_address => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
+ uav_burstcount => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ uav_read => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ uav_write => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ uav_waitrequest => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ uav_readdatavalid => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ uav_byteenable => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ uav_readdata => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ uav_writedata => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ uav_lock => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ uav_debugaccess => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ av_address => tx_eth_pad_inserter_csr_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
+ av_write => tx_eth_pad_inserter_csr_translator_avalon_anti_slave_0_write, -- .write
+ av_read => tx_eth_pad_inserter_csr_translator_avalon_anti_slave_0_read, -- .read
+ av_readdata => tx_eth_pad_inserter_csr_translator_avalon_anti_slave_0_readdata, -- .readdata
+ av_writedata => tx_eth_pad_inserter_csr_translator_avalon_anti_slave_0_writedata -- .writedata
+ );
+
+ tx_eth_crc_inserter_csr_translator : component altera_merlin_slave_translator_0002
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- reset.reset
+ uav_address => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
+ uav_burstcount => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ uav_read => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ uav_write => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ uav_waitrequest => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ uav_readdatavalid => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ uav_byteenable => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ uav_readdata => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ uav_writedata => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ uav_lock => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ uav_debugaccess => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ av_address => tx_eth_crc_inserter_csr_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
+ av_write => tx_eth_crc_inserter_csr_translator_avalon_anti_slave_0_write, -- .write
+ av_read => tx_eth_crc_inserter_csr_translator_avalon_anti_slave_0_read, -- .read
+ av_readdata => tx_eth_crc_inserter_csr_translator_avalon_anti_slave_0_readdata, -- .readdata
+ av_writedata => tx_eth_crc_inserter_csr_translator_avalon_anti_slave_0_writedata -- .writedata
+ );
+
+ tx_eth_pause_ctrl_gen_csr_translator : component altera_merlin_slave_translator_0003
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- reset.reset
+ uav_address => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
+ uav_burstcount => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ uav_read => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ uav_write => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ uav_waitrequest => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ uav_readdatavalid => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ uav_byteenable => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ uav_readdata => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ uav_writedata => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ uav_lock => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ uav_debugaccess => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ av_address => tx_eth_pause_ctrl_gen_csr_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
+ av_write => tx_eth_pause_ctrl_gen_csr_translator_avalon_anti_slave_0_write, -- .write
+ av_read => tx_eth_pause_ctrl_gen_csr_translator_avalon_anti_slave_0_read, -- .read
+ av_readdata => tx_eth_pause_ctrl_gen_csr_translator_avalon_anti_slave_0_readdata, -- .readdata
+ av_writedata => tx_eth_pause_ctrl_gen_csr_translator_avalon_anti_slave_0_writedata -- .writedata
+ );
+
+ tx_eth_address_inserter_csr_translator : component altera_merlin_slave_translator_0003
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- reset.reset
+ uav_address => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
+ uav_burstcount => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ uav_read => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ uav_write => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ uav_waitrequest => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ uav_readdatavalid => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ uav_byteenable => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ uav_readdata => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ uav_writedata => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ uav_lock => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ uav_debugaccess => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ av_address => tx_eth_address_inserter_csr_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
+ av_write => tx_eth_address_inserter_csr_translator_avalon_anti_slave_0_write, -- .write
+ av_read => tx_eth_address_inserter_csr_translator_avalon_anti_slave_0_read, -- .read
+ av_readdata => tx_eth_address_inserter_csr_translator_avalon_anti_slave_0_readdata, -- .readdata
+ av_writedata => tx_eth_address_inserter_csr_translator_avalon_anti_slave_0_writedata -- .writedata
+ );
+
+ tx_eth_packet_underflow_control_avalon_slave_0_translator : component altera_merlin_slave_translator_0004
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- reset.reset
+ uav_address => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
+ uav_burstcount => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ uav_read => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ uav_write => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ uav_waitrequest => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ uav_readdatavalid => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ uav_byteenable => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ uav_readdata => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ uav_writedata => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ uav_lock => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ uav_debugaccess => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ av_address => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
+ av_read => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
+ av_readdata => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_anti_slave_0_readdata -- .readdata
+ );
+
+ tx_eth_frame_decoder_avalom_mm_csr_translator : component altera_merlin_slave_translator_0005
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- reset.reset
+ uav_address => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
+ uav_burstcount => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ uav_read => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ uav_write => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ uav_waitrequest => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ uav_readdatavalid => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ uav_byteenable => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ uav_readdata => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ uav_writedata => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ uav_lock => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ uav_debugaccess => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ av_address => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
+ av_write => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_write, -- .write
+ av_read => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_read, -- .read
+ av_readdata => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_readdata, -- .readdata
+ av_writedata => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_writedata -- .writedata
+ );
+
+ tx_eth_statistics_collector_csr_translator : component altera_merlin_slave_translator_0006
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- reset.reset
+ uav_address => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
+ uav_burstcount => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ uav_read => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ uav_write => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ uav_waitrequest => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ uav_readdatavalid => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ uav_byteenable => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ uav_readdata => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ uav_writedata => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ uav_lock => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ uav_debugaccess => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ av_address => tx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
+ av_write => tx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_write, -- .write
+ av_read => tx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_read, -- .read
+ av_readdata => tx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_readdata, -- .readdata
+ av_writedata => tx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_writedata -- .writedata
+ );
+
+ rx_bridge_m0_translator : component altera_merlin_master_translator_0003
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- reset.reset
+ uav_address => rx_bridge_m0_translator_avalon_universal_master_0_address, -- avalon_universal_master_0.address
+ uav_burstcount => rx_bridge_m0_translator_avalon_universal_master_0_burstcount, -- .burstcount
+ uav_read => rx_bridge_m0_translator_avalon_universal_master_0_read, -- .read
+ uav_write => rx_bridge_m0_translator_avalon_universal_master_0_write, -- .write
+ uav_waitrequest => rx_bridge_m0_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
+ uav_readdatavalid => rx_bridge_m0_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
+ uav_byteenable => rx_bridge_m0_translator_avalon_universal_master_0_byteenable, -- .byteenable
+ uav_readdata => rx_bridge_m0_translator_avalon_universal_master_0_readdata, -- .readdata
+ uav_writedata => rx_bridge_m0_translator_avalon_universal_master_0_writedata, -- .writedata
+ uav_lock => rx_bridge_m0_translator_avalon_universal_master_0_lock, -- .lock
+ uav_debugaccess => rx_bridge_m0_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
+ av_address => rx_bridge_m0_address, -- avalon_anti_master_0.address
+ av_waitrequest => rx_bridge_m0_waitrequest, -- .waitrequest
+ av_burstcount => rx_bridge_m0_burstcount(0), -- .burstcount
+ av_byteenable => rx_bridge_m0_byteenable, -- .byteenable
+ av_read => rx_bridge_m0_read, -- .read
+ av_readdata => rx_bridge_m0_readdata, -- .readdata
+ av_readdatavalid => rx_bridge_m0_readdatavalid, -- .readdatavalid
+ av_write => rx_bridge_m0_write, -- .write
+ av_writedata => rx_bridge_m0_writedata, -- .writedata
+ av_debugaccess => rx_bridge_m0_debugaccess -- .debugaccess
+ );
+
+ rx_eth_pkt_backpressure_control_csr_translator : component altera_merlin_slave_translator_0002
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- reset.reset
+ uav_address => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
+ uav_burstcount => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ uav_read => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ uav_write => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ uav_waitrequest => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ uav_readdatavalid => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ uav_byteenable => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ uav_readdata => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ uav_writedata => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ uav_lock => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ uav_debugaccess => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ av_address => rx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
+ av_write => rx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_write, -- .write
+ av_read => rx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_read, -- .read
+ av_readdata => rx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_readdata, -- .readdata
+ av_writedata => rx_eth_pkt_backpressure_control_csr_translator_avalon_anti_slave_0_writedata -- .writedata
+ );
+
+ rx_eth_crc_pad_rem_csr_translator : component altera_merlin_slave_translator_0003
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- reset.reset
+ uav_address => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
+ uav_burstcount => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ uav_read => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ uav_write => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ uav_waitrequest => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ uav_readdatavalid => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ uav_byteenable => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ uav_readdata => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ uav_writedata => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ uav_lock => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ uav_debugaccess => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ av_address => rx_eth_crc_pad_rem_csr_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
+ av_write => rx_eth_crc_pad_rem_csr_translator_avalon_anti_slave_0_write, -- .write
+ av_read => rx_eth_crc_pad_rem_csr_translator_avalon_anti_slave_0_read, -- .read
+ av_readdata => rx_eth_crc_pad_rem_csr_translator_avalon_anti_slave_0_readdata, -- .readdata
+ av_writedata => rx_eth_crc_pad_rem_csr_translator_avalon_anti_slave_0_writedata -- .writedata
+ );
+
+ rx_eth_crc_checker_csr_translator : component altera_merlin_slave_translator_0002
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- reset.reset
+ uav_address => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
+ uav_burstcount => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ uav_read => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ uav_write => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ uav_waitrequest => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ uav_readdatavalid => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ uav_byteenable => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ uav_readdata => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ uav_writedata => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ uav_lock => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ uav_debugaccess => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ av_address => rx_eth_crc_checker_csr_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
+ av_write => rx_eth_crc_checker_csr_translator_avalon_anti_slave_0_write, -- .write
+ av_read => rx_eth_crc_checker_csr_translator_avalon_anti_slave_0_read, -- .read
+ av_readdata => rx_eth_crc_checker_csr_translator_avalon_anti_slave_0_readdata, -- .readdata
+ av_writedata => rx_eth_crc_checker_csr_translator_avalon_anti_slave_0_writedata -- .writedata
+ );
+
+ rx_eth_frame_decoder_avalom_mm_csr_translator : component altera_merlin_slave_translator_0005
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- reset.reset
+ uav_address => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
+ uav_burstcount => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ uav_read => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ uav_write => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ uav_waitrequest => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ uav_readdatavalid => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ uav_byteenable => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ uav_readdata => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ uav_writedata => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ uav_lock => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ uav_debugaccess => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ av_address => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
+ av_write => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_write, -- .write
+ av_read => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_read, -- .read
+ av_readdata => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_readdata, -- .readdata
+ av_writedata => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_anti_slave_0_writedata -- .writedata
+ );
+
+ rx_eth_packet_overflow_control_csr_translator : component altera_merlin_slave_translator_0007
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- reset.reset
+ uav_address => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
+ uav_burstcount => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ uav_read => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ uav_write => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ uav_waitrequest => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ uav_readdatavalid => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ uav_byteenable => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ uav_readdata => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ uav_writedata => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ uav_lock => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ uav_debugaccess => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ av_address => rx_eth_packet_overflow_control_csr_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
+ av_read => rx_eth_packet_overflow_control_csr_translator_avalon_anti_slave_0_read, -- .read
+ av_readdata => rx_eth_packet_overflow_control_csr_translator_avalon_anti_slave_0_readdata -- .readdata
+ );
+
+ rx_eth_statistics_collector_csr_translator : component altera_merlin_slave_translator_0006
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- reset.reset
+ uav_address => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
+ uav_burstcount => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ uav_read => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ uav_write => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ uav_waitrequest => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ uav_readdatavalid => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ uav_byteenable => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ uav_readdata => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ uav_writedata => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ uav_lock => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ uav_debugaccess => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ av_address => rx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
+ av_write => rx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_write, -- .write
+ av_read => rx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_read, -- .read
+ av_readdata => rx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_readdata, -- .readdata
+ av_writedata => rx_eth_statistics_collector_csr_translator_avalon_anti_slave_0_writedata -- .writedata
+ );
+
+ rx_eth_lane_decoder_csr_translator : component altera_merlin_slave_translator_0002
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- reset.reset
+ uav_address => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
+ uav_burstcount => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ uav_read => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ uav_write => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ uav_waitrequest => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ uav_readdatavalid => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ uav_byteenable => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ uav_readdata => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ uav_writedata => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ uav_lock => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ uav_debugaccess => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ av_address => rx_eth_lane_decoder_csr_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
+ av_write => rx_eth_lane_decoder_csr_translator_avalon_anti_slave_0_write, -- .write
+ av_read => rx_eth_lane_decoder_csr_translator_avalon_anti_slave_0_read, -- .read
+ av_readdata => rx_eth_lane_decoder_csr_translator_avalon_anti_slave_0_readdata, -- .readdata
+ av_writedata => rx_eth_lane_decoder_csr_translator_avalon_anti_slave_0_writedata -- .writedata
+ );
+
+ tx_bridge_s0_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent_0001
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ m0_address => tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
+ m0_burstcount => tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ m0_byteenable => tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ m0_debugaccess => tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ m0_lock => tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ m0_readdata => tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ m0_readdatavalid => tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ m0_read => tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ m0_waitrequest => tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ m0_writedata => tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ m0_write => tx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ rp_endofpacket => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
+ rp_ready => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
+ rp_valid => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ rp_data => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ rp_startofpacket => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ cp_ready => crosser_out_ready, -- cp.ready
+ cp_valid => crosser_out_valid, -- .valid
+ cp_data => crosser_out_data, -- .data
+ cp_startofpacket => crosser_out_startofpacket, -- .startofpacket
+ cp_endofpacket => crosser_out_endofpacket, -- .endofpacket
+ cp_channel => crosser_out_channel, -- .channel
+ rf_sink_ready => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
+ rf_sink_valid => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ rf_sink_startofpacket => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ rf_sink_endofpacket => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
+ rf_sink_data => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
+ rf_source_ready => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
+ rf_source_valid => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ rf_source_startofpacket => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ rf_source_endofpacket => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ rf_source_data => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
+ rdata_fifo_sink_ready => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready, -- rdata_fifo_sink.ready
+ rdata_fifo_sink_valid => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid
+ rdata_fifo_sink_data => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- .data
+ rdata_fifo_src_ready => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
+ rdata_fifo_src_valid => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_src_data => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
+ );
+
+ tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo_0001
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ in_data => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
+ in_valid => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ in_ready => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
+ in_startofpacket => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ in_endofpacket => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ out_data => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
+ out_valid => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ out_ready => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
+ out_startofpacket => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ out_endofpacket => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
+ );
+
+ tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo : component altera_avalon_sc_fifo_0002
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ in_data => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- in.data
+ in_valid => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ in_ready => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- .ready
+ out_data => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- out.data
+ out_valid => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid
+ out_ready => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready -- .ready
+ );
+
+ merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent : component altera_merlin_master_agent_0001
+ port map (
+ clk => csr_clk_clk, -- clk.clk
+ reset => rst_controller_reset_out_reset, -- clk_reset.reset
+ av_address => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_address, -- av.address
+ av_write => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_write, -- .write
+ av_read => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_read, -- .read
+ av_writedata => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_writedata, -- .writedata
+ av_readdata => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_readdata, -- .readdata
+ av_waitrequest => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
+ av_readdatavalid => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
+ av_byteenable => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_byteenable, -- .byteenable
+ av_burstcount => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_burstcount, -- .burstcount
+ av_debugaccess => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
+ av_lock => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_lock, -- .lock
+ cp_valid => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent_cp_valid, -- cp.valid
+ cp_data => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent_cp_data, -- .data
+ cp_startofpacket => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
+ cp_endofpacket => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
+ cp_ready => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent_cp_ready, -- .ready
+ rp_valid => limiter_rsp_src_valid, -- rp.valid
+ rp_data => limiter_rsp_src_data, -- .data
+ rp_channel => limiter_rsp_src_channel, -- .channel
+ rp_startofpacket => limiter_rsp_src_startofpacket, -- .startofpacket
+ rp_endofpacket => limiter_rsp_src_endofpacket, -- .endofpacket
+ rp_ready => limiter_rsp_src_ready -- .ready
+ );
+
+ rx_bridge_s0_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent_0002
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ m0_address => rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
+ m0_burstcount => rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ m0_byteenable => rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ m0_debugaccess => rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ m0_lock => rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ m0_readdata => rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ m0_readdatavalid => rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ m0_read => rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ m0_waitrequest => rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ m0_writedata => rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ m0_write => rx_bridge_s0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ rp_endofpacket => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
+ rp_ready => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
+ rp_valid => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ rp_data => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ rp_startofpacket => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ cp_ready => crosser_001_out_ready, -- cp.ready
+ cp_valid => crosser_001_out_valid, -- .valid
+ cp_data => crosser_001_out_data, -- .data
+ cp_startofpacket => crosser_001_out_startofpacket, -- .startofpacket
+ cp_endofpacket => crosser_001_out_endofpacket, -- .endofpacket
+ cp_channel => crosser_001_out_channel, -- .channel
+ rf_sink_ready => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
+ rf_sink_valid => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ rf_sink_startofpacket => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ rf_sink_endofpacket => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
+ rf_sink_data => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
+ rf_source_ready => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
+ rf_source_valid => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ rf_source_startofpacket => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ rf_source_endofpacket => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ rf_source_data => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
+ rdata_fifo_sink_ready => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready, -- rdata_fifo_sink.ready
+ rdata_fifo_sink_valid => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid
+ rdata_fifo_sink_data => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- .data
+ rdata_fifo_src_ready => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
+ rdata_fifo_src_valid => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_src_data => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
+ );
+
+ rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo_0001
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ in_data => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
+ in_valid => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ in_ready => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
+ in_startofpacket => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ in_endofpacket => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ out_data => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
+ out_valid => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ out_ready => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
+ out_startofpacket => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ out_endofpacket => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
+ );
+
+ rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo : component altera_avalon_sc_fifo_0002
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ in_data => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- in.data
+ in_valid => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ in_ready => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- .ready
+ out_data => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- out.data
+ out_valid => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid
+ out_ready => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready -- .ready
+ );
+
+ tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent_0003
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ m0_address => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
+ m0_burstcount => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ m0_byteenable => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ m0_debugaccess => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ m0_lock => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ m0_readdata => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ m0_readdatavalid => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ m0_read => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ m0_waitrequest => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ m0_writedata => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ m0_write => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ rp_endofpacket => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
+ rp_ready => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
+ rp_valid => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ rp_data => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ rp_startofpacket => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ cp_ready => cmd_xbar_demux_001_src7_ready, -- cp.ready
+ cp_valid => cmd_xbar_demux_001_src7_valid, -- .valid
+ cp_data => cmd_xbar_demux_001_src7_data, -- .data
+ cp_startofpacket => cmd_xbar_demux_001_src7_startofpacket, -- .startofpacket
+ cp_endofpacket => cmd_xbar_demux_001_src7_endofpacket, -- .endofpacket
+ cp_channel => cmd_xbar_demux_001_src7_channel, -- .channel
+ rf_sink_ready => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
+ rf_sink_valid => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ rf_sink_startofpacket => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ rf_sink_endofpacket => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
+ rf_sink_data => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
+ rf_source_ready => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
+ rf_source_valid => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ rf_source_startofpacket => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ rf_source_endofpacket => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ rf_source_data => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
+ rdata_fifo_sink_ready => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
+ rdata_fifo_sink_valid => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_sink_data => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
+ rdata_fifo_src_ready => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
+ rdata_fifo_src_valid => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_src_data => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
+ );
+
+ tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo_0003
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ in_data => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
+ in_valid => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ in_ready => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
+ in_startofpacket => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ in_endofpacket => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ out_data => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
+ out_valid => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ out_ready => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
+ out_startofpacket => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ out_endofpacket => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
+ );
+
+ tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent_0004
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ m0_address => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
+ m0_burstcount => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ m0_byteenable => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ m0_debugaccess => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ m0_lock => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ m0_readdata => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ m0_readdatavalid => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ m0_read => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ m0_waitrequest => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ m0_writedata => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ m0_write => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ rp_endofpacket => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
+ rp_ready => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
+ rp_valid => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ rp_data => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ rp_startofpacket => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ cp_ready => cmd_xbar_demux_001_src1_ready, -- cp.ready
+ cp_valid => cmd_xbar_demux_001_src1_valid, -- .valid
+ cp_data => cmd_xbar_demux_001_src1_data, -- .data
+ cp_startofpacket => cmd_xbar_demux_001_src1_startofpacket, -- .startofpacket
+ cp_endofpacket => cmd_xbar_demux_001_src1_endofpacket, -- .endofpacket
+ cp_channel => cmd_xbar_demux_001_src1_channel, -- .channel
+ rf_sink_ready => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
+ rf_sink_valid => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ rf_sink_startofpacket => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ rf_sink_endofpacket => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
+ rf_sink_data => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
+ rf_source_ready => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
+ rf_source_valid => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ rf_source_startofpacket => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ rf_source_endofpacket => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ rf_source_data => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
+ rdata_fifo_sink_ready => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
+ rdata_fifo_sink_valid => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_sink_data => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
+ rdata_fifo_src_ready => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
+ rdata_fifo_src_valid => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_src_data => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
+ );
+
+ tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo_0004
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ in_data => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
+ in_valid => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ in_ready => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
+ in_startofpacket => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ in_endofpacket => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ out_data => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
+ out_valid => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ out_ready => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
+ out_startofpacket => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ out_endofpacket => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
+ );
+
+ tx_bridge_m0_translator_avalon_universal_master_0_agent : component altera_merlin_master_agent_0002
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ av_address => tx_bridge_m0_translator_avalon_universal_master_0_address, -- av.address
+ av_write => tx_bridge_m0_translator_avalon_universal_master_0_write, -- .write
+ av_read => tx_bridge_m0_translator_avalon_universal_master_0_read, -- .read
+ av_writedata => tx_bridge_m0_translator_avalon_universal_master_0_writedata, -- .writedata
+ av_readdata => tx_bridge_m0_translator_avalon_universal_master_0_readdata, -- .readdata
+ av_waitrequest => tx_bridge_m0_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
+ av_readdatavalid => tx_bridge_m0_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
+ av_byteenable => tx_bridge_m0_translator_avalon_universal_master_0_byteenable, -- .byteenable
+ av_burstcount => tx_bridge_m0_translator_avalon_universal_master_0_burstcount, -- .burstcount
+ av_debugaccess => tx_bridge_m0_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
+ av_lock => tx_bridge_m0_translator_avalon_universal_master_0_lock, -- .lock
+ cp_valid => tx_bridge_m0_translator_avalon_universal_master_0_agent_cp_valid, -- cp.valid
+ cp_data => tx_bridge_m0_translator_avalon_universal_master_0_agent_cp_data, -- .data
+ cp_startofpacket => tx_bridge_m0_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
+ cp_endofpacket => tx_bridge_m0_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
+ cp_ready => tx_bridge_m0_translator_avalon_universal_master_0_agent_cp_ready, -- .ready
+ rp_valid => limiter_001_rsp_src_valid, -- rp.valid
+ rp_data => limiter_001_rsp_src_data, -- .data
+ rp_channel => limiter_001_rsp_src_channel, -- .channel
+ rp_startofpacket => limiter_001_rsp_src_startofpacket, -- .startofpacket
+ rp_endofpacket => limiter_001_rsp_src_endofpacket, -- .endofpacket
+ rp_ready => limiter_001_rsp_src_ready -- .ready
+ );
+
+ tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent_0005
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ m0_address => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
+ m0_burstcount => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ m0_byteenable => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ m0_debugaccess => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ m0_lock => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ m0_readdata => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ m0_readdatavalid => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ m0_read => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ m0_waitrequest => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ m0_writedata => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ m0_write => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ rp_endofpacket => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
+ rp_ready => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
+ rp_valid => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ rp_data => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ rp_startofpacket => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ cp_ready => cmd_xbar_demux_001_src2_ready, -- cp.ready
+ cp_valid => cmd_xbar_demux_001_src2_valid, -- .valid
+ cp_data => cmd_xbar_demux_001_src2_data, -- .data
+ cp_startofpacket => cmd_xbar_demux_001_src2_startofpacket, -- .startofpacket
+ cp_endofpacket => cmd_xbar_demux_001_src2_endofpacket, -- .endofpacket
+ cp_channel => cmd_xbar_demux_001_src2_channel, -- .channel
+ rf_sink_ready => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
+ rf_sink_valid => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ rf_sink_startofpacket => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ rf_sink_endofpacket => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
+ rf_sink_data => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
+ rf_source_ready => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
+ rf_source_valid => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ rf_source_startofpacket => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ rf_source_endofpacket => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ rf_source_data => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
+ rdata_fifo_sink_ready => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
+ rdata_fifo_sink_valid => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_sink_data => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
+ rdata_fifo_src_ready => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
+ rdata_fifo_src_valid => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_src_data => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
+ );
+
+ tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo_0004
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ in_data => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
+ in_valid => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ in_ready => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
+ in_startofpacket => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ in_endofpacket => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ out_data => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
+ out_valid => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ out_ready => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
+ out_startofpacket => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ out_endofpacket => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
+ );
+
+ tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent_0006
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ m0_address => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
+ m0_burstcount => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ m0_byteenable => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ m0_debugaccess => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ m0_lock => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ m0_readdata => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ m0_readdatavalid => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ m0_read => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ m0_waitrequest => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ m0_writedata => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ m0_write => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ rp_endofpacket => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
+ rp_ready => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
+ rp_valid => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ rp_data => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ rp_startofpacket => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ cp_ready => cmd_xbar_demux_001_src4_ready, -- cp.ready
+ cp_valid => cmd_xbar_demux_001_src4_valid, -- .valid
+ cp_data => cmd_xbar_demux_001_src4_data, -- .data
+ cp_startofpacket => cmd_xbar_demux_001_src4_startofpacket, -- .startofpacket
+ cp_endofpacket => cmd_xbar_demux_001_src4_endofpacket, -- .endofpacket
+ cp_channel => cmd_xbar_demux_001_src4_channel, -- .channel
+ rf_sink_ready => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
+ rf_sink_valid => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ rf_sink_startofpacket => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ rf_sink_endofpacket => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
+ rf_sink_data => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
+ rf_source_ready => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
+ rf_source_valid => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ rf_source_startofpacket => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ rf_source_endofpacket => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ rf_source_data => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
+ rdata_fifo_sink_ready => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
+ rdata_fifo_sink_valid => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_sink_data => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
+ rdata_fifo_src_ready => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
+ rdata_fifo_src_valid => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_src_data => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
+ );
+
+ tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo_0004
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ in_data => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
+ in_valid => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ in_ready => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
+ in_startofpacket => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ in_endofpacket => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ out_data => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
+ out_valid => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ out_ready => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
+ out_startofpacket => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ out_endofpacket => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
+ );
+
+ tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent_0007
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ m0_address => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
+ m0_burstcount => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ m0_byteenable => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ m0_debugaccess => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ m0_lock => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ m0_readdata => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ m0_readdatavalid => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ m0_read => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ m0_waitrequest => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ m0_writedata => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ m0_write => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ rp_endofpacket => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
+ rp_ready => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
+ rp_valid => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ rp_data => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ rp_startofpacket => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ cp_ready => cmd_xbar_demux_001_src6_ready, -- cp.ready
+ cp_valid => cmd_xbar_demux_001_src6_valid, -- .valid
+ cp_data => cmd_xbar_demux_001_src6_data, -- .data
+ cp_startofpacket => cmd_xbar_demux_001_src6_startofpacket, -- .startofpacket
+ cp_endofpacket => cmd_xbar_demux_001_src6_endofpacket, -- .endofpacket
+ cp_channel => cmd_xbar_demux_001_src6_channel, -- .channel
+ rf_sink_ready => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
+ rf_sink_valid => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ rf_sink_startofpacket => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ rf_sink_endofpacket => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
+ rf_sink_data => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
+ rf_source_ready => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
+ rf_source_valid => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ rf_source_startofpacket => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ rf_source_endofpacket => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ rf_source_data => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
+ rdata_fifo_sink_ready => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
+ rdata_fifo_sink_valid => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_sink_data => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
+ rdata_fifo_src_ready => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
+ rdata_fifo_src_valid => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_src_data => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
+ );
+
+ tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo_0004
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ in_data => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
+ in_valid => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ in_ready => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
+ in_startofpacket => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ in_endofpacket => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ out_data => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
+ out_valid => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ out_ready => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
+ out_startofpacket => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ out_endofpacket => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
+ );
+
+ tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent_0008
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ m0_address => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
+ m0_burstcount => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ m0_byteenable => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ m0_debugaccess => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ m0_lock => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ m0_readdata => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ m0_readdatavalid => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ m0_read => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ m0_waitrequest => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ m0_writedata => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ m0_write => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ rp_endofpacket => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
+ rp_ready => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
+ rp_valid => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ rp_data => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ rp_startofpacket => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ cp_ready => cmd_xbar_demux_001_src0_ready, -- cp.ready
+ cp_valid => cmd_xbar_demux_001_src0_valid, -- .valid
+ cp_data => cmd_xbar_demux_001_src0_data, -- .data
+ cp_startofpacket => cmd_xbar_demux_001_src0_startofpacket, -- .startofpacket
+ cp_endofpacket => cmd_xbar_demux_001_src0_endofpacket, -- .endofpacket
+ cp_channel => cmd_xbar_demux_001_src0_channel, -- .channel
+ rf_sink_ready => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
+ rf_sink_valid => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ rf_sink_startofpacket => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ rf_sink_endofpacket => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
+ rf_sink_data => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
+ rf_source_ready => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
+ rf_source_valid => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ rf_source_startofpacket => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ rf_source_endofpacket => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ rf_source_data => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
+ rdata_fifo_sink_ready => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
+ rdata_fifo_sink_valid => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_sink_data => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
+ rdata_fifo_src_ready => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
+ rdata_fifo_src_valid => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_src_data => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
+ );
+
+ tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo_0004
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ in_data => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
+ in_valid => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ in_ready => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
+ in_startofpacket => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ in_endofpacket => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ out_data => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
+ out_valid => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ out_ready => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
+ out_startofpacket => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ out_endofpacket => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
+ );
+
+ tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent_0009
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ m0_address => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
+ m0_burstcount => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ m0_byteenable => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ m0_debugaccess => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ m0_lock => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ m0_readdata => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ m0_readdatavalid => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ m0_read => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ m0_waitrequest => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ m0_writedata => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ m0_write => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ rp_endofpacket => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
+ rp_ready => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
+ rp_valid => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ rp_data => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ rp_startofpacket => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ cp_ready => cmd_xbar_demux_001_src5_ready, -- cp.ready
+ cp_valid => cmd_xbar_demux_001_src5_valid, -- .valid
+ cp_data => cmd_xbar_demux_001_src5_data, -- .data
+ cp_startofpacket => cmd_xbar_demux_001_src5_startofpacket, -- .startofpacket
+ cp_endofpacket => cmd_xbar_demux_001_src5_endofpacket, -- .endofpacket
+ cp_channel => cmd_xbar_demux_001_src5_channel, -- .channel
+ rf_sink_ready => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
+ rf_sink_valid => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ rf_sink_startofpacket => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ rf_sink_endofpacket => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
+ rf_sink_data => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
+ rf_source_ready => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
+ rf_source_valid => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ rf_source_startofpacket => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ rf_source_endofpacket => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ rf_source_data => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
+ rdata_fifo_sink_ready => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
+ rdata_fifo_sink_valid => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_sink_data => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
+ rdata_fifo_src_ready => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
+ rdata_fifo_src_valid => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_src_data => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
+ );
+
+ tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo_0004
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ in_data => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
+ in_valid => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ in_ready => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
+ in_startofpacket => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ in_endofpacket => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ out_data => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
+ out_valid => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ out_ready => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
+ out_startofpacket => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ out_endofpacket => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
+ );
+
+ tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent_0010
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ m0_address => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
+ m0_burstcount => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ m0_byteenable => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ m0_debugaccess => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ m0_lock => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ m0_readdata => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ m0_readdatavalid => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ m0_read => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ m0_waitrequest => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ m0_writedata => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ m0_write => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ rp_endofpacket => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
+ rp_ready => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
+ rp_valid => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ rp_data => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ rp_startofpacket => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ cp_ready => cmd_xbar_demux_001_src3_ready, -- cp.ready
+ cp_valid => cmd_xbar_demux_001_src3_valid, -- .valid
+ cp_data => cmd_xbar_demux_001_src3_data, -- .data
+ cp_startofpacket => cmd_xbar_demux_001_src3_startofpacket, -- .startofpacket
+ cp_endofpacket => cmd_xbar_demux_001_src3_endofpacket, -- .endofpacket
+ cp_channel => cmd_xbar_demux_001_src3_channel, -- .channel
+ rf_sink_ready => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
+ rf_sink_valid => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ rf_sink_startofpacket => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ rf_sink_endofpacket => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
+ rf_sink_data => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
+ rf_source_ready => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
+ rf_source_valid => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ rf_source_startofpacket => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ rf_source_endofpacket => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ rf_source_data => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
+ rdata_fifo_sink_ready => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
+ rdata_fifo_sink_valid => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_sink_data => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
+ rdata_fifo_src_ready => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
+ rdata_fifo_src_valid => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_src_data => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
+ );
+
+ tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo_0004
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ in_data => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
+ in_valid => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ in_ready => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
+ in_startofpacket => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ in_endofpacket => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ out_data => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
+ out_valid => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ out_ready => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
+ out_startofpacket => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ out_endofpacket => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
+ );
+
+ rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent_0011
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ m0_address => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
+ m0_burstcount => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ m0_byteenable => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ m0_debugaccess => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ m0_lock => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ m0_readdata => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ m0_readdatavalid => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ m0_read => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ m0_waitrequest => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ m0_writedata => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ m0_write => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ rp_endofpacket => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
+ rp_ready => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
+ rp_valid => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ rp_data => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ rp_startofpacket => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ cp_ready => cmd_xbar_demux_002_src1_ready, -- cp.ready
+ cp_valid => cmd_xbar_demux_002_src1_valid, -- .valid
+ cp_data => cmd_xbar_demux_002_src1_data, -- .data
+ cp_startofpacket => cmd_xbar_demux_002_src1_startofpacket, -- .startofpacket
+ cp_endofpacket => cmd_xbar_demux_002_src1_endofpacket, -- .endofpacket
+ cp_channel => cmd_xbar_demux_002_src1_channel, -- .channel
+ rf_sink_ready => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
+ rf_sink_valid => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ rf_sink_startofpacket => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ rf_sink_endofpacket => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
+ rf_sink_data => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
+ rf_source_ready => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
+ rf_source_valid => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ rf_source_startofpacket => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ rf_source_endofpacket => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ rf_source_data => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
+ rdata_fifo_sink_ready => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
+ rdata_fifo_sink_valid => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_sink_data => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
+ rdata_fifo_src_ready => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
+ rdata_fifo_src_valid => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_src_data => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
+ );
+
+ rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo_0004
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ in_data => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
+ in_valid => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ in_ready => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
+ in_startofpacket => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ in_endofpacket => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ out_data => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
+ out_valid => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ out_ready => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
+ out_startofpacket => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ out_endofpacket => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
+ );
+
+ rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent_0012
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ m0_address => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
+ m0_burstcount => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ m0_byteenable => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ m0_debugaccess => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ m0_lock => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ m0_readdata => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ m0_readdatavalid => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ m0_read => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ m0_waitrequest => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ m0_writedata => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ m0_write => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ rp_endofpacket => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
+ rp_ready => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
+ rp_valid => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ rp_data => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ rp_startofpacket => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ cp_ready => cmd_xbar_demux_002_src3_ready, -- cp.ready
+ cp_valid => cmd_xbar_demux_002_src3_valid, -- .valid
+ cp_data => cmd_xbar_demux_002_src3_data, -- .data
+ cp_startofpacket => cmd_xbar_demux_002_src3_startofpacket, -- .startofpacket
+ cp_endofpacket => cmd_xbar_demux_002_src3_endofpacket, -- .endofpacket
+ cp_channel => cmd_xbar_demux_002_src3_channel, -- .channel
+ rf_sink_ready => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
+ rf_sink_valid => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ rf_sink_startofpacket => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ rf_sink_endofpacket => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
+ rf_sink_data => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
+ rf_source_ready => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
+ rf_source_valid => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ rf_source_startofpacket => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ rf_source_endofpacket => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ rf_source_data => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
+ rdata_fifo_sink_ready => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
+ rdata_fifo_sink_valid => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_sink_data => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
+ rdata_fifo_src_ready => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
+ rdata_fifo_src_valid => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_src_data => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
+ );
+
+ rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo_0004
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ in_data => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
+ in_valid => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ in_ready => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
+ in_startofpacket => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ in_endofpacket => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ out_data => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
+ out_valid => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ out_ready => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
+ out_startofpacket => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ out_endofpacket => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
+ );
+
+ rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent_0013
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ m0_address => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
+ m0_burstcount => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ m0_byteenable => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ m0_debugaccess => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ m0_lock => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ m0_readdata => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ m0_readdatavalid => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ m0_read => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ m0_waitrequest => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ m0_writedata => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ m0_write => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ rp_endofpacket => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
+ rp_ready => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
+ rp_valid => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ rp_data => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ rp_startofpacket => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ cp_ready => cmd_xbar_demux_002_src2_ready, -- cp.ready
+ cp_valid => cmd_xbar_demux_002_src2_valid, -- .valid
+ cp_data => cmd_xbar_demux_002_src2_data, -- .data
+ cp_startofpacket => cmd_xbar_demux_002_src2_startofpacket, -- .startofpacket
+ cp_endofpacket => cmd_xbar_demux_002_src2_endofpacket, -- .endofpacket
+ cp_channel => cmd_xbar_demux_002_src2_channel, -- .channel
+ rf_sink_ready => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
+ rf_sink_valid => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ rf_sink_startofpacket => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ rf_sink_endofpacket => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
+ rf_sink_data => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
+ rf_source_ready => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
+ rf_source_valid => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ rf_source_startofpacket => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ rf_source_endofpacket => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ rf_source_data => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
+ rdata_fifo_sink_ready => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
+ rdata_fifo_sink_valid => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_sink_data => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
+ rdata_fifo_src_ready => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
+ rdata_fifo_src_valid => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_src_data => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
+ );
+
+ rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo_0004
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ in_data => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
+ in_valid => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ in_ready => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
+ in_startofpacket => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ in_endofpacket => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ out_data => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
+ out_valid => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ out_ready => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
+ out_startofpacket => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ out_endofpacket => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
+ );
+
+ rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent_0014
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ m0_address => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
+ m0_burstcount => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ m0_byteenable => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ m0_debugaccess => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ m0_lock => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ m0_readdata => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ m0_readdatavalid => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ m0_read => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ m0_waitrequest => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ m0_writedata => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ m0_write => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ rp_endofpacket => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
+ rp_ready => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
+ rp_valid => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ rp_data => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ rp_startofpacket => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ cp_ready => cmd_xbar_demux_002_src6_ready, -- cp.ready
+ cp_valid => cmd_xbar_demux_002_src6_valid, -- .valid
+ cp_data => cmd_xbar_demux_002_src6_data, -- .data
+ cp_startofpacket => cmd_xbar_demux_002_src6_startofpacket, -- .startofpacket
+ cp_endofpacket => cmd_xbar_demux_002_src6_endofpacket, -- .endofpacket
+ cp_channel => cmd_xbar_demux_002_src6_channel, -- .channel
+ rf_sink_ready => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
+ rf_sink_valid => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ rf_sink_startofpacket => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ rf_sink_endofpacket => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
+ rf_sink_data => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
+ rf_source_ready => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
+ rf_source_valid => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ rf_source_startofpacket => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ rf_source_endofpacket => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ rf_source_data => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
+ rdata_fifo_sink_ready => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
+ rdata_fifo_sink_valid => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_sink_data => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
+ rdata_fifo_src_ready => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
+ rdata_fifo_src_valid => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_src_data => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
+ );
+
+ rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo_0004
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ in_data => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
+ in_valid => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ in_ready => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
+ in_startofpacket => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ in_endofpacket => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ out_data => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
+ out_valid => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ out_ready => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
+ out_startofpacket => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ out_endofpacket => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
+ );
+
+ rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent_0015
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ m0_address => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
+ m0_burstcount => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ m0_byteenable => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ m0_debugaccess => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ m0_lock => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ m0_readdata => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ m0_readdatavalid => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ m0_read => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ m0_waitrequest => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ m0_writedata => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ m0_write => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ rp_endofpacket => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
+ rp_ready => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
+ rp_valid => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ rp_data => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ rp_startofpacket => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ cp_ready => cmd_xbar_demux_002_src4_ready, -- cp.ready
+ cp_valid => cmd_xbar_demux_002_src4_valid, -- .valid
+ cp_data => cmd_xbar_demux_002_src4_data, -- .data
+ cp_startofpacket => cmd_xbar_demux_002_src4_startofpacket, -- .startofpacket
+ cp_endofpacket => cmd_xbar_demux_002_src4_endofpacket, -- .endofpacket
+ cp_channel => cmd_xbar_demux_002_src4_channel, -- .channel
+ rf_sink_ready => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
+ rf_sink_valid => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ rf_sink_startofpacket => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ rf_sink_endofpacket => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
+ rf_sink_data => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
+ rf_source_ready => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
+ rf_source_valid => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ rf_source_startofpacket => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ rf_source_endofpacket => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ rf_source_data => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
+ rdata_fifo_sink_ready => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
+ rdata_fifo_sink_valid => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_sink_data => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
+ rdata_fifo_src_ready => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
+ rdata_fifo_src_valid => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_src_data => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
+ );
+
+ rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo_0004
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ in_data => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
+ in_valid => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ in_ready => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
+ in_startofpacket => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ in_endofpacket => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ out_data => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
+ out_valid => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ out_ready => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
+ out_startofpacket => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ out_endofpacket => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
+ );
+
+ rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent_0016
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ m0_address => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
+ m0_burstcount => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ m0_byteenable => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ m0_debugaccess => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ m0_lock => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ m0_readdata => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ m0_readdatavalid => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ m0_read => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ m0_waitrequest => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ m0_writedata => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ m0_write => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ rp_endofpacket => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
+ rp_ready => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
+ rp_valid => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ rp_data => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ rp_startofpacket => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ cp_ready => cmd_xbar_demux_002_src0_ready, -- cp.ready
+ cp_valid => cmd_xbar_demux_002_src0_valid, -- .valid
+ cp_data => cmd_xbar_demux_002_src0_data, -- .data
+ cp_startofpacket => cmd_xbar_demux_002_src0_startofpacket, -- .startofpacket
+ cp_endofpacket => cmd_xbar_demux_002_src0_endofpacket, -- .endofpacket
+ cp_channel => cmd_xbar_demux_002_src0_channel, -- .channel
+ rf_sink_ready => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
+ rf_sink_valid => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ rf_sink_startofpacket => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ rf_sink_endofpacket => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
+ rf_sink_data => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
+ rf_source_ready => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
+ rf_source_valid => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ rf_source_startofpacket => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ rf_source_endofpacket => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ rf_source_data => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
+ rdata_fifo_sink_ready => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
+ rdata_fifo_sink_valid => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_sink_data => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
+ rdata_fifo_src_ready => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
+ rdata_fifo_src_valid => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_src_data => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
+ );
+
+ rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo_0004
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ in_data => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
+ in_valid => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ in_ready => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
+ in_startofpacket => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ in_endofpacket => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ out_data => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
+ out_valid => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ out_ready => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
+ out_startofpacket => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ out_endofpacket => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
+ );
+
+ rx_bridge_m0_translator_avalon_universal_master_0_agent : component altera_merlin_master_agent_0003
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ av_address => rx_bridge_m0_translator_avalon_universal_master_0_address, -- av.address
+ av_write => rx_bridge_m0_translator_avalon_universal_master_0_write, -- .write
+ av_read => rx_bridge_m0_translator_avalon_universal_master_0_read, -- .read
+ av_writedata => rx_bridge_m0_translator_avalon_universal_master_0_writedata, -- .writedata
+ av_readdata => rx_bridge_m0_translator_avalon_universal_master_0_readdata, -- .readdata
+ av_waitrequest => rx_bridge_m0_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
+ av_readdatavalid => rx_bridge_m0_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
+ av_byteenable => rx_bridge_m0_translator_avalon_universal_master_0_byteenable, -- .byteenable
+ av_burstcount => rx_bridge_m0_translator_avalon_universal_master_0_burstcount, -- .burstcount
+ av_debugaccess => rx_bridge_m0_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
+ av_lock => rx_bridge_m0_translator_avalon_universal_master_0_lock, -- .lock
+ cp_valid => rx_bridge_m0_translator_avalon_universal_master_0_agent_cp_valid, -- cp.valid
+ cp_data => rx_bridge_m0_translator_avalon_universal_master_0_agent_cp_data, -- .data
+ cp_startofpacket => rx_bridge_m0_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
+ cp_endofpacket => rx_bridge_m0_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
+ cp_ready => rx_bridge_m0_translator_avalon_universal_master_0_agent_cp_ready, -- .ready
+ rp_valid => limiter_002_rsp_src_valid, -- rp.valid
+ rp_data => limiter_002_rsp_src_data, -- .data
+ rp_channel => limiter_002_rsp_src_channel, -- .channel
+ rp_startofpacket => limiter_002_rsp_src_startofpacket, -- .startofpacket
+ rp_endofpacket => limiter_002_rsp_src_endofpacket, -- .endofpacket
+ rp_ready => limiter_002_rsp_src_ready -- .ready
+ );
+
+ rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent_0017
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ m0_address => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
+ m0_burstcount => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
+ m0_byteenable => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
+ m0_debugaccess => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
+ m0_lock => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
+ m0_readdata => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
+ m0_readdatavalid => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
+ m0_read => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_read, -- .read
+ m0_waitrequest => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
+ m0_writedata => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
+ m0_write => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_m0_write, -- .write
+ rp_endofpacket => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
+ rp_ready => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
+ rp_valid => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ rp_data => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ rp_startofpacket => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ cp_ready => cmd_xbar_demux_002_src5_ready, -- cp.ready
+ cp_valid => cmd_xbar_demux_002_src5_valid, -- .valid
+ cp_data => cmd_xbar_demux_002_src5_data, -- .data
+ cp_startofpacket => cmd_xbar_demux_002_src5_startofpacket, -- .startofpacket
+ cp_endofpacket => cmd_xbar_demux_002_src5_endofpacket, -- .endofpacket
+ cp_channel => cmd_xbar_demux_002_src5_channel, -- .channel
+ rf_sink_ready => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
+ rf_sink_valid => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ rf_sink_startofpacket => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ rf_sink_endofpacket => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
+ rf_sink_data => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
+ rf_source_ready => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
+ rf_source_valid => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ rf_source_startofpacket => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ rf_source_endofpacket => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ rf_source_data => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
+ rdata_fifo_sink_ready => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
+ rdata_fifo_sink_valid => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_sink_data => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
+ rdata_fifo_src_ready => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
+ rdata_fifo_src_valid => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
+ rdata_fifo_src_data => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
+ );
+
+ rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo_0003
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ in_data => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
+ in_valid => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
+ in_ready => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
+ in_startofpacket => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
+ in_endofpacket => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
+ out_data => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
+ out_valid => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
+ out_ready => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
+ out_startofpacket => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
+ out_endofpacket => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
+ );
+
+ addr_router : component altera_merlin_router_0001
+ port map (
+ sink_ready => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent_cp_ready, -- sink.ready
+ sink_valid => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent_cp_valid, -- .valid
+ sink_data => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent_cp_data, -- .data
+ sink_startofpacket => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
+ sink_endofpacket => merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
+ clk => csr_clk_clk, -- clk.clk
+ reset => rst_controller_reset_out_reset, -- clk_reset.reset
+ src_ready => addr_router_src_ready, -- src.ready
+ src_valid => addr_router_src_valid, -- .valid
+ src_data => addr_router_src_data, -- .data
+ src_channel => addr_router_src_channel, -- .channel
+ src_startofpacket => addr_router_src_startofpacket, -- .startofpacket
+ src_endofpacket => addr_router_src_endofpacket -- .endofpacket
+ );
+
+ id_router : component altera_merlin_router_0002
+ port map (
+ sink_ready => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
+ sink_valid => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ sink_data => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ sink_startofpacket => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ sink_endofpacket => tx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ src_ready => id_router_src_ready, -- src.ready
+ src_valid => id_router_src_valid, -- .valid
+ src_data => id_router_src_data, -- .data
+ src_channel => id_router_src_channel, -- .channel
+ src_startofpacket => id_router_src_startofpacket, -- .startofpacket
+ src_endofpacket => id_router_src_endofpacket -- .endofpacket
+ );
+
+ id_router_001 : component altera_merlin_router_0002
+ port map (
+ sink_ready => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
+ sink_valid => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ sink_data => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ sink_startofpacket => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ sink_endofpacket => rx_bridge_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ src_ready => id_router_001_src_ready, -- src.ready
+ src_valid => id_router_001_src_valid, -- .valid
+ src_data => id_router_001_src_data, -- .data
+ src_channel => id_router_001_src_channel, -- .channel
+ src_startofpacket => id_router_001_src_startofpacket, -- .startofpacket
+ src_endofpacket => id_router_001_src_endofpacket -- .endofpacket
+ );
+
+ addr_router_001 : component altera_merlin_router_0003
+ port map (
+ sink_ready => tx_bridge_m0_translator_avalon_universal_master_0_agent_cp_ready, -- sink.ready
+ sink_valid => tx_bridge_m0_translator_avalon_universal_master_0_agent_cp_valid, -- .valid
+ sink_data => tx_bridge_m0_translator_avalon_universal_master_0_agent_cp_data, -- .data
+ sink_startofpacket => tx_bridge_m0_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
+ sink_endofpacket => tx_bridge_m0_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ src_ready => addr_router_001_src_ready, -- src.ready
+ src_valid => addr_router_001_src_valid, -- .valid
+ src_data => addr_router_001_src_data, -- .data
+ src_channel => addr_router_001_src_channel, -- .channel
+ src_startofpacket => addr_router_001_src_startofpacket, -- .startofpacket
+ src_endofpacket => addr_router_001_src_endofpacket -- .endofpacket
+ );
+
+ id_router_002 : component altera_merlin_router_0004
+ port map (
+ sink_ready => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
+ sink_valid => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ sink_data => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ sink_startofpacket => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ sink_endofpacket => tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ src_ready => id_router_002_src_ready, -- src.ready
+ src_valid => id_router_002_src_valid, -- .valid
+ src_data => id_router_002_src_data, -- .data
+ src_channel => id_router_002_src_channel, -- .channel
+ src_startofpacket => id_router_002_src_startofpacket, -- .startofpacket
+ src_endofpacket => id_router_002_src_endofpacket -- .endofpacket
+ );
+
+ id_router_003 : component altera_merlin_router_0004
+ port map (
+ sink_ready => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
+ sink_valid => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ sink_data => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ sink_startofpacket => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ sink_endofpacket => tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ src_ready => id_router_003_src_ready, -- src.ready
+ src_valid => id_router_003_src_valid, -- .valid
+ src_data => id_router_003_src_data, -- .data
+ src_channel => id_router_003_src_channel, -- .channel
+ src_startofpacket => id_router_003_src_startofpacket, -- .startofpacket
+ src_endofpacket => id_router_003_src_endofpacket -- .endofpacket
+ );
+
+ id_router_004 : component altera_merlin_router_0004
+ port map (
+ sink_ready => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
+ sink_valid => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ sink_data => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ sink_startofpacket => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ sink_endofpacket => tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ src_ready => id_router_004_src_ready, -- src.ready
+ src_valid => id_router_004_src_valid, -- .valid
+ src_data => id_router_004_src_data, -- .data
+ src_channel => id_router_004_src_channel, -- .channel
+ src_startofpacket => id_router_004_src_startofpacket, -- .startofpacket
+ src_endofpacket => id_router_004_src_endofpacket -- .endofpacket
+ );
+
+ id_router_005 : component altera_merlin_router_0004
+ port map (
+ sink_ready => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
+ sink_valid => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ sink_data => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ sink_startofpacket => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ sink_endofpacket => tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ src_ready => id_router_005_src_ready, -- src.ready
+ src_valid => id_router_005_src_valid, -- .valid
+ src_data => id_router_005_src_data, -- .data
+ src_channel => id_router_005_src_channel, -- .channel
+ src_startofpacket => id_router_005_src_startofpacket, -- .startofpacket
+ src_endofpacket => id_router_005_src_endofpacket -- .endofpacket
+ );
+
+ id_router_006 : component altera_merlin_router_0004
+ port map (
+ sink_ready => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
+ sink_valid => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ sink_data => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ sink_startofpacket => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ sink_endofpacket => tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ src_ready => id_router_006_src_ready, -- src.ready
+ src_valid => id_router_006_src_valid, -- .valid
+ src_data => id_router_006_src_data, -- .data
+ src_channel => id_router_006_src_channel, -- .channel
+ src_startofpacket => id_router_006_src_startofpacket, -- .startofpacket
+ src_endofpacket => id_router_006_src_endofpacket -- .endofpacket
+ );
+
+ id_router_007 : component altera_merlin_router_0004
+ port map (
+ sink_ready => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
+ sink_valid => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ sink_data => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ sink_startofpacket => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ sink_endofpacket => tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ src_ready => id_router_007_src_ready, -- src.ready
+ src_valid => id_router_007_src_valid, -- .valid
+ src_data => id_router_007_src_data, -- .data
+ src_channel => id_router_007_src_channel, -- .channel
+ src_startofpacket => id_router_007_src_startofpacket, -- .startofpacket
+ src_endofpacket => id_router_007_src_endofpacket -- .endofpacket
+ );
+
+ id_router_008 : component altera_merlin_router_0004
+ port map (
+ sink_ready => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
+ sink_valid => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ sink_data => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ sink_startofpacket => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ sink_endofpacket => tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ src_ready => id_router_008_src_ready, -- src.ready
+ src_valid => id_router_008_src_valid, -- .valid
+ src_data => id_router_008_src_data, -- .data
+ src_channel => id_router_008_src_channel, -- .channel
+ src_startofpacket => id_router_008_src_startofpacket, -- .startofpacket
+ src_endofpacket => id_router_008_src_endofpacket -- .endofpacket
+ );
+
+ id_router_009 : component altera_merlin_router_0004
+ port map (
+ sink_ready => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
+ sink_valid => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ sink_data => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ sink_startofpacket => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ sink_endofpacket => tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ src_ready => id_router_009_src_ready, -- src.ready
+ src_valid => id_router_009_src_valid, -- .valid
+ src_data => id_router_009_src_data, -- .data
+ src_channel => id_router_009_src_channel, -- .channel
+ src_startofpacket => id_router_009_src_startofpacket, -- .startofpacket
+ src_endofpacket => id_router_009_src_endofpacket -- .endofpacket
+ );
+
+ addr_router_002 : component altera_merlin_router_0005
+ port map (
+ sink_ready => rx_bridge_m0_translator_avalon_universal_master_0_agent_cp_ready, -- sink.ready
+ sink_valid => rx_bridge_m0_translator_avalon_universal_master_0_agent_cp_valid, -- .valid
+ sink_data => rx_bridge_m0_translator_avalon_universal_master_0_agent_cp_data, -- .data
+ sink_startofpacket => rx_bridge_m0_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
+ sink_endofpacket => rx_bridge_m0_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ src_ready => addr_router_002_src_ready, -- src.ready
+ src_valid => addr_router_002_src_valid, -- .valid
+ src_data => addr_router_002_src_data, -- .data
+ src_channel => addr_router_002_src_channel, -- .channel
+ src_startofpacket => addr_router_002_src_startofpacket, -- .startofpacket
+ src_endofpacket => addr_router_002_src_endofpacket -- .endofpacket
+ );
+
+ id_router_010 : component altera_merlin_router_0006
+ port map (
+ sink_ready => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
+ sink_valid => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ sink_data => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ sink_startofpacket => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ sink_endofpacket => rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ src_ready => id_router_010_src_ready, -- src.ready
+ src_valid => id_router_010_src_valid, -- .valid
+ src_data => id_router_010_src_data, -- .data
+ src_channel => id_router_010_src_channel, -- .channel
+ src_startofpacket => id_router_010_src_startofpacket, -- .startofpacket
+ src_endofpacket => id_router_010_src_endofpacket -- .endofpacket
+ );
+
+ id_router_011 : component altera_merlin_router_0006
+ port map (
+ sink_ready => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
+ sink_valid => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ sink_data => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ sink_startofpacket => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ sink_endofpacket => rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ src_ready => id_router_011_src_ready, -- src.ready
+ src_valid => id_router_011_src_valid, -- .valid
+ src_data => id_router_011_src_data, -- .data
+ src_channel => id_router_011_src_channel, -- .channel
+ src_startofpacket => id_router_011_src_startofpacket, -- .startofpacket
+ src_endofpacket => id_router_011_src_endofpacket -- .endofpacket
+ );
+
+ id_router_012 : component altera_merlin_router_0006
+ port map (
+ sink_ready => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
+ sink_valid => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ sink_data => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ sink_startofpacket => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ sink_endofpacket => rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ src_ready => id_router_012_src_ready, -- src.ready
+ src_valid => id_router_012_src_valid, -- .valid
+ src_data => id_router_012_src_data, -- .data
+ src_channel => id_router_012_src_channel, -- .channel
+ src_startofpacket => id_router_012_src_startofpacket, -- .startofpacket
+ src_endofpacket => id_router_012_src_endofpacket -- .endofpacket
+ );
+
+ id_router_013 : component altera_merlin_router_0006
+ port map (
+ sink_ready => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
+ sink_valid => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ sink_data => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ sink_startofpacket => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ sink_endofpacket => rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ src_ready => id_router_013_src_ready, -- src.ready
+ src_valid => id_router_013_src_valid, -- .valid
+ src_data => id_router_013_src_data, -- .data
+ src_channel => id_router_013_src_channel, -- .channel
+ src_startofpacket => id_router_013_src_startofpacket, -- .startofpacket
+ src_endofpacket => id_router_013_src_endofpacket -- .endofpacket
+ );
+
+ id_router_014 : component altera_merlin_router_0006
+ port map (
+ sink_ready => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
+ sink_valid => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ sink_data => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ sink_startofpacket => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ sink_endofpacket => rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ src_ready => id_router_014_src_ready, -- src.ready
+ src_valid => id_router_014_src_valid, -- .valid
+ src_data => id_router_014_src_data, -- .data
+ src_channel => id_router_014_src_channel, -- .channel
+ src_startofpacket => id_router_014_src_startofpacket, -- .startofpacket
+ src_endofpacket => id_router_014_src_endofpacket -- .endofpacket
+ );
+
+ id_router_015 : component altera_merlin_router_0006
+ port map (
+ sink_ready => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
+ sink_valid => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ sink_data => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ sink_startofpacket => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ sink_endofpacket => rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ src_ready => id_router_015_src_ready, -- src.ready
+ src_valid => id_router_015_src_valid, -- .valid
+ src_data => id_router_015_src_data, -- .data
+ src_channel => id_router_015_src_channel, -- .channel
+ src_startofpacket => id_router_015_src_startofpacket, -- .startofpacket
+ src_endofpacket => id_router_015_src_endofpacket -- .endofpacket
+ );
+
+ id_router_016 : component altera_merlin_router_0006
+ port map (
+ sink_ready => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
+ sink_valid => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
+ sink_data => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rp_data, -- .data
+ sink_startofpacket => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
+ sink_endofpacket => rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ src_ready => id_router_016_src_ready, -- src.ready
+ src_valid => id_router_016_src_valid, -- .valid
+ src_data => id_router_016_src_data, -- .data
+ src_channel => id_router_016_src_channel, -- .channel
+ src_startofpacket => id_router_016_src_startofpacket, -- .startofpacket
+ src_endofpacket => id_router_016_src_endofpacket -- .endofpacket
+ );
+
+ limiter : component altera_merlin_traffic_limiter_0001
+ port map (
+ clk => csr_clk_clk, -- clk.clk
+ reset => rst_controller_reset_out_reset, -- clk_reset.reset
+ cmd_sink_ready => addr_router_src_ready, -- cmd_sink.ready
+ cmd_sink_valid => addr_router_src_valid, -- .valid
+ cmd_sink_data => addr_router_src_data, -- .data
+ cmd_sink_channel => addr_router_src_channel, -- .channel
+ cmd_sink_startofpacket => addr_router_src_startofpacket, -- .startofpacket
+ cmd_sink_endofpacket => addr_router_src_endofpacket, -- .endofpacket
+ cmd_src_ready => limiter_cmd_src_ready, -- cmd_src.ready
+ cmd_src_data => limiter_cmd_src_data, -- .data
+ cmd_src_channel => limiter_cmd_src_channel, -- .channel
+ cmd_src_startofpacket => limiter_cmd_src_startofpacket, -- .startofpacket
+ cmd_src_endofpacket => limiter_cmd_src_endofpacket, -- .endofpacket
+ rsp_sink_ready => rsp_xbar_mux_src_ready, -- rsp_sink.ready
+ rsp_sink_valid => rsp_xbar_mux_src_valid, -- .valid
+ rsp_sink_channel => rsp_xbar_mux_src_channel, -- .channel
+ rsp_sink_data => rsp_xbar_mux_src_data, -- .data
+ rsp_sink_startofpacket => rsp_xbar_mux_src_startofpacket, -- .startofpacket
+ rsp_sink_endofpacket => rsp_xbar_mux_src_endofpacket, -- .endofpacket
+ rsp_src_ready => limiter_rsp_src_ready, -- rsp_src.ready
+ rsp_src_valid => limiter_rsp_src_valid, -- .valid
+ rsp_src_data => limiter_rsp_src_data, -- .data
+ rsp_src_channel => limiter_rsp_src_channel, -- .channel
+ rsp_src_startofpacket => limiter_rsp_src_startofpacket, -- .startofpacket
+ rsp_src_endofpacket => limiter_rsp_src_endofpacket, -- .endofpacket
+ cmd_src_valid => limiter_cmd_valid_data -- cmd_valid.data
+ );
+
+ limiter_001 : component altera_merlin_traffic_limiter_0002
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ cmd_sink_ready => addr_router_001_src_ready, -- cmd_sink.ready
+ cmd_sink_valid => addr_router_001_src_valid, -- .valid
+ cmd_sink_data => addr_router_001_src_data, -- .data
+ cmd_sink_channel => addr_router_001_src_channel, -- .channel
+ cmd_sink_startofpacket => addr_router_001_src_startofpacket, -- .startofpacket
+ cmd_sink_endofpacket => addr_router_001_src_endofpacket, -- .endofpacket
+ cmd_src_ready => limiter_001_cmd_src_ready, -- cmd_src.ready
+ cmd_src_data => limiter_001_cmd_src_data, -- .data
+ cmd_src_channel => limiter_001_cmd_src_channel, -- .channel
+ cmd_src_startofpacket => limiter_001_cmd_src_startofpacket, -- .startofpacket
+ cmd_src_endofpacket => limiter_001_cmd_src_endofpacket, -- .endofpacket
+ rsp_sink_ready => rsp_xbar_mux_001_src_ready, -- rsp_sink.ready
+ rsp_sink_valid => rsp_xbar_mux_001_src_valid, -- .valid
+ rsp_sink_channel => rsp_xbar_mux_001_src_channel, -- .channel
+ rsp_sink_data => rsp_xbar_mux_001_src_data, -- .data
+ rsp_sink_startofpacket => rsp_xbar_mux_001_src_startofpacket, -- .startofpacket
+ rsp_sink_endofpacket => rsp_xbar_mux_001_src_endofpacket, -- .endofpacket
+ rsp_src_ready => limiter_001_rsp_src_ready, -- rsp_src.ready
+ rsp_src_valid => limiter_001_rsp_src_valid, -- .valid
+ rsp_src_data => limiter_001_rsp_src_data, -- .data
+ rsp_src_channel => limiter_001_rsp_src_channel, -- .channel
+ rsp_src_startofpacket => limiter_001_rsp_src_startofpacket, -- .startofpacket
+ rsp_src_endofpacket => limiter_001_rsp_src_endofpacket, -- .endofpacket
+ cmd_src_valid => limiter_001_cmd_valid_data -- cmd_valid.data
+ );
+
+ limiter_002 : component altera_merlin_traffic_limiter_0003
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ cmd_sink_ready => addr_router_002_src_ready, -- cmd_sink.ready
+ cmd_sink_valid => addr_router_002_src_valid, -- .valid
+ cmd_sink_data => addr_router_002_src_data, -- .data
+ cmd_sink_channel => addr_router_002_src_channel, -- .channel
+ cmd_sink_startofpacket => addr_router_002_src_startofpacket, -- .startofpacket
+ cmd_sink_endofpacket => addr_router_002_src_endofpacket, -- .endofpacket
+ cmd_src_ready => limiter_002_cmd_src_ready, -- cmd_src.ready
+ cmd_src_data => limiter_002_cmd_src_data, -- .data
+ cmd_src_channel => limiter_002_cmd_src_channel, -- .channel
+ cmd_src_startofpacket => limiter_002_cmd_src_startofpacket, -- .startofpacket
+ cmd_src_endofpacket => limiter_002_cmd_src_endofpacket, -- .endofpacket
+ rsp_sink_ready => rsp_xbar_mux_002_src_ready, -- rsp_sink.ready
+ rsp_sink_valid => rsp_xbar_mux_002_src_valid, -- .valid
+ rsp_sink_channel => rsp_xbar_mux_002_src_channel, -- .channel
+ rsp_sink_data => rsp_xbar_mux_002_src_data, -- .data
+ rsp_sink_startofpacket => rsp_xbar_mux_002_src_startofpacket, -- .startofpacket
+ rsp_sink_endofpacket => rsp_xbar_mux_002_src_endofpacket, -- .endofpacket
+ rsp_src_ready => limiter_002_rsp_src_ready, -- rsp_src.ready
+ rsp_src_valid => limiter_002_rsp_src_valid, -- .valid
+ rsp_src_data => limiter_002_rsp_src_data, -- .data
+ rsp_src_channel => limiter_002_rsp_src_channel, -- .channel
+ rsp_src_startofpacket => limiter_002_rsp_src_startofpacket, -- .startofpacket
+ rsp_src_endofpacket => limiter_002_rsp_src_endofpacket, -- .endofpacket
+ cmd_src_valid => limiter_002_cmd_valid_data -- cmd_valid.data
+ );
+
+ rst_controller : component altera_reset_controller_0001
+ port map (
+ reset_in0 => csr_reset_reset_n_ports_inv, -- reset_in0.reset
+ clk => csr_clk_clk, -- clk.clk
+ reset_out => rst_controller_reset_out_reset -- reset_out.reset
+ );
+
+ rst_controller_001 : component altera_reset_controller_0001
+ port map (
+ reset_in0 => tx_reset_reset_n_ports_inv, -- reset_in0.reset
+ clk => tx_clk_clk, -- clk.clk
+ reset_out => rst_controller_001_reset_out_reset -- reset_out.reset
+ );
+
+ rst_controller_002 : component altera_reset_controller_0001
+ port map (
+ reset_in0 => rx_reset_reset_n_ports_inv, -- reset_in0.reset
+ clk => rx_clk_clk, -- clk.clk
+ reset_out => rst_controller_002_reset_out_reset -- reset_out.reset
+ );
+
+ cmd_xbar_demux : component altera_merlin_demultiplexer_0001
+ port map (
+ clk => csr_clk_clk, -- clk.clk
+ reset => rst_controller_reset_out_reset, -- clk_reset.reset
+ sink_ready => limiter_cmd_src_ready, -- sink.ready
+ sink_channel => limiter_cmd_src_channel, -- .channel
+ sink_data => limiter_cmd_src_data, -- .data
+ sink_startofpacket => limiter_cmd_src_startofpacket, -- .startofpacket
+ sink_endofpacket => limiter_cmd_src_endofpacket, -- .endofpacket
+ sink_valid => limiter_cmd_valid_data, -- sink_valid.data
+ src0_ready => cmd_xbar_demux_src0_ready, -- src0.ready
+ src0_valid => cmd_xbar_demux_src0_valid, -- .valid
+ src0_data => cmd_xbar_demux_src0_data, -- .data
+ src0_channel => cmd_xbar_demux_src0_channel, -- .channel
+ src0_startofpacket => cmd_xbar_demux_src0_startofpacket, -- .startofpacket
+ src0_endofpacket => cmd_xbar_demux_src0_endofpacket, -- .endofpacket
+ src1_ready => cmd_xbar_demux_src1_ready, -- src1.ready
+ src1_valid => cmd_xbar_demux_src1_valid, -- .valid
+ src1_data => cmd_xbar_demux_src1_data, -- .data
+ src1_channel => cmd_xbar_demux_src1_channel, -- .channel
+ src1_startofpacket => cmd_xbar_demux_src1_startofpacket, -- .startofpacket
+ src1_endofpacket => cmd_xbar_demux_src1_endofpacket -- .endofpacket
+ );
+
+ rsp_xbar_demux : component altera_merlin_demultiplexer_0002
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ sink_ready => id_router_src_ready, -- sink.ready
+ sink_channel => id_router_src_channel, -- .channel
+ sink_data => id_router_src_data, -- .data
+ sink_startofpacket => id_router_src_startofpacket, -- .startofpacket
+ sink_endofpacket => id_router_src_endofpacket, -- .endofpacket
+ sink_valid(0) => id_router_src_valid, -- .valid
+ src0_ready => rsp_xbar_demux_src0_ready, -- src0.ready
+ src0_valid => rsp_xbar_demux_src0_valid, -- .valid
+ src0_data => rsp_xbar_demux_src0_data, -- .data
+ src0_channel => rsp_xbar_demux_src0_channel, -- .channel
+ src0_startofpacket => rsp_xbar_demux_src0_startofpacket, -- .startofpacket
+ src0_endofpacket => rsp_xbar_demux_src0_endofpacket -- .endofpacket
+ );
+
+ rsp_xbar_demux_001 : component altera_merlin_demultiplexer_0002
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ sink_ready => id_router_001_src_ready, -- sink.ready
+ sink_channel => id_router_001_src_channel, -- .channel
+ sink_data => id_router_001_src_data, -- .data
+ sink_startofpacket => id_router_001_src_startofpacket, -- .startofpacket
+ sink_endofpacket => id_router_001_src_endofpacket, -- .endofpacket
+ sink_valid(0) => id_router_001_src_valid, -- .valid
+ src0_ready => rsp_xbar_demux_001_src0_ready, -- src0.ready
+ src0_valid => rsp_xbar_demux_001_src0_valid, -- .valid
+ src0_data => rsp_xbar_demux_001_src0_data, -- .data
+ src0_channel => rsp_xbar_demux_001_src0_channel, -- .channel
+ src0_startofpacket => rsp_xbar_demux_001_src0_startofpacket, -- .startofpacket
+ src0_endofpacket => rsp_xbar_demux_001_src0_endofpacket -- .endofpacket
+ );
+
+ rsp_xbar_mux : component altera_merlin_multiplexer_0001
+ port map (
+ clk => csr_clk_clk, -- clk.clk
+ reset => rst_controller_reset_out_reset, -- clk_reset.reset
+ src_ready => rsp_xbar_mux_src_ready, -- src.ready
+ src_valid => rsp_xbar_mux_src_valid, -- .valid
+ src_data => rsp_xbar_mux_src_data, -- .data
+ src_channel => rsp_xbar_mux_src_channel, -- .channel
+ src_startofpacket => rsp_xbar_mux_src_startofpacket, -- .startofpacket
+ src_endofpacket => rsp_xbar_mux_src_endofpacket, -- .endofpacket
+ sink0_ready => crosser_002_out_ready, -- sink0.ready
+ sink0_valid => crosser_002_out_valid, -- .valid
+ sink0_channel => crosser_002_out_channel, -- .channel
+ sink0_data => crosser_002_out_data, -- .data
+ sink0_startofpacket => crosser_002_out_startofpacket, -- .startofpacket
+ sink0_endofpacket => crosser_002_out_endofpacket, -- .endofpacket
+ sink1_ready => crosser_003_out_ready, -- sink1.ready
+ sink1_valid => crosser_003_out_valid, -- .valid
+ sink1_channel => crosser_003_out_channel, -- .channel
+ sink1_data => crosser_003_out_data, -- .data
+ sink1_startofpacket => crosser_003_out_startofpacket, -- .startofpacket
+ sink1_endofpacket => crosser_003_out_endofpacket -- .endofpacket
+ );
+
+ cmd_xbar_demux_001 : component altera_merlin_demultiplexer_0003
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ sink_ready => limiter_001_cmd_src_ready, -- sink.ready
+ sink_channel => limiter_001_cmd_src_channel, -- .channel
+ sink_data => limiter_001_cmd_src_data, -- .data
+ sink_startofpacket => limiter_001_cmd_src_startofpacket, -- .startofpacket
+ sink_endofpacket => limiter_001_cmd_src_endofpacket, -- .endofpacket
+ sink_valid => limiter_001_cmd_valid_data, -- sink_valid.data
+ src0_ready => cmd_xbar_demux_001_src0_ready, -- src0.ready
+ src0_valid => cmd_xbar_demux_001_src0_valid, -- .valid
+ src0_data => cmd_xbar_demux_001_src0_data, -- .data
+ src0_channel => cmd_xbar_demux_001_src0_channel, -- .channel
+ src0_startofpacket => cmd_xbar_demux_001_src0_startofpacket, -- .startofpacket
+ src0_endofpacket => cmd_xbar_demux_001_src0_endofpacket, -- .endofpacket
+ src1_ready => cmd_xbar_demux_001_src1_ready, -- src1.ready
+ src1_valid => cmd_xbar_demux_001_src1_valid, -- .valid
+ src1_data => cmd_xbar_demux_001_src1_data, -- .data
+ src1_channel => cmd_xbar_demux_001_src1_channel, -- .channel
+ src1_startofpacket => cmd_xbar_demux_001_src1_startofpacket, -- .startofpacket
+ src1_endofpacket => cmd_xbar_demux_001_src1_endofpacket, -- .endofpacket
+ src2_ready => cmd_xbar_demux_001_src2_ready, -- src2.ready
+ src2_valid => cmd_xbar_demux_001_src2_valid, -- .valid
+ src2_data => cmd_xbar_demux_001_src2_data, -- .data
+ src2_channel => cmd_xbar_demux_001_src2_channel, -- .channel
+ src2_startofpacket => cmd_xbar_demux_001_src2_startofpacket, -- .startofpacket
+ src2_endofpacket => cmd_xbar_demux_001_src2_endofpacket, -- .endofpacket
+ src3_ready => cmd_xbar_demux_001_src3_ready, -- src3.ready
+ src3_valid => cmd_xbar_demux_001_src3_valid, -- .valid
+ src3_data => cmd_xbar_demux_001_src3_data, -- .data
+ src3_channel => cmd_xbar_demux_001_src3_channel, -- .channel
+ src3_startofpacket => cmd_xbar_demux_001_src3_startofpacket, -- .startofpacket
+ src3_endofpacket => cmd_xbar_demux_001_src3_endofpacket, -- .endofpacket
+ src4_ready => cmd_xbar_demux_001_src4_ready, -- src4.ready
+ src4_valid => cmd_xbar_demux_001_src4_valid, -- .valid
+ src4_data => cmd_xbar_demux_001_src4_data, -- .data
+ src4_channel => cmd_xbar_demux_001_src4_channel, -- .channel
+ src4_startofpacket => cmd_xbar_demux_001_src4_startofpacket, -- .startofpacket
+ src4_endofpacket => cmd_xbar_demux_001_src4_endofpacket, -- .endofpacket
+ src5_ready => cmd_xbar_demux_001_src5_ready, -- src5.ready
+ src5_valid => cmd_xbar_demux_001_src5_valid, -- .valid
+ src5_data => cmd_xbar_demux_001_src5_data, -- .data
+ src5_channel => cmd_xbar_demux_001_src5_channel, -- .channel
+ src5_startofpacket => cmd_xbar_demux_001_src5_startofpacket, -- .startofpacket
+ src5_endofpacket => cmd_xbar_demux_001_src5_endofpacket, -- .endofpacket
+ src6_ready => cmd_xbar_demux_001_src6_ready, -- src6.ready
+ src6_valid => cmd_xbar_demux_001_src6_valid, -- .valid
+ src6_data => cmd_xbar_demux_001_src6_data, -- .data
+ src6_channel => cmd_xbar_demux_001_src6_channel, -- .channel
+ src6_startofpacket => cmd_xbar_demux_001_src6_startofpacket, -- .startofpacket
+ src6_endofpacket => cmd_xbar_demux_001_src6_endofpacket, -- .endofpacket
+ src7_ready => cmd_xbar_demux_001_src7_ready, -- src7.ready
+ src7_valid => cmd_xbar_demux_001_src7_valid, -- .valid
+ src7_data => cmd_xbar_demux_001_src7_data, -- .data
+ src7_channel => cmd_xbar_demux_001_src7_channel, -- .channel
+ src7_startofpacket => cmd_xbar_demux_001_src7_startofpacket, -- .startofpacket
+ src7_endofpacket => cmd_xbar_demux_001_src7_endofpacket -- .endofpacket
+ );
+
+ rsp_xbar_demux_002 : component altera_merlin_demultiplexer_0004
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ sink_ready => id_router_002_src_ready, -- sink.ready
+ sink_channel => id_router_002_src_channel, -- .channel
+ sink_data => id_router_002_src_data, -- .data
+ sink_startofpacket => id_router_002_src_startofpacket, -- .startofpacket
+ sink_endofpacket => id_router_002_src_endofpacket, -- .endofpacket
+ sink_valid(0) => id_router_002_src_valid, -- .valid
+ src0_ready => rsp_xbar_demux_002_src0_ready, -- src0.ready
+ src0_valid => rsp_xbar_demux_002_src0_valid, -- .valid
+ src0_data => rsp_xbar_demux_002_src0_data, -- .data
+ src0_channel => rsp_xbar_demux_002_src0_channel, -- .channel
+ src0_startofpacket => rsp_xbar_demux_002_src0_startofpacket, -- .startofpacket
+ src0_endofpacket => rsp_xbar_demux_002_src0_endofpacket -- .endofpacket
+ );
+
+ rsp_xbar_demux_003 : component altera_merlin_demultiplexer_0004
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ sink_ready => id_router_003_src_ready, -- sink.ready
+ sink_channel => id_router_003_src_channel, -- .channel
+ sink_data => id_router_003_src_data, -- .data
+ sink_startofpacket => id_router_003_src_startofpacket, -- .startofpacket
+ sink_endofpacket => id_router_003_src_endofpacket, -- .endofpacket
+ sink_valid(0) => id_router_003_src_valid, -- .valid
+ src0_ready => rsp_xbar_demux_003_src0_ready, -- src0.ready
+ src0_valid => rsp_xbar_demux_003_src0_valid, -- .valid
+ src0_data => rsp_xbar_demux_003_src0_data, -- .data
+ src0_channel => rsp_xbar_demux_003_src0_channel, -- .channel
+ src0_startofpacket => rsp_xbar_demux_003_src0_startofpacket, -- .startofpacket
+ src0_endofpacket => rsp_xbar_demux_003_src0_endofpacket -- .endofpacket
+ );
+
+ rsp_xbar_demux_004 : component altera_merlin_demultiplexer_0004
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ sink_ready => id_router_004_src_ready, -- sink.ready
+ sink_channel => id_router_004_src_channel, -- .channel
+ sink_data => id_router_004_src_data, -- .data
+ sink_startofpacket => id_router_004_src_startofpacket, -- .startofpacket
+ sink_endofpacket => id_router_004_src_endofpacket, -- .endofpacket
+ sink_valid(0) => id_router_004_src_valid, -- .valid
+ src0_ready => rsp_xbar_demux_004_src0_ready, -- src0.ready
+ src0_valid => rsp_xbar_demux_004_src0_valid, -- .valid
+ src0_data => rsp_xbar_demux_004_src0_data, -- .data
+ src0_channel => rsp_xbar_demux_004_src0_channel, -- .channel
+ src0_startofpacket => rsp_xbar_demux_004_src0_startofpacket, -- .startofpacket
+ src0_endofpacket => rsp_xbar_demux_004_src0_endofpacket -- .endofpacket
+ );
+
+ rsp_xbar_demux_005 : component altera_merlin_demultiplexer_0004
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ sink_ready => id_router_005_src_ready, -- sink.ready
+ sink_channel => id_router_005_src_channel, -- .channel
+ sink_data => id_router_005_src_data, -- .data
+ sink_startofpacket => id_router_005_src_startofpacket, -- .startofpacket
+ sink_endofpacket => id_router_005_src_endofpacket, -- .endofpacket
+ sink_valid(0) => id_router_005_src_valid, -- .valid
+ src0_ready => rsp_xbar_demux_005_src0_ready, -- src0.ready
+ src0_valid => rsp_xbar_demux_005_src0_valid, -- .valid
+ src0_data => rsp_xbar_demux_005_src0_data, -- .data
+ src0_channel => rsp_xbar_demux_005_src0_channel, -- .channel
+ src0_startofpacket => rsp_xbar_demux_005_src0_startofpacket, -- .startofpacket
+ src0_endofpacket => rsp_xbar_demux_005_src0_endofpacket -- .endofpacket
+ );
+
+ rsp_xbar_demux_006 : component altera_merlin_demultiplexer_0004
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ sink_ready => id_router_006_src_ready, -- sink.ready
+ sink_channel => id_router_006_src_channel, -- .channel
+ sink_data => id_router_006_src_data, -- .data
+ sink_startofpacket => id_router_006_src_startofpacket, -- .startofpacket
+ sink_endofpacket => id_router_006_src_endofpacket, -- .endofpacket
+ sink_valid(0) => id_router_006_src_valid, -- .valid
+ src0_ready => rsp_xbar_demux_006_src0_ready, -- src0.ready
+ src0_valid => rsp_xbar_demux_006_src0_valid, -- .valid
+ src0_data => rsp_xbar_demux_006_src0_data, -- .data
+ src0_channel => rsp_xbar_demux_006_src0_channel, -- .channel
+ src0_startofpacket => rsp_xbar_demux_006_src0_startofpacket, -- .startofpacket
+ src0_endofpacket => rsp_xbar_demux_006_src0_endofpacket -- .endofpacket
+ );
+
+ rsp_xbar_demux_007 : component altera_merlin_demultiplexer_0004
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ sink_ready => id_router_007_src_ready, -- sink.ready
+ sink_channel => id_router_007_src_channel, -- .channel
+ sink_data => id_router_007_src_data, -- .data
+ sink_startofpacket => id_router_007_src_startofpacket, -- .startofpacket
+ sink_endofpacket => id_router_007_src_endofpacket, -- .endofpacket
+ sink_valid(0) => id_router_007_src_valid, -- .valid
+ src0_ready => rsp_xbar_demux_007_src0_ready, -- src0.ready
+ src0_valid => rsp_xbar_demux_007_src0_valid, -- .valid
+ src0_data => rsp_xbar_demux_007_src0_data, -- .data
+ src0_channel => rsp_xbar_demux_007_src0_channel, -- .channel
+ src0_startofpacket => rsp_xbar_demux_007_src0_startofpacket, -- .startofpacket
+ src0_endofpacket => rsp_xbar_demux_007_src0_endofpacket -- .endofpacket
+ );
+
+ rsp_xbar_demux_008 : component altera_merlin_demultiplexer_0004
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ sink_ready => id_router_008_src_ready, -- sink.ready
+ sink_channel => id_router_008_src_channel, -- .channel
+ sink_data => id_router_008_src_data, -- .data
+ sink_startofpacket => id_router_008_src_startofpacket, -- .startofpacket
+ sink_endofpacket => id_router_008_src_endofpacket, -- .endofpacket
+ sink_valid(0) => id_router_008_src_valid, -- .valid
+ src0_ready => rsp_xbar_demux_008_src0_ready, -- src0.ready
+ src0_valid => rsp_xbar_demux_008_src0_valid, -- .valid
+ src0_data => rsp_xbar_demux_008_src0_data, -- .data
+ src0_channel => rsp_xbar_demux_008_src0_channel, -- .channel
+ src0_startofpacket => rsp_xbar_demux_008_src0_startofpacket, -- .startofpacket
+ src0_endofpacket => rsp_xbar_demux_008_src0_endofpacket -- .endofpacket
+ );
+
+ rsp_xbar_demux_009 : component altera_merlin_demultiplexer_0004
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ sink_ready => id_router_009_src_ready, -- sink.ready
+ sink_channel => id_router_009_src_channel, -- .channel
+ sink_data => id_router_009_src_data, -- .data
+ sink_startofpacket => id_router_009_src_startofpacket, -- .startofpacket
+ sink_endofpacket => id_router_009_src_endofpacket, -- .endofpacket
+ sink_valid(0) => id_router_009_src_valid, -- .valid
+ src0_ready => rsp_xbar_demux_009_src0_ready, -- src0.ready
+ src0_valid => rsp_xbar_demux_009_src0_valid, -- .valid
+ src0_data => rsp_xbar_demux_009_src0_data, -- .data
+ src0_channel => rsp_xbar_demux_009_src0_channel, -- .channel
+ src0_startofpacket => rsp_xbar_demux_009_src0_startofpacket, -- .startofpacket
+ src0_endofpacket => rsp_xbar_demux_009_src0_endofpacket -- .endofpacket
+ );
+
+ rsp_xbar_mux_001 : component altera_merlin_multiplexer_0002
+ port map (
+ clk => tx_clk_clk, -- clk.clk
+ reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
+ src_ready => rsp_xbar_mux_001_src_ready, -- src.ready
+ src_valid => rsp_xbar_mux_001_src_valid, -- .valid
+ src_data => rsp_xbar_mux_001_src_data, -- .data
+ src_channel => rsp_xbar_mux_001_src_channel, -- .channel
+ src_startofpacket => rsp_xbar_mux_001_src_startofpacket, -- .startofpacket
+ src_endofpacket => rsp_xbar_mux_001_src_endofpacket, -- .endofpacket
+ sink0_ready => rsp_xbar_demux_002_src0_ready, -- sink0.ready
+ sink0_valid => rsp_xbar_demux_002_src0_valid, -- .valid
+ sink0_channel => rsp_xbar_demux_002_src0_channel, -- .channel
+ sink0_data => rsp_xbar_demux_002_src0_data, -- .data
+ sink0_startofpacket => rsp_xbar_demux_002_src0_startofpacket, -- .startofpacket
+ sink0_endofpacket => rsp_xbar_demux_002_src0_endofpacket, -- .endofpacket
+ sink1_ready => rsp_xbar_demux_003_src0_ready, -- sink1.ready
+ sink1_valid => rsp_xbar_demux_003_src0_valid, -- .valid
+ sink1_channel => rsp_xbar_demux_003_src0_channel, -- .channel
+ sink1_data => rsp_xbar_demux_003_src0_data, -- .data
+ sink1_startofpacket => rsp_xbar_demux_003_src0_startofpacket, -- .startofpacket
+ sink1_endofpacket => rsp_xbar_demux_003_src0_endofpacket, -- .endofpacket
+ sink2_ready => rsp_xbar_demux_004_src0_ready, -- sink2.ready
+ sink2_valid => rsp_xbar_demux_004_src0_valid, -- .valid
+ sink2_channel => rsp_xbar_demux_004_src0_channel, -- .channel
+ sink2_data => rsp_xbar_demux_004_src0_data, -- .data
+ sink2_startofpacket => rsp_xbar_demux_004_src0_startofpacket, -- .startofpacket
+ sink2_endofpacket => rsp_xbar_demux_004_src0_endofpacket, -- .endofpacket
+ sink3_ready => rsp_xbar_demux_005_src0_ready, -- sink3.ready
+ sink3_valid => rsp_xbar_demux_005_src0_valid, -- .valid
+ sink3_channel => rsp_xbar_demux_005_src0_channel, -- .channel
+ sink3_data => rsp_xbar_demux_005_src0_data, -- .data
+ sink3_startofpacket => rsp_xbar_demux_005_src0_startofpacket, -- .startofpacket
+ sink3_endofpacket => rsp_xbar_demux_005_src0_endofpacket, -- .endofpacket
+ sink4_ready => rsp_xbar_demux_006_src0_ready, -- sink4.ready
+ sink4_valid => rsp_xbar_demux_006_src0_valid, -- .valid
+ sink4_channel => rsp_xbar_demux_006_src0_channel, -- .channel
+ sink4_data => rsp_xbar_demux_006_src0_data, -- .data
+ sink4_startofpacket => rsp_xbar_demux_006_src0_startofpacket, -- .startofpacket
+ sink4_endofpacket => rsp_xbar_demux_006_src0_endofpacket, -- .endofpacket
+ sink5_ready => rsp_xbar_demux_007_src0_ready, -- sink5.ready
+ sink5_valid => rsp_xbar_demux_007_src0_valid, -- .valid
+ sink5_channel => rsp_xbar_demux_007_src0_channel, -- .channel
+ sink5_data => rsp_xbar_demux_007_src0_data, -- .data
+ sink5_startofpacket => rsp_xbar_demux_007_src0_startofpacket, -- .startofpacket
+ sink5_endofpacket => rsp_xbar_demux_007_src0_endofpacket, -- .endofpacket
+ sink6_ready => rsp_xbar_demux_008_src0_ready, -- sink6.ready
+ sink6_valid => rsp_xbar_demux_008_src0_valid, -- .valid
+ sink6_channel => rsp_xbar_demux_008_src0_channel, -- .channel
+ sink6_data => rsp_xbar_demux_008_src0_data, -- .data
+ sink6_startofpacket => rsp_xbar_demux_008_src0_startofpacket, -- .startofpacket
+ sink6_endofpacket => rsp_xbar_demux_008_src0_endofpacket, -- .endofpacket
+ sink7_ready => rsp_xbar_demux_009_src0_ready, -- sink7.ready
+ sink7_valid => rsp_xbar_demux_009_src0_valid, -- .valid
+ sink7_channel => rsp_xbar_demux_009_src0_channel, -- .channel
+ sink7_data => rsp_xbar_demux_009_src0_data, -- .data
+ sink7_startofpacket => rsp_xbar_demux_009_src0_startofpacket, -- .startofpacket
+ sink7_endofpacket => rsp_xbar_demux_009_src0_endofpacket -- .endofpacket
+ );
+
+ cmd_xbar_demux_002 : component altera_merlin_demultiplexer_0005
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ sink_ready => limiter_002_cmd_src_ready, -- sink.ready
+ sink_channel => limiter_002_cmd_src_channel, -- .channel
+ sink_data => limiter_002_cmd_src_data, -- .data
+ sink_startofpacket => limiter_002_cmd_src_startofpacket, -- .startofpacket
+ sink_endofpacket => limiter_002_cmd_src_endofpacket, -- .endofpacket
+ sink_valid => limiter_002_cmd_valid_data, -- sink_valid.data
+ src0_ready => cmd_xbar_demux_002_src0_ready, -- src0.ready
+ src0_valid => cmd_xbar_demux_002_src0_valid, -- .valid
+ src0_data => cmd_xbar_demux_002_src0_data, -- .data
+ src0_channel => cmd_xbar_demux_002_src0_channel, -- .channel
+ src0_startofpacket => cmd_xbar_demux_002_src0_startofpacket, -- .startofpacket
+ src0_endofpacket => cmd_xbar_demux_002_src0_endofpacket, -- .endofpacket
+ src1_ready => cmd_xbar_demux_002_src1_ready, -- src1.ready
+ src1_valid => cmd_xbar_demux_002_src1_valid, -- .valid
+ src1_data => cmd_xbar_demux_002_src1_data, -- .data
+ src1_channel => cmd_xbar_demux_002_src1_channel, -- .channel
+ src1_startofpacket => cmd_xbar_demux_002_src1_startofpacket, -- .startofpacket
+ src1_endofpacket => cmd_xbar_demux_002_src1_endofpacket, -- .endofpacket
+ src2_ready => cmd_xbar_demux_002_src2_ready, -- src2.ready
+ src2_valid => cmd_xbar_demux_002_src2_valid, -- .valid
+ src2_data => cmd_xbar_demux_002_src2_data, -- .data
+ src2_channel => cmd_xbar_demux_002_src2_channel, -- .channel
+ src2_startofpacket => cmd_xbar_demux_002_src2_startofpacket, -- .startofpacket
+ src2_endofpacket => cmd_xbar_demux_002_src2_endofpacket, -- .endofpacket
+ src3_ready => cmd_xbar_demux_002_src3_ready, -- src3.ready
+ src3_valid => cmd_xbar_demux_002_src3_valid, -- .valid
+ src3_data => cmd_xbar_demux_002_src3_data, -- .data
+ src3_channel => cmd_xbar_demux_002_src3_channel, -- .channel
+ src3_startofpacket => cmd_xbar_demux_002_src3_startofpacket, -- .startofpacket
+ src3_endofpacket => cmd_xbar_demux_002_src3_endofpacket, -- .endofpacket
+ src4_ready => cmd_xbar_demux_002_src4_ready, -- src4.ready
+ src4_valid => cmd_xbar_demux_002_src4_valid, -- .valid
+ src4_data => cmd_xbar_demux_002_src4_data, -- .data
+ src4_channel => cmd_xbar_demux_002_src4_channel, -- .channel
+ src4_startofpacket => cmd_xbar_demux_002_src4_startofpacket, -- .startofpacket
+ src4_endofpacket => cmd_xbar_demux_002_src4_endofpacket, -- .endofpacket
+ src5_ready => cmd_xbar_demux_002_src5_ready, -- src5.ready
+ src5_valid => cmd_xbar_demux_002_src5_valid, -- .valid
+ src5_data => cmd_xbar_demux_002_src5_data, -- .data
+ src5_channel => cmd_xbar_demux_002_src5_channel, -- .channel
+ src5_startofpacket => cmd_xbar_demux_002_src5_startofpacket, -- .startofpacket
+ src5_endofpacket => cmd_xbar_demux_002_src5_endofpacket, -- .endofpacket
+ src6_ready => cmd_xbar_demux_002_src6_ready, -- src6.ready
+ src6_valid => cmd_xbar_demux_002_src6_valid, -- .valid
+ src6_data => cmd_xbar_demux_002_src6_data, -- .data
+ src6_channel => cmd_xbar_demux_002_src6_channel, -- .channel
+ src6_startofpacket => cmd_xbar_demux_002_src6_startofpacket, -- .startofpacket
+ src6_endofpacket => cmd_xbar_demux_002_src6_endofpacket -- .endofpacket
+ );
+
+ rsp_xbar_demux_010 : component altera_merlin_demultiplexer_0006
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ sink_ready => id_router_010_src_ready, -- sink.ready
+ sink_channel => id_router_010_src_channel, -- .channel
+ sink_data => id_router_010_src_data, -- .data
+ sink_startofpacket => id_router_010_src_startofpacket, -- .startofpacket
+ sink_endofpacket => id_router_010_src_endofpacket, -- .endofpacket
+ sink_valid(0) => id_router_010_src_valid, -- .valid
+ src0_ready => rsp_xbar_demux_010_src0_ready, -- src0.ready
+ src0_valid => rsp_xbar_demux_010_src0_valid, -- .valid
+ src0_data => rsp_xbar_demux_010_src0_data, -- .data
+ src0_channel => rsp_xbar_demux_010_src0_channel, -- .channel
+ src0_startofpacket => rsp_xbar_demux_010_src0_startofpacket, -- .startofpacket
+ src0_endofpacket => rsp_xbar_demux_010_src0_endofpacket -- .endofpacket
+ );
+
+ rsp_xbar_demux_011 : component altera_merlin_demultiplexer_0006
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ sink_ready => id_router_011_src_ready, -- sink.ready
+ sink_channel => id_router_011_src_channel, -- .channel
+ sink_data => id_router_011_src_data, -- .data
+ sink_startofpacket => id_router_011_src_startofpacket, -- .startofpacket
+ sink_endofpacket => id_router_011_src_endofpacket, -- .endofpacket
+ sink_valid(0) => id_router_011_src_valid, -- .valid
+ src0_ready => rsp_xbar_demux_011_src0_ready, -- src0.ready
+ src0_valid => rsp_xbar_demux_011_src0_valid, -- .valid
+ src0_data => rsp_xbar_demux_011_src0_data, -- .data
+ src0_channel => rsp_xbar_demux_011_src0_channel, -- .channel
+ src0_startofpacket => rsp_xbar_demux_011_src0_startofpacket, -- .startofpacket
+ src0_endofpacket => rsp_xbar_demux_011_src0_endofpacket -- .endofpacket
+ );
+
+ rsp_xbar_demux_012 : component altera_merlin_demultiplexer_0006
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ sink_ready => id_router_012_src_ready, -- sink.ready
+ sink_channel => id_router_012_src_channel, -- .channel
+ sink_data => id_router_012_src_data, -- .data
+ sink_startofpacket => id_router_012_src_startofpacket, -- .startofpacket
+ sink_endofpacket => id_router_012_src_endofpacket, -- .endofpacket
+ sink_valid(0) => id_router_012_src_valid, -- .valid
+ src0_ready => rsp_xbar_demux_012_src0_ready, -- src0.ready
+ src0_valid => rsp_xbar_demux_012_src0_valid, -- .valid
+ src0_data => rsp_xbar_demux_012_src0_data, -- .data
+ src0_channel => rsp_xbar_demux_012_src0_channel, -- .channel
+ src0_startofpacket => rsp_xbar_demux_012_src0_startofpacket, -- .startofpacket
+ src0_endofpacket => rsp_xbar_demux_012_src0_endofpacket -- .endofpacket
+ );
+
+ rsp_xbar_demux_013 : component altera_merlin_demultiplexer_0006
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ sink_ready => id_router_013_src_ready, -- sink.ready
+ sink_channel => id_router_013_src_channel, -- .channel
+ sink_data => id_router_013_src_data, -- .data
+ sink_startofpacket => id_router_013_src_startofpacket, -- .startofpacket
+ sink_endofpacket => id_router_013_src_endofpacket, -- .endofpacket
+ sink_valid(0) => id_router_013_src_valid, -- .valid
+ src0_ready => rsp_xbar_demux_013_src0_ready, -- src0.ready
+ src0_valid => rsp_xbar_demux_013_src0_valid, -- .valid
+ src0_data => rsp_xbar_demux_013_src0_data, -- .data
+ src0_channel => rsp_xbar_demux_013_src0_channel, -- .channel
+ src0_startofpacket => rsp_xbar_demux_013_src0_startofpacket, -- .startofpacket
+ src0_endofpacket => rsp_xbar_demux_013_src0_endofpacket -- .endofpacket
+ );
+
+ rsp_xbar_demux_014 : component altera_merlin_demultiplexer_0006
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ sink_ready => id_router_014_src_ready, -- sink.ready
+ sink_channel => id_router_014_src_channel, -- .channel
+ sink_data => id_router_014_src_data, -- .data
+ sink_startofpacket => id_router_014_src_startofpacket, -- .startofpacket
+ sink_endofpacket => id_router_014_src_endofpacket, -- .endofpacket
+ sink_valid(0) => id_router_014_src_valid, -- .valid
+ src0_ready => rsp_xbar_demux_014_src0_ready, -- src0.ready
+ src0_valid => rsp_xbar_demux_014_src0_valid, -- .valid
+ src0_data => rsp_xbar_demux_014_src0_data, -- .data
+ src0_channel => rsp_xbar_demux_014_src0_channel, -- .channel
+ src0_startofpacket => rsp_xbar_demux_014_src0_startofpacket, -- .startofpacket
+ src0_endofpacket => rsp_xbar_demux_014_src0_endofpacket -- .endofpacket
+ );
+
+ rsp_xbar_demux_015 : component altera_merlin_demultiplexer_0006
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ sink_ready => id_router_015_src_ready, -- sink.ready
+ sink_channel => id_router_015_src_channel, -- .channel
+ sink_data => id_router_015_src_data, -- .data
+ sink_startofpacket => id_router_015_src_startofpacket, -- .startofpacket
+ sink_endofpacket => id_router_015_src_endofpacket, -- .endofpacket
+ sink_valid(0) => id_router_015_src_valid, -- .valid
+ src0_ready => rsp_xbar_demux_015_src0_ready, -- src0.ready
+ src0_valid => rsp_xbar_demux_015_src0_valid, -- .valid
+ src0_data => rsp_xbar_demux_015_src0_data, -- .data
+ src0_channel => rsp_xbar_demux_015_src0_channel, -- .channel
+ src0_startofpacket => rsp_xbar_demux_015_src0_startofpacket, -- .startofpacket
+ src0_endofpacket => rsp_xbar_demux_015_src0_endofpacket -- .endofpacket
+ );
+
+ rsp_xbar_demux_016 : component altera_merlin_demultiplexer_0006
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ sink_ready => id_router_016_src_ready, -- sink.ready
+ sink_channel => id_router_016_src_channel, -- .channel
+ sink_data => id_router_016_src_data, -- .data
+ sink_startofpacket => id_router_016_src_startofpacket, -- .startofpacket
+ sink_endofpacket => id_router_016_src_endofpacket, -- .endofpacket
+ sink_valid(0) => id_router_016_src_valid, -- .valid
+ src0_ready => rsp_xbar_demux_016_src0_ready, -- src0.ready
+ src0_valid => rsp_xbar_demux_016_src0_valid, -- .valid
+ src0_data => rsp_xbar_demux_016_src0_data, -- .data
+ src0_channel => rsp_xbar_demux_016_src0_channel, -- .channel
+ src0_startofpacket => rsp_xbar_demux_016_src0_startofpacket, -- .startofpacket
+ src0_endofpacket => rsp_xbar_demux_016_src0_endofpacket -- .endofpacket
+ );
+
+ rsp_xbar_mux_002 : component altera_merlin_multiplexer_0003
+ port map (
+ clk => rx_clk_clk, -- clk.clk
+ reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
+ src_ready => rsp_xbar_mux_002_src_ready, -- src.ready
+ src_valid => rsp_xbar_mux_002_src_valid, -- .valid
+ src_data => rsp_xbar_mux_002_src_data, -- .data
+ src_channel => rsp_xbar_mux_002_src_channel, -- .channel
+ src_startofpacket => rsp_xbar_mux_002_src_startofpacket, -- .startofpacket
+ src_endofpacket => rsp_xbar_mux_002_src_endofpacket, -- .endofpacket
+ sink0_ready => rsp_xbar_demux_010_src0_ready, -- sink0.ready
+ sink0_valid => rsp_xbar_demux_010_src0_valid, -- .valid
+ sink0_channel => rsp_xbar_demux_010_src0_channel, -- .channel
+ sink0_data => rsp_xbar_demux_010_src0_data, -- .data
+ sink0_startofpacket => rsp_xbar_demux_010_src0_startofpacket, -- .startofpacket
+ sink0_endofpacket => rsp_xbar_demux_010_src0_endofpacket, -- .endofpacket
+ sink1_ready => rsp_xbar_demux_011_src0_ready, -- sink1.ready
+ sink1_valid => rsp_xbar_demux_011_src0_valid, -- .valid
+ sink1_channel => rsp_xbar_demux_011_src0_channel, -- .channel
+ sink1_data => rsp_xbar_demux_011_src0_data, -- .data
+ sink1_startofpacket => rsp_xbar_demux_011_src0_startofpacket, -- .startofpacket
+ sink1_endofpacket => rsp_xbar_demux_011_src0_endofpacket, -- .endofpacket
+ sink2_ready => rsp_xbar_demux_012_src0_ready, -- sink2.ready
+ sink2_valid => rsp_xbar_demux_012_src0_valid, -- .valid
+ sink2_channel => rsp_xbar_demux_012_src0_channel, -- .channel
+ sink2_data => rsp_xbar_demux_012_src0_data, -- .data
+ sink2_startofpacket => rsp_xbar_demux_012_src0_startofpacket, -- .startofpacket
+ sink2_endofpacket => rsp_xbar_demux_012_src0_endofpacket, -- .endofpacket
+ sink3_ready => rsp_xbar_demux_013_src0_ready, -- sink3.ready
+ sink3_valid => rsp_xbar_demux_013_src0_valid, -- .valid
+ sink3_channel => rsp_xbar_demux_013_src0_channel, -- .channel
+ sink3_data => rsp_xbar_demux_013_src0_data, -- .data
+ sink3_startofpacket => rsp_xbar_demux_013_src0_startofpacket, -- .startofpacket
+ sink3_endofpacket => rsp_xbar_demux_013_src0_endofpacket, -- .endofpacket
+ sink4_ready => rsp_xbar_demux_014_src0_ready, -- sink4.ready
+ sink4_valid => rsp_xbar_demux_014_src0_valid, -- .valid
+ sink4_channel => rsp_xbar_demux_014_src0_channel, -- .channel
+ sink4_data => rsp_xbar_demux_014_src0_data, -- .data
+ sink4_startofpacket => rsp_xbar_demux_014_src0_startofpacket, -- .startofpacket
+ sink4_endofpacket => rsp_xbar_demux_014_src0_endofpacket, -- .endofpacket
+ sink5_ready => rsp_xbar_demux_015_src0_ready, -- sink5.ready
+ sink5_valid => rsp_xbar_demux_015_src0_valid, -- .valid
+ sink5_channel => rsp_xbar_demux_015_src0_channel, -- .channel
+ sink5_data => rsp_xbar_demux_015_src0_data, -- .data
+ sink5_startofpacket => rsp_xbar_demux_015_src0_startofpacket, -- .startofpacket
+ sink5_endofpacket => rsp_xbar_demux_015_src0_endofpacket, -- .endofpacket
+ sink6_ready => rsp_xbar_demux_016_src0_ready, -- sink6.ready
+ sink6_valid => rsp_xbar_demux_016_src0_valid, -- .valid
+ sink6_channel => rsp_xbar_demux_016_src0_channel, -- .channel
+ sink6_data => rsp_xbar_demux_016_src0_data, -- .data
+ sink6_startofpacket => rsp_xbar_demux_016_src0_startofpacket, -- .startofpacket
+ sink6_endofpacket => rsp_xbar_demux_016_src0_endofpacket -- .endofpacket
+ );
+
+ crosser : component altera_avalon_st_handshake_clock_crosser_0001
+ port map (
+ in_clk => csr_clk_clk, -- in_clk.clk
+ in_reset => rst_controller_reset_out_reset, -- in_clk_reset.reset
+ out_clk => tx_clk_clk, -- out_clk.clk
+ out_reset => rst_controller_001_reset_out_reset, -- out_clk_reset.reset
+ in_ready => cmd_xbar_demux_src0_ready, -- in.ready
+ in_valid => cmd_xbar_demux_src0_valid, -- .valid
+ in_startofpacket => cmd_xbar_demux_src0_startofpacket, -- .startofpacket
+ in_endofpacket => cmd_xbar_demux_src0_endofpacket, -- .endofpacket
+ in_channel => cmd_xbar_demux_src0_channel, -- .channel
+ in_data => cmd_xbar_demux_src0_data, -- .data
+ out_ready => crosser_out_ready, -- out.ready
+ out_valid => crosser_out_valid, -- .valid
+ out_startofpacket => crosser_out_startofpacket, -- .startofpacket
+ out_endofpacket => crosser_out_endofpacket, -- .endofpacket
+ out_channel => crosser_out_channel, -- .channel
+ out_data => crosser_out_data -- .data
+ );
+
+ crosser_001 : component altera_avalon_st_handshake_clock_crosser_0001
+ port map (
+ in_clk => csr_clk_clk, -- in_clk.clk
+ in_reset => rst_controller_reset_out_reset, -- in_clk_reset.reset
+ out_clk => rx_clk_clk, -- out_clk.clk
+ out_reset => rst_controller_002_reset_out_reset, -- out_clk_reset.reset
+ in_ready => cmd_xbar_demux_src1_ready, -- in.ready
+ in_valid => cmd_xbar_demux_src1_valid, -- .valid
+ in_startofpacket => cmd_xbar_demux_src1_startofpacket, -- .startofpacket
+ in_endofpacket => cmd_xbar_demux_src1_endofpacket, -- .endofpacket
+ in_channel => cmd_xbar_demux_src1_channel, -- .channel
+ in_data => cmd_xbar_demux_src1_data, -- .data
+ out_ready => crosser_001_out_ready, -- out.ready
+ out_valid => crosser_001_out_valid, -- .valid
+ out_startofpacket => crosser_001_out_startofpacket, -- .startofpacket
+ out_endofpacket => crosser_001_out_endofpacket, -- .endofpacket
+ out_channel => crosser_001_out_channel, -- .channel
+ out_data => crosser_001_out_data -- .data
+ );
+
+ crosser_002 : component altera_avalon_st_handshake_clock_crosser_0001
+ port map (
+ in_clk => tx_clk_clk, -- in_clk.clk
+ in_reset => rst_controller_001_reset_out_reset, -- in_clk_reset.reset
+ out_clk => csr_clk_clk, -- out_clk.clk
+ out_reset => rst_controller_reset_out_reset, -- out_clk_reset.reset
+ in_ready => rsp_xbar_demux_src0_ready, -- in.ready
+ in_valid => rsp_xbar_demux_src0_valid, -- .valid
+ in_startofpacket => rsp_xbar_demux_src0_startofpacket, -- .startofpacket
+ in_endofpacket => rsp_xbar_demux_src0_endofpacket, -- .endofpacket
+ in_channel => rsp_xbar_demux_src0_channel, -- .channel
+ in_data => rsp_xbar_demux_src0_data, -- .data
+ out_ready => crosser_002_out_ready, -- out.ready
+ out_valid => crosser_002_out_valid, -- .valid
+ out_startofpacket => crosser_002_out_startofpacket, -- .startofpacket
+ out_endofpacket => crosser_002_out_endofpacket, -- .endofpacket
+ out_channel => crosser_002_out_channel, -- .channel
+ out_data => crosser_002_out_data -- .data
+ );
+
+ crosser_003 : component altera_avalon_st_handshake_clock_crosser_0001
+ port map (
+ in_clk => rx_clk_clk, -- in_clk.clk
+ in_reset => rst_controller_002_reset_out_reset, -- in_clk_reset.reset
+ out_clk => csr_clk_clk, -- out_clk.clk
+ out_reset => rst_controller_reset_out_reset, -- out_clk_reset.reset
+ in_ready => rsp_xbar_demux_001_src0_ready, -- in.ready
+ in_valid => rsp_xbar_demux_001_src0_valid, -- .valid
+ in_startofpacket => rsp_xbar_demux_001_src0_startofpacket, -- .startofpacket
+ in_endofpacket => rsp_xbar_demux_001_src0_endofpacket, -- .endofpacket
+ in_channel => rsp_xbar_demux_001_src0_channel, -- .channel
+ in_data => rsp_xbar_demux_001_src0_data, -- .data
+ out_ready => crosser_003_out_ready, -- out.ready
+ out_valid => crosser_003_out_valid, -- .valid
+ out_startofpacket => crosser_003_out_startofpacket, -- .startofpacket
+ out_endofpacket => crosser_003_out_endofpacket, -- .endofpacket
+ out_channel => crosser_003_out_channel, -- .channel
+ out_data => crosser_003_out_data -- .data
+ );
+
+ rx_reset_reset_n_ports_inv <= not rx_reset_reset_n;
+
+ csr_reset_reset_n_ports_inv <= not csr_reset_reset_n;
+
+ tx_reset_reset_n_ports_inv <= not tx_reset_reset_n;
+
+ rst_controller_001_reset_out_reset_ports_inv <= not rst_controller_001_reset_out_reset;
+
+ rst_controller_002_reset_out_reset_ports_inv <= not rst_controller_002_reset_out_reset;
+
+end architecture rtl; -- of ip_stratixiv_mac_10g
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g_rx_eth_crc_checker.vhd b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g_rx_eth_crc_checker.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2bb17a4d6e1809dde3b43e12457bde387891aab8
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g_rx_eth_crc_checker.vhd
@@ -0,0 +1,110 @@
+-- ip_stratixiv_mac_10g_rx_eth_crc_checker.vhd
+
+-- This file was auto-generated from altera_eth_10g_mac_hw.tcl. If you edit it your changes
+-- will probably be lost.
+--
+-- Generated using ACDS version 11.1sp2 259 at 2014.10.02.11:39:51
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity ip_stratixiv_mac_10g_rx_eth_crc_checker is
+ generic (
+ BITSPERSYMBOL : integer := 8;
+ SYMBOLSPERBEAT : integer := 8;
+ ERROR_WIDTH : integer := 1;
+ MODE_CHECKER_0_INSERTER_1 : integer := 0
+ );
+ port (
+ clk : in std_logic := '0'; -- clock_reset.clk
+ reset : in std_logic := '0'; -- clock_reset_reset.reset
+ csr_write : in std_logic := '0'; -- csr.write
+ csr_read : in std_logic := '0'; -- .read
+ csr_address : in std_logic := '0'; -- .address
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ csr_readdata : out std_logic_vector(31 downto 0); -- .readdata
+ data_sink_sop : in std_logic := '0'; -- avalon_streaming_sink.startofpacket
+ data_sink_eop : in std_logic := '0'; -- .endofpacket
+ data_sink_valid : in std_logic := '0'; -- .valid
+ data_sink_data : in std_logic_vector(63 downto 0) := (others => '0'); -- .data
+ data_sink_empty : in std_logic_vector(2 downto 0) := (others => '0'); -- .empty
+ data_sink_error : in std_logic_vector(0 downto 0) := (others => '0'); -- .error
+ data_src_sop : out std_logic; -- avalon_streaming_source.startofpacket
+ data_src_eop : out std_logic; -- .endofpacket
+ data_src_valid : out std_logic; -- .valid
+ data_src_data : out std_logic_vector(63 downto 0); -- .data
+ data_src_empty : out std_logic_vector(2 downto 0); -- .empty
+ data_src_error : out std_logic_vector(1 downto 0); -- .error
+ data_sink_ready : out std_logic;
+ data_src_ready : in std_logic := '0'
+ );
+end entity ip_stratixiv_mac_10g_rx_eth_crc_checker;
+
+architecture rtl of ip_stratixiv_mac_10g_rx_eth_crc_checker is
+ component altera_eth_crc is
+ generic (
+ BITSPERSYMBOL : integer := 8;
+ SYMBOLSPERBEAT : integer := 8;
+ ERROR_WIDTH : integer := 2;
+ MODE_CHECKER_0_INSERTER_1 : integer := 1
+ );
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ csr_write : in std_logic := 'X'; -- write
+ csr_read : in std_logic := 'X'; -- read
+ csr_address : in std_logic := 'X'; -- address
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ csr_readdata : out std_logic_vector(31 downto 0); -- readdata
+ data_sink_sop : in std_logic := 'X'; -- startofpacket
+ data_sink_eop : in std_logic := 'X'; -- endofpacket
+ data_sink_valid : in std_logic := 'X'; -- valid
+ data_sink_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ data_sink_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ data_sink_error : in std_logic_vector(0 downto 0) := (others => 'X'); -- error
+ data_src_sop : out std_logic; -- startofpacket
+ data_src_eop : out std_logic; -- endofpacket
+ data_src_valid : out std_logic; -- valid
+ data_src_data : out std_logic_vector(63 downto 0); -- data
+ data_src_empty : out std_logic_vector(2 downto 0); -- empty
+ data_src_error : out std_logic_vector(1 downto 0); -- error
+ data_sink_ready : out std_logic; -- ready
+ data_src_ready : in std_logic := 'X' -- ready
+ );
+ end component altera_eth_crc;
+
+begin
+
+ rx_eth_crc_checker : component altera_eth_crc
+ generic map (
+ BITSPERSYMBOL => BITSPERSYMBOL,
+ SYMBOLSPERBEAT => SYMBOLSPERBEAT,
+ ERROR_WIDTH => ERROR_WIDTH,
+ MODE_CHECKER_0_INSERTER_1 => MODE_CHECKER_0_INSERTER_1
+ )
+ port map (
+ clk => clk, -- clock_reset.clk
+ reset => reset, -- clock_reset_reset.reset
+ csr_write => csr_write, -- csr.write
+ csr_read => csr_read, -- .read
+ csr_address => csr_address, -- .address
+ csr_writedata => csr_writedata, -- .writedata
+ csr_readdata => csr_readdata, -- .readdata
+ data_sink_sop => data_sink_sop, -- avalon_streaming_sink.startofpacket
+ data_sink_eop => data_sink_eop, -- .endofpacket
+ data_sink_valid => data_sink_valid, -- .valid
+ data_sink_data => data_sink_data, -- .data
+ data_sink_empty => data_sink_empty, -- .empty
+ data_sink_error => data_sink_error, -- .error
+ data_src_sop => data_src_sop, -- avalon_streaming_source.startofpacket
+ data_src_eop => data_src_eop, -- .endofpacket
+ data_src_valid => data_src_valid, -- .valid
+ data_src_data => data_src_data, -- .data
+ data_src_empty => data_src_empty, -- .empty
+ data_src_error => data_src_error, -- .error
+ data_sink_ready => open, -- (terminated)
+ data_src_ready => '1' -- (terminated)
+ );
+
+end architecture rtl; -- of ip_stratixiv_mac_10g_rx_eth_crc_checker
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g_rx_eth_frame_decoder.vhd b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g_rx_eth_frame_decoder.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d047ce86e3a37e4815e897b5be45f62ff94f2cf9
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g_rx_eth_frame_decoder.vhd
@@ -0,0 +1,149 @@
+-- ip_stratixiv_mac_10g_rx_eth_frame_decoder.vhd
+
+-- This file was auto-generated from altera_eth_10g_mac_hw.tcl. If you edit it your changes
+-- will probably be lost.
+--
+-- Generated using ACDS version 11.1sp2 259 at 2014.10.02.11:39:51
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity ip_stratixiv_mac_10g_rx_eth_frame_decoder is
+ generic (
+ BITSPERSYMBOL : integer := 8;
+ SYMBOLSPERBEAT : integer := 8;
+ ERROR_WIDTH : integer := 1;
+ ENABLE_SUPP_ADDR : integer := 1;
+ ENABLE_PFC : integer := 0;
+ PFC_PRIORITY_NUM : integer := 8
+ );
+ port (
+ clk : in std_logic := '0'; -- clock_reset.clk
+ reset : in std_logic := '0'; -- clock_reset_reset.reset
+ csr_readdata : out std_logic_vector(31 downto 0); -- avalom_mm_csr.readdata
+ csr_write : in std_logic := '0'; -- .write
+ csr_read : in std_logic := '0'; -- .read
+ csr_address : in std_logic_vector(4 downto 0) := (others => '0'); -- .address
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ data_sink_sop : in std_logic := '0'; -- avalon_st_data_sink.startofpacket
+ data_sink_eop : in std_logic := '0'; -- .endofpacket
+ data_sink_valid : in std_logic := '0'; -- .valid
+ data_sink_data : in std_logic_vector(63 downto 0) := (others => '0'); -- .data
+ data_sink_empty : in std_logic_vector(2 downto 0) := (others => '0'); -- .empty
+ data_sink_error : in std_logic_vector(0 downto 0) := (others => '0'); -- .error
+ data_src_sop : out std_logic; -- avalon_st_data_src.startofpacket
+ data_src_eop : out std_logic; -- .endofpacket
+ data_src_valid : out std_logic; -- .valid
+ data_src_data : out std_logic_vector(63 downto 0); -- .data
+ data_src_empty : out std_logic_vector(2 downto 0); -- .empty
+ data_src_error : out std_logic_vector(3 downto 0); -- .error
+ pauselen_src_valid : out std_logic; -- avalon_st_pauselen_src.valid
+ pauselen_src_data : out std_logic_vector(15 downto 0); -- .data
+ rxstatus_src_valid : out std_logic; -- avalon_st_rxstatus_src.valid
+ rxstatus_src_data : out std_logic_vector(39 downto 0); -- .data
+ rxstatus_src_error : out std_logic_vector(3 downto 0); -- .error
+ pktinfo_src_valid : out std_logic; -- avalon_st_pktinfo_src.valid
+ pktinfo_src_data : out std_logic_vector(22 downto 0); -- .data
+ data_sink_ready : out std_logic;
+ data_src_ready : in std_logic := '0';
+ pfc_pause_quanta_src_data : out std_logic_vector(135 downto 0);
+ pfc_pause_quanta_src_valid : out std_logic;
+ pfc_status_src_data : out std_logic_vector(15 downto 0);
+ pfc_status_src_valid : out std_logic
+ );
+end entity ip_stratixiv_mac_10g_rx_eth_frame_decoder;
+
+architecture rtl of ip_stratixiv_mac_10g_rx_eth_frame_decoder is
+ component altera_eth_frame_decoder is
+ generic (
+ BITSPERSYMBOL : integer := 8;
+ SYMBOLSPERBEAT : integer := 8;
+ ERROR_WIDTH : integer := 2;
+ ENABLE_SUPP_ADDR : integer := 1;
+ ENABLE_PFC : integer := 0;
+ PFC_PRIORITY_NUM : integer := 8
+ );
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ csr_readdata : out std_logic_vector(31 downto 0); -- readdata
+ csr_write : in std_logic := 'X'; -- write
+ csr_read : in std_logic := 'X'; -- read
+ csr_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ data_sink_sop : in std_logic := 'X'; -- startofpacket
+ data_sink_eop : in std_logic := 'X'; -- endofpacket
+ data_sink_valid : in std_logic := 'X'; -- valid
+ data_sink_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ data_sink_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ data_sink_error : in std_logic_vector(0 downto 0) := (others => 'X'); -- error
+ data_src_sop : out std_logic; -- startofpacket
+ data_src_eop : out std_logic; -- endofpacket
+ data_src_valid : out std_logic; -- valid
+ data_src_data : out std_logic_vector(63 downto 0); -- data
+ data_src_empty : out std_logic_vector(2 downto 0); -- empty
+ data_src_error : out std_logic_vector(3 downto 0); -- error
+ pauselen_src_valid : out std_logic; -- valid
+ pauselen_src_data : out std_logic_vector(15 downto 0); -- data
+ rxstatus_src_valid : out std_logic; -- valid
+ rxstatus_src_data : out std_logic_vector(39 downto 0); -- data
+ rxstatus_src_error : out std_logic_vector(3 downto 0); -- error
+ pktinfo_src_valid : out std_logic; -- valid
+ pktinfo_src_data : out std_logic_vector(22 downto 0); -- data
+ data_sink_ready : out std_logic; -- ready
+ data_src_ready : in std_logic := 'X'; -- ready
+ pfc_pause_quanta_src_valid : out std_logic; -- valid
+ pfc_pause_quanta_src_data : out std_logic_vector(135 downto 0); -- data
+ pfc_status_src_valid : out std_logic; -- valid
+ pfc_status_src_data : out std_logic_vector(15 downto 0) -- data
+ );
+ end component altera_eth_frame_decoder;
+
+begin
+
+ rx_eth_frame_decoder : component altera_eth_frame_decoder
+ generic map (
+ BITSPERSYMBOL => BITSPERSYMBOL,
+ SYMBOLSPERBEAT => SYMBOLSPERBEAT,
+ ERROR_WIDTH => ERROR_WIDTH,
+ ENABLE_SUPP_ADDR => ENABLE_SUPP_ADDR,
+ ENABLE_PFC => ENABLE_PFC,
+ PFC_PRIORITY_NUM => PFC_PRIORITY_NUM
+ )
+ port map (
+ clk => clk, -- clock_reset.clk
+ reset => reset, -- clock_reset_reset.reset
+ csr_readdata => csr_readdata, -- avalom_mm_csr.readdata
+ csr_write => csr_write, -- .write
+ csr_read => csr_read, -- .read
+ csr_address => csr_address, -- .address
+ csr_writedata => csr_writedata, -- .writedata
+ data_sink_sop => data_sink_sop, -- avalon_st_data_sink.startofpacket
+ data_sink_eop => data_sink_eop, -- .endofpacket
+ data_sink_valid => data_sink_valid, -- .valid
+ data_sink_data => data_sink_data, -- .data
+ data_sink_empty => data_sink_empty, -- .empty
+ data_sink_error => data_sink_error, -- .error
+ data_src_sop => data_src_sop, -- avalon_st_data_src.startofpacket
+ data_src_eop => data_src_eop, -- .endofpacket
+ data_src_valid => data_src_valid, -- .valid
+ data_src_data => data_src_data, -- .data
+ data_src_empty => data_src_empty, -- .empty
+ data_src_error => data_src_error, -- .error
+ pauselen_src_valid => pauselen_src_valid, -- avalon_st_pauselen_src.valid
+ pauselen_src_data => pauselen_src_data, -- .data
+ rxstatus_src_valid => rxstatus_src_valid, -- avalon_st_rxstatus_src.valid
+ rxstatus_src_data => rxstatus_src_data, -- .data
+ rxstatus_src_error => rxstatus_src_error, -- .error
+ pktinfo_src_valid => pktinfo_src_valid, -- avalon_st_pktinfo_src.valid
+ pktinfo_src_data => pktinfo_src_data, -- .data
+ data_sink_ready => open, -- (terminated)
+ data_src_ready => '1', -- (terminated)
+ pfc_pause_quanta_src_valid => open, -- (terminated)
+ pfc_pause_quanta_src_data => open, -- (terminated)
+ pfc_status_src_valid => open, -- (terminated)
+ pfc_status_src_data => open -- (terminated)
+ );
+
+end architecture rtl; -- of ip_stratixiv_mac_10g_rx_eth_frame_decoder
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g_rx_eth_pkt_backpressure_control.vhd b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g_rx_eth_pkt_backpressure_control.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d072810c1ea2c7faa9ac143204da15e5bfcb28da
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g_rx_eth_pkt_backpressure_control.vhd
@@ -0,0 +1,116 @@
+-- ip_stratixiv_mac_10g_rx_eth_pkt_backpressure_control.vhd
+
+-- This file was auto-generated from altera_eth_10g_mac_hw.tcl. If you edit it your changes
+-- will probably be lost.
+--
+-- Generated using ACDS version 11.1sp2 259 at 2014.10.02.11:39:51
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity ip_stratixiv_mac_10g_rx_eth_pkt_backpressure_control is
+ generic (
+ BITSPERSYMBOL : integer := 8;
+ SYMBOLSPERBEAT : integer := 8;
+ ERROR_WIDTH : integer := 1;
+ USE_READY : integer := 0
+ );
+ port (
+ clk : in std_logic := '0'; -- clock_reset.clk
+ reset : in std_logic := '0'; -- clock_reset_reset.reset
+ csr_write : in std_logic := '0'; -- csr.write
+ csr_read : in std_logic := '0'; -- .read
+ csr_address : in std_logic_vector(0 downto 0) := (others => '0'); -- .address
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ csr_readdata : out std_logic_vector(31 downto 0); -- .readdata
+ data_src_sop : out std_logic; -- avalon_st_source_data.startofpacket
+ data_src_eop : out std_logic; -- .endofpacket
+ data_src_valid : out std_logic; -- .valid
+ data_src_data : out std_logic_vector(63 downto 0); -- .data
+ data_src_empty : out std_logic_vector(2 downto 0); -- .empty
+ data_src_error : out std_logic_vector(0 downto 0); -- .error
+ data_sink_sop : in std_logic := '0'; -- avalon_st_sink_data.startofpacket
+ data_sink_eop : in std_logic := '0'; -- .endofpacket
+ data_sink_valid : in std_logic := '0'; -- .valid
+ data_sink_data : in std_logic_vector(63 downto 0) := (others => '0'); -- .data
+ data_sink_empty : in std_logic_vector(2 downto 0) := (others => '0'); -- .empty
+ data_sink_error : in std_logic_vector(0 downto 0) := (others => '0'); -- .error
+ data_sink_ready : out std_logic;
+ data_src_ready : in std_logic := '0';
+ pausebeats_sink_data : in std_logic_vector(31 downto 0) := (others => '0');
+ pausebeats_sink_valid : in std_logic := '0'
+ );
+end entity ip_stratixiv_mac_10g_rx_eth_pkt_backpressure_control;
+
+architecture rtl of ip_stratixiv_mac_10g_rx_eth_pkt_backpressure_control is
+ component altera_eth_pkt_backpressure_control is
+ generic (
+ BITSPERSYMBOL : integer := 8;
+ SYMBOLSPERBEAT : integer := 8;
+ ERROR_WIDTH : integer := 1;
+ USE_READY : integer := 1
+ );
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ csr_write : in std_logic := 'X'; -- write
+ csr_read : in std_logic := 'X'; -- read
+ csr_address : in std_logic_vector(0 downto 0) := (others => 'X'); -- address
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ csr_readdata : out std_logic_vector(31 downto 0); -- readdata
+ data_src_sop : out std_logic; -- startofpacket
+ data_src_eop : out std_logic; -- endofpacket
+ data_src_valid : out std_logic; -- valid
+ data_src_data : out std_logic_vector(63 downto 0); -- data
+ data_src_empty : out std_logic_vector(2 downto 0); -- empty
+ data_src_error : out std_logic_vector(0 downto 0); -- error
+ data_sink_sop : in std_logic := 'X'; -- startofpacket
+ data_sink_eop : in std_logic := 'X'; -- endofpacket
+ data_sink_valid : in std_logic := 'X'; -- valid
+ data_sink_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ data_sink_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ data_sink_error : in std_logic_vector(0 downto 0) := (others => 'X'); -- error
+ data_src_ready : in std_logic := 'X'; -- ready
+ data_sink_ready : out std_logic; -- ready
+ pausebeats_sink_valid : in std_logic := 'X'; -- valid
+ pausebeats_sink_data : in std_logic_vector(31 downto 0) := (others => 'X') -- data
+ );
+ end component altera_eth_pkt_backpressure_control;
+
+begin
+
+ rx_eth_pkt_backpressure_control : component altera_eth_pkt_backpressure_control
+ generic map (
+ BITSPERSYMBOL => BITSPERSYMBOL,
+ SYMBOLSPERBEAT => SYMBOLSPERBEAT,
+ ERROR_WIDTH => ERROR_WIDTH,
+ USE_READY => USE_READY
+ )
+ port map (
+ clk => clk, -- clock_reset.clk
+ reset => reset, -- clock_reset_reset.reset
+ csr_write => csr_write, -- csr.write
+ csr_read => csr_read, -- .read
+ csr_address => csr_address, -- .address
+ csr_writedata => csr_writedata, -- .writedata
+ csr_readdata => csr_readdata, -- .readdata
+ data_src_sop => data_src_sop, -- avalon_st_source_data.startofpacket
+ data_src_eop => data_src_eop, -- .endofpacket
+ data_src_valid => data_src_valid, -- .valid
+ data_src_data => data_src_data, -- .data
+ data_src_empty => data_src_empty, -- .empty
+ data_src_error => data_src_error, -- .error
+ data_sink_sop => data_sink_sop, -- avalon_st_sink_data.startofpacket
+ data_sink_eop => data_sink_eop, -- .endofpacket
+ data_sink_valid => data_sink_valid, -- .valid
+ data_sink_data => data_sink_data, -- .data
+ data_sink_empty => data_sink_empty, -- .empty
+ data_sink_error => data_sink_error, -- .error
+ data_src_ready => '1', -- (terminated)
+ data_sink_ready => open, -- (terminated)
+ pausebeats_sink_valid => '0', -- (terminated)
+ pausebeats_sink_data => "00000000000000000000000000000000" -- (terminated)
+ );
+
+end architecture rtl; -- of ip_stratixiv_mac_10g_rx_eth_pkt_backpressure_control
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g_tx_eth_crc_inserter.vhd b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g_tx_eth_crc_inserter.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..8014af392216940e2fc51617d367396cc50db67d
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g_tx_eth_crc_inserter.vhd
@@ -0,0 +1,110 @@
+-- ip_stratixiv_mac_10g_tx_eth_crc_inserter.vhd
+
+-- This file was auto-generated from altera_eth_10g_mac_hw.tcl. If you edit it your changes
+-- will probably be lost.
+--
+-- Generated using ACDS version 11.1sp2 259 at 2014.10.02.11:39:51
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity ip_stratixiv_mac_10g_tx_eth_crc_inserter is
+ generic (
+ BITSPERSYMBOL : integer := 8;
+ SYMBOLSPERBEAT : integer := 8;
+ ERROR_WIDTH : integer := 2;
+ MODE_CHECKER_0_INSERTER_1 : integer := 1
+ );
+ port (
+ clk : in std_logic := '0'; -- clock_reset.clk
+ reset : in std_logic := '0'; -- clock_reset_reset.reset
+ csr_write : in std_logic := '0'; -- csr.write
+ csr_read : in std_logic := '0'; -- .read
+ csr_address : in std_logic := '0'; -- .address
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ csr_readdata : out std_logic_vector(31 downto 0); -- .readdata
+ data_sink_sop : in std_logic := '0'; -- avalon_streaming_sink.startofpacket
+ data_sink_eop : in std_logic := '0'; -- .endofpacket
+ data_sink_valid : in std_logic := '0'; -- .valid
+ data_sink_ready : out std_logic; -- .ready
+ data_sink_data : in std_logic_vector(63 downto 0) := (others => '0'); -- .data
+ data_sink_empty : in std_logic_vector(2 downto 0) := (others => '0'); -- .empty
+ data_sink_error : in std_logic_vector(1 downto 0) := (others => '0'); -- .error
+ data_src_sop : out std_logic; -- avalon_streaming_source.startofpacket
+ data_src_eop : out std_logic; -- .endofpacket
+ data_src_valid : out std_logic; -- .valid
+ data_src_ready : in std_logic := '0'; -- .ready
+ data_src_data : out std_logic_vector(63 downto 0); -- .data
+ data_src_empty : out std_logic_vector(2 downto 0); -- .empty
+ data_src_error : out std_logic_vector(2 downto 0) -- .error
+ );
+end entity ip_stratixiv_mac_10g_tx_eth_crc_inserter;
+
+architecture rtl of ip_stratixiv_mac_10g_tx_eth_crc_inserter is
+ component altera_eth_crc is
+ generic (
+ BITSPERSYMBOL : integer := 8;
+ SYMBOLSPERBEAT : integer := 8;
+ ERROR_WIDTH : integer := 2;
+ MODE_CHECKER_0_INSERTER_1 : integer := 1
+ );
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ csr_write : in std_logic := 'X'; -- write
+ csr_read : in std_logic := 'X'; -- read
+ csr_address : in std_logic := 'X'; -- address
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ csr_readdata : out std_logic_vector(31 downto 0); -- readdata
+ data_sink_sop : in std_logic := 'X'; -- startofpacket
+ data_sink_eop : in std_logic := 'X'; -- endofpacket
+ data_sink_valid : in std_logic := 'X'; -- valid
+ data_sink_ready : out std_logic; -- ready
+ data_sink_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ data_sink_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ data_sink_error : in std_logic_vector(1 downto 0) := (others => 'X'); -- error
+ data_src_sop : out std_logic; -- startofpacket
+ data_src_eop : out std_logic; -- endofpacket
+ data_src_valid : out std_logic; -- valid
+ data_src_ready : in std_logic := 'X'; -- ready
+ data_src_data : out std_logic_vector(63 downto 0); -- data
+ data_src_empty : out std_logic_vector(2 downto 0); -- empty
+ data_src_error : out std_logic_vector(2 downto 0) -- error
+ );
+ end component altera_eth_crc;
+
+begin
+
+ tx_eth_crc_inserter : component altera_eth_crc
+ generic map (
+ BITSPERSYMBOL => BITSPERSYMBOL,
+ SYMBOLSPERBEAT => SYMBOLSPERBEAT,
+ ERROR_WIDTH => ERROR_WIDTH,
+ MODE_CHECKER_0_INSERTER_1 => MODE_CHECKER_0_INSERTER_1
+ )
+ port map (
+ clk => clk, -- clock_reset.clk
+ reset => reset, -- clock_reset_reset.reset
+ csr_write => csr_write, -- csr.write
+ csr_read => csr_read, -- .read
+ csr_address => csr_address, -- .address
+ csr_writedata => csr_writedata, -- .writedata
+ csr_readdata => csr_readdata, -- .readdata
+ data_sink_sop => data_sink_sop, -- avalon_streaming_sink.startofpacket
+ data_sink_eop => data_sink_eop, -- .endofpacket
+ data_sink_valid => data_sink_valid, -- .valid
+ data_sink_ready => data_sink_ready, -- .ready
+ data_sink_data => data_sink_data, -- .data
+ data_sink_empty => data_sink_empty, -- .empty
+ data_sink_error => data_sink_error, -- .error
+ data_src_sop => data_src_sop, -- avalon_streaming_source.startofpacket
+ data_src_eop => data_src_eop, -- .endofpacket
+ data_src_valid => data_src_valid, -- .valid
+ data_src_ready => data_src_ready, -- .ready
+ data_src_data => data_src_data, -- .data
+ data_src_empty => data_src_empty, -- .empty
+ data_src_error => data_src_error -- .error
+ );
+
+end architecture rtl; -- of ip_stratixiv_mac_10g_tx_eth_crc_inserter
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g_tx_eth_frame_decoder.vhd b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g_tx_eth_frame_decoder.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..37e2cf3c5deaae6a763b296b3c06cf2e613f467f
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g_tx_eth_frame_decoder.vhd
@@ -0,0 +1,149 @@
+-- ip_stratixiv_mac_10g_tx_eth_frame_decoder.vhd
+
+-- This file was auto-generated from altera_eth_10g_mac_hw.tcl. If you edit it your changes
+-- will probably be lost.
+--
+-- Generated using ACDS version 11.1sp2 259 at 2014.10.02.11:39:51
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity ip_stratixiv_mac_10g_tx_eth_frame_decoder is
+ generic (
+ BITSPERSYMBOL : integer := 8;
+ SYMBOLSPERBEAT : integer := 8;
+ ERROR_WIDTH : integer := 3;
+ ENABLE_SUPP_ADDR : integer := 0;
+ ENABLE_PFC : integer := 0;
+ PFC_PRIORITY_NUM : integer := 8
+ );
+ port (
+ clk : in std_logic := '0'; -- clock_reset.clk
+ reset : in std_logic := '0'; -- clock_reset_reset.reset
+ csr_readdata : out std_logic_vector(31 downto 0); -- avalom_mm_csr.readdata
+ csr_write : in std_logic := '0'; -- .write
+ csr_read : in std_logic := '0'; -- .read
+ csr_address : in std_logic_vector(4 downto 0) := (others => '0'); -- .address
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ data_sink_sop : in std_logic := '0'; -- avalon_st_data_sink.startofpacket
+ data_sink_eop : in std_logic := '0'; -- .endofpacket
+ data_sink_valid : in std_logic := '0'; -- .valid
+ data_sink_data : in std_logic_vector(63 downto 0) := (others => '0'); -- .data
+ data_sink_empty : in std_logic_vector(2 downto 0) := (others => '0'); -- .empty
+ data_sink_error : in std_logic_vector(2 downto 0) := (others => '0'); -- .error
+ rxstatus_src_valid : out std_logic; -- avalon_st_rxstatus_src.valid
+ rxstatus_src_data : out std_logic_vector(39 downto 0); -- .data
+ rxstatus_src_error : out std_logic_vector(5 downto 0); -- .error
+ data_sink_ready : out std_logic;
+ data_src_data : out std_logic_vector(63 downto 0);
+ data_src_empty : out std_logic_vector(2 downto 0);
+ data_src_eop : out std_logic;
+ data_src_error : out std_logic_vector(5 downto 0);
+ data_src_ready : in std_logic := '0';
+ data_src_sop : out std_logic;
+ data_src_valid : out std_logic;
+ pauselen_src_data : out std_logic_vector(15 downto 0);
+ pauselen_src_valid : out std_logic;
+ pfc_pause_quanta_src_data : out std_logic_vector(135 downto 0);
+ pfc_pause_quanta_src_valid : out std_logic;
+ pfc_status_src_data : out std_logic_vector(15 downto 0);
+ pfc_status_src_valid : out std_logic;
+ pktinfo_src_data : out std_logic_vector(22 downto 0);
+ pktinfo_src_valid : out std_logic
+ );
+end entity ip_stratixiv_mac_10g_tx_eth_frame_decoder;
+
+architecture rtl of ip_stratixiv_mac_10g_tx_eth_frame_decoder is
+ component altera_eth_frame_decoder is
+ generic (
+ BITSPERSYMBOL : integer := 8;
+ SYMBOLSPERBEAT : integer := 8;
+ ERROR_WIDTH : integer := 2;
+ ENABLE_SUPP_ADDR : integer := 1;
+ ENABLE_PFC : integer := 0;
+ PFC_PRIORITY_NUM : integer := 8
+ );
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ csr_readdata : out std_logic_vector(31 downto 0); -- readdata
+ csr_write : in std_logic := 'X'; -- write
+ csr_read : in std_logic := 'X'; -- read
+ csr_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ data_sink_sop : in std_logic := 'X'; -- startofpacket
+ data_sink_eop : in std_logic := 'X'; -- endofpacket
+ data_sink_valid : in std_logic := 'X'; -- valid
+ data_sink_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ data_sink_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ data_sink_error : in std_logic_vector(2 downto 0) := (others => 'X'); -- error
+ rxstatus_src_valid : out std_logic; -- valid
+ rxstatus_src_data : out std_logic_vector(39 downto 0); -- data
+ rxstatus_src_error : out std_logic_vector(5 downto 0); -- error
+ data_sink_ready : out std_logic; -- ready
+ data_src_sop : out std_logic; -- startofpacket
+ data_src_eop : out std_logic; -- endofpacket
+ data_src_valid : out std_logic; -- valid
+ data_src_ready : in std_logic := 'X'; -- ready
+ data_src_data : out std_logic_vector(63 downto 0); -- data
+ data_src_empty : out std_logic_vector(2 downto 0); -- empty
+ data_src_error : out std_logic_vector(5 downto 0); -- error
+ pauselen_src_valid : out std_logic; -- valid
+ pauselen_src_data : out std_logic_vector(15 downto 0); -- data
+ pfc_pause_quanta_src_valid : out std_logic; -- valid
+ pfc_pause_quanta_src_data : out std_logic_vector(135 downto 0); -- data
+ pfc_status_src_valid : out std_logic; -- valid
+ pfc_status_src_data : out std_logic_vector(15 downto 0); -- data
+ pktinfo_src_valid : out std_logic; -- valid
+ pktinfo_src_data : out std_logic_vector(22 downto 0) -- data
+ );
+ end component altera_eth_frame_decoder;
+
+begin
+
+ tx_eth_frame_decoder : component altera_eth_frame_decoder
+ generic map (
+ BITSPERSYMBOL => BITSPERSYMBOL,
+ SYMBOLSPERBEAT => SYMBOLSPERBEAT,
+ ERROR_WIDTH => ERROR_WIDTH,
+ ENABLE_SUPP_ADDR => ENABLE_SUPP_ADDR,
+ ENABLE_PFC => ENABLE_PFC,
+ PFC_PRIORITY_NUM => PFC_PRIORITY_NUM
+ )
+ port map (
+ clk => clk, -- clock_reset.clk
+ reset => reset, -- clock_reset_reset.reset
+ csr_readdata => csr_readdata, -- avalom_mm_csr.readdata
+ csr_write => csr_write, -- .write
+ csr_read => csr_read, -- .read
+ csr_address => csr_address, -- .address
+ csr_writedata => csr_writedata, -- .writedata
+ data_sink_sop => data_sink_sop, -- avalon_st_data_sink.startofpacket
+ data_sink_eop => data_sink_eop, -- .endofpacket
+ data_sink_valid => data_sink_valid, -- .valid
+ data_sink_data => data_sink_data, -- .data
+ data_sink_empty => data_sink_empty, -- .empty
+ data_sink_error => data_sink_error, -- .error
+ rxstatus_src_valid => rxstatus_src_valid, -- avalon_st_rxstatus_src.valid
+ rxstatus_src_data => rxstatus_src_data, -- .data
+ rxstatus_src_error => rxstatus_src_error, -- .error
+ data_sink_ready => open, -- (terminated)
+ data_src_sop => open, -- (terminated)
+ data_src_eop => open, -- (terminated)
+ data_src_valid => open, -- (terminated)
+ data_src_ready => '1', -- (terminated)
+ data_src_data => open, -- (terminated)
+ data_src_empty => open, -- (terminated)
+ data_src_error => open, -- (terminated)
+ pauselen_src_valid => open, -- (terminated)
+ pauselen_src_data => open, -- (terminated)
+ pfc_pause_quanta_src_valid => open, -- (terminated)
+ pfc_pause_quanta_src_data => open, -- (terminated)
+ pfc_status_src_valid => open, -- (terminated)
+ pfc_status_src_data => open, -- (terminated)
+ pktinfo_src_valid => open, -- (terminated)
+ pktinfo_src_data => open -- (terminated)
+ );
+
+end architecture rtl; -- of ip_stratixiv_mac_10g_tx_eth_frame_decoder
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control.vhd b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b07edaade459d04fb229e5ad28275df9d664a518
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control.vhd
@@ -0,0 +1,116 @@
+-- ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control.vhd
+
+-- This file was auto-generated from altera_eth_10g_mac_hw.tcl. If you edit it your changes
+-- will probably be lost.
+--
+-- Generated using ACDS version 11.1sp2 259 at 2014.10.02.11:39:51
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control is
+ generic (
+ BITSPERSYMBOL : integer := 8;
+ SYMBOLSPERBEAT : integer := 8;
+ ERROR_WIDTH : integer := 2;
+ USE_READY : integer := 1
+ );
+ port (
+ clk : in std_logic := '0'; -- clock_reset.clk
+ reset : in std_logic := '0'; -- clock_reset_reset.reset
+ csr_write : in std_logic := '0'; -- csr.write
+ csr_read : in std_logic := '0'; -- .read
+ csr_address : in std_logic_vector(0 downto 0) := (others => '0'); -- .address
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ csr_readdata : out std_logic_vector(31 downto 0); -- .readdata
+ data_src_sop : out std_logic; -- avalon_st_source_data.startofpacket
+ data_src_eop : out std_logic; -- .endofpacket
+ data_src_valid : out std_logic; -- .valid
+ data_src_ready : in std_logic := '0'; -- .ready
+ data_src_data : out std_logic_vector(63 downto 0); -- .data
+ data_src_empty : out std_logic_vector(2 downto 0); -- .empty
+ data_src_error : out std_logic_vector(1 downto 0); -- .error
+ data_sink_sop : in std_logic := '0'; -- avalon_st_sink_data.startofpacket
+ data_sink_eop : in std_logic := '0'; -- .endofpacket
+ data_sink_valid : in std_logic := '0'; -- .valid
+ data_sink_ready : out std_logic; -- .ready
+ data_sink_data : in std_logic_vector(63 downto 0) := (others => '0'); -- .data
+ data_sink_empty : in std_logic_vector(2 downto 0) := (others => '0'); -- .empty
+ data_sink_error : in std_logic_vector(1 downto 0) := (others => '0'); -- .error
+ pausebeats_sink_valid : in std_logic := '0'; -- avalon_st_pause.valid
+ pausebeats_sink_data : in std_logic_vector(31 downto 0) := (others => '0') -- .data
+ );
+end entity ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control;
+
+architecture rtl of ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control is
+ component altera_eth_pkt_backpressure_control is
+ generic (
+ BITSPERSYMBOL : integer := 8;
+ SYMBOLSPERBEAT : integer := 8;
+ ERROR_WIDTH : integer := 1;
+ USE_READY : integer := 1
+ );
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ csr_write : in std_logic := 'X'; -- write
+ csr_read : in std_logic := 'X'; -- read
+ csr_address : in std_logic_vector(0 downto 0) := (others => 'X'); -- address
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ csr_readdata : out std_logic_vector(31 downto 0); -- readdata
+ data_src_sop : out std_logic; -- startofpacket
+ data_src_eop : out std_logic; -- endofpacket
+ data_src_valid : out std_logic; -- valid
+ data_src_ready : in std_logic := 'X'; -- ready
+ data_src_data : out std_logic_vector(63 downto 0); -- data
+ data_src_empty : out std_logic_vector(2 downto 0); -- empty
+ data_src_error : out std_logic_vector(1 downto 0); -- error
+ data_sink_sop : in std_logic := 'X'; -- startofpacket
+ data_sink_eop : in std_logic := 'X'; -- endofpacket
+ data_sink_valid : in std_logic := 'X'; -- valid
+ data_sink_ready : out std_logic; -- ready
+ data_sink_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ data_sink_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ data_sink_error : in std_logic_vector(1 downto 0) := (others => 'X'); -- error
+ pausebeats_sink_valid : in std_logic := 'X'; -- valid
+ pausebeats_sink_data : in std_logic_vector(31 downto 0) := (others => 'X') -- data
+ );
+ end component altera_eth_pkt_backpressure_control;
+
+begin
+
+ tx_eth_pkt_backpressure_control : component altera_eth_pkt_backpressure_control
+ generic map (
+ BITSPERSYMBOL => BITSPERSYMBOL,
+ SYMBOLSPERBEAT => SYMBOLSPERBEAT,
+ ERROR_WIDTH => ERROR_WIDTH,
+ USE_READY => USE_READY
+ )
+ port map (
+ clk => clk, -- clock_reset.clk
+ reset => reset, -- clock_reset_reset.reset
+ csr_write => csr_write, -- csr.write
+ csr_read => csr_read, -- .read
+ csr_address => csr_address, -- .address
+ csr_writedata => csr_writedata, -- .writedata
+ csr_readdata => csr_readdata, -- .readdata
+ data_src_sop => data_src_sop, -- avalon_st_source_data.startofpacket
+ data_src_eop => data_src_eop, -- .endofpacket
+ data_src_valid => data_src_valid, -- .valid
+ data_src_ready => data_src_ready, -- .ready
+ data_src_data => data_src_data, -- .data
+ data_src_empty => data_src_empty, -- .empty
+ data_src_error => data_src_error, -- .error
+ data_sink_sop => data_sink_sop, -- avalon_st_sink_data.startofpacket
+ data_sink_eop => data_sink_eop, -- .endofpacket
+ data_sink_valid => data_sink_valid, -- .valid
+ data_sink_ready => data_sink_ready, -- .ready
+ data_sink_data => data_sink_data, -- .data
+ data_sink_empty => data_sink_empty, -- .empty
+ data_sink_error => data_sink_error, -- .error
+ pausebeats_sink_valid => pausebeats_sink_valid, -- avalon_st_pause.valid
+ pausebeats_sink_data => pausebeats_sink_data -- .data
+ );
+
+end architecture rtl; -- of ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/mentor/msim_setup.tcl b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/mentor/msim_setup.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..0db3db774261eb972d42cf92fcf9df1c1b3a92d4
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/mentor/msim_setup.tcl
@@ -0,0 +1,489 @@
+
+# (C) 2001-2014 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and
+# other software and tools, and its AMPP partner logic functions, and
+# any output files any of the foregoing (including device programming
+# or simulation files), and any associated documentation or information
+# are expressly subject to the terms and conditions of the Altera
+# Program License Subscription Agreement, Altera MegaCore Function
+# License Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by Altera
+# or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+# ----------------------------------------
+# Auto-generated simulation script
+
+# ----------------------------------------
+# Initialize the variable
+if ![info exists SYSTEM_INSTANCE_NAME] {
+ set SYSTEM_INSTANCE_NAME ""
+} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
+ set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
+}
+
+if ![info exists TOP_LEVEL_NAME] {
+ set TOP_LEVEL_NAME "ip_stratixiv_mac_10g"
+} elseif { ![ string match "" $TOP_LEVEL_NAME ] } {
+ set TOP_LEVEL_NAME "$TOP_LEVEL_NAME"
+}
+
+if ![info exists QSYS_SIMDIR] {
+ set QSYS_SIMDIR "./../"
+} elseif { ![ string match "" $QSYS_SIMDIR ] } {
+ set QSYS_SIMDIR "$QSYS_SIMDIR"
+}
+
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+
+# ----------------------------------------
+# Create compilation libraries
+proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
+ensure_lib ./libraries/
+ensure_lib ./libraries/work/
+vmap work ./libraries/work/
+if { ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] } {
+ ensure_lib ./libraries/altera_ver/
+ vmap altera_ver ./libraries/altera_ver/
+ ensure_lib ./libraries/lpm_ver/
+ vmap lpm_ver ./libraries/lpm_ver/
+ ensure_lib ./libraries/sgate_ver/
+ vmap sgate_ver ./libraries/sgate_ver/
+ ensure_lib ./libraries/altera_mf_ver/
+ vmap altera_mf_ver ./libraries/altera_mf_ver/
+ ensure_lib ./libraries/altera_lnsim_ver/
+ vmap altera_lnsim_ver ./libraries/altera_lnsim_ver/
+ ensure_lib ./libraries/stratixiv_hssi_ver/
+ vmap stratixiv_hssi_ver ./libraries/stratixiv_hssi_ver/
+ ensure_lib ./libraries/stratixiv_pcie_hip_ver/
+ vmap stratixiv_pcie_hip_ver ./libraries/stratixiv_pcie_hip_ver/
+ ensure_lib ./libraries/stratixiv_ver/
+ vmap stratixiv_ver ./libraries/stratixiv_ver/
+ ensure_lib ./libraries/altera/
+ vmap altera ./libraries/altera/
+ ensure_lib ./libraries/lpm/
+ vmap lpm ./libraries/lpm/
+ ensure_lib ./libraries/sgate/
+ vmap sgate ./libraries/sgate/
+ ensure_lib ./libraries/altera_mf/
+ vmap altera_mf ./libraries/altera_mf/
+ ensure_lib ./libraries/altera_lnsim/
+ vmap altera_lnsim ./libraries/altera_lnsim/
+ ensure_lib ./libraries/stratixiv_hssi/
+ vmap stratixiv_hssi ./libraries/stratixiv_hssi/
+ ensure_lib ./libraries/stratixiv_pcie_hip/
+ vmap stratixiv_pcie_hip ./libraries/stratixiv_pcie_hip/
+ ensure_lib ./libraries/stratixiv/
+ vmap stratixiv ./libraries/stratixiv/
+}
+ensure_lib ./libraries/ip_stratixiv_mac_10g_crosser/
+vmap ip_stratixiv_mac_10g_crosser ./libraries/ip_stratixiv_mac_10g_crosser/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rsp_xbar_mux_002/
+vmap ip_stratixiv_mac_10g_rsp_xbar_mux_002 ./libraries/ip_stratixiv_mac_10g_rsp_xbar_mux_002/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rsp_xbar_demux_010/
+vmap ip_stratixiv_mac_10g_rsp_xbar_demux_010 ./libraries/ip_stratixiv_mac_10g_rsp_xbar_demux_010/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_cmd_xbar_demux_002/
+vmap ip_stratixiv_mac_10g_cmd_xbar_demux_002 ./libraries/ip_stratixiv_mac_10g_cmd_xbar_demux_002/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rsp_xbar_mux_001/
+vmap ip_stratixiv_mac_10g_rsp_xbar_mux_001 ./libraries/ip_stratixiv_mac_10g_rsp_xbar_mux_001/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rsp_xbar_demux_002/
+vmap ip_stratixiv_mac_10g_rsp_xbar_demux_002 ./libraries/ip_stratixiv_mac_10g_rsp_xbar_demux_002/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_cmd_xbar_demux_001/
+vmap ip_stratixiv_mac_10g_cmd_xbar_demux_001 ./libraries/ip_stratixiv_mac_10g_cmd_xbar_demux_001/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rsp_xbar_mux/
+vmap ip_stratixiv_mac_10g_rsp_xbar_mux ./libraries/ip_stratixiv_mac_10g_rsp_xbar_mux/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rsp_xbar_demux/
+vmap ip_stratixiv_mac_10g_rsp_xbar_demux ./libraries/ip_stratixiv_mac_10g_rsp_xbar_demux/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_cmd_xbar_demux/
+vmap ip_stratixiv_mac_10g_cmd_xbar_demux ./libraries/ip_stratixiv_mac_10g_cmd_xbar_demux/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rst_controller/
+vmap ip_stratixiv_mac_10g_rst_controller ./libraries/ip_stratixiv_mac_10g_rst_controller/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_limiter_002/
+vmap ip_stratixiv_mac_10g_limiter_002 ./libraries/ip_stratixiv_mac_10g_limiter_002/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_limiter_001/
+vmap ip_stratixiv_mac_10g_limiter_001 ./libraries/ip_stratixiv_mac_10g_limiter_001/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_limiter/
+vmap ip_stratixiv_mac_10g_limiter ./libraries/ip_stratixiv_mac_10g_limiter/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_id_router_010/
+vmap ip_stratixiv_mac_10g_id_router_010 ./libraries/ip_stratixiv_mac_10g_id_router_010/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_addr_router_002/
+vmap ip_stratixiv_mac_10g_addr_router_002 ./libraries/ip_stratixiv_mac_10g_addr_router_002/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_id_router_002/
+vmap ip_stratixiv_mac_10g_id_router_002 ./libraries/ip_stratixiv_mac_10g_id_router_002/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_addr_router_001/
+vmap ip_stratixiv_mac_10g_addr_router_001 ./libraries/ip_stratixiv_mac_10g_addr_router_001/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_id_router/
+vmap ip_stratixiv_mac_10g_id_router ./libraries/ip_stratixiv_mac_10g_id_router/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_addr_router/
+vmap ip_stratixiv_mac_10g_addr_router ./libraries/ip_stratixiv_mac_10g_addr_router/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/
+vmap ip_stratixiv_mac_10g_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent ./libraries/ip_stratixiv_mac_10g_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rx_bridge_m0_translator_avalon_universal_master_0_agent/
+vmap ip_stratixiv_mac_10g_rx_bridge_m0_translator_avalon_universal_master_0_agent ./libraries/ip_stratixiv_mac_10g_rx_bridge_m0_translator_avalon_universal_master_0_agent/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/
+vmap ip_stratixiv_mac_10g_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent ./libraries/ip_stratixiv_mac_10g_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/
+vmap ip_stratixiv_mac_10g_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent ./libraries/ip_stratixiv_mac_10g_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/
+vmap ip_stratixiv_mac_10g_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent ./libraries/ip_stratixiv_mac_10g_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/
+vmap ip_stratixiv_mac_10g_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent ./libraries/ip_stratixiv_mac_10g_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/
+vmap ip_stratixiv_mac_10g_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent ./libraries/ip_stratixiv_mac_10g_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/
+vmap ip_stratixiv_mac_10g_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent ./libraries/ip_stratixiv_mac_10g_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/
+vmap ip_stratixiv_mac_10g_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent ./libraries/ip_stratixiv_mac_10g_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/
+vmap ip_stratixiv_mac_10g_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent ./libraries/ip_stratixiv_mac_10g_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/
+vmap ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent ./libraries/ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/
+vmap ip_stratixiv_mac_10g_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent ./libraries/ip_stratixiv_mac_10g_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/
+vmap ip_stratixiv_mac_10g_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent ./libraries/ip_stratixiv_mac_10g_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/
+vmap ip_stratixiv_mac_10g_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent ./libraries/ip_stratixiv_mac_10g_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_bridge_m0_translator_avalon_universal_master_0_agent/
+vmap ip_stratixiv_mac_10g_tx_bridge_m0_translator_avalon_universal_master_0_agent ./libraries/ip_stratixiv_mac_10g_tx_bridge_m0_translator_avalon_universal_master_0_agent/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo/
+vmap ip_stratixiv_mac_10g_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo ./libraries/ip_stratixiv_mac_10g_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/
+vmap ip_stratixiv_mac_10g_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent ./libraries/ip_stratixiv_mac_10g_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo/
+vmap ip_stratixiv_mac_10g_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo ./libraries/ip_stratixiv_mac_10g_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/
+vmap ip_stratixiv_mac_10g_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent ./libraries/ip_stratixiv_mac_10g_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rx_bridge_s0_translator_avalon_universal_slave_0_agent/
+vmap ip_stratixiv_mac_10g_rx_bridge_s0_translator_avalon_universal_slave_0_agent ./libraries/ip_stratixiv_mac_10g_rx_bridge_s0_translator_avalon_universal_slave_0_agent/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent/
+vmap ip_stratixiv_mac_10g_merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent ./libraries/ip_stratixiv_mac_10g_merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo/
+vmap ip_stratixiv_mac_10g_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo ./libraries/ip_stratixiv_mac_10g_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo/
+vmap ip_stratixiv_mac_10g_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo ./libraries/ip_stratixiv_mac_10g_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_bridge_s0_translator_avalon_universal_slave_0_agent/
+vmap ip_stratixiv_mac_10g_tx_bridge_s0_translator_avalon_universal_slave_0_agent ./libraries/ip_stratixiv_mac_10g_tx_bridge_s0_translator_avalon_universal_slave_0_agent/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rx_eth_packet_overflow_control_csr_translator/
+vmap ip_stratixiv_mac_10g_rx_eth_packet_overflow_control_csr_translator ./libraries/ip_stratixiv_mac_10g_rx_eth_packet_overflow_control_csr_translator/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_eth_statistics_collector_csr_translator/
+vmap ip_stratixiv_mac_10g_tx_eth_statistics_collector_csr_translator ./libraries/ip_stratixiv_mac_10g_tx_eth_statistics_collector_csr_translator/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_eth_frame_decoder_avalom_mm_csr_translator/
+vmap ip_stratixiv_mac_10g_tx_eth_frame_decoder_avalom_mm_csr_translator ./libraries/ip_stratixiv_mac_10g_tx_eth_frame_decoder_avalom_mm_csr_translator/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_eth_packet_underflow_control_avalon_slave_0_translator/
+vmap ip_stratixiv_mac_10g_tx_eth_packet_underflow_control_avalon_slave_0_translator ./libraries/ip_stratixiv_mac_10g_tx_eth_packet_underflow_control_avalon_slave_0_translator/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_eth_pause_ctrl_gen_csr_translator/
+vmap ip_stratixiv_mac_10g_tx_eth_pause_ctrl_gen_csr_translator ./libraries/ip_stratixiv_mac_10g_tx_eth_pause_ctrl_gen_csr_translator/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control_csr_translator/
+vmap ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control_csr_translator ./libraries/ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control_csr_translator/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_bridge_m0_translator/
+vmap ip_stratixiv_mac_10g_tx_bridge_m0_translator ./libraries/ip_stratixiv_mac_10g_tx_bridge_m0_translator/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_bridge_s0_translator/
+vmap ip_stratixiv_mac_10g_tx_bridge_s0_translator ./libraries/ip_stratixiv_mac_10g_tx_bridge_s0_translator/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_merlin_master_translator_avalon_universal_master_0_translator/
+vmap ip_stratixiv_mac_10g_merlin_master_translator_avalon_universal_master_0_translator ./libraries/ip_stratixiv_mac_10g_merlin_master_translator_avalon_universal_master_0_translator/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_tx/
+vmap ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_tx ./libraries/ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_tx/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rxtx_dc_fifo_pauselen/
+vmap ip_stratixiv_mac_10g_rxtx_dc_fifo_pauselen ./libraries/ip_stratixiv_mac_10g_rxtx_dc_fifo_pauselen/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_rx/
+vmap ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_rx ./libraries/ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_rx/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rxtx_dc_fifo_link_fault_status/
+vmap ip_stratixiv_mac_10g_rxtx_dc_fifo_link_fault_status ./libraries/ip_stratixiv_mac_10g_rxtx_dc_fifo_link_fault_status/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_export/
+vmap ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_export ./libraries/ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_export/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_txrx_st_splitter_link_fault_status/
+vmap ip_stratixiv_mac_10g_txrx_st_splitter_link_fault_status ./libraries/ip_stratixiv_mac_10g_txrx_st_splitter_link_fault_status/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_rx/
+vmap ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_rx ./libraries/ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_rx/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rx_st_status_statistics_delay/
+vmap ip_stratixiv_mac_10g_rx_st_status_statistics_delay ./libraries/ip_stratixiv_mac_10g_rx_st_status_statistics_delay/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rx_st_error_adapter_stat/
+vmap ip_stratixiv_mac_10g_rx_st_error_adapter_stat ./libraries/ip_stratixiv_mac_10g_rx_st_error_adapter_stat/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rx_st_status_output_delay/
+vmap ip_stratixiv_mac_10g_rx_st_status_output_delay ./libraries/ip_stratixiv_mac_10g_rx_st_status_output_delay/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rx_eth_packet_overflow_control/
+vmap ip_stratixiv_mac_10g_rx_eth_packet_overflow_control ./libraries/ip_stratixiv_mac_10g_rx_eth_packet_overflow_control/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rx_eth_crc_pad_rem/
+vmap ip_stratixiv_mac_10g_rx_eth_crc_pad_rem ./libraries/ip_stratixiv_mac_10g_rx_eth_crc_pad_rem/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rx_eth_frame_status_merger/
+vmap ip_stratixiv_mac_10g_rx_eth_frame_status_merger ./libraries/ip_stratixiv_mac_10g_rx_eth_frame_status_merger/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rx_timing_adapter_frame_status_out_frame_decoder/
+vmap ip_stratixiv_mac_10g_rx_timing_adapter_frame_status_out_frame_decoder ./libraries/ip_stratixiv_mac_10g_rx_timing_adapter_frame_status_out_frame_decoder/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rx_st_frame_status_splitter/
+vmap ip_stratixiv_mac_10g_rx_st_frame_status_splitter ./libraries/ip_stratixiv_mac_10g_rx_st_frame_status_splitter/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rx_st_timing_adapter_frame_status_in/
+vmap ip_stratixiv_mac_10g_rx_st_timing_adapter_frame_status_in ./libraries/ip_stratixiv_mac_10g_rx_st_timing_adapter_frame_status_in/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rx_eth_lane_decoder/
+vmap ip_stratixiv_mac_10g_rx_eth_lane_decoder ./libraries/ip_stratixiv_mac_10g_rx_eth_lane_decoder/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rx_eth_link_fault_detection/
+vmap ip_stratixiv_mac_10g_rx_eth_link_fault_detection ./libraries/ip_stratixiv_mac_10g_rx_eth_link_fault_detection/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rx_st_timing_adapter_lane_decoder/
+vmap ip_stratixiv_mac_10g_rx_st_timing_adapter_lane_decoder ./libraries/ip_stratixiv_mac_10g_rx_st_timing_adapter_lane_decoder/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rx_st_splitter_xgmii/
+vmap ip_stratixiv_mac_10g_rx_st_splitter_xgmii ./libraries/ip_stratixiv_mac_10g_rx_st_splitter_xgmii/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_rx_st_timing_adapter_interface_conversion/
+vmap ip_stratixiv_mac_10g_rx_st_timing_adapter_interface_conversion ./libraries/ip_stratixiv_mac_10g_rx_st_timing_adapter_interface_conversion/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_eth_link_fault_generation/
+vmap ip_stratixiv_mac_10g_tx_eth_link_fault_generation ./libraries/ip_stratixiv_mac_10g_tx_eth_link_fault_generation/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_eth_xgmii_termination/
+vmap ip_stratixiv_mac_10g_tx_eth_xgmii_termination ./libraries/ip_stratixiv_mac_10g_tx_eth_xgmii_termination/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_eth_packet_formatter/
+vmap ip_stratixiv_mac_10g_tx_eth_packet_formatter ./libraries/ip_stratixiv_mac_10g_tx_eth_packet_formatter/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_eth_statistics_collector/
+vmap ip_stratixiv_mac_10g_tx_eth_statistics_collector ./libraries/ip_stratixiv_mac_10g_tx_eth_statistics_collector/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_st_status_splitter/
+vmap ip_stratixiv_mac_10g_tx_st_status_splitter ./libraries/ip_stratixiv_mac_10g_tx_st_status_splitter/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_output/
+vmap ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_output ./libraries/ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_output/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_in/
+vmap ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_in ./libraries/ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_in/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_st_error_adapter_stat/
+vmap ip_stratixiv_mac_10g_tx_st_error_adapter_stat ./libraries/ip_stratixiv_mac_10g_tx_st_error_adapter_stat/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_eth_frame_decoder/
+vmap ip_stratixiv_mac_10g_tx_eth_frame_decoder ./libraries/ip_stratixiv_mac_10g_tx_eth_frame_decoder/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_st_timing_adapter_frame_decoder/
+vmap ip_stratixiv_mac_10g_tx_st_timing_adapter_frame_decoder ./libraries/ip_stratixiv_mac_10g_tx_st_timing_adapter_frame_decoder/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_st_splitter_1/
+vmap ip_stratixiv_mac_10g_tx_st_splitter_1 ./libraries/ip_stratixiv_mac_10g_tx_st_splitter_1/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_st_pipeline_stage_rs/
+vmap ip_stratixiv_mac_10g_tx_st_pipeline_stage_rs ./libraries/ip_stratixiv_mac_10g_tx_st_pipeline_stage_rs/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_eth_crc_inserter/
+vmap ip_stratixiv_mac_10g_tx_eth_crc_inserter ./libraries/ip_stratixiv_mac_10g_tx_eth_crc_inserter/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_eth_address_inserter/
+vmap ip_stratixiv_mac_10g_tx_eth_address_inserter ./libraries/ip_stratixiv_mac_10g_tx_eth_address_inserter/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_st_mux_flow_control_user_frame/
+vmap ip_stratixiv_mac_10g_tx_st_mux_flow_control_user_frame ./libraries/ip_stratixiv_mac_10g_tx_st_mux_flow_control_user_frame/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_st_pause_ctrl_error_adapter/
+vmap ip_stratixiv_mac_10g_tx_st_pause_ctrl_error_adapter ./libraries/ip_stratixiv_mac_10g_tx_st_pause_ctrl_error_adapter/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_eth_pause_ctrl_gen/
+vmap ip_stratixiv_mac_10g_tx_eth_pause_ctrl_gen ./libraries/ip_stratixiv_mac_10g_tx_eth_pause_ctrl_gen/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_eth_pause_beat_conversion/
+vmap ip_stratixiv_mac_10g_tx_eth_pause_beat_conversion ./libraries/ip_stratixiv_mac_10g_tx_eth_pause_beat_conversion/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control/
+vmap ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control ./libraries/ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_eth_pad_inserter/
+vmap ip_stratixiv_mac_10g_tx_eth_pad_inserter ./libraries/ip_stratixiv_mac_10g_tx_eth_pad_inserter/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_eth_packet_underflow_control/
+vmap ip_stratixiv_mac_10g_tx_eth_packet_underflow_control ./libraries/ip_stratixiv_mac_10g_tx_eth_packet_underflow_control/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_tx_bridge/
+vmap ip_stratixiv_mac_10g_tx_bridge ./libraries/ip_stratixiv_mac_10g_tx_bridge/
+ensure_lib ./libraries/ip_stratixiv_mac_10g_merlin_master_translator/
+vmap ip_stratixiv_mac_10g_merlin_master_translator ./libraries/ip_stratixiv_mac_10g_merlin_master_translator/
+
+# ----------------------------------------
+# Compile device library files
+alias dev_com {
+ echo "\[exec\] dev_com"
+ if { ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] } {
+ vlog "/home/software/Altera/11.1/quartus/eda/sim_lib/altera_primitives.v" -work altera_ver
+ vlog "/home/software/Altera/11.1/quartus/eda/sim_lib/220model.v" -work lpm_ver
+ vlog "/home/software/Altera/11.1/quartus/eda/sim_lib/sgate.v" -work sgate_ver
+ vlog "/home/software/Altera/11.1/quartus/eda/sim_lib/altera_mf.v" -work altera_mf_ver
+ vlog -sv "/home/software/Altera/11.1/quartus/eda/sim_lib/mentor/altera_lnsim_for_vhdl.sv" -work altera_lnsim_ver
+ vlog "/home/software/Altera/11.1/quartus/eda/sim_lib/stratixiv_hssi_atoms.v" -work stratixiv_hssi_ver
+ vlog "/home/software/Altera/11.1/quartus/eda/sim_lib/stratixiv_pcie_hip_atoms.v" -work stratixiv_pcie_hip_ver
+ vlog "/home/software/Altera/11.1/quartus/eda/sim_lib/stratixiv_atoms.v" -work stratixiv_ver
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/altera_syn_attributes.vhd" -work altera
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/altera_standard_functions.vhd" -work altera
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/altera_europa_support_lib.vhd" -work altera
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/altera_primitives_components.vhd" -work altera
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/altera_primitives.vhd" -work altera
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/220pack.vhd" -work lpm
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/220model.vhd" -work lpm
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/sgate_pack.vhd" -work sgate
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/sgate.vhd" -work sgate
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/altera_mf_components.vhd" -work altera_mf
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/altera_mf.vhd" -work altera_mf
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/stratixiv_hssi_components.vhd" -work stratixiv_hssi
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/stratixiv_hssi_atoms.vhd" -work stratixiv_hssi
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/stratixiv_pcie_hip_components.vhd" -work stratixiv_pcie_hip
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/stratixiv_pcie_hip_atoms.vhd" -work stratixiv_pcie_hip
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/stratixiv_atoms.vhd" -work stratixiv
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/stratixiv_components.vhd" -work stratixiv
+ }
+}
+
+# ----------------------------------------
+# Compile the design files in correct order
+alias com {
+ echo "\[exec\] com"
+ vcom "$QSYS_SIMDIR/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser_0001.vho" -work ip_stratixiv_mac_10g_crosser
+ vcom "$QSYS_SIMDIR/altera_merlin_multiplexer/altera_merlin_multiplexer_0003.vho" -work ip_stratixiv_mac_10g_rsp_xbar_mux_002
+ vcom "$QSYS_SIMDIR/altera_merlin_demultiplexer/altera_merlin_demultiplexer_0006.vho" -work ip_stratixiv_mac_10g_rsp_xbar_demux_010
+ vcom "$QSYS_SIMDIR/altera_merlin_demultiplexer/altera_merlin_demultiplexer_0005.vho" -work ip_stratixiv_mac_10g_cmd_xbar_demux_002
+ vcom "$QSYS_SIMDIR/altera_merlin_multiplexer/altera_merlin_multiplexer_0002.vho" -work ip_stratixiv_mac_10g_rsp_xbar_mux_001
+ vcom "$QSYS_SIMDIR/altera_merlin_demultiplexer/altera_merlin_demultiplexer_0004.vho" -work ip_stratixiv_mac_10g_rsp_xbar_demux_002
+ vcom "$QSYS_SIMDIR/altera_merlin_demultiplexer/altera_merlin_demultiplexer_0003.vho" -work ip_stratixiv_mac_10g_cmd_xbar_demux_001
+ vcom "$QSYS_SIMDIR/altera_merlin_multiplexer/altera_merlin_multiplexer_0001.vho" -work ip_stratixiv_mac_10g_rsp_xbar_mux
+ vcom "$QSYS_SIMDIR/altera_merlin_demultiplexer/altera_merlin_demultiplexer_0002.vho" -work ip_stratixiv_mac_10g_rsp_xbar_demux
+ vcom "$QSYS_SIMDIR/altera_merlin_demultiplexer/altera_merlin_demultiplexer_0001.vho" -work ip_stratixiv_mac_10g_cmd_xbar_demux
+ vcom "$QSYS_SIMDIR/altera_reset_controller/altera_reset_controller_0001.vho" -work ip_stratixiv_mac_10g_rst_controller
+ vcom "$QSYS_SIMDIR/altera_merlin_traffic_limiter/altera_merlin_traffic_limiter_0003.vho" -work ip_stratixiv_mac_10g_limiter_002
+ vcom "$QSYS_SIMDIR/altera_merlin_traffic_limiter/altera_merlin_traffic_limiter_0002.vho" -work ip_stratixiv_mac_10g_limiter_001
+ vcom "$QSYS_SIMDIR/altera_merlin_traffic_limiter/altera_merlin_traffic_limiter_0001.vho" -work ip_stratixiv_mac_10g_limiter
+ vcom "$QSYS_SIMDIR/altera_merlin_router/altera_merlin_router_0006.vho" -work ip_stratixiv_mac_10g_id_router_010
+ vcom "$QSYS_SIMDIR/altera_merlin_router/altera_merlin_router_0005.vho" -work ip_stratixiv_mac_10g_addr_router_002
+ vcom "$QSYS_SIMDIR/altera_merlin_router/altera_merlin_router_0004.vho" -work ip_stratixiv_mac_10g_id_router_002
+ vcom "$QSYS_SIMDIR/altera_merlin_router/altera_merlin_router_0003.vho" -work ip_stratixiv_mac_10g_addr_router_001
+ vcom "$QSYS_SIMDIR/altera_merlin_router/altera_merlin_router_0002.vho" -work ip_stratixiv_mac_10g_id_router
+ vcom "$QSYS_SIMDIR/altera_merlin_router/altera_merlin_router_0001.vho" -work ip_stratixiv_mac_10g_addr_router
+ vcom "$QSYS_SIMDIR/altera_merlin_slave_agent/altera_merlin_slave_agent_0017.vho" -work ip_stratixiv_mac_10g_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent
+ vcom "$QSYS_SIMDIR/altera_merlin_master_agent/altera_merlin_master_agent_0003.vho" -work ip_stratixiv_mac_10g_rx_bridge_m0_translator_avalon_universal_master_0_agent
+ vcom "$QSYS_SIMDIR/altera_merlin_slave_agent/altera_merlin_slave_agent_0016.vho" -work ip_stratixiv_mac_10g_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent
+ vcom "$QSYS_SIMDIR/altera_merlin_slave_agent/altera_merlin_slave_agent_0015.vho" -work ip_stratixiv_mac_10g_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent
+ vcom "$QSYS_SIMDIR/altera_merlin_slave_agent/altera_merlin_slave_agent_0014.vho" -work ip_stratixiv_mac_10g_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent
+ vcom "$QSYS_SIMDIR/altera_merlin_slave_agent/altera_merlin_slave_agent_0013.vho" -work ip_stratixiv_mac_10g_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent
+ vcom "$QSYS_SIMDIR/altera_merlin_slave_agent/altera_merlin_slave_agent_0012.vho" -work ip_stratixiv_mac_10g_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent
+ vcom "$QSYS_SIMDIR/altera_merlin_slave_agent/altera_merlin_slave_agent_0011.vho" -work ip_stratixiv_mac_10g_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent
+ vcom "$QSYS_SIMDIR/altera_merlin_slave_agent/altera_merlin_slave_agent_0010.vho" -work ip_stratixiv_mac_10g_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent
+ vcom "$QSYS_SIMDIR/altera_merlin_slave_agent/altera_merlin_slave_agent_0009.vho" -work ip_stratixiv_mac_10g_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent
+ vcom "$QSYS_SIMDIR/altera_merlin_slave_agent/altera_merlin_slave_agent_0008.vho" -work ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent
+ vcom "$QSYS_SIMDIR/altera_merlin_slave_agent/altera_merlin_slave_agent_0007.vho" -work ip_stratixiv_mac_10g_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent
+ vcom "$QSYS_SIMDIR/altera_merlin_slave_agent/altera_merlin_slave_agent_0006.vho" -work ip_stratixiv_mac_10g_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent
+ vcom "$QSYS_SIMDIR/altera_merlin_slave_agent/altera_merlin_slave_agent_0005.vho" -work ip_stratixiv_mac_10g_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent
+ vcom "$QSYS_SIMDIR/altera_merlin_master_agent/altera_merlin_master_agent_0002.vho" -work ip_stratixiv_mac_10g_tx_bridge_m0_translator_avalon_universal_master_0_agent
+ vcom "$QSYS_SIMDIR/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0004.vho" -work ip_stratixiv_mac_10g_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo
+ vcom "$QSYS_SIMDIR/altera_merlin_slave_agent/altera_merlin_slave_agent_0004.vho" -work ip_stratixiv_mac_10g_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent
+ vcom "$QSYS_SIMDIR/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0003.vho" -work ip_stratixiv_mac_10g_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo
+ vcom "$QSYS_SIMDIR/altera_merlin_slave_agent/altera_merlin_slave_agent_0003.vho" -work ip_stratixiv_mac_10g_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent
+ vcom "$QSYS_SIMDIR/altera_merlin_slave_agent/altera_merlin_slave_agent_0002.vho" -work ip_stratixiv_mac_10g_rx_bridge_s0_translator_avalon_universal_slave_0_agent
+ vcom "$QSYS_SIMDIR/altera_merlin_master_agent/altera_merlin_master_agent_0001.vho" -work ip_stratixiv_mac_10g_merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent
+ vcom "$QSYS_SIMDIR/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0002.vho" -work ip_stratixiv_mac_10g_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo
+ vcom "$QSYS_SIMDIR/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0001.vho" -work ip_stratixiv_mac_10g_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo
+ vcom "$QSYS_SIMDIR/altera_merlin_slave_agent/altera_merlin_slave_agent_0001.vho" -work ip_stratixiv_mac_10g_tx_bridge_s0_translator_avalon_universal_slave_0_agent
+ vcom "$QSYS_SIMDIR/altera_merlin_slave_translator/altera_merlin_slave_translator_0007.vho" -work ip_stratixiv_mac_10g_rx_eth_packet_overflow_control_csr_translator
+ vcom "$QSYS_SIMDIR/altera_merlin_slave_translator/altera_merlin_slave_translator_0006.vho" -work ip_stratixiv_mac_10g_tx_eth_statistics_collector_csr_translator
+ vcom "$QSYS_SIMDIR/altera_merlin_slave_translator/altera_merlin_slave_translator_0005.vho" -work ip_stratixiv_mac_10g_tx_eth_frame_decoder_avalom_mm_csr_translator
+ vcom "$QSYS_SIMDIR/altera_merlin_slave_translator/altera_merlin_slave_translator_0004.vho" -work ip_stratixiv_mac_10g_tx_eth_packet_underflow_control_avalon_slave_0_translator
+ vcom "$QSYS_SIMDIR/altera_merlin_slave_translator/altera_merlin_slave_translator_0003.vho" -work ip_stratixiv_mac_10g_tx_eth_pause_ctrl_gen_csr_translator
+ vcom "$QSYS_SIMDIR/altera_merlin_slave_translator/altera_merlin_slave_translator_0002.vho" -work ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control_csr_translator
+ vcom "$QSYS_SIMDIR/altera_merlin_master_translator/altera_merlin_master_translator_0003.vho" -work ip_stratixiv_mac_10g_tx_bridge_m0_translator
+ vcom "$QSYS_SIMDIR/altera_merlin_slave_translator/altera_merlin_slave_translator_0001.vho" -work ip_stratixiv_mac_10g_tx_bridge_s0_translator
+ vcom "$QSYS_SIMDIR/altera_merlin_master_translator/altera_merlin_master_translator_0002.vho" -work ip_stratixiv_mac_10g_merlin_master_translator_avalon_universal_master_0_translator
+ vcom "$QSYS_SIMDIR/timing_adapter/timing_adapter_0011.vho" -work ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_tx
+ vcom "$QSYS_SIMDIR/altera_avalon_dc_fifo/altera_avalon_dc_fifo_0002.vho" -work ip_stratixiv_mac_10g_rxtx_dc_fifo_pauselen
+ vcom "$QSYS_SIMDIR/timing_adapter/timing_adapter_0010.vho" -work ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_rx
+ vcom "$QSYS_SIMDIR/altera_avalon_dc_fifo/altera_avalon_dc_fifo_0001.vho" -work ip_stratixiv_mac_10g_rxtx_dc_fifo_link_fault_status
+ vcom "$QSYS_SIMDIR/timing_adapter/timing_adapter_0009.vho" -work ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_export
+ vcom "$QSYS_SIMDIR/altera_avalon_st_splitter/altera_avalon_st_splitter_0005.vho" -work ip_stratixiv_mac_10g_txrx_st_splitter_link_fault_status
+ vcom "$QSYS_SIMDIR/timing_adapter/timing_adapter_0008.vho" -work ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_rx
+ vcom "$QSYS_SIMDIR/altera_avalon_st_delay/altera_avalon_st_delay_0002.vho" -work ip_stratixiv_mac_10g_rx_st_status_statistics_delay
+ vcom "$QSYS_SIMDIR/error_adapter/error_adapter_0003.vho" -work ip_stratixiv_mac_10g_rx_st_error_adapter_stat
+ vcom "$QSYS_SIMDIR/altera_avalon_st_delay/altera_avalon_st_delay_0001.vho" -work ip_stratixiv_mac_10g_rx_st_status_output_delay
+ vlog "$QSYS_SIMDIR/altera_eth_packet_overflow_control/mentor/altera_eth_packet_overflow_control.v" -work ip_stratixiv_mac_10g_rx_eth_packet_overflow_control
+ vlog "$QSYS_SIMDIR/altera_eth_crc_pad_rem/mentor/altera_eth_crc_pad_rem.v" -work ip_stratixiv_mac_10g_rx_eth_crc_pad_rem
+ vlog "$QSYS_SIMDIR/altera_eth_crc_pad_rem/mentor/altera_eth_crc_rem.v" -work ip_stratixiv_mac_10g_rx_eth_crc_pad_rem
+ vlog "$QSYS_SIMDIR/altera_eth_crc_pad_rem/mentor/altera_packet_stripper.v" -work ip_stratixiv_mac_10g_rx_eth_crc_pad_rem
+ vlog -sv "$QSYS_SIMDIR/altera_eth_crc_pad_rem/altera_avalon_st_pipeline_stage.sv" -work ip_stratixiv_mac_10g_rx_eth_crc_pad_rem
+ vlog "$QSYS_SIMDIR/altera_eth_crc_pad_rem/altera_avalon_st_pipeline_base.v" -work ip_stratixiv_mac_10g_rx_eth_crc_pad_rem
+ vlog "$QSYS_SIMDIR/altera_eth_frame_status_merger/mentor/altera_eth_frame_status_merger.v" -work ip_stratixiv_mac_10g_rx_eth_frame_status_merger
+ vcom "$QSYS_SIMDIR/timing_adapter/timing_adapter_0007.vho" -work ip_stratixiv_mac_10g_rx_timing_adapter_frame_status_out_frame_decoder
+ vcom "$QSYS_SIMDIR/altera_avalon_st_splitter/altera_avalon_st_splitter_0004.vho" -work ip_stratixiv_mac_10g_rx_st_frame_status_splitter
+ vcom "$QSYS_SIMDIR/timing_adapter/timing_adapter_0006.vho" -work ip_stratixiv_mac_10g_rx_st_timing_adapter_frame_status_in
+ vlog "$QSYS_SIMDIR/altera_eth_lane_decoder/mentor/altera_eth_lane_decoder.v" -work ip_stratixiv_mac_10g_rx_eth_lane_decoder
+ vlog "$QSYS_SIMDIR/altera_eth_link_fault_detection/mentor/altera_eth_link_fault_detection.v" -work ip_stratixiv_mac_10g_rx_eth_link_fault_detection
+ vcom "$QSYS_SIMDIR/timing_adapter/timing_adapter_0005.vho" -work ip_stratixiv_mac_10g_rx_st_timing_adapter_lane_decoder
+ vcom "$QSYS_SIMDIR/altera_avalon_st_splitter/altera_avalon_st_splitter_0003.vho" -work ip_stratixiv_mac_10g_rx_st_splitter_xgmii
+ vcom "$QSYS_SIMDIR/timing_adapter/timing_adapter_0004.vho" -work ip_stratixiv_mac_10g_rx_st_timing_adapter_interface_conversion
+ vlog "$QSYS_SIMDIR/altera_eth_link_fault_generation/mentor/altera_eth_link_fault_generation.v" -work ip_stratixiv_mac_10g_tx_eth_link_fault_generation
+ vlog "$QSYS_SIMDIR/altera_eth_xgmii_termination/mentor/altera_eth_xgmii_termination.v" -work ip_stratixiv_mac_10g_tx_eth_xgmii_termination
+ vlog "$QSYS_SIMDIR/altera_eth_packet_formatter/mentor/altera_eth_packet_formatter.v" -work ip_stratixiv_mac_10g_tx_eth_packet_formatter
+ vlog "$QSYS_SIMDIR/altera_eth_10gmem_statistics_collector/mentor/altera_eth_10gmem_statistics_collector.v" -work ip_stratixiv_mac_10g_tx_eth_statistics_collector
+ vcom "$QSYS_SIMDIR/altera_avalon_st_splitter/altera_avalon_st_splitter_0002.vho" -work ip_stratixiv_mac_10g_tx_st_status_splitter
+ vcom "$QSYS_SIMDIR/timing_adapter/timing_adapter_0003.vho" -work ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_output
+ vcom "$QSYS_SIMDIR/timing_adapter/timing_adapter_0002.vho" -work ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_in
+ vcom "$QSYS_SIMDIR/error_adapter/error_adapter_0002.vho" -work ip_stratixiv_mac_10g_tx_st_error_adapter_stat
+ vlog "$QSYS_SIMDIR/altera_eth_frame_decoder/mentor/altera_eth_frame_decoder.v" -work ip_stratixiv_mac_10g_tx_eth_frame_decoder
+ vlog -sv "$QSYS_SIMDIR/altera_eth_frame_decoder/altera_avalon_st_pipeline_stage.sv" -work ip_stratixiv_mac_10g_tx_eth_frame_decoder
+ vlog "$QSYS_SIMDIR/altera_eth_frame_decoder/altera_avalon_st_pipeline_base.v" -work ip_stratixiv_mac_10g_tx_eth_frame_decoder
+ vcom "$QSYS_SIMDIR/timing_adapter/timing_adapter_0001.vho" -work ip_stratixiv_mac_10g_tx_st_timing_adapter_frame_decoder
+ vcom "$QSYS_SIMDIR/altera_avalon_st_splitter/altera_avalon_st_splitter_0001.vho" -work ip_stratixiv_mac_10g_tx_st_splitter_1
+ vcom "$QSYS_SIMDIR/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_stage_0001.vho" -work ip_stratixiv_mac_10g_tx_st_pipeline_stage_rs
+ vlog "$QSYS_SIMDIR/altera_eth_crc/mentor/altera_eth_crc.v" -work ip_stratixiv_mac_10g_tx_eth_crc_inserter
+ vlog "$QSYS_SIMDIR/altera_eth_crc/mentor/crc32.v" -work ip_stratixiv_mac_10g_tx_eth_crc_inserter
+ vlog "$QSYS_SIMDIR/altera_eth_crc/mentor/gf_mult32_kc.v" -work ip_stratixiv_mac_10g_tx_eth_crc_inserter
+ vlog "$QSYS_SIMDIR/altera_eth_address_inserter/mentor/altera_eth_address_inserter.v" -work ip_stratixiv_mac_10g_tx_eth_address_inserter
+ vcom "$QSYS_SIMDIR/multiplexer/multiplexer_0001.vho" -work ip_stratixiv_mac_10g_tx_st_mux_flow_control_user_frame
+ vcom "$QSYS_SIMDIR/error_adapter/error_adapter_0001.vho" -work ip_stratixiv_mac_10g_tx_st_pause_ctrl_error_adapter
+ vlog "$QSYS_SIMDIR/altera_eth_pause_ctrl_gen/mentor/altera_eth_pause_ctrl_gen.v" -work ip_stratixiv_mac_10g_tx_eth_pause_ctrl_gen
+ vlog "$QSYS_SIMDIR/altera_eth_pause_ctrl_gen/mentor/altera_eth_pause_controller.v" -work ip_stratixiv_mac_10g_tx_eth_pause_ctrl_gen
+ vlog "$QSYS_SIMDIR/altera_eth_pause_ctrl_gen/mentor/altera_eth_pause_gen.v" -work ip_stratixiv_mac_10g_tx_eth_pause_ctrl_gen
+ vlog "$QSYS_SIMDIR/altera_eth_pause_beat_conversion/mentor/altera_eth_pause_beat_conversion.v" -work ip_stratixiv_mac_10g_tx_eth_pause_beat_conversion
+ vlog "$QSYS_SIMDIR/altera_eth_pkt_backpressure_control/mentor/altera_eth_pkt_backpressure_control.v" -work ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control
+ vlog "$QSYS_SIMDIR/altera_eth_pad_inserter/mentor/altera_eth_pad_inserter.v" -work ip_stratixiv_mac_10g_tx_eth_pad_inserter
+ vlog "$QSYS_SIMDIR/altera_eth_packet_underflow_control/mentor/altera_eth_packet_underflow_control.v" -work ip_stratixiv_mac_10g_tx_eth_packet_underflow_control
+ vcom "$QSYS_SIMDIR/altera_avalon_mm_bridge/altera_avalon_mm_bridge_0001.vho" -work ip_stratixiv_mac_10g_tx_bridge
+ vcom "$QSYS_SIMDIR/altera_merlin_master_translator/altera_merlin_master_translator_0001.vho" -work ip_stratixiv_mac_10g_merlin_master_translator
+ vcom "$QSYS_SIMDIR/ip_stratixiv_mac_10g.vhd"
+ vcom "$QSYS_SIMDIR/ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control.vhd"
+ vcom "$QSYS_SIMDIR/ip_stratixiv_mac_10g_rx_eth_pkt_backpressure_control.vhd"
+ vcom "$QSYS_SIMDIR/ip_stratixiv_mac_10g_tx_eth_frame_decoder.vhd"
+ vcom "$QSYS_SIMDIR/ip_stratixiv_mac_10g_rx_eth_frame_decoder.vhd"
+ vcom "$QSYS_SIMDIR/ip_stratixiv_mac_10g_tx_eth_crc_inserter.vhd"
+ vcom "$QSYS_SIMDIR/ip_stratixiv_mac_10g_rx_eth_crc_checker.vhd"
+}
+
+# ----------------------------------------
+# Elaborate top level design
+alias elab {
+ echo "\[exec\] elab"
+ vsim -t ps -L work -L ip_stratixiv_mac_10g_crosser -L ip_stratixiv_mac_10g_rsp_xbar_mux_002 -L ip_stratixiv_mac_10g_rsp_xbar_demux_010 -L ip_stratixiv_mac_10g_cmd_xbar_demux_002 -L ip_stratixiv_mac_10g_rsp_xbar_mux_001 -L ip_stratixiv_mac_10g_rsp_xbar_demux_002 -L ip_stratixiv_mac_10g_cmd_xbar_demux_001 -L ip_stratixiv_mac_10g_rsp_xbar_mux -L ip_stratixiv_mac_10g_rsp_xbar_demux -L ip_stratixiv_mac_10g_cmd_xbar_demux -L ip_stratixiv_mac_10g_rst_controller -L ip_stratixiv_mac_10g_limiter_002 -L ip_stratixiv_mac_10g_limiter_001 -L ip_stratixiv_mac_10g_limiter -L ip_stratixiv_mac_10g_id_router_010 -L ip_stratixiv_mac_10g_addr_router_002 -L ip_stratixiv_mac_10g_id_router_002 -L ip_stratixiv_mac_10g_addr_router_001 -L ip_stratixiv_mac_10g_id_router -L ip_stratixiv_mac_10g_addr_router -L ip_stratixiv_mac_10g_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_rx_bridge_m0_translator_avalon_universal_master_0_agent -L ip_stratixiv_mac_10g_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_tx_bridge_m0_translator_avalon_universal_master_0_agent -L ip_stratixiv_mac_10g_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo -L ip_stratixiv_mac_10g_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo -L ip_stratixiv_mac_10g_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_rx_bridge_s0_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent -L ip_stratixiv_mac_10g_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo -L ip_stratixiv_mac_10g_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo -L ip_stratixiv_mac_10g_tx_bridge_s0_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_rx_eth_packet_overflow_control_csr_translator -L ip_stratixiv_mac_10g_tx_eth_statistics_collector_csr_translator -L ip_stratixiv_mac_10g_tx_eth_frame_decoder_avalom_mm_csr_translator -L ip_stratixiv_mac_10g_tx_eth_packet_underflow_control_avalon_slave_0_translator -L ip_stratixiv_mac_10g_tx_eth_pause_ctrl_gen_csr_translator -L ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control_csr_translator -L ip_stratixiv_mac_10g_tx_bridge_m0_translator -L ip_stratixiv_mac_10g_tx_bridge_s0_translator -L ip_stratixiv_mac_10g_merlin_master_translator_avalon_universal_master_0_translator -L ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_tx -L ip_stratixiv_mac_10g_rxtx_dc_fifo_pauselen -L ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_rx -L ip_stratixiv_mac_10g_rxtx_dc_fifo_link_fault_status -L ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_export -L ip_stratixiv_mac_10g_txrx_st_splitter_link_fault_status -L ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_rx -L ip_stratixiv_mac_10g_rx_st_status_statistics_delay -L ip_stratixiv_mac_10g_rx_st_error_adapter_stat -L ip_stratixiv_mac_10g_rx_st_status_output_delay -L ip_stratixiv_mac_10g_rx_eth_packet_overflow_control -L ip_stratixiv_mac_10g_rx_eth_crc_pad_rem -L ip_stratixiv_mac_10g_rx_eth_frame_status_merger -L ip_stratixiv_mac_10g_rx_timing_adapter_frame_status_out_frame_decoder -L ip_stratixiv_mac_10g_rx_st_frame_status_splitter -L ip_stratixiv_mac_10g_rx_st_timing_adapter_frame_status_in -L ip_stratixiv_mac_10g_rx_eth_lane_decoder -L ip_stratixiv_mac_10g_rx_eth_link_fault_detection -L ip_stratixiv_mac_10g_rx_st_timing_adapter_lane_decoder -L ip_stratixiv_mac_10g_rx_st_splitter_xgmii -L ip_stratixiv_mac_10g_rx_st_timing_adapter_interface_conversion -L ip_stratixiv_mac_10g_tx_eth_link_fault_generation -L ip_stratixiv_mac_10g_tx_eth_xgmii_termination -L ip_stratixiv_mac_10g_tx_eth_packet_formatter -L ip_stratixiv_mac_10g_tx_eth_statistics_collector -L ip_stratixiv_mac_10g_tx_st_status_splitter -L ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_output -L ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_in -L ip_stratixiv_mac_10g_tx_st_error_adapter_stat -L ip_stratixiv_mac_10g_tx_eth_frame_decoder -L ip_stratixiv_mac_10g_tx_st_timing_adapter_frame_decoder -L ip_stratixiv_mac_10g_tx_st_splitter_1 -L ip_stratixiv_mac_10g_tx_st_pipeline_stage_rs -L ip_stratixiv_mac_10g_tx_eth_crc_inserter -L ip_stratixiv_mac_10g_tx_eth_address_inserter -L ip_stratixiv_mac_10g_tx_st_mux_flow_control_user_frame -L ip_stratixiv_mac_10g_tx_st_pause_ctrl_error_adapter -L ip_stratixiv_mac_10g_tx_eth_pause_ctrl_gen -L ip_stratixiv_mac_10g_tx_eth_pause_beat_conversion -L ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control -L ip_stratixiv_mac_10g_tx_eth_pad_inserter -L ip_stratixiv_mac_10g_tx_eth_packet_underflow_control -L ip_stratixiv_mac_10g_tx_bridge -L ip_stratixiv_mac_10g_merlin_master_translator -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L stratixiv_hssi_ver -L stratixiv_pcie_hip_ver -L stratixiv_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L stratixiv_hssi -L stratixiv_pcie_hip -L stratixiv $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Elaborate the top level design with novopt option
+alias elab_debug {
+ echo "\[exec\] elab_debug"
+ vsim -novopt -t ps -L work -L ip_stratixiv_mac_10g_crosser -L ip_stratixiv_mac_10g_rsp_xbar_mux_002 -L ip_stratixiv_mac_10g_rsp_xbar_demux_010 -L ip_stratixiv_mac_10g_cmd_xbar_demux_002 -L ip_stratixiv_mac_10g_rsp_xbar_mux_001 -L ip_stratixiv_mac_10g_rsp_xbar_demux_002 -L ip_stratixiv_mac_10g_cmd_xbar_demux_001 -L ip_stratixiv_mac_10g_rsp_xbar_mux -L ip_stratixiv_mac_10g_rsp_xbar_demux -L ip_stratixiv_mac_10g_cmd_xbar_demux -L ip_stratixiv_mac_10g_rst_controller -L ip_stratixiv_mac_10g_limiter_002 -L ip_stratixiv_mac_10g_limiter_001 -L ip_stratixiv_mac_10g_limiter -L ip_stratixiv_mac_10g_id_router_010 -L ip_stratixiv_mac_10g_addr_router_002 -L ip_stratixiv_mac_10g_id_router_002 -L ip_stratixiv_mac_10g_addr_router_001 -L ip_stratixiv_mac_10g_id_router -L ip_stratixiv_mac_10g_addr_router -L ip_stratixiv_mac_10g_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_rx_bridge_m0_translator_avalon_universal_master_0_agent -L ip_stratixiv_mac_10g_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_tx_bridge_m0_translator_avalon_universal_master_0_agent -L ip_stratixiv_mac_10g_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo -L ip_stratixiv_mac_10g_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo -L ip_stratixiv_mac_10g_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_rx_bridge_s0_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_merlin_master_translator_avalon_universal_master_0_translator_avalon_universal_master_0_agent -L ip_stratixiv_mac_10g_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo -L ip_stratixiv_mac_10g_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo -L ip_stratixiv_mac_10g_tx_bridge_s0_translator_avalon_universal_slave_0_agent -L ip_stratixiv_mac_10g_rx_eth_packet_overflow_control_csr_translator -L ip_stratixiv_mac_10g_tx_eth_statistics_collector_csr_translator -L ip_stratixiv_mac_10g_tx_eth_frame_decoder_avalom_mm_csr_translator -L ip_stratixiv_mac_10g_tx_eth_packet_underflow_control_avalon_slave_0_translator -L ip_stratixiv_mac_10g_tx_eth_pause_ctrl_gen_csr_translator -L ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control_csr_translator -L ip_stratixiv_mac_10g_tx_bridge_m0_translator -L ip_stratixiv_mac_10g_tx_bridge_s0_translator -L ip_stratixiv_mac_10g_merlin_master_translator_avalon_universal_master_0_translator -L ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_tx -L ip_stratixiv_mac_10g_rxtx_dc_fifo_pauselen -L ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_rx -L ip_stratixiv_mac_10g_rxtx_dc_fifo_link_fault_status -L ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_export -L ip_stratixiv_mac_10g_txrx_st_splitter_link_fault_status -L ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_rx -L ip_stratixiv_mac_10g_rx_st_status_statistics_delay -L ip_stratixiv_mac_10g_rx_st_error_adapter_stat -L ip_stratixiv_mac_10g_rx_st_status_output_delay -L ip_stratixiv_mac_10g_rx_eth_packet_overflow_control -L ip_stratixiv_mac_10g_rx_eth_crc_pad_rem -L ip_stratixiv_mac_10g_rx_eth_frame_status_merger -L ip_stratixiv_mac_10g_rx_timing_adapter_frame_status_out_frame_decoder -L ip_stratixiv_mac_10g_rx_st_frame_status_splitter -L ip_stratixiv_mac_10g_rx_st_timing_adapter_frame_status_in -L ip_stratixiv_mac_10g_rx_eth_lane_decoder -L ip_stratixiv_mac_10g_rx_eth_link_fault_detection -L ip_stratixiv_mac_10g_rx_st_timing_adapter_lane_decoder -L ip_stratixiv_mac_10g_rx_st_splitter_xgmii -L ip_stratixiv_mac_10g_rx_st_timing_adapter_interface_conversion -L ip_stratixiv_mac_10g_tx_eth_link_fault_generation -L ip_stratixiv_mac_10g_tx_eth_xgmii_termination -L ip_stratixiv_mac_10g_tx_eth_packet_formatter -L ip_stratixiv_mac_10g_tx_eth_statistics_collector -L ip_stratixiv_mac_10g_tx_st_status_splitter -L ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_output -L ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_in -L ip_stratixiv_mac_10g_tx_st_error_adapter_stat -L ip_stratixiv_mac_10g_tx_eth_frame_decoder -L ip_stratixiv_mac_10g_tx_st_timing_adapter_frame_decoder -L ip_stratixiv_mac_10g_tx_st_splitter_1 -L ip_stratixiv_mac_10g_tx_st_pipeline_stage_rs -L ip_stratixiv_mac_10g_tx_eth_crc_inserter -L ip_stratixiv_mac_10g_tx_eth_address_inserter -L ip_stratixiv_mac_10g_tx_st_mux_flow_control_user_frame -L ip_stratixiv_mac_10g_tx_st_pause_ctrl_error_adapter -L ip_stratixiv_mac_10g_tx_eth_pause_ctrl_gen -L ip_stratixiv_mac_10g_tx_eth_pause_beat_conversion -L ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control -L ip_stratixiv_mac_10g_tx_eth_pad_inserter -L ip_stratixiv_mac_10g_tx_eth_packet_underflow_control -L ip_stratixiv_mac_10g_tx_bridge -L ip_stratixiv_mac_10g_merlin_master_translator -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L stratixiv_hssi_ver -L stratixiv_pcie_hip_ver -L stratixiv_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L stratixiv_hssi -L stratixiv_pcie_hip -L stratixiv $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design
+alias ld "
+ dev_com
+ com
+ elab
+"
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design with -novopt
+alias ld_debug "
+ dev_com
+ com
+ elab_debug
+"
+
+# ----------------------------------------
+# Print out user commmand line aliases
+alias h {
+ echo "List Of Command Line Aliases"
+ echo
+ echo "dev_com -- Compile device library files"
+ echo
+ echo "com -- Compile the design files in correct order"
+ echo
+ echo "elab -- Elaborate top level design"
+ echo
+ echo "elab_debug -- Elaborate the top level design with novopt option"
+ echo
+ echo "ld -- Compile all the design files and elaborate the top level design"
+ echo
+ echo "ld_debug -- Compile all the design files and elaborate the top level design with -novopt"
+ echo
+ echo
+ echo
+ echo "List Of Variables"
+ echo
+ echo "TOP_LEVEL_NAME -- Top level module name."
+ echo
+ echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
+ echo
+ echo "QSYS_SIMDIR -- Qsys base simulation directory."
+}
+h
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/multiplexer/multiplexer_0001.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/multiplexer/multiplexer_0001.vho
new file mode 100644
index 0000000000000000000000000000000000000000..a542510eda504ca586f2fc252a98c4b45ee2250e
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/multiplexer/multiplexer_0001.vho
@@ -0,0 +1,532 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+ LIBRARY sgate;
+ USE sgate.sgate_pack.all;
+
+--synthesis_resources = lut 75 mux21 83 oper_decoder 2
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY multiplexer_0001 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ in0_data : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+ in0_empty : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+ in0_endofpacket : IN STD_LOGIC;
+ in0_error : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+ in0_ready : OUT STD_LOGIC;
+ in0_startofpacket : IN STD_LOGIC;
+ in0_valid : IN STD_LOGIC;
+ in1_data : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+ in1_empty : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+ in1_endofpacket : IN STD_LOGIC;
+ in1_error : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+ in1_ready : OUT STD_LOGIC;
+ in1_startofpacket : IN STD_LOGIC;
+ in1_valid : IN STD_LOGIC;
+ out_channel : OUT STD_LOGIC;
+ out_data : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
+ out_empty : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ out_endofpacket : OUT STD_LOGIC;
+ out_error : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+ out_ready : IN STD_LOGIC;
+ out_startofpacket : OUT STD_LOGIC;
+ out_valid : OUT STD_LOGIC;
+ reset_n : IN STD_LOGIC
+ );
+ END multiplexer_0001;
+
+ ARCHITECTURE RTL OF multiplexer_0001 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_0_545q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_10_681q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_11_680q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_12_679q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_13_678q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_14_677q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_15_676q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_16_675q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_17_674q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_18_673q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_19_672q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_1_690q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_20_671q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_21_670q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_22_669q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_23_668q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_24_667q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_25_666q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_26_665q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_27_664q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_28_663q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_29_662q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_2_689q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_30_661q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_31_660q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_32_659q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_33_658q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_34_657q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_35_656q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_36_655q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_37_654q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_38_653q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_39_652q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_3_688q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_40_651q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_41_650q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_42_649q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_43_648q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_44_647q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_45_646q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_46_645q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_47_644q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_48_643q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_49_642q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_4_687q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_50_641q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_51_640q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_52_639q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_53_638q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_54_637q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_55_636q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_56_635q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_57_634q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_58_633q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_59_632q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_5_686q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_60_631q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_61_630q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_62_629q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_63_628q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_64_627q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_65_626q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_66_625q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_67_624q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_68_623q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_69_622q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_6_685q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_70_621q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_71_620q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_7_684q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_8_683q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_9_682q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_valid_619q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_packet_in_progress_3q : STD_LOGIC := '0';
+ SIGNAL multiplexer_0001_select_14q : STD_LOGIC := '0';
+ SIGNAL wire_nO_w224w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_nO_w_lg_multiplexer_0001_packet_in_progress_3q2w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_multiplexer_0001_decision_1m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_decision_2m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_in0_ready_93m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_in1_ready_91m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_valid_470m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_valid_471m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_packet_in_progress_13m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_packet_in_progress_9m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_select_12m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_select_8m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_endofpacket_88m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_0_86m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_10_76m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_11_75m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_12_74m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_13_73m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_14_72m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_15_71m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_16_70m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_17_69m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_18_68m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_19_67m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_1_85m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_20_66m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_21_65m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_22_64m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_23_63m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_24_62m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_25_61m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_26_60m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_27_59m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_28_58m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_29_57m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_2_84m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_30_56m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_31_55m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_32_54m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_33_53m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_34_52m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_35_51m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_36_50m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_37_49m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_38_48m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_39_47m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_3_83m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_40_46m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_41_45m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_42_44m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_43_43m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_44_42m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_45_41m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_46_40m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_47_39m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_48_38m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_49_37m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_4_82m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_50_36m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_51_35m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_52_34m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_53_33m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_54_32m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_55_31m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_56_30m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_57_29m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_58_28m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_59_27m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_5_81m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_60_26m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_61_25m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_62_24m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_63_23m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_64_22m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_65_21m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_66_20m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_67_19m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_68_18m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_69_17m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_6_80m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_70_16m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_7_79m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_8_78m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_payload_9_77m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_valid_87m_dataout : STD_LOGIC;
+ SIGNAL wire_multiplexer_0001_selected_valid_87m_w_lg_dataout3w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_multiplexer_0001_decoder0_15_i : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_multiplexer_0001_decoder0_15_o : STD_LOGIC_VECTOR (1 DOWNTO 0);
+ SIGNAL wire_multiplexer_0001_decoder1_92_i : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_multiplexer_0001_decoder1_92_o : STD_LOGIC_VECTOR (1 DOWNTO 0);
+ SIGNAL wire_w_lg_in0_valid151w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_lg_in1_valid148w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL s_wire_multiplexer_0001_always2_11_dataout : STD_LOGIC;
+ SIGNAL s_wire_multiplexer_0001_always2_7_dataout : STD_LOGIC;
+ SIGNAL s_wire_multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_always1_472_dataout : STD_LOGIC;
+ SIGNAL s_wire_multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_in_ready_468_dataout : STD_LOGIC;
+ SIGNAL s_wire_vcc : STD_LOGIC;
+ BEGIN
+
+ wire_w_lg_in0_valid151w(0) <= NOT in0_valid;
+ wire_w_lg_in1_valid148w(0) <= NOT in1_valid;
+ in0_ready <= wire_multiplexer_0001_in0_ready_93m_dataout;
+ in1_ready <= wire_multiplexer_0001_in1_ready_91m_dataout;
+ out_channel <= multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_71_620q;
+ out_data <= ( multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_70_621q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_69_622q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_68_623q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_67_624q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_66_625q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_65_626q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_64_627q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_63_628q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_62_629q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_61_630q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_60_631q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_59_632q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_58_633q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_57_634q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_56_635q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_55_636q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_54_637q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_53_638q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_52_639q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_51_640q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_50_641q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_49_642q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_48_643q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_47_644q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_46_645q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_45_646q
+ & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_44_647q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_43_648q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_42_649q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_41_650q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_40_651q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_39_652q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_38_653q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_37_654q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_36_655q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_35_656q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_34_657q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_33_658q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_32_659q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_31_660q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_30_661q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_29_662q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_28_663q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_27_664q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_26_665q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_25_666q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_24_667q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_23_668q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_22_669q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_21_670q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_20_671q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_19_672q
+ & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_18_673q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_17_674q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_16_675q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_15_676q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_14_677q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_13_678q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_12_679q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_11_680q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_10_681q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_9_682q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_8_683q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_7_684q);
+ out_empty <= ( multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_6_685q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_5_686q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_4_687q);
+ out_endofpacket <= multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_3_688q;
+ out_error <= ( multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_2_689q & multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_1_690q);
+ out_startofpacket <= multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_0_545q;
+ out_valid <= multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_valid_619q;
+ s_wire_multiplexer_0001_always2_11_dataout <= ((wire_multiplexer_0001_selected_valid_87m_dataout AND wire_multiplexer_0001_selected_endofpacket_88m_dataout) AND s_wire_multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_in_ready_468_dataout);
+ s_wire_multiplexer_0001_always2_7_dataout <= (wire_nO_w_lg_multiplexer_0001_packet_in_progress_3q2w(0) AND wire_multiplexer_0001_selected_valid_87m_w_lg_dataout3w(0));
+ s_wire_multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_always1_472_dataout <= (wire_multiplexer_0001_selected_valid_87m_dataout AND s_wire_multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_in_ready_468_dataout);
+ s_wire_multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_in_ready_468_dataout <= (out_ready OR wire_nO_w224w(0));
+ s_wire_vcc <= '1';
+ PROCESS (clk, reset_n)
+ BEGIN
+ IF (reset_n = '0') THEN
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_0_545q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_10_681q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_11_680q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_12_679q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_13_678q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_14_677q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_15_676q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_16_675q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_17_674q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_18_673q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_19_672q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_1_690q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_20_671q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_21_670q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_22_669q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_23_668q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_24_667q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_25_666q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_26_665q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_27_664q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_28_663q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_29_662q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_2_689q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_30_661q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_31_660q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_32_659q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_33_658q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_34_657q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_35_656q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_36_655q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_37_654q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_38_653q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_39_652q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_3_688q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_40_651q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_41_650q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_42_649q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_43_648q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_44_647q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_45_646q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_46_645q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_47_644q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_48_643q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_49_642q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_4_687q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_50_641q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_51_640q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_52_639q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_53_638q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_54_637q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_55_636q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_56_635q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_57_634q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_58_633q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_59_632q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_5_686q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_60_631q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_61_630q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_62_629q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_63_628q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_64_627q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_65_626q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_66_625q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_67_624q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_68_623q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_69_622q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_6_685q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_70_621q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_71_620q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_7_684q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_8_683q <= '0';
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_9_682q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ IF (s_wire_multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_always1_472_dataout = '1') THEN
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_0_545q <= wire_multiplexer_0001_selected_payload_0_86m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_10_681q <= wire_multiplexer_0001_selected_payload_10_76m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_11_680q <= wire_multiplexer_0001_selected_payload_11_75m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_12_679q <= wire_multiplexer_0001_selected_payload_12_74m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_13_678q <= wire_multiplexer_0001_selected_payload_13_73m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_14_677q <= wire_multiplexer_0001_selected_payload_14_72m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_15_676q <= wire_multiplexer_0001_selected_payload_15_71m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_16_675q <= wire_multiplexer_0001_selected_payload_16_70m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_17_674q <= wire_multiplexer_0001_selected_payload_17_69m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_18_673q <= wire_multiplexer_0001_selected_payload_18_68m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_19_672q <= wire_multiplexer_0001_selected_payload_19_67m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_1_690q <= wire_multiplexer_0001_selected_payload_1_85m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_20_671q <= wire_multiplexer_0001_selected_payload_20_66m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_21_670q <= wire_multiplexer_0001_selected_payload_21_65m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_22_669q <= wire_multiplexer_0001_selected_payload_22_64m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_23_668q <= wire_multiplexer_0001_selected_payload_23_63m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_24_667q <= wire_multiplexer_0001_selected_payload_24_62m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_25_666q <= wire_multiplexer_0001_selected_payload_25_61m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_26_665q <= wire_multiplexer_0001_selected_payload_26_60m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_27_664q <= wire_multiplexer_0001_selected_payload_27_59m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_28_663q <= wire_multiplexer_0001_selected_payload_28_58m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_29_662q <= wire_multiplexer_0001_selected_payload_29_57m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_2_689q <= wire_multiplexer_0001_selected_payload_2_84m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_30_661q <= wire_multiplexer_0001_selected_payload_30_56m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_31_660q <= wire_multiplexer_0001_selected_payload_31_55m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_32_659q <= wire_multiplexer_0001_selected_payload_32_54m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_33_658q <= wire_multiplexer_0001_selected_payload_33_53m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_34_657q <= wire_multiplexer_0001_selected_payload_34_52m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_35_656q <= wire_multiplexer_0001_selected_payload_35_51m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_36_655q <= wire_multiplexer_0001_selected_payload_36_50m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_37_654q <= wire_multiplexer_0001_selected_payload_37_49m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_38_653q <= wire_multiplexer_0001_selected_payload_38_48m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_39_652q <= wire_multiplexer_0001_selected_payload_39_47m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_3_688q <= wire_multiplexer_0001_selected_payload_3_83m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_40_651q <= wire_multiplexer_0001_selected_payload_40_46m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_41_650q <= wire_multiplexer_0001_selected_payload_41_45m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_42_649q <= wire_multiplexer_0001_selected_payload_42_44m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_43_648q <= wire_multiplexer_0001_selected_payload_43_43m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_44_647q <= wire_multiplexer_0001_selected_payload_44_42m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_45_646q <= wire_multiplexer_0001_selected_payload_45_41m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_46_645q <= wire_multiplexer_0001_selected_payload_46_40m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_47_644q <= wire_multiplexer_0001_selected_payload_47_39m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_48_643q <= wire_multiplexer_0001_selected_payload_48_38m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_49_642q <= wire_multiplexer_0001_selected_payload_49_37m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_4_687q <= wire_multiplexer_0001_selected_payload_4_82m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_50_641q <= wire_multiplexer_0001_selected_payload_50_36m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_51_640q <= wire_multiplexer_0001_selected_payload_51_35m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_52_639q <= wire_multiplexer_0001_selected_payload_52_34m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_53_638q <= wire_multiplexer_0001_selected_payload_53_33m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_54_637q <= wire_multiplexer_0001_selected_payload_54_32m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_55_636q <= wire_multiplexer_0001_selected_payload_55_31m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_56_635q <= wire_multiplexer_0001_selected_payload_56_30m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_57_634q <= wire_multiplexer_0001_selected_payload_57_29m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_58_633q <= wire_multiplexer_0001_selected_payload_58_28m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_59_632q <= wire_multiplexer_0001_selected_payload_59_27m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_5_686q <= wire_multiplexer_0001_selected_payload_5_81m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_60_631q <= wire_multiplexer_0001_selected_payload_60_26m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_61_630q <= wire_multiplexer_0001_selected_payload_61_25m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_62_629q <= wire_multiplexer_0001_selected_payload_62_24m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_63_628q <= wire_multiplexer_0001_selected_payload_63_23m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_64_627q <= wire_multiplexer_0001_selected_payload_64_22m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_65_626q <= wire_multiplexer_0001_selected_payload_65_21m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_66_625q <= wire_multiplexer_0001_selected_payload_66_20m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_67_624q <= wire_multiplexer_0001_selected_payload_67_19m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_68_623q <= wire_multiplexer_0001_selected_payload_68_18m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_69_622q <= wire_multiplexer_0001_selected_payload_69_17m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_6_685q <= wire_multiplexer_0001_selected_payload_6_80m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_70_621q <= wire_multiplexer_0001_selected_payload_70_16m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_71_620q <= multiplexer_0001_select_14q;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_7_684q <= wire_multiplexer_0001_selected_payload_7_79m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_8_683q <= wire_multiplexer_0001_selected_payload_8_78m_dataout;
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_payload_9_682q <= wire_multiplexer_0001_selected_payload_9_77m_dataout;
+ END IF;
+ END IF;
+ END PROCESS;
+ PROCESS (clk, reset_n)
+ BEGIN
+ IF (reset_n = '0') THEN
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_valid_619q <= '0';
+ multiplexer_0001_packet_in_progress_3q <= '0';
+ multiplexer_0001_select_14q <= '0';
+ ELSIF (clk = '1' AND clk'event) THEN
+ multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_valid_619q <= wire_multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_valid_471m_dataout;
+ multiplexer_0001_packet_in_progress_3q <= wire_multiplexer_0001_packet_in_progress_13m_dataout;
+ multiplexer_0001_select_14q <= wire_multiplexer_0001_select_12m_dataout;
+ END IF;
+ END PROCESS;
+ wire_nO_w224w(0) <= NOT multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_valid_619q;
+ wire_nO_w_lg_multiplexer_0001_packet_in_progress_3q2w(0) <= NOT multiplexer_0001_packet_in_progress_3q;
+ wire_multiplexer_0001_decision_1m_dataout <= in1_valid AND NOT(in0_valid);
+ wire_multiplexer_0001_decision_2m_dataout <= wire_multiplexer_0001_decision_1m_dataout WHEN wire_multiplexer_0001_decoder1_92_o(1) = '1' ELSE in1_valid;
+ wire_multiplexer_0001_in0_ready_93m_dataout <= wire_w_lg_in0_valid151w(0) WHEN wire_multiplexer_0001_decoder1_92_o(1) = '1' ELSE s_wire_multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_in_ready_468_dataout;
+ wire_multiplexer_0001_in1_ready_91m_dataout <= s_wire_multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_in_ready_468_dataout WHEN wire_multiplexer_0001_decoder1_92_o(1) = '1' ELSE wire_w_lg_in1_valid148w(0);
+ wire_multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_valid_470m_dataout <= multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_valid_619q AND NOT(out_ready);
+ wire_multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_valid_471m_dataout <= wire_multiplexer_0001_multiplexer_0001_1stage_pipeline_outpipe_out_valid_470m_dataout OR wire_multiplexer_0001_selected_valid_87m_dataout;
+ wire_multiplexer_0001_packet_in_progress_13m_dataout <= wire_multiplexer_0001_packet_in_progress_9m_dataout AND NOT(s_wire_multiplexer_0001_always2_11_dataout);
+ wire_multiplexer_0001_packet_in_progress_9m_dataout <= multiplexer_0001_packet_in_progress_3q OR NOT(s_wire_multiplexer_0001_always2_7_dataout);
+ wire_multiplexer_0001_select_12m_dataout <= wire_multiplexer_0001_decision_2m_dataout WHEN s_wire_multiplexer_0001_always2_11_dataout = '1' ELSE wire_multiplexer_0001_select_8m_dataout;
+ wire_multiplexer_0001_select_8m_dataout <= wire_multiplexer_0001_decision_2m_dataout WHEN s_wire_multiplexer_0001_always2_7_dataout = '1' ELSE multiplexer_0001_select_14q;
+ wire_multiplexer_0001_selected_endofpacket_88m_dataout <= in1_endofpacket WHEN wire_multiplexer_0001_decoder1_92_o(1) = '1' ELSE in0_endofpacket;
+ wire_multiplexer_0001_selected_payload_0_86m_dataout <= in1_startofpacket WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_startofpacket;
+ wire_multiplexer_0001_selected_payload_10_76m_dataout <= in1_data(3) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(3);
+ wire_multiplexer_0001_selected_payload_11_75m_dataout <= in1_data(4) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(4);
+ wire_multiplexer_0001_selected_payload_12_74m_dataout <= in1_data(5) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(5);
+ wire_multiplexer_0001_selected_payload_13_73m_dataout <= in1_data(6) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(6);
+ wire_multiplexer_0001_selected_payload_14_72m_dataout <= in1_data(7) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(7);
+ wire_multiplexer_0001_selected_payload_15_71m_dataout <= in1_data(8) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(8);
+ wire_multiplexer_0001_selected_payload_16_70m_dataout <= in1_data(9) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(9);
+ wire_multiplexer_0001_selected_payload_17_69m_dataout <= in1_data(10) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(10);
+ wire_multiplexer_0001_selected_payload_18_68m_dataout <= in1_data(11) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(11);
+ wire_multiplexer_0001_selected_payload_19_67m_dataout <= in1_data(12) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(12);
+ wire_multiplexer_0001_selected_payload_1_85m_dataout <= in1_error(0) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_error(0);
+ wire_multiplexer_0001_selected_payload_20_66m_dataout <= in1_data(13) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(13);
+ wire_multiplexer_0001_selected_payload_21_65m_dataout <= in1_data(14) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(14);
+ wire_multiplexer_0001_selected_payload_22_64m_dataout <= in1_data(15) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(15);
+ wire_multiplexer_0001_selected_payload_23_63m_dataout <= in1_data(16) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(16);
+ wire_multiplexer_0001_selected_payload_24_62m_dataout <= in1_data(17) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(17);
+ wire_multiplexer_0001_selected_payload_25_61m_dataout <= in1_data(18) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(18);
+ wire_multiplexer_0001_selected_payload_26_60m_dataout <= in1_data(19) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(19);
+ wire_multiplexer_0001_selected_payload_27_59m_dataout <= in1_data(20) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(20);
+ wire_multiplexer_0001_selected_payload_28_58m_dataout <= in1_data(21) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(21);
+ wire_multiplexer_0001_selected_payload_29_57m_dataout <= in1_data(22) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(22);
+ wire_multiplexer_0001_selected_payload_2_84m_dataout <= in1_error(1) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_error(1);
+ wire_multiplexer_0001_selected_payload_30_56m_dataout <= in1_data(23) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(23);
+ wire_multiplexer_0001_selected_payload_31_55m_dataout <= in1_data(24) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(24);
+ wire_multiplexer_0001_selected_payload_32_54m_dataout <= in1_data(25) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(25);
+ wire_multiplexer_0001_selected_payload_33_53m_dataout <= in1_data(26) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(26);
+ wire_multiplexer_0001_selected_payload_34_52m_dataout <= in1_data(27) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(27);
+ wire_multiplexer_0001_selected_payload_35_51m_dataout <= in1_data(28) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(28);
+ wire_multiplexer_0001_selected_payload_36_50m_dataout <= in1_data(29) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(29);
+ wire_multiplexer_0001_selected_payload_37_49m_dataout <= in1_data(30) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(30);
+ wire_multiplexer_0001_selected_payload_38_48m_dataout <= in1_data(31) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(31);
+ wire_multiplexer_0001_selected_payload_39_47m_dataout <= in1_data(32) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(32);
+ wire_multiplexer_0001_selected_payload_3_83m_dataout <= in1_endofpacket WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_endofpacket;
+ wire_multiplexer_0001_selected_payload_40_46m_dataout <= in1_data(33) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(33);
+ wire_multiplexer_0001_selected_payload_41_45m_dataout <= in1_data(34) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(34);
+ wire_multiplexer_0001_selected_payload_42_44m_dataout <= in1_data(35) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(35);
+ wire_multiplexer_0001_selected_payload_43_43m_dataout <= in1_data(36) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(36);
+ wire_multiplexer_0001_selected_payload_44_42m_dataout <= in1_data(37) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(37);
+ wire_multiplexer_0001_selected_payload_45_41m_dataout <= in1_data(38) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(38);
+ wire_multiplexer_0001_selected_payload_46_40m_dataout <= in1_data(39) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(39);
+ wire_multiplexer_0001_selected_payload_47_39m_dataout <= in1_data(40) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(40);
+ wire_multiplexer_0001_selected_payload_48_38m_dataout <= in1_data(41) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(41);
+ wire_multiplexer_0001_selected_payload_49_37m_dataout <= in1_data(42) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(42);
+ wire_multiplexer_0001_selected_payload_4_82m_dataout <= in1_empty(0) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_empty(0);
+ wire_multiplexer_0001_selected_payload_50_36m_dataout <= in1_data(43) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(43);
+ wire_multiplexer_0001_selected_payload_51_35m_dataout <= in1_data(44) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(44);
+ wire_multiplexer_0001_selected_payload_52_34m_dataout <= in1_data(45) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(45);
+ wire_multiplexer_0001_selected_payload_53_33m_dataout <= in1_data(46) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(46);
+ wire_multiplexer_0001_selected_payload_54_32m_dataout <= in1_data(47) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(47);
+ wire_multiplexer_0001_selected_payload_55_31m_dataout <= in1_data(48) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(48);
+ wire_multiplexer_0001_selected_payload_56_30m_dataout <= in1_data(49) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(49);
+ wire_multiplexer_0001_selected_payload_57_29m_dataout <= in1_data(50) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(50);
+ wire_multiplexer_0001_selected_payload_58_28m_dataout <= in1_data(51) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(51);
+ wire_multiplexer_0001_selected_payload_59_27m_dataout <= in1_data(52) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(52);
+ wire_multiplexer_0001_selected_payload_5_81m_dataout <= in1_empty(1) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_empty(1);
+ wire_multiplexer_0001_selected_payload_60_26m_dataout <= in1_data(53) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(53);
+ wire_multiplexer_0001_selected_payload_61_25m_dataout <= in1_data(54) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(54);
+ wire_multiplexer_0001_selected_payload_62_24m_dataout <= in1_data(55) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(55);
+ wire_multiplexer_0001_selected_payload_63_23m_dataout <= in1_data(56) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(56);
+ wire_multiplexer_0001_selected_payload_64_22m_dataout <= in1_data(57) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(57);
+ wire_multiplexer_0001_selected_payload_65_21m_dataout <= in1_data(58) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(58);
+ wire_multiplexer_0001_selected_payload_66_20m_dataout <= in1_data(59) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(59);
+ wire_multiplexer_0001_selected_payload_67_19m_dataout <= in1_data(60) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(60);
+ wire_multiplexer_0001_selected_payload_68_18m_dataout <= in1_data(61) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(61);
+ wire_multiplexer_0001_selected_payload_69_17m_dataout <= in1_data(62) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(62);
+ wire_multiplexer_0001_selected_payload_6_80m_dataout <= in1_empty(2) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_empty(2);
+ wire_multiplexer_0001_selected_payload_70_16m_dataout <= in1_data(63) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(63);
+ wire_multiplexer_0001_selected_payload_7_79m_dataout <= in1_data(0) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(0);
+ wire_multiplexer_0001_selected_payload_8_78m_dataout <= in1_data(1) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(1);
+ wire_multiplexer_0001_selected_payload_9_77m_dataout <= in1_data(2) WHEN wire_multiplexer_0001_decoder0_15_o(1) = '1' ELSE in0_data(2);
+ wire_multiplexer_0001_selected_valid_87m_dataout <= in1_valid WHEN wire_multiplexer_0001_decoder1_92_o(1) = '1' ELSE in0_valid;
+ wire_multiplexer_0001_selected_valid_87m_w_lg_dataout3w(0) <= NOT wire_multiplexer_0001_selected_valid_87m_dataout;
+ wire_multiplexer_0001_decoder0_15_i(0) <= ( multiplexer_0001_select_14q);
+ multiplexer_0001_decoder0_15 : oper_decoder
+ GENERIC MAP (
+ width_i => 1,
+ width_o => 2
+ )
+ PORT MAP (
+ i => wire_multiplexer_0001_decoder0_15_i,
+ o => wire_multiplexer_0001_decoder0_15_o
+ );
+ wire_multiplexer_0001_decoder1_92_i(0) <= ( multiplexer_0001_select_14q);
+ multiplexer_0001_decoder1_92 : oper_decoder
+ GENERIC MAP (
+ width_i => 1,
+ width_o => 2
+ )
+ PORT MAP (
+ i => wire_multiplexer_0001_decoder1_92_i,
+ o => wire_multiplexer_0001_decoder1_92_o
+ );
+
+ END RTL; --multiplexer_0001
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0001.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0001.vho
new file mode 100644
index 0000000000000000000000000000000000000000..209e06dc117dbbd71617ec20c290ffbec3468cd5
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0001.vho
@@ -0,0 +1,67 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY timing_adapter_0001 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ in_data : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+ in_empty : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+ in_endofpacket : IN STD_LOGIC;
+ in_error : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+ in_ready : OUT STD_LOGIC;
+ in_startofpacket : IN STD_LOGIC;
+ in_valid : IN STD_LOGIC;
+ out_data : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
+ out_empty : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ out_endofpacket : OUT STD_LOGIC;
+ out_error : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ out_startofpacket : OUT STD_LOGIC;
+ out_valid : OUT STD_LOGIC;
+ reset_n : IN STD_LOGIC
+ );
+ END timing_adapter_0001;
+
+ ARCHITECTURE RTL OF timing_adapter_0001 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ BEGIN
+
+ in_ready <= '1';
+ out_data <= ( in_data(63 DOWNTO 0));
+ out_empty <= ( in_empty(2 DOWNTO 0));
+ out_endofpacket <= in_endofpacket;
+ out_error <= ( in_error(2 DOWNTO 0));
+ out_startofpacket <= in_startofpacket;
+ out_valid <= in_valid;
+
+ END RTL; --timing_adapter_0001
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0002.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0002.vho
new file mode 100644
index 0000000000000000000000000000000000000000..accf7c6902d6fc8a783871758b4a0d039fa9b395
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0002.vho
@@ -0,0 +1,57 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY timing_adapter_0002 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ in_data : IN STD_LOGIC_VECTOR (39 DOWNTO 0);
+ in_error : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+ in_valid : IN STD_LOGIC;
+ out_data : OUT STD_LOGIC_VECTOR (39 DOWNTO 0);
+ out_error : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
+ out_ready : IN STD_LOGIC;
+ out_valid : OUT STD_LOGIC;
+ reset_n : IN STD_LOGIC
+ );
+ END timing_adapter_0002;
+
+ ARCHITECTURE RTL OF timing_adapter_0002 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ BEGIN
+
+ out_data <= ( in_data(39 DOWNTO 0));
+ out_error <= ( in_error(6 DOWNTO 0));
+ out_valid <= in_valid;
+
+ END RTL; --timing_adapter_0002
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0003.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0003.vho
new file mode 100644
index 0000000000000000000000000000000000000000..2104524773fcd0e95f05396da9e6a44fa25607b2
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0003.vho
@@ -0,0 +1,58 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY timing_adapter_0003 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ in_data : IN STD_LOGIC_VECTOR (39 DOWNTO 0);
+ in_error : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+ in_ready : OUT STD_LOGIC;
+ in_valid : IN STD_LOGIC;
+ out_data : OUT STD_LOGIC_VECTOR (39 DOWNTO 0);
+ out_error : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
+ out_valid : OUT STD_LOGIC;
+ reset_n : IN STD_LOGIC
+ );
+ END timing_adapter_0003;
+
+ ARCHITECTURE RTL OF timing_adapter_0003 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ BEGIN
+
+ in_ready <= '1';
+ out_data <= ( in_data(39 DOWNTO 0));
+ out_error <= ( in_error(6 DOWNTO 0));
+ out_valid <= in_valid;
+
+ END RTL; --timing_adapter_0003
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0004.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0004.vho
new file mode 100644
index 0000000000000000000000000000000000000000..9bc8e8c04cf08be5251bc98d5dfbe0ac9ec93b52
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0004.vho
@@ -0,0 +1,53 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY timing_adapter_0004 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ in_data : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
+ out_data : OUT STD_LOGIC_VECTOR (71 DOWNTO 0);
+ out_ready : IN STD_LOGIC;
+ out_valid : OUT STD_LOGIC;
+ reset_n : IN STD_LOGIC
+ );
+ END timing_adapter_0004;
+
+ ARCHITECTURE RTL OF timing_adapter_0004 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ BEGIN
+
+ out_data <= ( in_data(71 DOWNTO 0));
+ out_valid <= out_ready;
+
+ END RTL; --timing_adapter_0004
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0005.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0005.vho
new file mode 100644
index 0000000000000000000000000000000000000000..b7f930be44abfa6cf0ebb8684c19bdd47eb72e91
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0005.vho
@@ -0,0 +1,53 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY timing_adapter_0005 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ in_data : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
+ in_ready : OUT STD_LOGIC;
+ in_valid : IN STD_LOGIC;
+ out_data : OUT STD_LOGIC_VECTOR (71 DOWNTO 0);
+ reset_n : IN STD_LOGIC
+ );
+ END timing_adapter_0005;
+
+ ARCHITECTURE RTL OF timing_adapter_0005 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ BEGIN
+
+ in_ready <= '1';
+ out_data <= ( in_data(71 DOWNTO 0));
+
+ END RTL; --timing_adapter_0005
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0006.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0006.vho
new file mode 100644
index 0000000000000000000000000000000000000000..0146291ba0525bb3fede82edd34a1540492ac946
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0006.vho
@@ -0,0 +1,66 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY timing_adapter_0006 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ in_data : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+ in_empty : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+ in_endofpacket : IN STD_LOGIC;
+ in_error : IN STD_LOGIC;
+ in_startofpacket : IN STD_LOGIC;
+ in_valid : IN STD_LOGIC;
+ out_data : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
+ out_empty : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ out_endofpacket : OUT STD_LOGIC;
+ out_error : OUT STD_LOGIC;
+ out_ready : IN STD_LOGIC;
+ out_startofpacket : OUT STD_LOGIC;
+ out_valid : OUT STD_LOGIC;
+ reset_n : IN STD_LOGIC
+ );
+ END timing_adapter_0006;
+
+ ARCHITECTURE RTL OF timing_adapter_0006 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ BEGIN
+
+ out_data <= ( in_data(63 DOWNTO 0));
+ out_empty <= ( in_empty(2 DOWNTO 0));
+ out_endofpacket <= in_endofpacket;
+ out_error <= in_error;
+ out_startofpacket <= in_startofpacket;
+ out_valid <= in_valid;
+
+ END RTL; --timing_adapter_0006
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0007.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0007.vho
new file mode 100644
index 0000000000000000000000000000000000000000..a127d235e0bf762c70aa50bd86cf5c7c8fa347f9
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0007.vho
@@ -0,0 +1,67 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY timing_adapter_0007 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ in_data : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+ in_empty : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+ in_endofpacket : IN STD_LOGIC;
+ in_error : IN STD_LOGIC;
+ in_ready : OUT STD_LOGIC;
+ in_startofpacket : IN STD_LOGIC;
+ in_valid : IN STD_LOGIC;
+ out_data : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
+ out_empty : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ out_endofpacket : OUT STD_LOGIC;
+ out_error : OUT STD_LOGIC;
+ out_startofpacket : OUT STD_LOGIC;
+ out_valid : OUT STD_LOGIC;
+ reset_n : IN STD_LOGIC
+ );
+ END timing_adapter_0007;
+
+ ARCHITECTURE RTL OF timing_adapter_0007 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ BEGIN
+
+ in_ready <= '1';
+ out_data <= ( in_data(63 DOWNTO 0));
+ out_empty <= ( in_empty(2 DOWNTO 0));
+ out_endofpacket <= in_endofpacket;
+ out_error <= in_error;
+ out_startofpacket <= in_startofpacket;
+ out_valid <= in_valid;
+
+ END RTL; --timing_adapter_0007
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0008.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0008.vho
new file mode 100644
index 0000000000000000000000000000000000000000..6fedf41fd4e7ff8c8de7536aac80c512a98d14cb
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0008.vho
@@ -0,0 +1,53 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY timing_adapter_0008 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ in_data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+ out_data : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+ out_ready : IN STD_LOGIC;
+ out_valid : OUT STD_LOGIC;
+ reset_n : IN STD_LOGIC
+ );
+ END timing_adapter_0008;
+
+ ARCHITECTURE RTL OF timing_adapter_0008 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ BEGIN
+
+ out_data <= ( in_data(1 DOWNTO 0));
+ out_valid <= out_ready;
+
+ END RTL; --timing_adapter_0008
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0009.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0009.vho
new file mode 100644
index 0000000000000000000000000000000000000000..dec6c4a1f3b9aab3629f4a8f56436487b9dd0753
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0009.vho
@@ -0,0 +1,53 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY timing_adapter_0009 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ in_data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+ in_ready : OUT STD_LOGIC;
+ in_valid : IN STD_LOGIC;
+ out_data : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+ reset_n : IN STD_LOGIC
+ );
+ END timing_adapter_0009;
+
+ ARCHITECTURE RTL OF timing_adapter_0009 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ BEGIN
+
+ in_ready <= '1';
+ out_data <= ( in_data(1 DOWNTO 0));
+
+ END RTL; --timing_adapter_0009
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0010.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0010.vho
new file mode 100644
index 0000000000000000000000000000000000000000..2e148f05bbcb3fa1a21a4a77add66adb75f03596
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0010.vho
@@ -0,0 +1,54 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY timing_adapter_0010 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ in_data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+ in_valid : IN STD_LOGIC;
+ out_data : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
+ out_ready : IN STD_LOGIC;
+ out_valid : OUT STD_LOGIC;
+ reset_n : IN STD_LOGIC
+ );
+ END timing_adapter_0010;
+
+ ARCHITECTURE RTL OF timing_adapter_0010 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ BEGIN
+
+ out_data <= ( in_data(15 DOWNTO 0));
+ out_valid <= in_valid;
+
+ END RTL; --timing_adapter_0010
+--synopsys translate_on
+--VALID FILE
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0011.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0011.vho
new file mode 100644
index 0000000000000000000000000000000000000000..b104e65921b7ba8a72a3c18ae4e7ee5094950967
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/timing_adapter/timing_adapter_0011.vho
@@ -0,0 +1,55 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:26:09:SJ cbx_simgen 2012:01:25:21:25:27:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2011 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+--synthesis_resources =
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY timing_adapter_0011 IS
+ PORT
+ (
+ clk : IN STD_LOGIC;
+ in_data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+ in_ready : OUT STD_LOGIC;
+ in_valid : IN STD_LOGIC;
+ out_data : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
+ out_valid : OUT STD_LOGIC;
+ reset_n : IN STD_LOGIC
+ );
+ END timing_adapter_0011;
+
+ ARCHITECTURE RTL OF timing_adapter_0011 IS
+
+ ATTRIBUTE synthesis_clearbox : natural;
+ ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+ BEGIN
+
+ in_ready <= '1';
+ out_data <= ( in_data(15 DOWNTO 0));
+ out_valid <= in_valid;
+
+ END RTL; --timing_adapter_0011
+--synopsys translate_on
+--VALID FILE