Added MAC 10GbE IP generated with Quartus 11.1 SP2.

.../ip_stratixiv_mac_10g_rx_st_timing_adapter_lane_decoder.v

...ac_10g_rx_timing_adapter_frame_status_out_frame_decoder.v

...0g/ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_rx.v

...0g/ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_tx.v

...v_mac_10g/ip_stratixiv_mac_10g_tx_st_error_adapter_stat.v

.../ip_stratixiv_mac_10g_tx_st_mux_flow_control_user_frame.v

...10g/ip_stratixiv_mac_10g_tx_st_pause_ctrl_error_adapter.v

...ip_stratixiv_mac_10g_tx_st_timing_adapter_frame_decoder.v

...ratixiv_mac_10g_tx_st_timing_adapter_splitter_status_in.v

...xiv_mac_10g_tx_st_timing_adapter_splitter_status_output.v

...iv_mac_10g_txrx_timing_adapter_link_fault_status_export.v

...atixiv_mac_10g_txrx_timing_adapter_link_fault_status_rx.v

..._sim/altera_avalon_dc_fifo/altera_avalon_dc_fifo_0001.vho

..._sim/altera_avalon_dc_fifo/altera_avalon_dc_fifo_0002.vho

.../altera_avalon_mm_bridge/altera_avalon_mm_bridge_0001.vho

..._sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0001.vho

..._sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0002.vho

..._sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0003.vho

..._sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0004.vho

...im/altera_avalon_st_delay/altera_avalon_st_delay_0001.vho