-Added clock groups for the following generated clocks:

 . XAUI/10GbE
 . SA_CLK~input~INSERTED_REF_CLK_DIVIDER|clkout
-Now designs apertif_unb1_correlator and apertif_unb1_fn_beamformer don't show 
 any false timing violations anymore.

boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc

@@ -39,6 +39,8 @@ set_clock_groups -asynchronous -group [get_clocks SB_CLK]
 set_clock_groups -asynchronous -group [get_clocks SA_CLK]
 set_clock_groups -asynchronous -group [get_clocks ETH_CLK]
 
+set_clock_groups -asynchronous -group [get_clocks SA_CLK~input~INSERTED_REFCLK_DIVIDER|clkout]
+
 set_clock_groups -asynchronous -group [get_clocks *u_sopc|the_altpll_0|sd1|pll7|clk[0]]
 set_clock_groups -asynchronous -group [get_clocks *u_sopc|the_altpll_0|sd1|pll7|clk[1]]
 set_clock_groups -asynchronous -group [get_clocks *u_sopc|the_altpll_0|sd1|pll7|clk[2]]
@@ -60,4 +62,6 @@ set_clock_groups -asynchronous -group [get_clocks ADC_BI_D_CLK]
 set_clock_groups -asynchronous -group [get_clocks {*|receive_pcs0|clkout}]
 # Transceivers: ALTGX generated TX clock
 set_clock_groups -asynchronous -group [get_clocks {*|transmit_pcs0|clkout}]
+# Transceivers: XAUI/10GbE generated clock
+set_clock_groups -asynchronous -group [get_clocks {*|central_clk_div0|coreclkout}]