From a9820c4d16e7c7f7b7f9cd82d90cd49507237b49 Mon Sep 17 00:00:00 2001
From: Daniel van der Schuur <schuur@astron.nl>
Date: Fri, 8 May 2015 09:24:49 +0000
Subject: [PATCH] -Added clock groups for the following generated clocks: .
XAUI/10GbE . SA_CLK~input~INSERTED_REF_CLK_DIVIDER|clkout -Now designs
apertif_unb1_correlator and apertif_unb1_fn_beamformer don't show any false
timing violations anymore.
---
boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
index 2afd4c4d62..930d7ddab0 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+++ b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
@@ -39,6 +39,8 @@ set_clock_groups -asynchronous -group [get_clocks SB_CLK]
set_clock_groups -asynchronous -group [get_clocks SA_CLK]
set_clock_groups -asynchronous -group [get_clocks ETH_CLK]
+set_clock_groups -asynchronous -group [get_clocks SA_CLK~input~INSERTED_REFCLK_DIVIDER|clkout]
+
set_clock_groups -asynchronous -group [get_clocks *u_sopc|the_altpll_0|sd1|pll7|clk[0]]
set_clock_groups -asynchronous -group [get_clocks *u_sopc|the_altpll_0|sd1|pll7|clk[1]]
set_clock_groups -asynchronous -group [get_clocks *u_sopc|the_altpll_0|sd1|pll7|clk[2]]
@@ -60,4 +62,6 @@ set_clock_groups -asynchronous -group [get_clocks ADC_BI_D_CLK]
set_clock_groups -asynchronous -group [get_clocks {*|receive_pcs0|clkout}]
# Transceivers: ALTGX generated TX clock
set_clock_groups -asynchronous -group [get_clocks {*|transmit_pcs0|clkout}]
+# Transceivers: XAUI/10GbE generated clock
+set_clock_groups -asynchronous -group [get_clocks {*|central_clk_div0|coreclkout}]
--
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