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Commit a2e8d3a4 authored by Eric Kooistra's avatar Eric Kooistra
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Correct wr_fifo_usedw, it gets already assigned in dp_fifo_core. To avoid...

Correct wr_fifo_usedw, it gets already assigned in dp_fifo_core. To avoid tristate insertion in synthesis due to double driver.
parent a069296e
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1 merge request!293Rename eth_stream into eth_stream_udp. Create new eth_stream.vhd that contains...
Pipeline #40015 passed
...@@ -224,8 +224,7 @@ BEGIN ...@@ -224,8 +224,7 @@ BEGIN
-- No need to transfer eop counter across clock domains for single clock -- No need to transfer eop counter across clock domains for single clock
gen_rd_eop_cnt_sc : IF g_use_dual_clock=FALSE GENERATE gen_rd_eop_cnt_sc : IF g_use_dual_clock=FALSE GENERATE
wr_fifo_usedw <= rd_fifo_usedw; rd_eop_new <= '1';
rd_eop_new <= '1';
END GENERATE; END GENERATE;
-- Set rd_eop_cnt outside generate statements to avoid Modelsim warning "Nonresolved signal 'rd_eop_cnt' may have multiple sources". -- Set rd_eop_cnt outside generate statements to avoid Modelsim warning "Nonresolved signal 'rd_eop_cnt' may have multiple sources".
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