Avoid no driver warning in synthesis.

libraries/base/dp/src/vhdl/dp_fifo_core.vhd

@@ -111,7 +111,7 @@ ARCHITECTURE str OF dp_fifo_core IS
   SIGNAL fifo_wr_dat   : STD_LOGIC_VECTOR(c_fifo_dat_w-1 DOWNTO 0);
   SIGNAL fifo_wr_req   : STD_LOGIC;
   SIGNAL fifo_wr_ful   : STD_LOGIC;
-  SIGNAL wr_init       : STD_LOGIC                                 := '0';
+  SIGNAL wr_init       : STD_LOGIC := '0';
   SIGNAL fifo_wr_usedw : STD_LOGIC_VECTOR(wr_usedw'RANGE);
   
   SIGNAL fifo_rd_dat   : STD_LOGIC_VECTOR(c_fifo_dat_w-1 DOWNTO 0) := (OTHERS=>'0');
@@ -191,6 +191,7 @@ BEGIN
       usedw    => fifo_rd_usedw
     );
     
+    wr_init <= '0';  -- to avoid no driver warning in synthesis
     fifo_wr_usedw <= fifo_rd_usedw;
   END GENERATE;