diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
index 62ddba22104d5a5ff2ba355a63bbe5150b39a20e..9d904f89e2cf577428a406bc5ee0fb2b1530b9f6 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
@@ -224,8 +224,7 @@ BEGIN
     
   -- No need to transfer eop counter across clock domains for single clock
   gen_rd_eop_cnt_sc : IF g_use_dual_clock=FALSE GENERATE
-    wr_fifo_usedw  <= rd_fifo_usedw;
-    rd_eop_new     <= '1';
+    rd_eop_new <= '1';
   END GENERATE;
 
   -- Set rd_eop_cnt outside generate statements to avoid Modelsim warning "Nonresolved signal 'rd_eop_cnt' may have multiple sources".