From a2e8d3a4d6d7f7bb474fceb61e0232a6a7abf941 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Thu, 24 Nov 2022 09:29:08 +0100
Subject: [PATCH] Correct wr_fifo_usedw, it gets already assigned in
dp_fifo_core. To avoid tristate insertion in synthesis due to double driver.
---
libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
index 62ddba2210..9d904f89e2 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
@@ -224,8 +224,7 @@ BEGIN
-- No need to transfer eop counter across clock domains for single clock
gen_rd_eop_cnt_sc : IF g_use_dual_clock=FALSE GENERATE
- wr_fifo_usedw <= rd_fifo_usedw;
- rd_eop_new <= '1';
+ rd_eop_new <= '1';
END GENERATE;
-- Set rd_eop_cnt outside generate statements to avoid Modelsim warning "Nonresolved signal 'rd_eop_cnt' may have multiple sources".
--
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