Explicitly set dplink_siso_arr(i).xon. Remove duplicate assignment of dp_sosi_arr and dp_sosi.

libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_v2.vhd

@@ -297,8 +297,6 @@ begin
   dplink_data <= dplink_sosi.data(c_jesd204b_rx_data_w - 1 downto 0);
   dplink_data_hi <= dplink_data(c_jesd204b_rx_data_w - 1 downto c_jesd204b_rx_framer_data_w);
   dplink_data_lo <= dplink_data(c_jesd204b_rx_framer_data_w - 1 downto 0);
-  dp_sosi_arr <= i_dp_sosi_arr;
-  dp_sosi <= i_dp_sosi_arr(0);
 
   -- The mm_rst resets the MM interface, but is also used to reset the JESD IP reset sequencer.
   -- Therefore a reset of mm_rst effectively resets the entire JESD IP.
@@ -487,6 +485,7 @@ begin
 
       -- Apply toggling ready control for cross 100 MHz rxlink_clk domain to 200MHz dp_clk domain
       -- u_dp_fifo_dc_arr FIFO.
+      dplink_siso_arr(i).xon <= '1';
       dplink_siso_arr(i).ready <= dp_ready;
     end generate;  -- gen_jesd204b_rx_channels : for I in 0 to g_nof_streams-1 generate
 

libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_v2.vhd

@@ -297,8 +297,6 @@ begin
   dplink_data <= dplink_sosi.data(c_jesd204b_rx_data_w - 1 downto 0);
   dplink_data_hi <= dplink_data(c_jesd204b_rx_data_w - 1 downto c_jesd204b_rx_framer_data_w);
   dplink_data_lo <= dplink_data(c_jesd204b_rx_framer_data_w - 1 downto 0);
-  dp_sosi_arr <= i_dp_sosi_arr;
-  dp_sosi <= i_dp_sosi_arr(0);
 
   -- The mm_rst resets the MM interface, but is also used to reset the JESD IP reset sequencer.
   -- Therefore a reset of mm_rst effectively resets the entire JESD IP.
@@ -487,6 +485,7 @@ begin
 
       -- Apply toggling ready control for cross 100 MHz rxlink_clk domain to 200MHz dp_clk domain
       -- u_dp_fifo_dc_arr FIFO.
+      dplink_siso_arr(i).xon <= '1';
       dplink_siso_arr(i).ready <= dp_ready;
     end generate;  -- gen_jesd204b_rx_channels : for I in 0 to g_nof_streams-1 generate