From 9d997f7ce349a47388d1945e29d884b3338e437d Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Tue, 13 Feb 2024 17:53:48 +0100
Subject: [PATCH] Explicitly set dplink_siso_arr(i).xon. Remove duplicate
assignment of dp_sosi_arr and dp_sosi.
---
.../ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_v2.vhd | 3 +--
.../ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_v2.vhd | 3 +--
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_v2.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_v2.vhd
index a13a82f0cd..4df0d51e3f 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_v2.vhd
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_v2.vhd
@@ -297,8 +297,6 @@ begin
dplink_data <= dplink_sosi.data(c_jesd204b_rx_data_w - 1 downto 0);
dplink_data_hi <= dplink_data(c_jesd204b_rx_data_w - 1 downto c_jesd204b_rx_framer_data_w);
dplink_data_lo <= dplink_data(c_jesd204b_rx_framer_data_w - 1 downto 0);
- dp_sosi_arr <= i_dp_sosi_arr;
- dp_sosi <= i_dp_sosi_arr(0);
-- The mm_rst resets the MM interface, but is also used to reset the JESD IP reset sequencer.
-- Therefore a reset of mm_rst effectively resets the entire JESD IP.
@@ -487,6 +485,7 @@ begin
-- Apply toggling ready control for cross 100 MHz rxlink_clk domain to 200MHz dp_clk domain
-- u_dp_fifo_dc_arr FIFO.
+ dplink_siso_arr(i).xon <= '1';
dplink_siso_arr(i).ready <= dp_ready;
end generate; -- gen_jesd204b_rx_channels : for I in 0 to g_nof_streams-1 generate
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_v2.vhd b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_v2.vhd
index 67de28d5d2..8512831a9a 100644
--- a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_v2.vhd
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_v2.vhd
@@ -297,8 +297,6 @@ begin
dplink_data <= dplink_sosi.data(c_jesd204b_rx_data_w - 1 downto 0);
dplink_data_hi <= dplink_data(c_jesd204b_rx_data_w - 1 downto c_jesd204b_rx_framer_data_w);
dplink_data_lo <= dplink_data(c_jesd204b_rx_framer_data_w - 1 downto 0);
- dp_sosi_arr <= i_dp_sosi_arr;
- dp_sosi <= i_dp_sosi_arr(0);
-- The mm_rst resets the MM interface, but is also used to reset the JESD IP reset sequencer.
-- Therefore a reset of mm_rst effectively resets the entire JESD IP.
@@ -487,6 +485,7 @@ begin
-- Apply toggling ready control for cross 100 MHz rxlink_clk domain to 200MHz dp_clk domain
-- u_dp_fifo_dc_arr FIFO.
+ dplink_siso_arr(i).xon <= '1';
dplink_siso_arr(i).ready <= dp_ready;
end generate; -- gen_jesd204b_rx_channels : for I in 0 to g_nof_streams-1 generate
--
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