Wait longer after reset release to acoount for DP - MM clock domain crossing for next MM read.

libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd

@@ -210,7 +210,7 @@ begin
   begin
     proc_common_wait_until_low(dp_clk, mm_rst);
     proc_common_wait_until_low(dp_clk, dp_rst);
-    proc_common_wait_some_cycles(mm_clk, 5);
+    proc_common_wait_some_cycles(mm_clk, 10);
 
     -- Read stream enable bits, default '1' after power up
     for I in 0 to c_nof_streams - 1 loop

libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd

@@ -102,7 +102,7 @@ begin
   begin
     proc_common_wait_until_low(dp_clk, mm_rst);
     proc_common_wait_until_low(dp_clk, dp_rst);
-    proc_common_wait_some_cycles(mm_clk, 5);
+    proc_common_wait_some_cycles(mm_clk, 10);
 
     ---------------------------------------------------------------------------
     -- Initial check