Use g_pipeline_ready_inp=true to ease timning closure.

libraries/base/ring/src/vhdl/ring_tx.vhd

@@ -164,7 +164,11 @@ begin
     g_data_w        => g_data_w,
     g_symbol_w      => g_symbol_w,
     g_hdr_field_arr => c_hdr_field_arr,
-    g_hdr_field_sel => c_hdr_field_sel
+    g_hdr_field_sel => c_hdr_field_sel,
+    g_pipeline_ready        => false,  -- unpack MM header
+    g_pipeline_ready_inp    => true,  -- use true to ease timning closure for ring_tx
+    g_capture_hdr_fields_in => false,  -- can use false when g_pipeline_ready_inp = true, because hdr_fields_in_reg captures hdr_fields_in
+    g_pipeline_ready_outp   => false  -- use false, because there is no src_in_arr flow control
   )
   port map (
     mm_rst => mm_rst,