From 58225f11af77518724c92ad4bc6ec8cca4905f35 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Thu, 20 Feb 2025 13:17:14 +0100
Subject: [PATCH] Wait longer after reset release to acoount for DP - MM clock
domain crossing for next MM read.
---
libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd | 2 +-
libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
index 7a612c135a..26a18faa8e 100644
--- a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
@@ -210,7 +210,7 @@ begin
begin
proc_common_wait_until_low(dp_clk, mm_rst);
proc_common_wait_until_low(dp_clk, dp_rst);
- proc_common_wait_some_cycles(mm_clk, 5);
+ proc_common_wait_some_cycles(mm_clk, 10);
-- Read stream enable bits, default '1' after power up
for I in 0 to c_nof_streams - 1 loop
diff --git a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
index f35a8bd290..a3565d0983 100644
--- a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
@@ -102,7 +102,7 @@ begin
begin
proc_common_wait_until_low(dp_clk, mm_rst);
proc_common_wait_until_low(dp_clk, dp_rst);
- proc_common_wait_some_cycles(mm_clk, 5);
+ proc_common_wait_some_cycles(mm_clk, 10);
---------------------------------------------------------------------------
-- Initial check
--
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