Merge branch 'master' of git.astron.nl:desp/hdl

boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node0/hdllib.cfg

@@ -31,6 +31,6 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_jesd_node0/qsys_unb2c_jesd/qsys_unb2c_jesd.qip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_jesd_node0/qsys_unb2c_jesd/qsys_unb2c_jesd.qip
 
 

boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node3/hdllib.cfg

@@ -31,6 +31,6 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_jesd_node3/qsys_unb2c_jesd/qsys_unb2c_jesd.qip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_jesd_node3/qsys_unb2c_jesd/qsys_unb2c_jesd.qip
 
 

boards/uniboard2c/designs/unb2c_minimal/hdllib.cfg

@@ -34,30 +34,30 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/qsys_unb2c_minimal/qsys_unb2c_minimal.qip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/qsys_unb2c_minimal/qsys_unb2c_minimal.qip
 
 quartus_ip_files =
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_avs_eth_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_clk_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_cpu_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_jtag_uart_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_onchip_memory2_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_pps.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_system_info.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_wdi.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_ctrl.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_data.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_epcs.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_temp_sens.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_voltage_sens.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_ctrl.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_data.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_remu.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_unb_pmbus.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_unb_sens.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_wdi.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_rom_system_info.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_timer_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_avs_eth_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_clk_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_cpu_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_jtag_uart_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_onchip_memory2_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_pps.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_system_info.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_wdi.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_ctrl.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_data.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_epcs.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_temp_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_voltage_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_ctrl.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_data.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_remu.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_unb_pmbus.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_unb_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_wdi.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_rom_system_info.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 

boards/uniboard2c/designs/unb2c_test/hdllib.cfg

@@ -37,63 +37,63 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/qsys_unb2c_test/qsys_unb2c_test.qip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/qsys_unb2c_test/qsys_unb2c_test.qip
 
 quartus_ip_files =
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_avs_eth_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_avs_eth_1.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_cpu_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_1gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_1gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_1GbE.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_1gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_1gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_1gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_1gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_ip_arria10_e1sg_phy_10gbase_r_24.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_unb_pmbus.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_unb_sens.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/reg_10gbase_r_24.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_avs_eth_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_avs_eth_1.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_cpu_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_1gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_1gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_1GbE.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_1gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_1gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_1gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_1gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_ip_arria10_e1sg_phy_10gbase_r_24.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_unb_pmbus.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_unb_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/reg_10gbase_r_24.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 

boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg

@@ -57,62 +57,62 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/qsys_unb2c_test/qsys_unb2c_test.qip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/qsys_unb2c_test/qsys_unb2c_test.qip
 
 quartus_ip_files =
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_avs_eth_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_avs_eth_1.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_clk_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_cpu_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_jtag_uart_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_onchip_memory2_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_pio_pps.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_pio_system_info.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_pio_wdi.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_bg_10gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_bg_1gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_data_buffer_1gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_bsn_monitor_1GbE.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_bg_10gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_bg_1gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_data_buffer_1gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_rx_seq_1gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_tx_seq_1gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_dpmm_ctrl.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_dpmm_data.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_epcs.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_eth10g_back0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_eth10g_back1.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_fpga_temp_sens.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_fpga_voltage_sens.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_io_ddr_MB_I.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_io_ddr_MB_II.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_ip_arria10_e1sg_phy_10gbase_r_24.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_mmdp_ctrl.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_mmdp_data.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_remu.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_tr_10GbE_back0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_tr_10GbE_back1.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_unb_pmbus.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_unb_sens.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_wdi.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_rom_system_info.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_timer_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/reg_10gbase_r_24.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_avs_eth_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_avs_eth_1.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_clk_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_cpu_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_jtag_uart_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_onchip_memory2_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_pio_pps.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_pio_system_info.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_pio_wdi.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_bg_10gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_bg_1gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_data_buffer_1gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_bsn_monitor_1GbE.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_bg_10gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_bg_1gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_data_buffer_1gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_rx_seq_1gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_tx_seq_1gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_dpmm_ctrl.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_dpmm_data.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_epcs.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_eth10g_back0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_eth10g_back1.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_fpga_temp_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_fpga_voltage_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_io_ddr_MB_I.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_io_ddr_MB_II.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_ip_arria10_e1sg_phy_10gbase_r_24.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_mmdp_ctrl.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_mmdp_data.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_remu.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_tr_10GbE_back0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_tr_10GbE_back1.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_unb_pmbus.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_unb_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_wdi.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_rom_system_info.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_timer_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/reg_10gbase_r_24.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2

init_hdl.sh

@@ -34,29 +34,42 @@ if [[ "$_" == "${0}" ]]; then
     exit
 fi
 
+# 
+if [ -z "${ALTERA_DIR}" ]; then
+    echo "== environ variable 'ALTERA_DIR' not set. =="
+    echo "should be in your .bashrc file."
+    echo "if it is your .bashrc file but not active run bash in your terminal"
+    exit
+fi
 
 # Figure out where this script is located and set environment variables accordingly
 export RADIOHDL_WORK="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
-# setup paths to build and config dir if not already defined by the user.
-export HDL_BUILD_DIR=${HDL_BUILD_DIR:-${RADIOHDL_WORK}/build}
 echo "HDL environment will be setup for" $RADIOHDL_WORK
 
+# setup paths to build and config dir if not already defined by the user.
+export ARGS_WORK=${RADIOHDL_WORK}
+export RADIOHDL_BUILD_DIR=${RADIOHDL_WORK}/build
+
 # modelsim uses this sim dir for testing
-export HDL_IOFILE_SIM_DIR=${HDL_IOFILE_SIM_DIR:-${HDL_BUILD_DIR}/sim}
-if ! [[ -e HDL_IOFILE_SIM_DIR ]]; then
+export HDL_IOFILE_SIM_DIR=${RADIOHDL_BUILD_DIR}/sim
+if [[ ! -d "${HDL_IOFILE_SIM_DIR}" ]]; then
     echo "make sim dir"
-    mkdir ${HDL_BUILD_DIR}/sim
+    mkdir "${HDL_IOFILE_SIM_DIR}"
+fi
+# if sim dir not empty, remove all files and dirs
+if [ ! -z "$(ls -A ${HDL_IOFILE_SIM_DIR})" ]; then
+    echo "clear sim dir"
+    rm -r ${HDL_IOFILE_SIM_DIR}/*
 fi
-rm -r ${HDL_BUILD_DIR}/sim/*
 
 # copy git user_componets.ipx into Altera dir's
 for altera_dir in ${ALTERA_DIR}/*; do
-    if [[ -d ${altera_dir} ]] &&  [[ ! -h ${altera_dir} ]]; then
+    if [[ -d "${altera_dir}" ]] &&  [[ ! -h "${altera_dir}" ]]; then
         echo "copy git hdl_user_components.ipx to ${altera_dir}/ip/altera/user_components.ipx"
         cp ${RADIOHDL_WORK}/hdl_user_components.ipx $altera_dir/ip/altera/user_components.ipx
     fi
 done
 
-if [ -z "${RADIOHDL_GEAR}" ]; then
+# source also radiohdl and args tools
 . ../radiohdl/init_radiohdl.sh
-fi
+. ../args/init_args.sh

libraries/base/diag/diag.peripheral.yaml

@@ -7,7 +7,7 @@ hdl_library_description: " This is the description for the bf package "
 
 peripherals:
   - 
-    peripheral_name:  diag_block_gen
+    peripheral_name:  block_gen
 
     parameters:
       - { name: g_nof_streams, value: 1 }
@@ -15,80 +15,73 @@ peripherals:
       - { name: g_buf_addr_w , value: 7 }
 
     slave_ports:
-      - 
         # actual hdl name: reg_diag_bg 
-        slave_prefix : DIAG 
-        slave_name   : BG  
-        slave_postfix: REG
+      - slave_name : ctrl  
         slave_type : REG
         fields:
-          - 
-            field_name    : Enable
+          - - field_name    : Enable
               width         : 2
               address_offset: 0x0
               field_description: |
                   "Bit 0: enable the block generator Bit 1: enable the blok generator on PPS"
-          - 
-            field_name    :     Samples_per_packet
+          
+          - - field_name    :     Samples_per_packet
               width         : 16
-            address_offset: 0x1
+              address_offset: 0x4
               reset_value   : 256
               field_description: |
                   "This REG specifies the number samples in a packet"
-          - 
-            field_name    :     Blocks_per_sync
+          
+          - - field_name    :     Blocks_per_sync
               width         : 16
-            address_offset: 0x2
+              address_offset: 0x8
               reset_value   : 781250
               field_description: |
                   "This REG specifies the number of packets in a sync period"
-          - 
-            field_name    :     Gapsize
+          
+          - - field_name    :     Gapsize
               width         : 16
-            address_offset: 0x3
+              address_offset: 0xc
               reset_value   : 80
               field_description: |
                   "This REG specifies the gap in number of clock cycles between two consecutive packets"
-          - 
-            field_name    :     Mem_low_address
+          
+          - - field_name    :     Mem_low_address
               width         : 8
-            address_offset: 0x4
+              address_offset: 0x10
               field_description: |
                   "This REG specifies the starting address for reading from the waveform memory"
-          - 
-            field_name    :     Mem_high_address
+          
+          - - field_name    :     Mem_high_address
               width         : 8
-            address_offset: 0x5
+              address_offset: 0x14
               field_description: |
                   "This REG specifies the last address to be read when from the waveform memory"
-          - 
-            field_name    :     BSN_init_low
-            address_offset: 0x6
+          
+          - - field_name    :     BSN_init_low
+              address_offset: 0x18
               field_description: |
                   "This REG specifies the lower(LSB) 32 bits [31:0] of the initialization BSN"
-          - 
-            field_name    :     BSN_init_high
-            address_offset: 0x7
+          
+          - - field_name    :     BSN_init_high
+              address_offset: 0x1c
               field_description: |
                   "This REG specifies the higher(MSB) 32 bits [63:32] of the initialization BSN"
-      - 
+        
         # actual hdl name: ram_diag_bg
-        slave_prefix : DIAG 
-        slave_name   : BG  
-        slave_postfix: RAM
+      - slave_name   : wave_data  
         number_of_slaves: g_nof_streams
         slave_type      : RAM
         fields:
-          - 
-            field_name: diag_bg
+          - - field_name: diag_bg
               width: g_buf_dat_w
               number_of_fields: 2**g_buf_addr_w
               field_description  : |
                   "Contains the Waveform data for the data-streams to be send"
     peripheral_description: |
         "Block generator"
-  - 
-    peripheral_name: diag_data_buffer
+  
+  - peripheral_name: data_buffer
 
     parameters:
       -  { name: g_nof_streams , value: 1 }
@@ -96,56 +89,48 @@ peripherals:
       -  { name: g_buf_nof_data, value: 1024 }
     
     slave_ports:
-      - 
         # actual hdl name: reg_diag_data_buffer
-        slave_prefix : DIAG 
-        slave_name   : DATA_BUFFER  
-        slave_postfix: REG
+      - slave_name   : status  
         slave_type   : REG
         fields:
-          - 
-            field_name    : Sync_cnt
+          - - field_name    : Sync_cnt
               access_mode   : RO
               address_offset: 0x0
               field_description: |
                   "Sync_cnt contains the nof times the buffer (ST) has received a sync pulse since the last MM read
                   (cleared when the last data word from the buffer is read)"
-          - 
-            field_name    : Word_cnt
+          
+          - - field_name    : Word_cnt
               access_mode   : RO
-            address_offset: 0x1
+              address_offset: 0x4
               field_description: |
                   "Word_cnt indicates the number of word currently (ST) written in the buffer. Cleared on (ST) re-write of buffer."
-          - 
-            field_name    : Valid_cnt_arm_ena
-            address_offset: 0x2
+          
+          - - field_name    : Valid_cnt_arm_ena
+              address_offset: 0x8
               field_description: |
                   "Valid_cnt contains the number of valid cycles since the last sync pulse. Cleared on every sync pulse.
                   Arm_enable: Write to this REG to arm the system.
                   After the system is armed the next syn pulse will trigger the acquisition of data."
-          - 
-            field_name    : Reg_sync_delay
-            address_offset: 0x3
+          
+          - - field_name    : Reg_sync_delay
+              address_offset: 0xc
               field_description: |
                   "Reg_sync_delay contains the number of valid cycles to delay/wait after an armed-syncpulse,
                   before the data is written to the databuffer."
-          - 
-            field_name    : Version
+          
+          - - field_name    : Version
               access_mode   : RO
-            address_offset: 0x7
+              address_offset: 0x1c
               field_description: |
                   "Version contains the version number of the databuffer peripheral."
         slave_description: ""
-      - 
         # actual hdl name: ram_diag_data_buffer
-        slave_prefix : DIAG 
-        slave_name   : DATA_BUFFER  
-        slave_postfix: RAM    
+      - slave_name   : data  
         number_of_slaves: g_nof_streams
         slave_type      : RAM
         fields:
-          - 
-            field_name    : ram
+          - - field_name    : ram
               width         : g_data_w
               number_of_fields: g_buf_nof_data
               field_description: |

libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg

@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
 hdl_lib_technology = ip_stratixiv
 
 synth_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_dp_offload/sopc_unb1_dp_offload.vhd
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_dp_offload/sopc_unb1_dp_offload.vhd
     src/vhdl/mmm_unb1_dp_offload.vhd
     src/vhdl/unb1_dp_offload.vhd
 
@@ -35,7 +35,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_dp_offload/sopc_unb1_dp_offload.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_dp_offload/sopc_unb1_dp_offload.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_SOPC
 

libraries/base/dp/dp.peripheral.yaml

@@ -6,23 +6,18 @@ hdl_library_name       : dp
 hdl_library_description: " This is the description for the dp package "
 
 peripherals:
-  - 
-    peripheral_name: dp_bsn_align
+  - peripheral_name: bsn
 
     parameters:
         - { name: g_nof_input, value : 2 }
 
     slave_ports:
-      - 
         # actual hdl name: reg_dp_bsn_align
-        slave_prefix : DP 
-        slave_name   : BSN_ALIGN  
-        slave_postfix: REG
+      - slave_name   : ALIGN
         number_of_slaves: g_nof_input
         slave_type      : REG
         fields:
-          - 
-            field_name       : Enable
+          - - field_name       : Enable
               width            : 1
               address_offset   : 0x0
               field_description: |
@@ -32,35 +27,30 @@ peripherals:
 
     peripheral_description: "This is the BSN aligner"
 
-  - 
-    peripheral_name: dp_fifo_fill
+  - peripheral_name: fifo
     parameters:
         - { name : g_nof_streams, value: 3 }
 
     slave_ports:
-      - 
         # actual hdl name: reg_dp_fifo_fill
-        slave_prefix : DP 
-        slave_name   : FIFO_FILL  
-        slave_postfix: REG
+      - slave_name   : fill_status
         number_of_slaves: g_nof_streams
         slave_type      : REG
         fields:
-          - 
-            field_name       : fifo_used_words
+          - - field_name       : fifo_used_words
               access_mode      : RO
               address_offset   : 0x0
               field_description: "Register reflects the currently used nof words on the fifo."
-          - 
-            field_name       : fifo_status
+
+          - - field_name       : fifo_status
               width            : 2
               access_mode      : RO
-            address_offset   : 0x1
+              address_offset   : 0x4
               field_description: "Bit 0: fifo_read_empty Bit 1: fifo_wr_full."
-          - 
-            field_name       : max_fifo_used_words
+
+          - - field_name       : max_fifo_used_words
               access_mode      : RO
-            address_offset   : 0x2
+              address_offset   : 0x8
               field_description: |
                   "Register contains the maximum number of words that have been in the fifo.
                     Will be cleared after it has been read."

libraries/dsp/bf/bf.peripheral.yaml

@@ -6,7 +6,7 @@ hdl_library_name       : bf
 hdl_library_description: " This is the description for the bf package "
 
 peripherals:
-  - peripheral_name: bf_unit
+  - peripheral_name: bf
  
     parameters:
       - { name: g_bf.in_weights_w            , value: 16 }
@@ -17,16 +17,12 @@ peripherals:
       - { name: c_nof_signal_paths_per_stream, value: g_bf.nof_signal_paths / g_bf.nof_input_streams }
 
     slave_ports:
-      - 
         # ram_bf_weights
-        slave_prefix : BF 
-        slave_name   : WEIGHTS 
-        slave_postfix: RAM
+      - slave_name   : WEIGHTS 
         number_of_slaves: g_bf.nof_weights
         slave_type: RAM
         fields:
-          - 
-            field_name    : bf_weights 
+          - - field_name    : bf_weights 
               width         : g_bf.in_weights_w * c_nof_complex
 
               number_of_fields: g_bf.nof_signal_paths
@@ -36,16 +32,12 @@ peripherals:
         slave_discription: >
                 " "
     
-      - 
         # ram_ss_ss_wide
-        slave_prefix : BF 
-        slave_name   : SS_SS_WIDE
-        slave_postfix: RAM    
+      - slave_name   : SS_SS_WIDE
         number_of_slaves: g_bf.nof_weights
         slave_type: RAM
         fields:
-          - 
-            field_name      : ss_ss_wide
+          - - field_name      : ss_ss_wide
               width           : 32
               number_of_fields: g_bf.nof_subbands * g_bf.nof_input_streams * c_nof_signal_paths_per_stream  # 16*4=64, nof_input_streams*nof_signal_paths_per_stream
               field_description: |
@@ -53,16 +45,12 @@ peripherals:
         slave_discription: >
             " "
       
-      - 
         # ram_st_sst_bf
-        slave_prefix : BF 
-        slave_name   : ST_SST
-        slave_postfix: RAM
+      - slave_name   : ST_SST
         number_of_slaves: g_bf.nof_weights
         slave_type: RAM 
         fields:
-          - 
-            field_name      : st_sst_bf
+          - - field_name      : st_sst_bf
               width           : 56
               number_of_fields: 512
               access_mode : RO   
@@ -70,17 +58,14 @@ peripherals:
                   "Contains the weights.
                   The real and the imaginary parts are concatenated: W_real in Lower part. W_imag in Higher part."
         slave_discription: >
+          " "
       
-      - 
         # reg_st_sst_bf
-        slave_prefix : BF 
-        slave_name   : ST_SST
-        slave_postfix: REG
+      - slave_name   : treshold
         number_of_slaves: 1
         slave_type: REG
         fields:
-          - 
-            field_name    : treshold
+          - - field_name    : treshold
               address_offset: 0x0
               field_description  : |
                   "When the treshold register is set to 0 the statistics will be auto-correlations.

libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg

@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
 hdl_lib_technology = ip_stratixiv
 
 synth_files =   
-    $HDL_BUILD_DIR/unb1/quartus/unb1_fn_bf/sopc_unb1_fn_bf.vhd
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_fn_bf/sopc_unb1_fn_bf.vhd
     src/vhdl/mmm_unb1_fn_bf.vhd
     src/vhdl/node_unb1_fn_bf.vhd    
     src/vhdl/unb1_fn_bf.vhd
@@ -31,7 +31,7 @@ quartus_tcl_files =
     quartus/unb1_fn_bf_pins.tcl
     
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_fn_bf/sopc_unb1_fn_bf.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_fn_bf/sopc_unb1_fn_bf.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_SOPC

libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg

@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
 hdl_lib_technology = ip_stratixiv
 
 synth_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_correlator/qsys_unb1_correlator/synthesis/qsys_unb1_correlator.v
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_correlator/qsys_unb1_correlator/synthesis/qsys_unb1_correlator.v
     src/vhdl/mmm_unb1_correlator.vhd
     src/vhdl/unb1_correlator.vhd
     
@@ -31,7 +31,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_correlator/qsys_unb1_correlator/synthesis/qsys_unb1_correlator.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_correlator/qsys_unb1_correlator/synthesis/qsys_unb1_correlator.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
 

libraries/dsp/fringe_stop/fringe_stop.peripheral.yaml

@@ -6,8 +6,7 @@ hdl_library_name       : fringe_stop
 hdl_library_description: " This is the description for the finge_stop library "
 
 peripherals:
-  - 
-    peripheral_name: fringe_stop_unit
+  - peripheral_name: fringe_stop
 
     parameters:
       - { name: g_nof_channels,  value: 256 }
@@ -15,30 +14,22 @@ peripherals:
       - { name: g_fs_step_w   ,  value: 17 }
     
     slave_ports:
-      - 
         # actual hdl name: ram_fringe_stop_step
-        slave_prefix : FRINGE_STOP 
-        slave_name   : STEP  
-        slave_postfix: RAM
+      - slave_name   : STEP
         slave_type   : RAM
         fields:
-          - 
-            field_name  : fringe_stop_step
+          - - field_name  : fringe_stop_step
               width: g_fs_step_w
               number_of_fields: g_nof_channels
               field_description: |
                   "Contains the step size for all nof_channels channels."
         slave_discription: " "
 
-      - 
         # actual hdl name: fringe_stop_offset
-        slave_prefix : FRINGE_STOP 
-        slave_name   : OFFSET  
-        slave_postfix: RAM
+      - slave_name   : STOP_OFFSET  
         slave_type   : RAM
         fields:
-          - 
-            field_name:  fringe_stop_offset
+          - - field_name:  fringe_stop_offset
               width: g_fs_offset_w
               number_of_fields: g_nof_channels
               field_description: |

libraries/io/ddr3/hdllib.cfg

@@ -28,9 +28,9 @@ regression_test_vhdl =
 
 [modelsim_project_file]
 modelsim_copy_files =
-    $HDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_AC_ROM.hex .
-    $HDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_inst_ROM.hex .
-    $HDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_sequencer_mem.hex .
+    $RADIOHDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_AC_ROM.hex .
+    $RADIOHDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_inst_ROM.hex .
+    $RADIOHDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_sequencer_mem.hex .
 
 modelsim_compile_ip_files =
      $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl

libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd

@@ -121,7 +121,7 @@ PACKAGE ddr3_pkg IS
 
   CONSTANT c_ddr3_seq : t_ddr3_seq := (64, 1, 16, 4, 0, 5);  
   
-  -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.v
+  -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.v
   COMPONENT ip_stratixiv_ddr3_uphy_4g_800_master IS
   PORT (
     pll_ref_clk                : IN    STD_LOGIC;                       --  pll_ref_clk.clk
@@ -173,7 +173,7 @@ PACKAGE ddr3_pkg IS
   );
   END COMPONENT;
 
-  -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.v
+  -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.v
   -- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
   COMPONENT ip_stratixiv_ddr3_uphy_4g_800_slave IS
   PORT (

libraries/io/epcs/epcs.peripheral.yaml

@@ -9,114 +9,89 @@ peripherals:
  
   # epcs_reg
   - 
-    peripheral_name: epcs_reg
+    peripheral_name: epcs
 
     parameters:
       - {name: "g_sim_flash_model", value: TRUE} 
 
     slave_ports:
-      - 
         # actual hdl name: epcs_reg
-        slave_prefix : EPCS
-        slave_name   : EPCS
-        slave_postfix: REG
+      - slave_name   : EPCS
         slave_type   : REG
         fields:
-          -
-            field_name    : addr
+          - - field_name    : addr
               width         : 24
               access_mode   : WO
               address_offset: 0x0
               field_description: " address to write to or read from "
         
-          -
-            field_name    : rden
+          - - field_name    : rden
               width         : 1
               access_mode   : WO
-            address_offset: 0x1
+              address_offset: 0x4
               field_description: " Read enable bit "
         
-          -
-            field_name    : read_bit
+          - - field_name    : read_bit
               width         : 1
               access_mode   : WO
               side_effect   : PW
-            address_offset: 0x2
+              address_offset: 0x8
               field_description: " Read bit "
 
-          -
-            field_name    : write_bit
+          - - field_name    : write_bit
               width         : 1
               access_mode   : WO
               side_effect   : PW
-            address_offset: 0x3
+              address_offset: 0xc
               field_description: " Write bit "
 
-          -
-            field_name    : sector_erase
+          - - field_name    : sector_erase
               width         : 1
               access_mode   : WO
-            address_offset: 0x4
+              address_offset: 0x10
               field_description: " Sector erase bit "
 
-          -
-            field_name    : busy
+          - - field_name    : busy
               width         : 1
               access_mode   : RO
-            address_offset: 0x5
+              address_offset: 0x14
               field_description: " busy "
 
         slave_description:  " Read and write access to flash "
 
       # actual hdl name: mms_dp_fifo_to_mm
-      - 
-        slave_prefix : EPCS
-        slave_name   : DPMM_CTRL
-        slave_postfix: REG
+      - slave_name   : DPMM_CTRL
         slave_type   : REG
         fields:
-          -
-            field_name    : ctrl
+          - - field_name    : ctrl
               width         : 32
               access_mode   : RW
               address_offset: 0x0
               field_description: "  "
       
-      -   
-        slave_prefix : EPCS
-        slave_name   : DPMM_DATA
-        slave_postfix: REG
+      - slave_name   : DPMM_DATA
         slave_type   : REG
         fields:
-          -
-            field_name    : data
+          - - field_name    : data
               width         : 32
               access_mode   : RW
               address_offset: 0x0
               field_description: "  "
 
       # actual hdl name: mms_dp_fifo_from_mm
-      - 
-        slave_prefix : EPCS
-        slave_name   : MMDP_CTRL
-        slave_postfix: REG
+      - slave_name   : MMDP_CTRL
         slave_type   : REG
         fields:
-          -
-            field_name    : ctrl
+          - - field_name    : ctrl
               width         : 32
               access_mode   : RW
               address_offset: 0x0
               field_description: "  "
       
-      -  
-        slave_prefix : EPCS
-        slave_name   : MMDP_DATA
-        slave_postfix: REG
+      - slave_name   : MMDP_DATA
         slave_type   : REG
         fields:
-          -
-            field_name    : data
+          - - field_name    : data
               width         : 32
               access_mode   : RW
               address_offset: 0x0

libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg

@@ -26,7 +26,7 @@ quartus_qsf_files =
 quartus_tcl_files =
     quartus/unb1_eth_10g_pins.tcl
     
-quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/unb1_eth_10g/qsys_unb1_eth_10g/synthesis/qsys_unb1_eth_10g.qip
+quartus_qip_files = $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_eth_10g/qsys_unb1_eth_10g/synthesis/qsys_unb1_eth_10g.qip
 
 quartus_sdc_files =
     $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc

libraries/io/eth/eth.peripheral.yaml

@@ -15,44 +15,33 @@ peripherals:
         #g_ETH_PHY   : "LVDS" 
 
     slave_ports:
-      - 
       # actual hdl name: reg_tse
-        slave_prefix : ETH 
-        slave_name   : TSE  
-        slave_postfix: REG
+      - slave_name   : TSE  
         slave_type   : REG
         fields:
-          - 
-            field_name      : status
+          - - field_name      : status
               access_mode     : RO
               address_offset  : 0x0
               number_of_fields: 1024
-            field_description: | 
-                " reg tse "
+              field_description: "reg tse"
         slave_description: " "
-      - 
+        
       # actual hdl name: reg
-        slave_prefix : ETH 
-        slave_name   : REG  
-        slave_postfix: REG
+      - slave_name   : ETH
         slave_type   : REG   
         fields:
-          - 
-            field_name      : status
+          - - field_name      : status
               access_mode     : RO
               address_offset  : 0x0
-            number_of_fields: 11
+              number_of_fields: 12
               field_description: "reg registers"
         slave_description: " "
-      - 
+        
       # actual hdl name: ram
-        slave_prefix : ETH 
-        slave_name   : RAM  
-        slave_postfix: RAM
+      - slave_name   : ETH  
         slave_type   : RAM
         fields:
-          - 
-            field_name      : ram
+          - - field_name      : ram
               number_of_fields: c_eth_ram_nof_words
               field_description: |
                   "Contains the Waveform data for the data-streams to be send"

libraries/io/eth/hdllib.cfg

@@ -45,10 +45,10 @@ regression_test_vhdl =
 
 [modelsim_project_file]
 modelsim_copy_files = 
-    #src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $HDL_BUILD_DIR/<buildset_name>/avs2_eth_coe_hw.tcl
+    #src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $RADIOHDL_BUILD_DIR/<buildset_name>/avs2_eth_coe_hw.tcl
     src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
 
 [quartus_project_file]
 quartus_copy_files =
-    #src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $HDL_BUILD_DIR/<buildset_name>/avs2_eth_coe_hw.tcl
+    #src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $RADIOHDL_BUILD_DIR/<buildset_name>/avs2_eth_coe_hw.tcl
     src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
\ No newline at end of file

libraries/io/ppsh/ppsh.peripheral.yaml

@@ -13,21 +13,17 @@ peripherals:
       - { name: g_st_clk_freq,        value: 200 * 10**6 }
     
     slave_ports:
-      - 
         # actual hdl name: reg_ppsh
-        slave_prefix : PPSH 
-        slave_name   : PPSH  
-        slave_postfix: REG
+      - slave_name   : PPSH 
         slave_type   : REG
         fields:
-          - 
-            field_name    : status
+          - - field_name    : status
               access_mode   : RO
               address_offset: 0x0
               field_description: " ppsh status "
-          - 
-            field_name    : control
-            address_offset: 0x1
+          
+          - - field_name    : control
+              address_offset: 0x4
               field_description: " ppsh control "
         slave_discription: " "