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Commit 0287cfbb authored by Eric Kooistra's avatar Eric Kooistra
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Worked on ring and workpackage planning, minor edits in other txt files.

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......@@ -49,9 +49,16 @@ M&C:
* Subband correlator
*******************************************************************************
First the local crosslets are correlated with themselves and then
the local crosslets are kept in a barrel shifter, such that they can also be correlated with the
remote crosslets that arrive in the packets.
- Subband select of N_crosslets local crosslets per signal input
- Interleave local crosslets from S_pn = 12 signal inputs
- XC ring
- XC dispatcher of local and remote crosslets
- X_sq correlator cell with N_crosslets * S_pn*S_pn visibilities and N_valid, N_flagged counts
- M&C:
. Subband select
. XC ring
. X_sq
*******************************************************************************
......
......@@ -23,7 +23,7 @@ Definitions
Introduction
- Context
. ADD fig 3.1-1 (E)ICD and L3 PBS overview
- Scope
- Scope and purpose
- Document overview
Station overview
......
......@@ -10,7 +10,7 @@ v1 v2
10 . - Ethernet access (OSI 1-4)
10 20 - Ring access
Applications:
Application:
15 . - ADC ingress and time stamp
20 10 - Subband filterbank (critically sampled)
0 30 - Subband filterbank (oversampled)
......@@ -51,7 +51,7 @@ v3 :
20 - Ring access
10 - 10GbE access (OSI 1-4)
Applications:
Application:
15 - ADC input and time stamp
10 - Subband filterbank (critically sampled)
20 - Subband correlator
......@@ -73,3 +73,147 @@ All:
No oversampled filterbank:
20 + 5 + 10 + 20 + 20 + 10 + 15 + 10 + 20 + 10 + 25 + 20 + 20 + 0 + 10 + 5 + 5 = 225
*******************************************************************************
* SDP Workpackage (UniBoard2 HW + FW)
*******************************************************************************
Firmware FPGA images:
- the SDP has one main firmware design unb2c_sdp,
- the integrated design of SDP is revision unb2c_sdp_station,
- per task there are revisions of unb2c_sdp that contain subsets of the SDP functionality,
Deliverables (D): items that are needed for a milestone
Milestones (M) : 'cake moments' when you demonstrate deliverables
- integration passed
- review passed
Tasks:
INFRASTRUCTURE UniBoard2:
weeks nr task
20 1) Maintain firmware development environment
- using GIT
- using RadioHDL
- updating existing VHDL library components
D=> Operational firmware development environment
D=> VHDL libraries verified in simulation
2) UniBoard2 board and test firmware
- unb2c board HW
D=> unb2c board detailed design document
D=> unb2c board schematic
D=> unb2c board layout
M=> unb2c board detailed design document review (unb2b modifications)
M=> unb2c board schematic review
M=> unb2c board layout review (production ready)
M=> unb2c board lab validation using JTAG, unb2c_test designs OK
M=> unb2c board production validation using JTAG, unb2c_minimal_gmi OK
5 - unb2c FPGA pinning design
10 - unb2c FPGA interface test designs
D=> unb2c_test design revisions (1GbE, 10GbE, DDR4, flash, ADC)
D=> unb2c_test_adc (read ADC samples from multiple inputs)
20 3) UniBoard2 board support package (BSP)
- M&C by SCU via Gemini protocol
- M&C interface definition and generation using ARGS (doc, C, HDL)
D=> Gemini board for SCU M&C tests
D=> unb2c_minimal_gmi (1GbE, flash)
M=> unb2c_minimal_gmi validated using M&C by SCU (read design name)
INFRASTRUCTURE SDP:
10 4) Network access via 10GbE
- Ethernet MAC, UDP/IPv4, ARP, ping
D=> 10GbE HDL component including support for UDP/IPv4, ARP, ping
D=> unb2c_10GbE
M=> unb2c_10GbE validated using data capture on PC and ping
20 5) Ring access using test data and BSN monitor
D=> unb2c_ring_combiner for BF
D=> unb2c_ring_multicast for XC
D=> unb2c_ring_endcast for SO, TB
M=> unb2c_ring revisions verified in simulation
M=> unb2c_ring revisions validated on hardware using M&C on SCU
APPLICATION SDP documents:
6) Required documents
D=> Detailed design document of SDP firmware
D=> L1 ICD-11109 SDP-CEP: beamlet data protocol
D=> L1 ICD-11109 SDP-CEP: transient data protocol
D=> L2 ICD-11211 SC-SDP: FW register map and register definitions
D=> L2 ICD-11211 SC-SDP: UniBoard2 hardware M&C
D=> L2 ICD-11207 RCU2S-SDP: ADC interface
D=> L2 ICD-11209 STF-SDP: Time and frequency interface
D=> L2 ICD-11218 SDP-STCA: Subrack interface
M=> SDP detailed design and interface documents ready for DDR
M=> SDP detailed design and interface documents updated for CDR
D=> SDP firmware verification and maintenance document
M=> SDP all documents finished
APPLICATION single node:
weeks nr task
15 7) ADC input and timestamp (RCU2 interface)
==> unb2c_sdp_adc_capture, read ADC or WG samples from databuffer via M&C
==> unb2c_sdp_station (ADC)
M=> SDP ready for CDR
All major technical UniBoard2 hardware and SDP firmware risks are mitigated (by design and
based on validation with at least two UniBoard2 using JTAG, unb2c_minimal_gmi, unb2c_ring,
and unb2c_sdp_adc_capture).
10 8) Subband filterbank (Fsub)
==> unb2c_sdp_filterbank to read SST via M&C
==> unb2c_sdp_station (ADC + SST)
APPLICATION multi node:
weeks nr task
20 9) Subband correlator (XC)
==> unb2c_sdp_correlator_one_node, read XST via M&C and create ACM for one node
==> unb2c_sdp_correlator_multi_node, read XST via M&C and use ring to create complete ACM
==> unb2c_sdp_station (ADC + SST + XST)
APPLICATION multi node / network output:
weeks nr task
10 10) Beamformer (BF)
==> unb2c_sdp_beamformer_bst_one_node, read BST via M&C
==> unb2c_sdp_beamformer_output_one_input, output to CEP for one input from one node
==> unb2c_sdp_beamformer_output_one_node, output to CEP and sum one node
==> unb2c_sdp_beamformer_output_multi_node, output to CEP and use ring to sum nodes
==> unb2c_sdp_station (ADC + SST + XST + BST + BF output)
==> detailed design doc
25 11) Transient buffer (TB)
==> unb2c_sdp_transient_buffer revisions (ADC + SST + TB readout, M&C access DDR4)
==> unb2c_sdp_station (ADC + SST + XST + BST + BF output + TB readout)
==> detailed design doc
20 12) Transient detection (TD)
==> unb2c_sdp_transient_buffer revisions (ADC + TD event)
==> unb2c_sdp_station (ADC + SST + XST + BST + BF output + TB readout + TD event)
==> detailed design doc
20 13) Subband offload (SO) for AARTFAAC2.0
==> unb2c_sdp_subband_offload revisions (ADC + SST + SO, one node, all nodes via ring)
==> unb2c_sdp_station (ADC + SST + XST + BST + BF output + TB readout + TD event + SO)
==> detailed design doc
INTEGRATION:
weeks nr task
20 14) Station integration tests (using unb2c_sdp_station)
- Laboratory tests
- Technical commissioning Dwingeloo Test Station ("Huisje West")
- Technical commissioning Prototype Test Station
- Technical commissioning Pre-production Test Station
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......@@ -2,21 +2,22 @@
* Fixed Station BSN grid and the PPS grid
*******************************************************************************
The Station needs an external trigger to align all ADCs in the RCU2S and all FPGA procesing nodes in the SDP.
For this trigger a pulse from the pulse per second (PPS) is used. The PPS is aliged to the top of second of the
UTC time of day (ToD). The PPS is a hardware trigger that is available within the entire SDP at sample clock
cycle accuracy. Thanks to the Timing Distributor (TD) the PPS trigger is also available as hardware trigger in
all Stations. Thanks to the TD the PPS is aligned to UTC ToD, and the ToD is available to the Telescope Manager
(TM) in LOFAR2.0 and to Station Control in each Station. The TM controls, via Station Control, which PPS pulse
is used to start SDP. The PPS is identified by a Seconds Sequence Number (SSN) that counts PPS since a certain
The Station needs an external trigger to align all ADCs in the RCU2S and all FPGA procesing nodes
in the SDP. For this trigger a pulse from the pulse per second (PPS) is used. The PPS is aliged to
the top of second of the UTC time of day (ToD). The PPS is a hardware trigger that is available
within the entire SDP at sample clock cycle accuracy. Thanks to the Timing Distributor (TD) the
PPS trigger is also available as hardware trigger in all Stations. Thanks to the TD the PPS is
aligned to UTC ToD, and the ToD is available to the Telescope Manager (TM) in LOFAR2.0 and to
Station Control in each Station. The TM controls, via Station Control, which PPS pulse is used to
start SDP. The PPS is identified by a Seconds Sequence Number (SSN) that counts PPS since a certain
date in the past, e.g. t_epoch = 1 jan 1970, but some other fixed date is possible too.
The SDP processes the data in blocks of ADC samples that are identified by a Station block sequence number
(BSN). The Station BSN time grid should be fixed, so independent of when the data processing starts. Therefore
the Station BSN counts blocks since the same t_epoch as the SSN, so the t_epoch defines the common reference
moment in history for the Station BSN grid and for the PPS grid. The PPS grid does not necessarily always
coincide with the Station BSN grid. The BSN period determines whether the Station BSN can start exactly at an
PPS or not.
The SDP processes the data in blocks of ADC samples that are identified by a Station block sequence
number (BSN). The Station BSN time grid should be fixed, so independent of when the data processing
starts. Therefore the Station BSN counts blocks since the same t_epoch as the SSN, so the t_epoch
defines the common reference moment in history for the Station BSN grid and for the PPS grid. The
PPS grid does not necessarily always coincide with the Station BSN grid. The BSN period determines
whether the Station BSN can start exactly at an PPS or not.
The processing of the ADC inputs in SDP is done by multiple FPGAs in parallel. Each FPGA has a BSN source that
creates the Station BSN grid. The BSN source is the wall clock of the FPGA. To be able to start the data
......@@ -371,6 +372,28 @@ Note:
Key ideas:
- Use Ethernet CRC and DP CRC to ensure detection of packet errors and to ensure error free blocks
within FPGA firmware
- Within SDP firmware the BSN at sync can be obtained from the local BSN source and subsequent
BSN can be derived by counting blocks:
. Use filler blocks to replace lost packets, to maintain BSN count within FPGA firmware
. Use local BSN source in FPGA and pass on sync within SDP firmware to know the BSN in the firmware.
RCU2 Subband Ring
PFB
data data
data ------> BSN --------> Move, -------> Packet
PPSH ------> source sync DSP sync encoding
BSN .........> BSN ring
Ring BF, XC
data data data
Packet --------> Validate --> Validate --> BSN --------> Move, --------> Packet
decoding sync CRC BSN aligner sync DSP sync encoding
ring BSN .......................................................> BSN output
......@@ -386,9 +409,7 @@ Design decisions:
but in simulation it can be much less.
- Use central UTC timestamp at PPS initialized by M&C and incremented by SDP firmware for the SSN
per FPGA.
- Use 32 bit SSN to fit UTC in seconds for 136 years since 1970
- Use local BSN that counts data blocks within a sync interval, so it restarts at 0 at the internal sync
- Within SDP transport the sync and the local BSN. The sync is transported via the MSbit of the local BSN.
At the sync transport the 31 bit SSN instead of local BSN 0, but only for monitoring purposes.
- Derive 64 bit UTC timestamp in units of T_sub in SDP firmware and use this for data output to CEP
- Use 64 bit continuous BSN that counts subband periods since 1970
- Within SDP transport the sync and the BSN. The sync is transported via the MSbit of the BSN.
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