hdllib.cfg

hdl_lib_name = ddr3
hdl_library_clause_name = ddr3_lib
hdl_lib_uses_synth = common dp diag diagnostics ss tech_ddr 
hdl_lib_uses_sim = 
hdl_lib_technology =

synth_files =
    src/vhdl/ddr3_pkg.vhd
    src/vhdl/ddr3_reg.vhd
    src/vhdl/ddr3_seq.vhd
    src/vhdl/ddr3_driver.vhd
    src/vhdl/ddr3_flush_ctrl.vhd
    src/vhdl/ddr3.vhd
    src/vhdl/ddr3_transpose.vhd
    src/vhdl/mms_ddr3.vhd
    src/vhdl/mms_ddr3_capture.vhd
    src/vhdl/seq_ddr3.vhd

test_bench_files = 
    tb/vhdl/tb_ddr3.vhd
    tb/vhdl/tb_mms_ddr3.vhd
    tb/vhdl/tb_seq_ddr3.vhd
    tb/vhdl/tb_ddr3_transpose.vhd

regression_test_vhdl = 
    #tb/vhdl/tb_ddr3.vhd   -- tb fails, ddr3 library may be obsolete, better use io_ddr


[modelsim_project_file]
modelsim_copy_files =
    $RADIOHDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_AC_ROM.hex .
    $RADIOHDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_inst_ROM.hex .
    $RADIOHDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_sequencer_mem.hex .

modelsim_compile_ip_files =
     $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
     #$RADIOHDL_WORK/libraries/io/ddr3/src/tcl/compile_ip.tcl


[quartus_project_file]