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Commit 40f67f29 authored by Jonathan Hargreaves's avatar Jonathan Hargreaves
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Merge branch 'master' of git.astron.nl:desp/hdl

parents 32fc5d38 0287cfbb
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with 119 additions and 164 deletions
......@@ -32,7 +32,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_minimal_sopc/sopc_unb1_minimal.qip
$RADIOHDL_BUILD_DIR/unb1/quartus/unb1_minimal_sopc/sopc_unb1_minimal.qip
nios2_app_userflags = -DCOMPILE_FOR_SOPC
......@@ -9,64 +9,42 @@ fpga_description: |
"unb1_minimal system for sopc"
peripherals:
- peripheral_name: rom_system_info
subsystem_name : ''
slave_port_names:
- rom_system_info
parameters:
- { name: lock_base_address, value: 0x1000 }
- peripheral_name: reg_system_info
subsystem_name : ''
- peripheral_name: unb1_board/system
slave_port_names:
- pio_system_info
parameters:
- { name: lock_base_address, value: 0x0 }
- peripheral_name: ctrl_unb1_board
subsystem_name : ''
- peripheral_name: unb1_board/rom_system
slave_port_names:
- rom_system_info
- peripheral_name: unb1_board/ctrl
slave_port_names:
- pio_wdi
- peripheral_name: unb1_board_wdi_reg
subsystem_name : ''
- peripheral_name: unb1_board/wdi
slave_port_names:
- reg_wdi
- peripheral_name: eth1g
subsystem_name : ''
- peripheral_name: eth/eth1g
slave_port_names:
- avs_eth_0_mms_tse
- avs_eth_0_mms_reg
- avs_eth_0_mms_ram
- peripheral_name: ppsh
subsystem_name : ''
- avs_eth_0_tse
- avs_eth_0_reg
- avs_eth_0_ram
- peripheral_name: ppsh/ppsh
slave_port_names:
- pio_pps
- peripheral_name: epcs_reg
subsystem_name : ''
- peripheral_name: epcs/epcs
slave_port_names:
- reg_epcs
- reg_mmdp_ctrl
- reg_mmdp_data
- reg_dpmm_ctrl
- reg_dpmm_data
parameters:
- reg_mmdp_ctrl
- reg_mmdp_data
parameter_overrides:
- { name : g_sim_flash_model, value: FALSE }
- peripheral_name: remu_reg
subsystem_name : ''
- peripheral_name: remu/remu
slave_port_names:
- reg_remu
- peripheral_name: unb1_board_sens_reg
subsystem_name : ''
- peripheral_name: unb1_board/sens
slave_port_names:
- reg_unb_sens
parameters:
parameter_overrides:
- { name : g_sim, value: FALSE }
- { name : g_clk_freq, value: 125E6 }
- { name : g_temp_high, value: 85 }
......@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
synth_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.v
$RADIOHDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.v
src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
src/vhdl/node_unb1_terminal_bg_mesh_db.vhd
src/vhdl/unb1_terminal_bg_mesh_db.vhd
......@@ -33,7 +33,7 @@ quartus_tcl_files =
quartus/unb1_terminal_bg_mesh_db_pins.tcl
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.qip
$RADIOHDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.qip
quartus_sdc_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
......
......@@ -121,7 +121,7 @@ The 2nd tcl file can be created with Quartus. Here are the steps:
- generate the IP's by running: $RADIOHDL_WORK/libraries/technology/ip_stratixiv/generate-all-ip.sh
- Start synthesis in the Quartus GUI. Only the Analysis step!!
- Then in Quartus click: Tools/TclScripts.
Open the Tcl file: $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0_pin_assignments.tcl
Open the Tcl file: $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0_pin_assignments.tcl
Click Run.
- Then Continue synthesis with Fitter, or restart with Analysis.
- Copy the generated build/unb1_test_ddr_MB_I_II.qsf file to ./designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/quartus/unb1_test_ddr_MB_I_II_pins_constraints.tcl
......
......@@ -35,7 +35,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_10GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_10GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
......
......@@ -35,7 +35,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_10GbE_tx_only/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_10GbE_tx_only/qsys_unb1_test/synthesis/qsys_unb1_test.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
......
......@@ -35,7 +35,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_1GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_1GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
......
......@@ -40,9 +40,9 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_all/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
#$HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
$RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_all/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
#$RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
......
......@@ -40,9 +40,9 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
#$HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
$RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
#$RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
......
......@@ -41,8 +41,8 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
$RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
......
......@@ -40,8 +40,8 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
$RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
......
......@@ -40,8 +40,8 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
$RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
......
......@@ -40,8 +40,8 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
$RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
......@@ -40,8 +40,8 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
$RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
......@@ -39,8 +39,8 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
$RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
......@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
synth_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_tr_10GbE/qsys_unb1_tr_10GbE/synthesis/qsys_unb1_tr_10GbE.v
$RADIOHDL_BUILD_DIR/unb1/quartus/unb1_tr_10GbE/qsys_unb1_tr_10GbE/synthesis/qsys_unb1_tr_10GbE.v
src/vhdl/mmm_unb1_tr_10GbE.vhd
src/vhdl/unb1_tr_10GbE.vhd
......@@ -36,7 +36,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_tr_10GbE/qsys_unb1_tr_10GbE/synthesis/qsys_unb1_tr_10GbE.qip
$RADIOHDL_BUILD_DIR/unb1/quartus/unb1_tr_10GbE/qsys_unb1_tr_10GbE/synthesis/qsys_unb1_tr_10GbE.qip
quartus_sdc_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
......
......@@ -5,19 +5,16 @@ schema_type : peripheral
hdl_library_name : unb1_board
hdl_library_description: " This is the description for the unb1_board package "
# <peripheral_group>_<peripheral_name>_<slave_name>_<slave_type>
peripherals:
-
peripheral_name: rom_system_info
- peripheral_name: rom_system
slave_ports:
-
# rom_system_info
slave_prefix : WORK
slave_name : ROM_SYSTEM_INFO
slave_postfix: REG
- slave_name : info
slave_type : REG
fields:
-
field_name : field_rom_info
- - field_name : info
access_mode : RO
address_offset: 0x0
number_of_fields: 1024
......@@ -27,21 +24,17 @@ peripherals:
peripheral_description: |
" settings for rom_system_info register "
-
peripheral_name: reg_system_info
- peripheral_name: system
slave_ports:
-
# reg_system_info
slave_prefix : WORK
slave_name : REG_SYSTEM_INFO
slave_postfix: REG
- slave_name : info
slave_type : REG
fields:
-
field_name : field_reg_info
- - field_name : info
access_mode : RO
address_offset: 0x0
number_of_fields: 31
number_of_fields: 32
field_description: |
"address place for reg_system_info"
slave_description: " reg_info "
......@@ -50,22 +43,18 @@ peripherals:
" settings for reg_system_info register "
# peripheral, unb1_board_wdi_reg
-
peripheral_name: ctrl_unb1_board
- peripheral_name: ctrl
slave_ports:
-
# actual hdl name: unb1_board_wdi_reg
slave_prefix : UNB1_BOARD
slave_name : PIO_WDI
slave_postfix: REG
- slave_name : pio_wdi
slave_type : REG
fields:
-
field_name : nios_reset
- - field_name : nios_reset
width : 32
access_mode : WO
address_offset : 0x0
number_of_fields: 4
number_of_fields: 1
field_description: " Reset done by nios "
slave_description: "Reset register, for nios "
......@@ -73,19 +62,14 @@ peripherals:
peripheral_description: " "
# peripheral, unb1_board_wdi_reg
-
peripheral_name: unb1_board_wdi_reg
- peripheral_name: wdi
slave_ports:
-
# actual hdl name: unb1_board_wdi_reg
slave_prefix : UNB1_BOARD
slave_name : WDI
slave_postfix: REG
- slave_name : wdi
slave_type : REG
fields:
-
field_name : reset_word
- - field_name : reset_word
access_mode : WO
address_offset: 0x0
field_description: " Only the value 0xB007FAC7 'Boot factory' will result in a reset "
......@@ -95,8 +79,7 @@ peripherals:
peripheral_description: " "
# periheral, unb1_board_sens
-
peripheral_name: unb1_board_sens_reg
- peripheral_name: sens
parameters:
- { name: g_sim, value: FALSE }
......@@ -104,15 +87,11 @@ peripherals:
- { name: g_temp_high, value: 85 }
slave_ports:
-
# actual hdl name: reg_unb1_sens
slave_prefix : UNB1_BOARD
slave_name : SENS
slave_postfix: REG
- slave_name : sens
slave_type : REG
fields:
-
field_name : sens_data
- - field_name : sens_data
width : 8
access_mode : RO
address_offset: 0x0
......@@ -124,18 +103,16 @@ peripherals:
0x2 = hot_swap_v_sens
0x3 = hot_swap_v_source"
-
field_name : sens_err
- - field_name : sens_err
width : 1
access_mode : RO
address_offset: 0x4
address_offset: 0x10
radix : unsigned
field_description: ""
-
field_name : temp_high
- - field_name : temp_high
width : 7
address_offset: 0x5
address_offset: 0x14
reset_value : g_temp_high
software_value: g_temp_high
field_description: ""
......
......@@ -34,7 +34,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb2/quartus/unb2_minimal/qsys_unb2_minimal/synthesis/qsys_unb2_minimal.qip
$RADIOHDL_BUILD_DIR/unb2/quartus/unb2_minimal/qsys_unb2_minimal/synthesis/qsys_unb2_minimal.qip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
......
......@@ -56,7 +56,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb2/quartus/unb2_test_10GbE/qsys_unb2_test/synthesis/qsys_unb2_test.qip
$RADIOHDL_BUILD_DIR/unb2/quartus/unb2_test_10GbE/qsys_unb2_test/synthesis/qsys_unb2_test.qip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
......@@ -35,7 +35,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb2/quartus/unb2_test_1GbE/qsys_unb2_test/synthesis/qsys_unb2_test.qip
$RADIOHDL_BUILD_DIR/unb2/quartus/unb2_test_1GbE/qsys_unb2_test/synthesis/qsys_unb2_test.qip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
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