diff --git a/applications/lofar2/doc/prestudy/station2_sdp_dsp.txt b/applications/lofar2/doc/prestudy/station2_sdp_dsp.txt
index 993d1734ffb94c9cb6f85c8e022f46ef4d71b355..8b659737013ef01fa996825d1c900f584ab3a097 100644
--- a/applications/lofar2/doc/prestudy/station2_sdp_dsp.txt
+++ b/applications/lofar2/doc/prestudy/station2_sdp_dsp.txt
@@ -44,10 +44,20 @@ M&C:
The (x+y) could be implemented as first (x+y) and then *w, or as first weight and then add.
+
*******************************************************************************
* Subband correlator
*******************************************************************************
+- Subband select of N_crosslets local crosslets per signal input
+- Interleave local crosslets from S_pn = 12 signal inputs
+- XC ring
+- XC dispatcher of local and remote crosslets
+- X_sq correlator cell with N_crosslets * S_pn*S_pn visibilities and N_valid, N_flagged counts
+- M&C:
+ . Subband select
+ . XC ring
+ . X_sq
diff --git a/applications/lofar2/doc/prestudy/station2_sdp_firmware_design.txt b/applications/lofar2/doc/prestudy/station2_sdp_firmware_design.txt
index f3c52363fd654395f910129a534e159f9b9f588a..600f497c64b3281c8f29e8e4604c5992cb6ae94f 100644
--- a/applications/lofar2/doc/prestudy/station2_sdp_firmware_design.txt
+++ b/applications/lofar2/doc/prestudy/station2_sdp_firmware_design.txt
@@ -23,7 +23,7 @@ Definitions
Introduction
- Context
. ADD fig 3.1-1 (E)ICD and L3 PBS overview
-- Scope
+- Scope and purpose
- Document overview
Station overview
diff --git a/applications/lofar2/doc/prestudy/station2_sdp_firmware_planning.txt b/applications/lofar2/doc/prestudy/station2_sdp_firmware_planning.txt
index 873b3c2a163a7685615e22fe60209fba0ee98ef6..19cb2fb62f00fd13365e5f2459fdb11d95e86e88 100644
--- a/applications/lofar2/doc/prestudy/station2_sdp_firmware_planning.txt
+++ b/applications/lofar2/doc/prestudy/station2_sdp_firmware_planning.txt
@@ -3,24 +3,24 @@
*******************************************************************************
Includes design, implementation, verification on HW, technical commissioning.
-v1 v2
+v1 v2
Infrastructure
10 20 - Development environment using GIT, RadioHDL, updating existing components
20 . - BSP using Gemini Protocol, ARGS
10 . - Ethernet access (OSI 1-4)
10 20 - Ring access
-
- Applications:
+
+ Application:
15 . - ADC ingress and time stamp
20 10 - Subband filterbank (critically sampled)
0 30 - Subband filterbank (oversampled)
10 . - Beamformer
20 . - Subband correlator
-25 . - Transient buffer (DDR4 interface, subband select and DM >= 0, packet format, M&C, RW access via M&C)
+25 . - Transient buffer (DDR4 interface, subband select and DM >= 0, packet format, M&C, RW access via M&C)
20 . - Transient detection
20 . - Subband offload
0 . - 160 MHz
-
+
35 . Integration
5 - FPGA pinning
10 - Interface test designs unb2c
@@ -41,7 +41,7 @@ v2 : 10 less for critically sampled PFB
==> EK, JH: v1 estimate of April 2019 is still valid as v2 on 10 Oct 2019.
-v3 :
+v3 :
Infrastructure
20 - Development environment using GIT, RadioHDL, updating existing components
@@ -51,7 +51,7 @@ v3 :
20 - Ring access
10 - 10GbE access (OSI 1-4)
- Applications:
+ Application:
15 - ADC input and time stamp
10 - Subband filterbank (critically sampled)
20 - Subband correlator
@@ -61,7 +61,7 @@ v3 :
20 - Transient detection
30 - Oversampled subband filterbank
0 - Support 160 MHz
-
+
Integration:
10 - Lab tests
5 - Technical commissioning Dwingeloo
@@ -73,3 +73,147 @@ All:
No oversampled filterbank:
20 + 5 + 10 + 20 + 20 + 10 + 15 + 10 + 20 + 10 + 25 + 20 + 20 + 0 + 10 + 5 + 5 = 225
+
+
+
+*******************************************************************************
+* SDP Workpackage (UniBoard2 HW + FW)
+*******************************************************************************
+
+Firmware FPGA images:
+- the SDP has one main firmware design unb2c_sdp,
+- the integrated design of SDP is revision unb2c_sdp_station,
+- per task there are revisions of unb2c_sdp that contain subsets of the SDP functionality,
+
+
+Deliverables (D): items that are needed for a milestone
+Milestones (M) : 'cake moments' when you demonstrate deliverables
+- integration passed
+- review passed
+
+
+Tasks:
+
+INFRASTRUCTURE UniBoard2:
+ weeks nr task
+ 20 1) Maintain firmware development environment
+ - using GIT
+ - using RadioHDL
+ - updating existing VHDL library components
+ D=> Operational firmware development environment
+ D=> VHDL libraries verified in simulation
+
+ 2) UniBoard2 board and test firmware
+ - unb2c board HW
+ D=> unb2c board detailed design document
+ D=> unb2c board schematic
+ D=> unb2c board layout
+
+ M=> unb2c board detailed design document review (unb2b modifications)
+ M=> unb2c board schematic review
+ M=> unb2c board layout review (production ready)
+ M=> unb2c board lab validation using JTAG, unb2c_test designs OK
+ M=> unb2c board production validation using JTAG, unb2c_minimal_gmi OK
+
+ 5 - unb2c FPGA pinning design
+ 10 - unb2c FPGA interface test designs
+ D=> unb2c_test design revisions (1GbE, 10GbE, DDR4, flash, ADC)
+ D=> unb2c_test_adc (read ADC samples from multiple inputs)
+
+
+ 20 3) UniBoard2 board support package (BSP)
+ - M&C by SCU via Gemini protocol
+ - M&C interface definition and generation using ARGS (doc, C, HDL)
+ D=> Gemini board for SCU M&C tests
+ D=> unb2c_minimal_gmi (1GbE, flash)
+ M=> unb2c_minimal_gmi validated using M&C by SCU (read design name)
+
+INFRASTRUCTURE SDP:
+ 10 4) Network access via 10GbE
+ - Ethernet MAC, UDP/IPv4, ARP, ping
+ D=> 10GbE HDL component including support for UDP/IPv4, ARP, ping
+ D=> unb2c_10GbE
+ M=> unb2c_10GbE validated using data capture on PC and ping
+
+ 20 5) Ring access using test data and BSN monitor
+ D=> unb2c_ring_combiner for BF
+ D=> unb2c_ring_multicast for XC
+ D=> unb2c_ring_endcast for SO, TB
+ M=> unb2c_ring revisions verified in simulation
+ M=> unb2c_ring revisions validated on hardware using M&C on SCU
+
+APPLICATION SDP documents:
+ 6) Required documents
+ D=> Detailed design document of SDP firmware
+ D=> L1 ICD-11109 SDP-CEP: beamlet data protocol
+ D=> L1 ICD-11109 SDP-CEP: transient data protocol
+ D=> L2 ICD-11211 SC-SDP: FW register map and register definitions
+ D=> L2 ICD-11211 SC-SDP: UniBoard2 hardware M&C
+ D=> L2 ICD-11207 RCU2S-SDP: ADC interface
+ D=> L2 ICD-11209 STF-SDP: Time and frequency interface
+ D=> L2 ICD-11218 SDP-STCA: Subrack interface
+
+ M=> SDP detailed design and interface documents ready for DDR
+ M=> SDP detailed design and interface documents updated for CDR
+
+ D=> SDP firmware verification and maintenance document
+ M=> SDP all documents finished
+
+APPLICATION single node:
+ weeks nr task
+ 15 7) ADC input and timestamp (RCU2 interface)
+ ==> unb2c_sdp_adc_capture, read ADC or WG samples from databuffer via M&C
+ ==> unb2c_sdp_station (ADC)
+
+
+M=> SDP ready for CDR
+ All major technical UniBoard2 hardware and SDP firmware risks are mitigated (by design and
+ based on validation with at least two UniBoard2 using JTAG, unb2c_minimal_gmi, unb2c_ring,
+ and unb2c_sdp_adc_capture).
+
+
+ 10 8) Subband filterbank (Fsub)
+ ==> unb2c_sdp_filterbank to read SST via M&C
+ ==> unb2c_sdp_station (ADC + SST)
+
+APPLICATION multi node:
+ weeks nr task
+ 20 9) Subband correlator (XC)
+ ==> unb2c_sdp_correlator_one_node, read XST via M&C and create ACM for one node
+ ==> unb2c_sdp_correlator_multi_node, read XST via M&C and use ring to create complete ACM
+ ==> unb2c_sdp_station (ADC + SST + XST)
+
+APPLICATION multi node / network output:
+ weeks nr task
+ 10 10) Beamformer (BF)
+ ==> unb2c_sdp_beamformer_bst_one_node, read BST via M&C
+ ==> unb2c_sdp_beamformer_output_one_input, output to CEP for one input from one node
+ ==> unb2c_sdp_beamformer_output_one_node, output to CEP and sum one node
+ ==> unb2c_sdp_beamformer_output_multi_node, output to CEP and use ring to sum nodes
+ ==> unb2c_sdp_station (ADC + SST + XST + BST + BF output)
+ ==> detailed design doc
+
+ 25 11) Transient buffer (TB)
+ ==> unb2c_sdp_transient_buffer revisions (ADC + SST + TB readout, M&C access DDR4)
+ ==> unb2c_sdp_station (ADC + SST + XST + BST + BF output + TB readout)
+ ==> detailed design doc
+
+ 20 12) Transient detection (TD)
+ ==> unb2c_sdp_transient_buffer revisions (ADC + TD event)
+ ==> unb2c_sdp_station (ADC + SST + XST + BST + BF output + TB readout + TD event)
+ ==> detailed design doc
+
+ 20 13) Subband offload (SO) for AARTFAAC2.0
+ ==> unb2c_sdp_subband_offload revisions (ADC + SST + SO, one node, all nodes via ring)
+ ==> unb2c_sdp_station (ADC + SST + XST + BST + BF output + TB readout + TD event + SO)
+ ==> detailed design doc
+
+INTEGRATION:
+ weeks nr task
+ 20 14) Station integration tests (using unb2c_sdp_station)
+ - Laboratory tests
+ - Technical commissioning Dwingeloo Test Station ("Huisje West")
+ - Technical commissioning Prototype Test Station
+ - Technical commissioning Pre-production Test Station
+
+
diff --git a/applications/lofar2/doc/prestudy/station2_sdp_hdl_components.txt b/applications/lofar2/doc/prestudy/station2_sdp_hdl_components.txt
index c82daa7080ed2731df74c909d9c5a4b095309e74..20e64e6cfc9e61871c6b8a22e870d6de330ba005 100644
--- a/applications/lofar2/doc/prestudy/station2_sdp_hdl_components.txt
+++ b/applications/lofar2/doc/prestudy/station2_sdp_hdl_components.txt
@@ -7,29 +7,31 @@
. rx_cnt: 18 bits, number Rx frames
. brc : 1 bit, 0 if no Rx frames with CRC error, 1 if >= 1 Rx frames had a CRC error
. sync : 1 bit, 1 if the frame with Rx sync was detected, else 0
- . align : 1 bit, 1 if all frames aligned OK, else 0
+ . align : 1 bit, 1 if all frames aligned correctly, else 0
- RSP rad_latency:
- . rx_latency : 16 bit, stores an internal count value when the Rx sync is detected. The internal count
- restarts at the PPS sync. This measures the latency in clock cycles.
+ . rx_latency : 16 bit, stores an internal count value when the Rx sync is detected. The
+ internal count restarts at the PPS sync. This measures the latency in clock
+ cycles.
- APERTIF dp_bsn_monitor
- . mon_sync_timeout = '1' when the Rx sync did not occur within 200M cycles since last Rx sync ~= sync
+ . mon_sync_timeout = '1' when the Rx sync did not occur within 200M cycles since last
+ Rx sync ~= sync
. mon_ready_stable = '1' when ready was always '1' during last Rx sync interval
. mon_xon_stable = '1' when xon was always '1' during last Rx sync interval
. mon_bsn_at_sync = BSN at Rx sync
- . mon_nof_sop = number of sop during last Rx sync interval = rx_cnt
- . mon_nof_err = number of err at eop during last Rx sync interval ~= brc
+ . mon_nof_sop = number of sop during last Rx sync interval = rx_cnt
+ . mon_nof_err = number of err at eop during last Rx sync interval ~= brc
. mon_nof_valid = number of valid during last Rx sync interval
. mon_bsn_first = BSN at first Rx sync --> not useful
. mon_bsn_first_cycle_cnt = latency at first Rx sync --> should use every Rx sync like on RSP
==> Reuse dp_bsn_monitor with improvements:
- . Monitor the packets per sync interval using Rx sync. This is more precise then using the PPS sync.
- The Rx sync based values are only valid if mon_sync_timeout = 0.
+ . Monitor the packets per sync interval using Rx sync. This is more precise then using the PPS
+ sync. The Rx sync based values are only valid if mon_sync_timeout = 0.
. Remove mon_bsn_first and mon_bsn_first_cycle_cnt.
- . Add mon_latency, use PPS sync like in RSP to measure the latency between PPS sync and Rx sync in
- number of clock cycles.
+ . Add mon_latency, use PPS sync like in RSP to measure the latency between PPS sync and Rx
+ sync in number of clock cycles.
@@ -37,54 +39,66 @@
* DP encoder / decoder
*******************************************************************************
- dp_packet_enc / dp_packet_dec
- . Current dp_packet_enc encodes sosi fields into: CHAN (32b), sync & BSN (64b), DATA (>= 1 b), ERR (32b).
+ . Current dp_packet_enc encodes sosi fields into: CHAN (32b), sync & BSN (64b), DATA (>= 1 b),
+ ERR (32b).
. Use new dp_packet_enc with CRC to mitigate false positive ETH CRC --> dp_packet_enc_crc:
CHAN (32b), Sync & BSN (64b), DATA (>= 1 b), ERR (32b), CRC (32b)
- RSP RAD frame:
. uses: FSI, FSN, DATA, CRC.
. The FSN is 16 bit but the MSbit is used for the sync. The other 15 bits count blocks.
- . After Rx frame the FSI is stripped and the CRC is replace by a BRC.
+ . After Rx frame the FSI is stripped and the CRC is replace by a boolean check (BRC).
- CRC Error checking:
- The CRC is a 32 bit number, so the chance that the CRC results in a false positive is 1/2**32 ~= 2.3e-10 or 1
- in 4.3e9. The packet rate is f_sub. Per T_sub interval the ring carries about 10 - 20 packets between N = 16
- nodes. Hence in total the packet rate of the ring for one LBA station is about 195312.5 * 20 * 16 ~= 60 M
- packets / s. With 50 stations and LBA and HBA this become about a factor 100 more, so about 6 G packets / s.
- If 0.01 % of the packets have errors, then the packet error rate is 0.6 M /s, so then once every 1 / (0.6e6 * 2.3e-10)
- ~= 2 hours somewhere in LOFAR there will occur a false positive CRC. If such an error occurs, then it must not
- cause the entire processing to stall. Therefore some additional check is necessary using a CRC. It is not
- sufficient to check e.g. the ETH type and the expected packet length, because these do not cover the other
- data in the packet.
- Each station has about 100 10GbE links and there are 50 stations. Suppose the BER per link is 1e-10, so one bit
- error per second per link, and that each bit error causes a CRC error. The total ring CRC error rate in LOFAR is then
- 5000/s, so a false positive CRC will occur about once per 2**32/5000 = 10 days. This is not often, but if it
- causes a station to fail then it is too often.
- Having false positive CRCs even on a daily or weekly basis is too often. Therefore the application payload
- should also have a CRC to ensure that no false positive CRC will occur during the life time of LOFAR 2.0.
+ The CRC is a 32 bit number, so the chance that the CRC results in a false positive is 1/2**32
+ ~= 2.3e-10 or 1 in 4.3e9. The packet rate is f_sub. Per T_sub interval the ring carries about
+ 10 - 20 packets between N = 16 nodes. Hence in total the packet rate of the ring for one LBA
+ station is about 195312.5 * 20 * 16 ~= 60 M packets / s. With 50 stations and LBA and HBA
+ this become about a factor 100 more, so about 6 G packets / s. If 0.01 % of the packets have
+ errors, then the packet error rate is 0.6 M /s, so then once every 1 / (0.6e6 * 2.3e-10) ~= 2
+ hours somewhere in LOFAR there will occur a false positive CRC. If such an error occurs, then it
+ must not cause the entire processing to stall. Therefore some additional check is necessary
+ using a CRC. It is not sufficient to check e.g. the ETH type and the expected packet length,
+ because these do not cover the other data in the packet.
+ Each station has about 100 10GbE links and there are 50 stations. Suppose the BER per link is
+ 1e-10, so one bit error per second per link, and that each bit error causes a CRC error. The
+ total ring CRC error rate in LOFAR is then 5000/s, so a false positive CRC will occur about
+ once per 2**32/5000 = 10 days. This is not often, but if it causes a station to fail then it
+ is too often. Having false positive CRCs even on a daily or weekly basis is too often.
+ Therefore the application payload should also have a CRC to ensure that no false positive CRC
+ will occur during the life time of LOFAR 2.0.
Design decisions:
-- Use CHAN (32b), Sync & BSN (64b), DATA (>= 1 b), ERR (32b), CRC (32b) to transport data between FPGAs
- without false positive CRCs during the lifetime of LOFAR 2.0 to garantuee that only correct packets
- enter the FPGA internal processing. The internal FPGA processing must be robust to lost packets, but
- it does not have to be robust against corrupted packets (wrong contents, wrong length).
+- Use CHAN (32b), Sync & BSN (64b), DATA (>= 1 b), ERR (32b), CRC (32b) to transport data between
+ FPGAs without false positive CRCs during the lifetime of LOFAR 2.0 to garantuee that only
+ correct packets enter the FPGA internal processing. The internal FPGA processing must be robust
+ to lost packets, but it does not have to be robust against corrupted packets (wrong contents,
+ wrong length).
*******************************************************************************
-* dp_validate_crc
+* dp_validate_crc (dp_store_and_forward)
* - Validate (geldig verklaren) CRC and store-and-forward or store-and-discard this packet
*******************************************************************************
The Ethernet/DP packet has two CRC checksums in the packet tail:
-- the Ethernet CRC is calculated by the 1GbE MAC
+- the Ethernet CRC is calculated by the 1GbE MAC and reported via the sosi.err field
- the DP packet CRC is calculated by the dp_packet_dec.
-The packet needs to be stored before it can be forwarded or discarded, because the entire packet is needed
-to calculate and verify the CRC. The CRC results are reported via the sosi.err field at the end of packet
-(eop). The dp_validate_crc forwards the packet when the CRC is oke and discards the packet when the CRC is
-wrong.
+The CRC information is in the packet tail. Therefore the packet needs to be stored, before it can
+be validated, because the entire packet is needed to calculate and verify the CRC. Dependent on
+the validation outcome the packet is either forwared or discarded. The CRC results are reported
+via the sosi.err field at the end of packet (eop). The dp_validate_crc forwards the packet when
+the sosi.err CRC is correct and discards the packet when the CRC is wrong.
+
+The dp_validate_crc uses dp_store_and_forward. The decision is known when the eop is received and
+must then be applied at the sop, to either release the block or discard it.
+
+- Rx ETH MAC puts ETH CRC result in sosi.err at eop
+- Rx DP decode puts DP CRC result in sosi.err at eop
+- dp_validate_crc stores the packet and forwards if it has no error at the eop
@@ -93,37 +107,40 @@ wrong.
* - Validate (geldig verklaren) BSN at Rx sync and pass on or discard packets until next Rx sync
*******************************************************************************
-The DP packet has a sync and BSN field in the packet header. This field is at the start of the packet (sop),
-so it can be verified while the packet arrives. The Rx BSN at the Rx sync in the received packet should be
-equal to the local Station BSN at the local sync. If the Rx sync BSN and the local sync BSN are:
+The DP packet has a sync and BSN field in the packet header. This field is at the start of the
+packet (sop), so it can be verified while the packet arrives. The Rx BSN at the Rx sync in the
+received packet should be equal to the local Station BSN at the local sync. If the Rx sync BSN
+and the local sync BSN are:
- not equal, then discard all subsequent blocks until the Rx sync BSN is equal again,
- equal, then pass on all subsequent blocks until the next Rx sync
-The assumption is that if the BSN at sync is wrong, then the block processing at this node or at the remote
-node has not been started properly, so then subsequent blocks will have wrong BSN also. If the BSN at
-sync is oke, all nodes have been started properly abd then the BSN for all subsequent blocks in the sync
-interval will be correct too. The sync and BSN value are not corrupted, because they are determined inside
-the local and remote FPGA (so error free, because the logic is error free) and the remote BSN is
-transported using a CRC (so error free, because the CRC detects all errors).
+The assumption is that if the BSN at sync is wrong, then the block processing at this node or at
+the remote node has not been started properly, so then subsequent blocks will have wrong BSN also.
+If the BSN at sync is correct, all nodes have been started properly and then the BSN for all
+subsequent blocks in the sync interval will be correct too. The sync and BSN value are not
+corrupted, because they are determined inside the local and remote FPGA (so error free, because
+the logic is error free) and the remote BSN is transported using a CRC (so error free, because
+the CRC detects all errors).
-The initial state to discard or pass on block is don't care, because the assumption is that the block
-processing was (re)started properly on all nodes. At power up, choose to initially pass on packets.
-If the packet with the Rx sync and BSN is lost, then the last decision to discard or pass on packets
-remains, because it is still valid.
+The initial state to discard or pass on block is don't care, because the assumption is that the
+block processing was (re)started properly on all nodes. At power up, choose to initially pass
+on packets. If the packet with the Rx sync and BSN is lost, then the last decision to discard
+or pass on packets remains, because it is still valid.
-The dp_validate_bsn_at_sync function verifies the entire 64 bit sync and BSN in an Rx packet. For local and
-remote inputs the BSN can only differ by a limited number dependent on the latency differences between the
-different inputs. Therefore if the input Rx BSN at sync matches the local Station BSN, then for the
-BSN aligner that aligns the inputs based on the BSN it is sufficient to only use a fraction of the BSN.
-Using the fraction of the BSN as index is suffivient to distinguish between blocks within the maximum BSN
-latency. If the fraction N is a power of 2 , then only the log2(N) LSbits of the BSN need to be compared
-to ensure that all inputs have the same 64 bit sync and BSN.
+The dp_validate_bsn_at_sync function verifies the entire 64 bit sync and BSN in an Rx packet.
+For local and remote inputs the BSN can only differ by a limited number dependent on the
+latency differences between the different inputs. Therefore if the input Rx BSN at sync matches
+the local Station BSN, then for the BSN aligner that aligns the inputs based on the BSN it is
+sufficient to only use a fraction of the BSN. Using the fraction of the BSN as index is
+sufficient to distinguish between blocks within the maximum BSN latency. If the fraction N is
+a power of 2 , then only the log2(N) LSbits of the BSN need to be compared to ensure that all
+inputs have the same 64 bit sync and BSN.
*******************************************************************************
-* BSN aligner
+* BSN aligner dp_bsn_align_v2
*******************************************************************************
Assumptions:
@@ -134,26 +151,29 @@ Assumptions:
- Usage schemes:
. N = 2 inputs aligner with 1 local data and 1 remote data
. N > 2 inputs aligner with 1 local data and N-1 remote data
- . N >=2 inputs aligner with 0 local data and N remote data (not used on ring, but was used in APERTIF)
+ . N >=2 inputs aligner with 0 local data and N remote data (not used on ring, but was used in
+ APERTIF)
. Treat all inputs equal, so no special role for a local input to suit more general usage
-- The local sync and BSN sources on all FPGAs are synchronous, to avoid additional BSN latency between inputs.
+- The local sync and BSN sources on all FPGAs are synchronous, to avoid additional BSN latency
+ between inputs.
- Static input enable or disable via M&C
- it is possible to enable or disable any combination of inputs
- if all inputs are disabled then the output stops.
- - if the input enable or disable setting is changed, then the BSN aligner restarts trying to achieve alignment.
+ - if the input enable or disable setting is changed, then the BSN aligner restarts trying to
+ achieve alignment.
- disabled inputs are output with zero or flagged data
- - for the ring with 1 local and 1 remote input the static input enable/disable supports the align modes:
+ - for the ring with 1 local and 1 remote input the static input enable/disable supports the
+ align modes:
. disabled,
. local only,
. remote only,
. local and remote
- Input latency:
- . the input latencies are fixed by design, so inputs have a maximum BSN latency g_bsn_latency that is fixed
- and that does not have to be programmable via M&C.
- . If all hops on the ring are active then the total latency will be (N-1)*(d + 1) where d is the transport
- latency of each hop and 1 is due to store-and-forward at each node. Typically the total transport latency
- on the ring is (N-1)*d < 1, so less than one block period. The total ring latency is covered by
- g_bsn_latency > (N-1)*(d + 1).
+ . the input latencies are fixed by design, so inputs have a maximum BSN latency g_bsn_latency
+ that is fixed and that does not have to be programmable via M&C.
+ . If all hops on the ring are active then the total latency will be (N-1)*t_hop, where t_hop is
+ the transport latency of each hop. The total transport latency on the ring is (N-1)*t_hop.
+ The total ring latency is covered by g_bsn_latency > (N-1)*t_hop.
- Lost input blocks:
. accept that the corresponding output is lost too, or output filler block to replace lost block
. should not cause subsequent blocks to get lost too
@@ -167,22 +187,23 @@ Assumptions:
. smoothen bursts (only an issue with remote drive output)
. provide output throttling (requires output FIFOs or data blocks that have sufficient gaps)
- Stopped input:
- . If after some block periods (e.g. g_bsn_latency) there is no more block pending at any input, then the
- output stops and the BSN aligner should restart trying to achieve alignment.
+ . If after some block periods (e.g. g_bsn_latency) there is no more block pending at any input,
+ then the output stops and the BSN aligner should restart trying to achieve alignment.
Notes:
- In LOFAR and APERTIF the BSN aligner does loose more blocks due to input flush and realign
-- a BSN aligner can align at any BSN, using a sync aligner that can only align at the sync, would cause
- loosing an entire sync interval to realign, which is not acceptable
+- a BSN aligner can align at any BSN, using a sync aligner that can only align at the sync, would
+ cause loosing an entire sync interval to realign, which is not acceptable
- in APERTIF the sync_checker looses entire sync intervals to ensure filled sync intervals
-- In LOFAR and APERTIF the output is driven by the remote input to add minimal latency, however this
- results in loosing more packets and having to realign if input packets get lost.
-- In dp_bsn_align the artifical local data stream was used to ensure that the output block size was correct,
- by using extra CRC checking (ETH CRC and DP CRC) and store and forward in Rx it is already certain that only
- correct input packets arrive at the BSN aligner input. Therefore an artifical local data stream is not needed.
+- In LOFAR and APERTIF the output is driven by the remote input to add minimal latency, however
+ this results in loosing more packets and having to realign if input packets get lost.
+- In dp_bsn_align the artifical local data stream was used to ensure that the output block size
+ was correct, by using extra CRC checking (ETH CRC and DP CRC) and store and forward in Rx it is
+ already certain that only correct input packets arrive at the BSN aligner input. Therefore an
+ artifical local data stream is not needed.
Design options:
@@ -190,40 +211,44 @@ Design options:
. Rely on next received packet:
- check per input that the BSN increments +1
- requires a timeout or overflow detection on other inputs to detect a burst of lost packets
- - after a burst of lost packets, typically the output cannot catch up anymore, so then the BSN aligner
- needs to flush its input buffer and restart.
+ - after a burst of lost packets, typically the output cannot catch up anymore, so then the BSN
+ aligner needs to flush its input buffer and restart.
. Per packet using a local block reference.
- The local block reference is offset by at least g_bsn_latency relative to the local BSN source, to
- ensure that all inputs should have a new block pending for output. This is possible, because the input
- latencies are static and within a fixed range:
+ The local block reference is offset by at least g_bsn_latency relative to the local BSN
+ source, to ensure that all inputs should have a new block pending for output. This is
+ possible, because the input latencies are static and within a fixed range:
- in circular buffer the Wr flag for the lost block remains unset
- in FIFO by no pending input or pending input with higher BSN then current output BSN
==> Design decision:
- - Use local block reference to define when to detect lost packets, because one lost block should not
- cause subsequent blocks to get lost too.
+ - Use local block reference to define when to detect lost packets, because one lost block
+ should not cause subsequent blocks to get lost too.
- Output driven by remote input block arrival or by local block reference
. in case of 1 remote input, the remote input does not need a FIFO if it drives the output
. in case of > 1 remote input, then the remote inputs also requires FIFOs
- . using local input increases the latency from remote input to output, because fixed to the T_sub grid
+ . using local input increases the latency from remote input to output, because fixed to the
+ T_sub grid
. using local input at T_sub grid avoids bursts, this can also be handled using flow control
- . with local input driving the output the assumption is that if the local input has M packets, then all remote
- inputs will have delivered at least one frame, so there should be a sop pending from all.
- . if there is no local input, then an artifical local input can be derived when BSN is equal on all enabled remote inputs.
- . if remote input is lost, then entire output is lost if remote drives output, because there is not enough spare time
- to still output the other input packets
- . For remote driven output a slot can be output when for all active inputs there is a block. However if one or
- a series of packets got lost, then the other inputs will overflow. Hence remote driven output needs a timeout
- to keep the output running, so a form of local driven output. Hence to avoid additional packet loss on other
- inputs or of subsequent packets in time it is necessary to have a local driven output. Therefore using a remote
- driven output is not feasible.
+ . with local input driving the output the assumption is that if the local input has M packets,
+ then all remote inputs will have delivered at least one frame, so there should be a sop
+ pending from all.
+ . if there is no local input, then an artifical local input can be derived when BSN is equal on
+ all enabled remote inputs.
+ . if remote input is lost, then entire output is lost if remote drives output, because there is
+ not enough spare time to still output the other input packets
+ . For remote driven output a slot can be output when for all active inputs there is a block.
+ However if one or a series of packets got lost, then the other inputs will overflow. Hence
+ remote driven output needs a timeout to keep the output running, so a form of local driven
+ output. Hence to avoid additional packet loss on other inputs or of subsequent packets in time
+ it is necessary to have a local driven output. Therefore using a remote driven output is not
+ feasible.
==> Design decision:
- - Use local block reference to define when aligned blocks should be output, because one lost block should
- not cause subsequent blocks to get lost too, which is more important then adding minimal latency and
- potentially saving BSN aligner input buffer memory.
+ - Use local block reference to define when aligned blocks should be output, because one lost
+ block should not cause subsequent blocks to get lost too, which is more important then
+ adding minimal latency and potentially saving BSN aligner input buffer memory.
- Generation of local block reference to define the output pace:
@@ -244,7 +269,7 @@ Design options:
- Filler data insertion
. Whether to drop a block or to replace it by a filler block depends on the application
- for BF drop all inputs, because beam is affected
- - for XC insert filler data, because visibilities of active inputs are still oke.
+ - for XC insert filler data, because visibilities of active inputs are still correct.
- for the output via the Network insert filler data to keep the output at the nominal rate, such that
the destination can distinguish between data blocks that got lost inside Station and packet loss on
the Network.
@@ -441,6 +466,12 @@ Design options:
- flush per packet or flush until empty?
- flush per input per input or flush all inputs?
- flush by reading, or by reset or by moving a Rd pointer
+ A FIFO can be flushed by resetting it, but this requires careful control to ensure that the reset is
+ noticed in both clock domains, and that the reset is applied in between input packets to avoid that
+ only a tail of a packet gets into a FIFO. Therefore in LOFAR 1.0 and APERTIF a FIFO is flushed by
+ reading the packets from it until it is empty. This scheme also allows flushing per packet. The
+ disadvantage of reading the packets and the discard them, is that it takes as long as reading at full
+ speed.
- Use packet count instead of FIFO full indicator
- can we do without flushing the FIFO? Not if we need to realign.
- If multiple packets on a remote input get lost, then the other inputs fill up if there is no timeout. Flush
@@ -464,7 +495,7 @@ Design options:
because the Station BSN is 50 bit.
-. Cicrular buffers on CEP
+. Circular buffers on CEP
On CEP the beamlet data is written into a circular buffer based on the time stamp. A flag indicates whether data in the
circular buffer is valid. The size of the circular buffer is in the order of hundreds of ms to cover the distance latency
of the international stations. An array of tupples lists the lenght of continuous blocks in the circular buffer, and
diff --git a/applications/lofar2/doc/prestudy/station2_sdp_ring.txt b/applications/lofar2/doc/prestudy/station2_sdp_ring.txt
index b484c32f0ece90b0c77debf5c079ce623ce21ddb..b7996af32d391333c47a3f1396acecc3748bcb14 100644
--- a/applications/lofar2/doc/prestudy/station2_sdp_ring.txt
+++ b/applications/lofar2/doc/prestudy/station2_sdp_ring.txt
@@ -2,60 +2,119 @@ Detailed design: RING
*******************************************************************************
-* Data format
+* Data rate
*******************************************************************************
Support for oversampled subband filterbank
-The oversampling increases the processing rate and data rate by a factor R_os. Typical R_os are 32/28 = 1.142,
-32/27 = 1.185, 32/26 = 1.231, 32/25 = 1.28, 32/24 = 1.333. Assume R_os <= 1.28.
-
-Assume the processing for critically sampled filterbank runs at 200 MHz and for oversampled subbands it will run at
-R_os * 200 MHz. For R_os = 1.28 this requires processing at >= 256 MHz. In this way if the processing fits for the
-critically sampled subbands, then it will also fit for the oversampled subbands.
-
-The IO data rate on the ring increases with the oversampling factor R_os. For oversampled data the ring 10GbE has
-the full 10 Gbps capacity and for critically sampled data the effective ring capacity becomes 10G / R_os =
-10G / 1.28 = 7.8125 Gbps. The aim is to be able to replace the critically sampled filterbank by an oversampled
-filterbank without having to change other parts in the design. Therefore assume that the ring capacity for the
-critically sampled data is restricted to 7.8125 Gbps. The alternative to use full ring capacity for critically
-sampled data and then support less (S_sub_bf / R_os = 488 / 1.28) beamlets for oversampled data is not compliant
-with the requirement of S_sub_bf = 488.
+The oversampling increases the processing rate and data rate by a factor R_os. Typical R_os are
+32/28 = 1.142, 32/27 = 1.185, 32/26 = 1.231, 32/25 = 1.28, 32/24 = 1.333. Assume R_os <= 1.28.
+
+Processing capacity per subband period:
+Assume the processing for critically sampled filterbank runs at 200 MHz and for oversampled
+subbands it will run at R_os * 200 MHz. For R_os = 1.28 this requires processing at >= 256 MHz.
+This means that the processing has N_clk = N_fft = 1024 clock cycles avaiable per subband
+period T_sub, independent of R_os. In this way if the processing for the critically sampled
+subbands fits within N_clk = N_fft = 1024 clock cycles, then it will also fit for the
+oversampled subbands.
+
+IO capacity per 10GbE lane:
+The IO data rate on the ring increases with the oversampling factor R_os. For oversampled data
+the ring 10GbE has the full 10 Gbps capacity and for critically sampled data the effective
+ring capacity per lane becomes L_lane = 10G / R_os = 10G / 1.28 = 7.8125 Gbps. The aim is to
+be able to replace the critically sampled filterbank by an oversampled filterbank without
+having to change other parts in the design. Therefore assume that the ring capacity for the
+critically sampled data is restricted to L_lane < 7.8125 Gbps.
+
+Note:
+The alternative to use full ring capacity for critically sampled data and then support less
+(S_sub_bf / R_os = 488 / 1.28 = 381, so almost 30 % less) beamlets for oversampled data is not
+compliant with the requirement of S_sub_bf = 488.
Design descision: Support S_sub_bf = 488 also for maximum R_os = 1.28.
W_beamlet_sum
-LOFAR 1.0 had 24 bit for 16 bit beamlet mode and 12 bit for 8 bit beamlet mode. LOFAR 2.0 will only support 8 bit.
-Using W_beamlet_sum = 18 bit provides 5 bits more dynamic range for 8 bit beamlet mode, which is sufficient to
-detect overflow. Using W_beamlet_sum = 18 bit also fits the input data width of the FPGA hard core multipliers in
-the BST. Given that the signal input level is 4 bit the beamformer could round 2 LSbit to effectively achieve
-20 bit dynamic range, even for S = 1 signal input. However the same effect can also be achieved by reducing the
-beamlet weights by a factor 2**2 = 4. Choose the same W_beamlet_sum = 18 bit for both the critically sampled
-beamlet data and the oversampled beamlet data, to avoid differences in the design.
-The beamlet sum that is transported across the ring needs to fit on a 10GbE link. With S_sub_bf = 488 and R_os <=
-1.28 the data rate for one full band station beam is N_pol * S_sub_bf * f_sub * R_os * N_complex * W_beamlet_sum
-= 2 * 488 * 195312.5 * 1.28 * 2 * 18 = 8.784 Gbps. This leaves about 13.8 % margin for packet overhead, which is
-sufficient. Using W_beamlet_sum = 18 bit fits the input data width of the FPGA hard core multipliers and also
-provides sufficent dynamic range to scale the final beamlet sum to W_beamlet = 8 bit for output.
-
-Design descision: W_beamlet_sum = 18 bit for both critically sampled beamlet and oversampled beamlets
+LOFAR 1.0 had 24 bit for 16 bit beamlet mode and 12 bit for 8 bit beamlet mode. LOFAR 2.0 will
+only support 8 bit. Using W_beamlet_sum = 18 bit provides 5 bits more dynamic range for 8 bit
+beamlet mode, which is sufficient to detect overflow. Using W_beamlet_sum = 18 bit also fits the
+input data width of the FPGA hard core multipliers in the BST. Given that the SDP signal input
+level is 4 bit the beamformer could round 2 LSbit to effectively achieve 20 bit dynamic range,
+even for S = 1 signal input. However the same effect can also be achieved by reducing the beamlet
+weights by a factor 2**2 = 4. Choose the same W_beamlet_sum = 18 bit for both the critically
+sampled beamlet data and the oversampled beamlet data, to avoid differences in the design. The
+beamlet sum that is transported across the ring needs to fit on a 10GbE lane. With S_sub_bf = 488
+the data rate for one full band station beam is N_pol * S_sub_bf * f_sub * N_complex *
+W_beamlet_sum = 2 * 488 * 195312.5 * 2 * 18 = 6.8625 Gbps. Using L_lane = 7.8125 Gbps this leaves
+about 1 - 6.8625 / 7.8125 = 12 % margin for packet overhead, which is sufficient.
+
+
+Design descision:
+ Use W_beamlet_sum = 18 bit for both critically sampled beamlet and oversampled beamlets.
+ Using W_beamlet_sum = 18 bit fits the on one 10GbE lane on the ring, fits the input data width
+ of the FPGA hard core multipliers and also provides sufficent dynamic range to scale the final
+ beamlet sum to W_beamlet = 8 bit for output.
+
*******************************************************************************
-* Ring function
+* Ring links:
*******************************************************************************
-Ring transceiver medium access (MAC):
-Use Ethernet per transceiver link.The Ethernet MAC provides link establishment, so it uses a full duplex transceiver. The
-Ethernet packet header contains destination MAC address, source MAC address and Ethernet type. The Ethernet packet tail
-contains a CRC. The CRC provides data error detection. No need to use UDP/IP and ARP, because the links in the ring are
-point to point and will not be used in a network. The Ethernet fields can be used as:
- - Destination MAC = destination PN index
- - Source MAC = source PN index
- - Ethernet type = packet type
+OSI 1 Phyisical layer: Transceivers
+
+OSI 2 Data link layer:
+Use Ethernet per transceiver link.The Ethernet MAC provides link establishment, so it uses a full
+duplex transceiver. The Ethernet packet header contains destination MAC address, source MAC
+address and Ethernet type. The Ethernet packet tail contains a CRC. The CRC provides data error
+detection. There is no need to use UDP/IP and ARP, because the links in the ring are point to
+point and will not be used in a network. The Ethernet fields can be used as:
+
+- Destination MAC = destination PN index
+- Source MAC = source PN index
+- Ethernet type = packet type
+
Design decision: Use Ethernet for the ring transceiver links
-Ring application packet types:
+
+Use 10GbE or 40GbE:
+From the low-latency Ethernet core user guides it follows that the Ethernet core with statistics
+registers use:
+
+- 10GbE core : 4300 FF, 4 M9K
+- 40GbE core : 21200 FF, 13 M20K
+
+The synhesis fitter results from Apertif BF and XC show that the tech_eth_10g takes about 5500 FF
+and 4 (BF) or 7 (XC) M9K.The BF MAC has no statistics, the XC MAC does have statistics.
+Hence the 40GbE core is about a factor 4 larger than the 10GbE core, so from a resource usage point
+of view it is does not matter whether we use 4 x 10GbE or 1 x 40GbE. The advantage of 40GbE is
+that it can fit data rates > 10Gbps per data type stream. The advantage of using 10GbE is that we
+can use one link per data type stream and thereby avoid having to multiplex different data streams
+onto the same 40GbE link. However some multiplexing of local packets and remote transit packets can
+also be needed. UniBoard2 has been tested with 10GbE but not yet with 40GbE.
+The Arria10 on UniBoard2 has 1708800 FF so 1708800 / 182400 = 9.3 times more than the Stratix IV
+on UniBoard1. On UniBoard2 one 10GbE interface uses maximum about 5500 / 1708800 = 0.32 % of the
+FF and maximum about 7 / 2713 = 0.25% of the block RAM. In total there will be 4 x 10GbE for the
+intra board ring, 4 x 10GbE for the inter board ring and 1 x 10GbE for external IO, so these will
+take about 3% of the FF and block RAM resources.
+The packet rate is f_sub = 195312.5 Hz. At 10GbE this means that the maximum packet size is
+10e9/195312.5 = 6400 octets. For oversampled subbands the maximum packet size drops to about
+6400 / 1.25 = 5120 octets. If the minimum packet size is e.g. 4000 octets, then at 10GbE this
+means that the link cannot be fully used, whereas at 40GbE multiple packets will still fit. The
+maximum packet size for 10GbE also depends on the number of packets on the ring:
+. With one packet on the ring the maximum packet size for 10GbE is 5120 (R_os = 1.25) octets,
+. With N = 16 nodes and all nodes sending to the same end node the maximum packet size is 5120/16
+ = 320 (R_os = 1.25) octets,
+. If the packet only needs to travel N/2 nodes then the maximum packet size is 5120/8 = 640
+ (R_os = 1.25) octets.
+
+Design descision: Assume the ring will use 4 x 10GbE, because it is known technology and suitable.
+
+
+Internally in the FPGA the 10GbE data on the ring interface is available as 64 bit data at
+156.25 MHz (64 * 156.25M = 10G).
+
+
+Ring application Ethernet packet types:
The ring is used for the following application packet types:
- 0x10FB for beamlets,
@@ -63,136 +122,263 @@ The ring is used for the following application packet types:
- 0x10FD for subband offload,
- 0x10FE for transient buffer read out
-The packet type information can be transported via the Ethernet type field or via an UDP port number. If each link
-is only used for one kind of packet type, then the packet type is only used for information, because the PN
-already knows the packet type. The packet type value is based on packet types that were defined in RSP, where
-0x10FA was used to identify M&C data (0x10FA ~= LOFAR) and the other type values just increment the 0x10FA value.
+The packet type information can be transported via the Ethernet type field or via an UDP port
+number. If each lane is only used for one kind of packet type, then the packet type is only used
+for information, because the PN already knows the packet type. The packet type value is based
+on packet types that were defined in RSP, where 0x10FA was used to identify M&C data (0x10FA ~=
+LOFAR) and the other type values just increment the 0x10FA value.
+
Design decision: Transport application packet type via Ethernet type field for information
-Use UDP/IP/ETH or only ETH on the ring:
-We already have a UDP offload component that supports UDP/IP/ETH, but a similar component that only supports ETH is
-easily derived from it. With an UDP the LOFAR packet type information can be transported via the UDP port field.
-Using UDP/IP makes it easier to send the data to a PC for monitoring purposes, however it is also possible to sniff
-raw Ethernet packets on a PC. Using a PC to verify the ring allows capturing large amounts of data. On an FPGA we
-can use a data buffer to sniff the packets, but only a few.
-The extra overhead of UDP = 8 octets and IP = 20, so 28 octets in total. The disadvantage of using UDP/IP is that
-it adds some extra traffic overhead and uses some extra logic resources, but that could be acceptable. The
-disadvantage of verifying the ring using a PC are:
+
+OSI 3 Network layer: Use ring
+
+Wormhole routing (or cut-through routing) or store-and-forward routing:
+With worm hole routing a received packet or a received and modified packet is already
+transmitted, while the tail of the packet is still being received. The advantage of wormhole
+routing is that it minimizes the latency along the ring and therefore also local buffering to
+align between local and remote data. The disadvantage of wormhole routing is that a CRC error
+on the received packet needs to be propagated by forcing the CRC of the transmitted packet to be
+wrong. This implies that all subsequent hops will show this CRC error. For link diagnoses this
+is confusing, because the subsequent links did not cause the CRC error. With store-and-forward
+routing a packet is first received entirely before it is passed on for transmit. This allows to
+discard a received packet with a CRC error, but does increase the latency on the ring. Packets
+with a CRC error cannot be allowed to enter the processing in the node, because any bit in the
+packet may be corrupted, especially in the packet header, so no meaningfull processing is
+possible.
+
+Design descision:
+ For LOFAR 2.0 choose to use store-and-forward, because it allows discarding packets with CRC
+ errors when they occur and because there is sufficient internal block RAM to buffer the local
+ data for the worst case ring latency.
+
+
+Only accept correct packets:
+Discard all packets that have a CRC error. This also prevents that packets of wrong length enter
+the internal processing. The Ethernet CRC error is 32 bit, so it is very unlikely that packet with
+errors still has a correct CRC. With wormhole routing it was necessary to limit or extend a packet
+to a known fixed length, because also packets with CRC error are passed on. With store-and-forward
+routing the CRC provides sufficient protection to ensure that only correct packets enter the
+application.
+
+
+Ring latency:
+The RSP boards use wormhole routing on the ring. The latency of 1 hop between RSP boards is about
+0.2 us. The time to transmit one Ethernet frame of 1500 octets at 10Gbps is about 1.2 us and a
+jumbo frame of 6400 octets takes about 5.12 us (= T_sub). Hence for packets >~ 300 octets the
+for LOFAR2.0 SDP ring latency will be dominated by the t_store for the store-and-forward routing
+at each node. The processing uses 2 * 18 bit beamlet data. The 10GbE Ethernet MAC uses 64 bit
+data. The repacking of the beamlet data into payload data causes gaps that need to be removed
+using a fill FIFO, before the packet can be transmitted. This fill FIFO adds t_fill to the
+latency. Other latency is caused by the pipelining delay t_pipe in the FPGA and the propagation
+delay t_prop. The travel latency t_travel = t_pipe + t_fill + t_prop + t_store of one hop
+consists of:
+
+ Delay Where
+- t_pipe Tx node : pipelining processing
+- t_fill Tx node : fill the Tx FIFO sufficiently to ensure Tx of complete packet
+- t_prop Lane : propagation on lane
+- t_store Rx node : store and forward or discard
+
+Packets are transmitted at a local block grid. The assumption is that at the local block grid the
+remote Rx packet has been received, if not then it is lost and will not arrive later. The local
+block grid is set by the BSN aligner when it first achieves input alignment. This BSN alignment
+is based on the t_travel latency that occured between this node and the previous node. The
+t_travel latency can vary slightly in time and vary slightly between hops, due to the clock
+domain crossings. The variation in t_travel will be small, because only one kind of packets are
+transported per lane, so the traffic is not influenced by other streams. To account for the
+variation in t_travel a margin is needed to start a fixed local block grid with period T_sub
+for the aligned packets. The t_margin ensures that at the block grid the expected remote packet
+must have been received, and if not then it was lost.
+- t_margin Rx node : margin to align inputs
+
+The actual latency per hop is t_hop = t_travel + t_margin. The variation in t_travel is small and
+t_margin is fixed by design, so t_hop is about the same for all hops in the ring and for all
+block periods in time. Hence the total latency along N nodes in the ring is then (N-1)*t_hop.
+The dominant latencies in t_hop are t_fill and t_store. If t_hop < T_sub, then each hop will
+require one block buffering of the local input to be able to align it to the remote input. The
+total buffering for the local input is then (N-1)*P_packet.
+
+
+OSI 4 Transport layer: Use UDP/IP/ETH or only ETH on the ring:
+We already have a UDP offload component that supports DP/UDP/IP/ETH, but a similar component that
+only supports DP/ETH is easily derived from it. With an UDP the LOFAR packet type information can
+be transported via the UDP port field. Using UDP/IP makes it easier to send the data to a PC for
+monitoring purposes, however it is also possible to sniff raw Ethernet packets on a PC. Using a
+PC to verify the ring allows capturing large amounts of data. On an FPGA we can use a data buffer
+to sniff the packets, but only a few. The extra overhead of UDP = 8 octets and IP = 20, so 28
+octets in total. The disadvantage of using UDP/IP is that it adds some extra traffic overhead and
+uses some extra logic resources, but that could be acceptable. The disadvantage of verifying the
+ring using a PC are:
+
- between FPGAs on the same UniBoard the ring can only be observed on the FPGA
-- the ring will only connect FPGAs in the application, so using a PC is a side track that as such may cause extra
- work.
-Using UDP/IP does not make it possible to replace the ring by a switch without modifications, so changing from a
-ring based design to a switch based design will still imply a redesign of the data transport scheme.
-Design decision: Use raw Ethernet and verification on FPGA, because that fits the ring (especially between FPGAs
- on UniBoard2) and avoids the extra overhead of UDP/IP.
-
-Ring application header:
-The packet payload needs to have an application header to carry the timestamp and a stream identifier. This
-information can be tranported via the DP packet header which has a BSN field and a channel field. The BSN is the
-timestamp. The channel field can carry the source PN index and destination PN index. These PN indices are also
-available in the ETH source and destination MAC addresses of ETH encoded packets, but they also need to be
-available in ETH decoded packets. In ETH encoded packets the destination MAC address allow direct pass on of
-transit packets on the ring, without having to ETH decode them. In ETH decoded packets the BSN and channel fields
-can be passed along inside the encoded DP packet or in parallel with the decoded DP packet application data. The
-channel information can be used to process the remote packets in parallel e.g. per source PN index.
-
-
-
-What is the ETH packet overhead?
-The ETH packet overhead consists of:
-. Add 8 octets (c_network_eth_preamble_len) for Ethernet preamble
-. Add 14 octets for the ETH header that contains destination MAC (6), source MAC (6) and Ethernet type (2)
-. Add 2 octets to pad the ETH header to align to 8 byte word boundary
-. Add 4 octets for CRC
-. Add 12 octets (c_network_eth_gap_len) for Ethernet gap size between packets
- = 8 + 14 + 2 + 4 + 12 = 40 octets
+- the ring will only connect FPGAs in the application, so using a PC is a side track that as such
+ may cause extra work.
+
+Using UDP/IP does not make it possible to replace the ring by a switch without modifications, so
+changing from a ring based design to a switch based design will still imply a redesign of the
+data transport scheme.
+
+Design decision:
+ Use raw ETH and verification on FPGA, because that fits the ring (especially between FPGAs on
+ UniBoard2) and avoids the extra overhead of UDP/IP.
+
+
+Ring application header DP/ETH:
+The packet payload needs to have an application header to carry the timestamp and a stream
+identifier. This information can be tranported via the DP packet header which has a BSN field and
+a channel field. The BSN is the timestamp. The channel field can carry the source PN index and
+destination PN index. These PN indices are also available in the ETH source and destination MAC
+addresses of ETH encoded packets, but they also need to be available in ETH decoded packets. In
+ETH encoded packets the destination MAC address allow direct pass on of transit packets on the
+ring, without having to ETH decode them. In ETH decoded packets the BSN and channel fields can be
+passed along inside the encoded DP packet or in parallel with the decoded DP packet application
+data. The channel information can be used to process the remote packets in parallel e.g. per
+source PN index. The channel information can also provide flagging information, to e.g. identify
+filler packets.
+
+Design decision:
+ Use DP/ETH. Together the CP CRC and ETH CRC ensure that for the lifetime of LOFAR2.0 packets
+ with correct CRC will not have false positives. Use a bit in the channel field to indicate
+ filler packets.
+
+
+What is the DP/ETH packet overhead?
+
+- The ETH packet overhead consists of:
+ . Add 8 octets (c_network_eth_preamble_len) for Ethernet preamble
+ . Add 14 octets for the ETH header that contains destination MAC (6), source MAC (6) and
+ Ethernet type (2)
+ . Add 2 octets to pad the ETH header to align to 8 byte word boundary
+ . Add 4 octets for CRC
+ . Add 12 octets (c_network_eth_gap_len) for Ethernet gap size between packets
+ = 8 + 14 + 2 + 4 + 12 = 40 octets
+- The DP packet overhead consists of (dp_packet_enc_crc / dp_packet_dec_crc):
+ . Add 4 octects for CHAN (32b)
+ . Add 8 octects for Sync & BSN (64b)
+ . Add 4 octects for ERR (32b)
+ . Add 4 octects for CRC (32b)
+ = 4 + 8 + 4 + 4 = 20 octets
+
+Design decision: The DP/ETH packet overhead is P_overhead = 60 octets.
+
+
+Use one packet type per ring lane:
+This avoids having to multiplex different packet types onto a single lane. Still the Ethernet type
+can be used to fill in the packet type to more easily identify data on different lanes of the ring.
How many transceivers are needed for the ring?
-There are four data types beamlets, crosslets, subband offload and transient buffer read out. The data loads are:
-- 488 beamlets (R_os = 1 --> W_beamlet_sum = 24 bit, R_os = 1.25 --> W_beamlet_sum = 19.2 ~= 20 bit)
+The ring uses 4 of the 12 available transceivers, to match the QSFP cable link that is needed to
+connect the ring between UniBoard2.
+There are four data types beamlets, crosslets, subband offload and transient buffer read out. The
+data loads are:
+- 488 beamlets (R_os = 1 --> W_beamlet_sum = 18 bit, R_os = 1.28)
- ~10 crosslets (R_os = 1 --> 15 crosslets, R_os = 1.25 --> 12 crosslets)
-- ~ subbands (R_os = 1
--
+- subbands (R_os = 1
+- << 10Gbps transient buffer data
+
+
+Link monitoring:
+The link should be monitored during normal operation and to avoid the need to define and control a
+test packet (e.g. like ping). The link monitoring should directly identify the source of a error
+(e.g. tx node, link, rx node).
+Design decision: Use DP/ETH packets to monitor the link quality.
+
-Choose to transport one data type packet per 10GbE link direction.
+*******************************************************************************
+* Ring usage:
+*******************************************************************************
+
+OSI 5 Session layer:
+OSI 6 Presentation layer:
+OSI 7 Application layer:
-The ring can be used in both directions. The forward direction is e.g. from PN0 to 15, the backward direction is e.g.
-from PN 15 to 0. The ring uses 4 of the 12 available transceivers, to match the QSFP cable link that is needed to connect
-the ring between UniBoard2.
The ring function has the following sub functions:
- Receive packets from ring (and remove CRC field)
- Discard incorrect packets (based on CRC)
-- Pass on transit packets (Destination MAC > PN index for forward ring, MAC < PN index for backward ring)
+- Pass on transit packets (Destination MAC > PN index for forward ring, MAC < PN index for backward
+ ring)
- Decode packets (get packet from ring for internal use)
- Encode packets (put internal packet onto ring)
- Multiplex local and transit packets
- Transmit packets onto ring
+- Monitor Rx and Tx packets
+- Align packets for processing (use filler data on inputs with lost packets)
+
+
+Ring access and transport schemes:
+
+- 1) ring combiner scheme: start node sends packet to end node, intermediate nodes modify the
+ packet (= combine local with remote).
+- 2a) ring endcast scheme: each node starts sending its packets to an end node (= end cast),
+ intermediate nodes pass on the packet
+- 2b) ring multicast scheme: each node starts sending its packets to an end node, intermediate
+ nodes pass on the packet and use the packet (= multi cast)
+
+If both scheme 1 and 2 are suitable, then scheme 1 typically yields a larger payload, because it
+reserves slots for all nodes, whereas the payload for scheme 2 only contains data from one node.
+Scheme 1 and 2b are useful if the transit nodes also use or modify the packet data. The multiple
+hops are then used to multi cast the data. Scheme 2a is suitable for packet transport from start
+to end node, whereby transit nodes only pass on the packet.
+
+For the beamformer beamlets scheme 1 is most suitable. The start node prepares the packet with
+the initial beamlet sums. The subsequent nodes add there local beamlet sum to the packet
+beamlet sums and then pass on the packet.
+
+For the subband correlator both scheme 1 and scheme 2b are suitable. For scheme 1 the start node
+creates a packet with slots for all nodes and fills in its own slot with its crosslets. Scheme 1
+was used in LOFAR 1.0. The subsequent nodes fill in their slots with their crosslets and also
+use the packets to correlate the remote crosslets with their local crosslets. With scheme 2b
+each node creates a packet with its own crosslets and sends it to N/2 nodes further. The
+intermediate node pass on or remove the packets and use the packets to correlate the remote
+crosslets with their local crosslets. The disadvantage of scheme 1 is that it requries a
+dedicated start node that initiates the aggregate packet. With scheme 2b each node acts as start
+node for its own packet. Intermediate nodes use the remote packets for correlation and pass
+them on. The final destination node removes the packet.
+
+For the subband offload both scheme 1 and scheme 2a are suitable. For scheme 1 the start node
+creates a packet with slots for all nodes and fills in its own slot with its subbands. The
+subsequent nodes fill in their slots with their subbands. With scheme 2a each node creates a
+packet with its own subbands and sends it to the output end node. The other nodes only pass on
+the remote packets.
+
+For transient buffer read out scheme 2a is most suitable to gather the read out data from each
+node at the output end node.
-Use 10GbE or 40GbE:
-From the low-latency Ethernet core user guides it follows that the Ethernet core with statistics registers use:
- 10GbE core : 4300 FF, 4 M9K
- 40GbE core : 21200 FF, 13 M20K
-The synhesis fitter results from Apertif BF and XC show that the tech_eth_10g takes about 5500 FF and 4 (BF) or 7 (XC) M9K.
-The BF MAC has no statistics, the XC MAC does have statistics.
-Hence the 40GbE core is about a factor 4 larger than the 10GbE core, so from a resource usage point of view it is does not matter
-whether we use 4 x 10GbE or 1 x 40GbE. The advantage of 40GbE is that it can fit data rates > 10Gbps per data type stream. The
-advantage of using 10GbE is that we can use one link per data type stream and thereby avoid having to multiplex different data
-streams onto the same 40GbE link. However some multiplexing of local packets and remote transit packets can also be needed.
-UniBoard2 has been tested with 10GbE but not yet with 40GbE.
-The Arria10 on UniBoard2 has 1708800 FF so 1708800 / 182400 = 9.3 times more than the Stratix IV on UniBoard1. On UniBoard2 one
-10GbE interface uses maximum about 5500 / 1708800 = 0.32 % of the FF and maximum about 7 / 2713 = 0.25% of the block RAM.
-In total there will be 4 x 10GbE for the intra board ring, 4 x 10GbE for the inter board ring and 1 x 10GbE for external IO, so
-these will take about 3% of the FF and block RAM resources.
-The packet rate is f_sub = 195312.5 Hz. At 10GbE this means that the maximum packet size is 10e9/195312.5 = 6400 octets. For
-oversampled subbands the maximum packet size drops to about 6400 / 1.25 = 5120 octets. If the minimum packet size is e.g. 4000
-octets, then at 10GbE this means that the link cannot be fully used, whereas at 40GbE multiple packets will still fit. The
-maximum packet size for 10GbE also depends on the number of packets on the ring:
-. With one packet on the ring the maximum packet size for 10GbE is 5120 (R_os = 1.25) octets,
-. With N = 16 nodes and all nodes sending to the same end node the maximum packet size is 5120/16 = 320 (R_os = 1.25) octets,
-. If the packet only needs to travel N/2 nodes then the maximum packet size is 5120/8 = 640 (R_os = 1.25) octets.
-Design descision: Assume the ring will use 4 x 10GbE, because it is known technology and suitable.
-
+Ring access directions:
+The ring can be used in both directions. The forward direction is e.g. from PN0 to 15, the
+backward direction is e.g. from PN 15 to 0 for N = 16 nodes.
+All schemes can be used in two directions for the same type of data transport. In one direction
+the maximum number of hops between start and end node is N-1, while by using both directions the
+maximum number of hops between start and end node is N/2. If the data is used on all intermediate
+nodes, then there is no advantage to use the ring in both directions. If the data is only passed
+along by intermediate nodes, then the link capacity is used about a factor two more efficiently
+by sending data in both directions. Disadvantages of using the ring in both directions for the
+same type of data are that each node needs to decide which direction to use, that the data arrives
+from both directions at the end node, and that it is somewhat more difficult to understand and
+diagnose.
-Use one packet type per ring link.
-This avoids having to multiplex different packet types onto a single link. Still the Ethernet type can be used to fill
-in the packet type to more easily identify data on different links of the ring.
+Design decision : Therefore choose to use the ring in only one direction per link.
-Use application packets to monitore the link quality:
-This allows monitoring the link during normal operation and avoids the need to define and control a test packet (e.g.
-like ping).
-Wormhole routing or store-and-forward routing:
-With worm hole routing a received packet or a received and modified packet is already transmitted, while the tail of
-the packet is still being received. The advantage of wormhole routing is that it minimizes the latency along the ring
-and therefore also local buffering to align between local and remote data. The disadvantage of wormhole routing is
-that a CRC error on the received packet needs to be propagated by forcing the CRC of the transmitted packet to be
-wrong. This implies that all subsequent hops will show this CRC error. For link diagnoses this is confusing, because
-the subsequent links did not cause the CRC error. With store-and-forward routing a packet is first received entirely
-before it is passed on for transmit. This allows to discard a received packet with a CRC error, but does increase the
-latency on the ring. For LOFAR 2.0 choose to use store-and-forward, because it allows discarding packets with CRC
-errors when they occur and because there is sufficient internal block RAM to buffer the local data for the worst case
-ring latency.
+Use one link per packet type:
+For scheme 2 use only one link for all source nodes, so do not let different source nodes use
+different links. For N/2 = 8 or N = 16 the number of links would become too large. By using one
+link for all sources, increasing the processing becomes a matter of using and instantiating more
+links.
-Ring latency:
-The latency of 1 hop is about 0.2 us. The time to transmit one Ethernet frame of 1500 octets at 10Gbps is about 1.2 us
-and a jumbo frame of 6400 octets takes about 5.12 us (= T_sub). Hence for packets >~ 300 octets the ring latency is
-dominated by the store and forward routing at each node. The 10GbE Ethernet MAC uses 64 bit data. At 200 MHz this can
-achieve 64 * 0.2 = 12.8 Gbps. Hence if the processing operates without data valid gaps, then the Ethernet transmit
-will not run empty during a payload. Therefore it is not necessary to use a fill FIFO, which would add to the ring
-latency. For a packet that travels the entire ring the latency is then about (N-1) * T_sub and the corresponding
-FIFO depth to align the local data with this remote data is (N-1) * packet size.
+Remote and local data alignment:
+In APERTIF the data arrived from >= 2 remote streams. With the LOFAR ring there is always local
+data that arrives first and needs to be aligned with only one remote data stream. The local data
+needs to be buffered until the remote data from the farthest PN has arrived. The latency on the
+ring is about 1 packet per transit hop, due to the store-and-forward. The first hop has negligible
+latency. Hence with H hops the local data buffer size needs to be (H-1) * local data size.
-Only accept correct packets:
-Discard all packets that have a CRC error. This also prevents that packets of wrong length enter the internal
-processing. The Ethernet CRC error is 32 bit, so it is very unlikely that packet with errors still has a
-correct CRC. With wormhole routing it was necessary to limit or extend a packet to a known fixed length, because
-also packets with CRC error are passed on. With store-and-forward routing the CRC provides sufficient protection
-to ensure that only correct packets enter the application.
Ring data transport schemes:
- beamlets on ring: l --> r+l --> r+l --> ... --> r+l
@@ -200,13 +386,10 @@ Ring data transport schemes:
. output filler data if remote got lost, to preserve nominal output rate to CEP
- crosslets on ring: rrrrrrrr,l --> rrrrrrrr,l --> ... --> rrrrrrrr,l
- . on each node separately align N/2 pairs of inputs l,r, have one pair per XC cell
- or
- . on each node first align all inputs l,N/2*r, and then split into N/2 pairs of l,r to have one pair per XC cell
- . discard output data if remote got lost, to count number of active blocks per integration sync interval
- or
- output filler data if remote got lost, and use zero to not disturb the intergation and count unflagged blocks
- to know the number of active blocks per integration sync interval
+ . on each node first align all inputs l,N/2*r, and then split into N/2 pairs of l,r to have one
+ pair per XC cell (or on each node separately align N/2 pairs of inputs l,r, have one pair per
+ XC cell). output filler data if remote got lost, and use zero to not disturb the intergation
+ and count unflagged blocks to know the number of active blocks per integration sync interval.
- subbands on ring: l, rl, rrl, rrrl, ..., rrrrrrrrrrrrrrrl
. on final node align all l,(N-1)*r inputs
@@ -216,56 +399,6 @@ Ring data transport schemes:
. no align, readout from one node at a time
-Ring access schemes:
-
-- 1) start node sends packet to end node, intermediate nodes modify the packet.
-- 2a) each node starts sending its packets to an end node, intermediate nodes pass on the packet
-- 2b) each node starts sending its packets to an end node, intermediate nodes pass on the packet and use the packet (= multi cast)
-
-If both scheme 1 and 2 are suitable than scheme 1 typically yields a larger payload, because it reserves slots for all
-nodes, whereas the payload for scheme 2 only contains data from one node. Scheme 1 and 2b are useful if the transit nodes
-also use or modify the packet data. Scheme 2a is suitable for packet transport from start to end node, whereby transit
-nodes only pass on the packet.
-
-For the beam former beamlets scheme 1 is most suitable. The start node prepares the packet with the initial beamlet sums.
-The subsequent nodes add there local beamlet sum to the packet beamlet sums and then pass on the packet.
-
-For the subband correlator both scheme 1 and scheme 2b are suitable. For scheme 1 the start node creates a packet with
-slots for all nodes and fills in its own slot with its crosslets. Scheme 1 was used in LOFAR 1.0. The subsequent nodes fill in
-their slots with their crosslets and also use the packets to correlate the remote crosslets with their local crosslets.
-With scheme 2b each node creates a packet with its own crosslets and sends it to N/2 nodes further. The intermediate node
-pass on the packets and use the packets to correlate the remote crosslets with their local crosslets.
-
-For the subband offload both scheme 1 and scheme 2a are suitable. For scheme 1 the start node creates a packet with slots for all
-nodes and fills in its own slot with its subbands. The subsequent nodes fill in their slots with their subbands. With scheme 2a
-each node creates a packet with its own subbands and sends it to the output end node. The other nodes only pass on the remote packets.
-
-For transient buffer read out scheme 2a is most suitable to gather the read out data from each node at the output end node.
-
-
-Ring access directions:
-All schemes can be used in two directions for the same type of data transport. In one direction the maximum number
-of hops between start and end node is N-1, while by using both directions the maximum number of hops between start
-and end node is N/2. If the data is used on all intermediate nodes, then there is no advantage to use the ring in
-both directions. If the data is only passed along by intermediate nodes, then the link capacity is used
-about a factor two more efficiently by sending data in both directions. Disadvantages of using the ring in both
-directions for the same type of data are that each node needs to decide which direction to use, that the data
-arrives from both directions at the end node, and that it is somewhat more difficult to understand and diagnose.
-Design decision : Therefore choose to use the ring in only one direction per link.
-
-Use one link per packet type:
-For scheme 2 use only one link for all source nodes, so do not let different source nodes use different links. For
-N/2 = 8 or N = 16 the number of links would become too large. By using one link, increasing the processing becomes
-a matter of using and instantiating more links.
-
-
-Remote and local data alignment:
-In APERTIF the data arrived from >= 2 remote streams. With the LOFAR ring there is always local data that arrives
-first and needs to be aligned with only one remote data stream. The local data needs to be buffered until the remote
-data from the farthest PN has arrived. The latency on the ring is about 1 packet per transit hop, due to the store
-and forward. The first hop has negligible latency. Hence with H hops the local data buffer size needs to be (H-1) *
-local data size. When the remote data arrive the local data is popped from the buffer. It the remote data has not
-arrived in time, then the local data is popped from the buffer when the next local data is pushed into the buffer.
*******************************************************************************
@@ -273,249 +406,278 @@ arrived in time, then the local data is popped from the buffer when the next loc
*******************************************************************************
What is the beamlet packet size?
-The beamlet sum is passed on along the ring from start PN to end PN using ring access scheme 1. At the end PN the
-final beamlet sum is scaled to W_beamlet = 8 bit and output to CEP. The intermediate beamlet sum has W_beamlet =
-18 bit and is complex. There are N_pol * S_sub_bf = 2 * 488 = 976 beamlets per packet. The payload size is
-N_pol * S_sub_bf * N_complex * W_beamlet_sum / W_byte = 2 * 488 * 2 * 18 / 8 = 4392 octets. The effective packet
-size is 40 + 4392 = 4432 octets. With f_sub = 195312.5 Hz and R_os = 1.28 the data rate is 4432 * 195312.5 * 1.28
-* 8 = 8.864 Gbps, which fits on a 10GbE link.
+The beamlet sum is passed on along the ring from start PN to end PN using ring access scheme 1. At
+the end PN the final beamlet sum is scaled to W_beamlet = 8 bit and output to CEP. The intermediate
+beamlet sum has W_beamlet = 18 bit and is complex. There are N_pol * S_sub_bf = 2 * 488 = 976
+beamlets per packet. The payload size is N_pol * S_sub_bf * N_complex * W_beamlet_sum / W_byte =
+2 * 488 * 2 * 18 / 8 = 4392 octets. The effective packet size is 60 + 4392 = 4452 octets. With
+f_sub = 195312.5 Hz the data rate is 4452 * 195312.5 * 8 = 6.95625 Gbps < L_lane = 7.8125, so it
+fits on a 10GbE lane.
Packet decoding and encoding:
-The start node encodes the packet and the end node decodes the packet. The intermediate nodes could operate on
-the encoded packet, however the payload beamlets are packed into bytes and are not word aligned. Therefore the
-intermediate nodes also need to decode the packet to be able to update the payload data, and then encode the
-packet. The decode and encode function is available in any node, because all nodes run the same firmware image.
-Therefore the decoding and encoding at intermediate nodes can reuse the encoding function of the start node and
-the decode function of the end node, so no extra logic is needed.
+The start node encodes the packet and the end node decodes the packet. The intermediate nodes could
+operate on the encoded packet, however the payload beamlets are packed into bytes and are not word
+aligned. Therefore the intermediate nodes also need to decode the packet to be able to update the
+payload data, and then encode the packet again. The decode and encode function is available in any
+node, because all nodes run the same firmware image. Therefore the decoding and encoding at
+intermediate nodes can reuse the encoding function of the start node and the decode function of the
+end node, so no extra logic is needed.
Ring adder payload processing:
-The station beam is a dual polarization beam and each beam has S_sub_bf = 488 beamlets, so in total there are
-976 complex beamlets per subband period of N_fft = 1024 cycles @ 200 MHz. For an oversampled filterbank with
-R_os = 4/3 there are N_fft / R_os = 768 cycles @ 200 * R_os MHz. Hence to be compatible with an oversampled
-filter bank the beamformer cannot process all 976 beamlets in series, instead it has to apply ceil(R_os) = 2
-streams in parallel that each process 488 beamlets. Therefore to support the oversampled beamlets the paylaod
-needs to be encoded from and decoded to two streams of beamlets:
-
- 0 : 0 2 4 ............. 974
- 1 : 1 3 5 ............. 975
-
-The 10Gbps data on the ring interface is available as 32 bit data at 312.5 MHz (32 * 312.5M = 10G).
+The full band station beam has S_sub_bf = 488 beamlets per polarization, so in total there are
+N_pol * S_sub_bf = 2 * 488 = 976 complex beamlets per subband period of N_clk = 1024 cycles. The
+ring adder adds the local beamlet sum to the received beamlet sum and passes on the result.
+The beamlet sum is received as a packet with 64 bit packed data at 156.25 MHz (64 * 156.25M =
+10G). The 976 beamlets fit in 976 * 18b * 2 / 64b = 549 64b words. The packet header and tail
+overhead is P_overhead = 60 octets, so about 8 64b words and thus the effected packet size is
+P_packet = 8 + 549 = 557 64b words.
+
+ . from 10GbE MAC -->
+ . @ 156MHz Rx packet 64b --> Rx FIFO from Rx domain to DP domain -->
+ . @ 200MHz Rx packet 64b --> DP/ETH decode to discard or extract payload of 549 words-->
+ . @ 200MHz Rx payload 64b --> repack 549 words to 976 beamlets -->
+ . @ 200MHz Align remote and local beamlets -->
+ . @ 200MHz Sum remote and local beamlets --> repack 976 beamlets to 549 words -->
+ . @ 200MHz Tx payload 64b --> DP/ETH encode to add header and tail -->
+ . @ 200MHz Tx packet 64b --> Tx fill FIFO from DP domain to Tx domain -->
+ . @ 156MHz Tx packet 64b -->
+ . to 10GbE MAC
+
+
+The DP/ETH encoding and decoding is done in the DP domain, because the Rx meta information is
+needed there and the Tx meta information is available there. The DP/ETH decoding first validates
+the ETH CRC (that was checked by the 10GbE MAC) and the DP CRC (that is checked by the DP
+decoding). Both CRC are validate using the same input store-and-forward buffer, so that the Rx
+packet only needs to be buffered once. If both CRC are correct then, the Rx payload is released
+from the store-and-forward buffer, else it is discarded. The released payload is then repacked
+to obtain the remote beamlets. The remote beamlets are then aligned to the local beamlets and
+summed. The summed beamlets are repacked to 64b data and then DP/ETH encoded. The DP encoding
+adds the DP CRC and the 10GbE MAC will add the ETH CRC.
+
+In the DP domain, at 200 * R_os MHz, there are N_clk = 1024 cycles available to process the
+packet. The clock domain crossing from Rx 156M to DP 200M causes gaps in the data, but these gaps
+are not sufficient (or equivalently, the DP clock is not fast enough) to perform the Rx repacking
+from 64b to 2*18b beamlets, because r = 200/156.25 * 36/64 = 0.72 < 1. Hence effectively the DP
+rate is a factor r slower than the Rx rate. Therefore the Rx repacking needs to apply
+backpressure that can be accepted by the Rx FIFO. When the Rx packet has been received, the DP
+processing will have accepted a fraction r of it, so the Rx FIFO will fill up to about
+(1-r) * P_packet = (1 - 0.72) * 557 = 156 64b words and then run empty again after the last 64b
+word was received. The processing of the beamlets occurs without gaps. However the Tx repacking
+from 2*18b beamlets to 64b does cause gaps, and these gaps in the DP domain are too many (or
+equivalently, the DP clock is too slow) to perform continuous packet transmission in the Tx
+domain, because r < 1. Therefore the clock domain crossing Tx FIFO needs to use a fill FIFO.
+The Tx FIFO will first need to be filled by about (1-r) * P_packet = (1 - 0.72) * 557 = 156 64b
+words, before the Tx can start to ensure that the packet is transmitted without gaps.
+Note that (1/r - 1)/(1/r) = (1-r)/1 = 1-r, so defining r or 1/r does not matter.
+
+The travel latency per hop t_travel can be expressed in DP clock cycles at 200 MHz by:
+- The latency of one hop between RSP boards is a good estimate of the sum of the pipelining and
+ propagation, so t_pipe + t_prop ~= 0.2 us, or 40 clock cycles.
+- The latency of the store-and-forward buffer is t_store ~= 557 / 156.25M = 3.6 us, or 713 clock
+ cycles
+- The latency of the Tx fill FIRO is t_fill ~= 156 / 156.25M = 1.0 us, or 200 clock cycles.
+Hence t_travel = 40 + 713 + 200 = 953 clock cycles, so using t_margin = 1024 - 953 = 71 would
+allow the beamformer ring to only have to buffer one block per hop. The t_margin must not be set
+too small, because then an Rx packet may be considered lost, while it is still just about to
+arrive. The minimal local input buffering occurs for t_margin = 0. Instead of N-1 blocks the
+buffer then needs to fit (N-1) * 953 / 1024 blocks. For N = 16 this would save one block, which
+is only 953/1024 = 7% so negligible.
+
+
+? Does align belong to ring or to beamlet ring adder?
+--> to beamlet ring adder:
+ - to avoid having an align input and output on the ring interface.
+ - implies that align monitor also belongs to beamlet ring adder
+? Does sum belong to ring or to beamlet ring adder or to local beamformer?
+--> to beamlet ring adder:
+ - it deserves a dedicated block, because it is art of the BF (so not of the ring) and it only
+ adds (so does not have BF weigths like the local BF).
+
+
+BF BSN aligner input buffer size:
+The local subband data needs to be buffered until the beamlet sum arrives. The size of the buffer
+is determined by last node, because then the beamlet sum has travelled N-1 hops. Assume that
+t_hop = T_sub, so buffering one local block per hop and one extra block is sufficient to
+compensate for the latency along the ring. This yields an input buffer size of K = N = 16
+blocks, so K * N_pol * S_sub_bf * N_complex * W_subband = 16 * 2 * 488 * 2 * 18 = 562176 bit,
+which takes about 32 M20k block RAMs. The BSN aligner for the beamlet ring adder has two inputs,
+so it will use 2 * 32 = 64 M20k block RAMs.
+
+
+What if a packet gets lost?
+The local beamlets cannot get lost, but remote packets may get lost. The BSN aligner will replace
+lost remote packets with filler packets that are flagged. The beamlets in the filler packets
+contain zero data, so in the beamformer they do not contribute to the beamlet sum and the beamlet
+sum that is passed on only contains the local beamlet values. Hence a lost packet results in an
+incomplete station beam. The incomplete beamlet sum is passed on along the ring, to preserve the
+nominal line rate at the subsequent hops (i.e. to avoid propagation of the lost packet). However,
+the incomplete beamlet sum must be flagged via a bit in the DP channel field. At the final node
+The flagged incomplete beamlet sum is send to CEP, to preserve the nominal line rate. At CEP the
+flagged incomplete beamlet data has to be discarded, because the shape and gain of the incomplete
+beam then differs, dependent on where on the ring the packet got lost.
+
-Local beamlet sums FIFO size:
-The local subband data needs to be buffered until the beamlet sum arrives. The last node experiences the largest
-latency, because then the beamlet sum has travelled N-1 hops, each adding about 5888 * 8 / 10G = 4.71 us. The
-total latency for the LBA ring is (16 - 1) * 4.71 us = 70.6 us or about 14 T_sub. With some extra margin assume
-that the last N-1 or N local beamlets need to be buffered. Per PN this yields a FIFO size of N_pol * S_sub_bf *
-N * N_complex * W_subband = 2 * 488 * 16 * 2 * 18 = 562176 bit, which takes about 32 M20k block RAMs.
Ring modes:
- off
- local
- remote
- combine
-With dp_bsn_align all these modes are supported by enabling/disabling the corresponding inputs.
-
-FIFO flush:
-A FIFO can be flushed by resetting it, but this requires careful control to ensure that the reset is noticed
-in both clock domains, and that the reset is applied in between input packets to avoid that only a tail
-of a packet gets into a FIFO. Therefore in LOFAR 1.0 and APERTIF a FIFO is flushed by reading the packets
-from it until it is empty. This scheme also allows flushing per packet. The disadvantage of reading the
-packets and the discard them, is that it takes as long as reading at full speed.
-
-Lost remote packet detection:
-Local FIFO full:
-The local FIFO needs to buffer the local data to be able to align with the remote data. The latency between
-nodes depends on the number of hops. With N = 16 nodes and store and forward packet transport the maximum
-latency will be < N * T_sub. To compensate for this latency the local FIFO needs to be able to store at most
-about N local packets. If the FIFO runs full, then this is an indicator that remote packets got lost and
-then the local FIFO needs to be flushed until it is empty.
-Rx timeout:
-The average packet rate on the ring is f_sub, so within T_sub there should arrive a new packet. If no packet
-arrives within T_sub, then the local FIFO can flush one packet. In this way the local FIFO does not need to
-be flushed until empty and less packets will get lost once the remote packets arrive again. Using Rx timeout
-does rely on that packets fit within a T_sub interval and that every T_sub interval contains at least part
-of a packet, so the actual packet rate must be close to the average packet rate.
-
-
-Remote packets:
-The remote packets drive the ring adder and are processed on arrival. The local packet with the same time stamp
-is already pending in the local beamlets FIFO. If a burst of remote packet gets lost, then the node will
-notice this because its local beamlets keep arriving and will overflow the local beamlets FIFO. The node will
-read and discard packets from the local beamlets FIFO to make sure that the FIFO does not overflow. If only
-one or a few remote packets got lost, then the node will noticethis during the time stamp alignment, but
-only as soon as the next packet has arrived. This next packet will be ahead of the local packet, so the local
-packets need to be flushed. The node will then read and discard packets from the local beamlets FIFO until it
-can align the remote and local data. During this realignment process the next remote packet may already arrive
-as well. Therefore the remote packet needs to be buffered, or discarded. Assume the FIFO is flushed by reading
-and then discarding packets from it. The local packets and the remote packets arrive at the same rate. If the
-flushing of the packets goes faster then reading them, because flushing can use all clock cycles. The flushing
-can only catch up if the gaps between packets are large enough. Therefore in LOFAR 1.0 the remote packets were
-discarded during the flushing. This does mean that when one packet gets lost, the flushing will also discard
-the next packet and some more for as long as it takes to empty the local beamlets FIFO. An alternative would
-be to keep on flushing and discarding remote packets, until the local beamlet FIFO is again ahead of the
-remote packets. Typically packets will get lost rarely or in bursts. In both cases it is fine to just flush
-the local beamlet FIFO until it is empty.
-
- PN0 PN1 PN2 PN3 PN4
-t
-0: L0 L1 L2 L3 L4 <-- S_sub_bf = 488 beamlets (dual pol complex) per packet
- R4 R0 R1 R2 R3
- R3 R4 R0 R1 R2
+
+With dp_bsn_align_v2 all these modes are supported by enabling/disabling the corresponding inputs.
+
The beamformer function has the following sub functions:
- "Beamlet subband select" : Select S_sub_bf = 488 subbands per signal input
-- "Local beamformer" : Form N_pol * S_sub_bf = 2 * 488 = 976 local beamlet sums for S_pn = 12 signal inputs
+- "Local beamformer" : Form N_pol * S_sub_bf = 2 * 488 = 976 local beamlet sums for S_pn = 12
+ signal inputs
- "Beamlet ring adder" :
- if start node:
- - Encode beamlet sums packet to ring
- else:
- - Buffer the local beamlet sums for >= N subband intervals
- - Decode remote beamlet sums packet from ring
- - Align remote beamlet sums packet and local beamlet sums packet
- - Add local beamlet sums to remote beamlet sums packet
- if transit node:
- - Encode beamlet sums packet to ring
- else:
- - "Beamlet data output" : Scale and output beamlet sums
-- "Beamlet statistics (BST)": Calculate BST
+ if start node:
+ - Encode local beamlet sums packet to ring
+ else:
+ - Buffer the local beamlet sums for ~= N subband intervals
+ - Decode remote beamlet sums packet from ring
+ - Align remote beamlet sums packet and local beamlet sums packet
+ - Add local beamlet sums to remote beamlet sums packet
+ if transit node:
+ - Encode beamlet sums packet to ring
+ else:
+ - "Beamlet data output" : On output node scale and output final beamlet sums
+- "Beamlet statistics (BST)": Calculate BST for beamlet sums, output node has final BST
+
*******************************************************************************
* Subband Correlator
*******************************************************************************
-Crosslet transport scheme:
-Use transport scheme 2b with N/2 hops where every node sends its local crosslets N/2 hops. The remote crosslets
-are correlated with the local crosslets. The remote crosslets arrive in packets from the N/2 preceding nodes.
-First the local crosslets are correlated with themselves and then the local crosslets are kept in a barrel shifter,
-such that they can also be correlated with the remote crosslets that arrive in the packets.
-- count N_int for monitoring
+With transport scheme 1 crosslets from different source nodes are combined into one packet.
+Scheme 2b packs only local crosslets into a packet. Compared to scheme 1, scheme 2b:
+- treats the local crosslets and remote crosslets independently
+- has small payload and thus more packet overhead, but the packet load still fits on a lane
+- has small payload that can be enlarged by transporting more local crosslets, to support
+ a subband correlator with N_crosslets > 1 per integration interval.
+Design decision:
+ Use transport scheme 2b with N/2 hops where every node sends its local crosslets N/2 hops,
+ because it is more flexible to have only local crosslets per packet.
-Square correlator cell:
-There are S_pn = 12 local crosslets. A packet contains S_pn = 12 remote crosslets. There are N/2 remote crosslet
-packets. The local crosslets have to be correlated with the local crosslets and with each of the remote crosslet
-packets. The correlation with the local crosslets is a square matrix that yields X_sq = S_pn * S_pn = 144 visibilities.
Number of square correlator cells per PN:
-With N = 16 PN for LBA there are N/2 = 8 remote crosslet packets. Hence together with the local crosslet visibilities
-this yields X_pn = (N/2 + 1) * X_sq = (8 + 1) * 144 = 1296 visibilities per PN.
-
-Crosslet period:
-The subband correlator needs to finished within one subband period, so T_xc < T_sub. For the critically sampled
-filterbank the subband period is N_fft = 1024 sample periods. The X_pn = 1296 visibililies per PN can be
-caluculated using one complex multiplier if the multiplier runs at 1296 / 1024 * 200 M > 253 MHz. For an oversampled
-filterbank with R_os <= 1.25 this requires 1.25 * 253 = 317 MHz, which may be too much.
-
-Time in diagrams:
-- equal time for all PN in same row and in same relative column
-- left to right time in time slot
-- top to bottom time slots
-
- PN0 PN1 PN2 PN3 PN4
-t
-0: L0 L1 L2 L3 L4 <-- S_pn = 12 crosslets (single pol complex subband) per packet
- R4 R0 R1 R2 R3
- R3 R4 R0 R1 R2
- <-- T_sub > latency on ring
-1: L0 L1 L2 L3 L4
- R4 R0 R1 R2 R3
- R3 R4 R0 R1 R2
-
-2: ...
- For every slot intergate
- 00 11 22 33 44 <-- XST first LL at each PN upon L arrival
- 04 10 21 32 43 <-- XST then LR at each PN upon R arrival with L in barrel
- 03 14 20 31 42 <-- XST then LR at each PN upon R arrival with L in barrel
-
-N_int-1: <-- Dump and restart XST:
-
- 0 00 10 20 * *
- 1 - 11 21 31 *
- 2 - - 22 32 42
- 3 03 - - 33 43
- 4 04 14 - - 44
- 0 1 2 3 4
-
- * is obtained via conj()
- - not calculated because conj()
-
+There are S_pn = 12 local crosslets. A packet contains S_pn = 12 remote crosslets. There are N/2
+remote crosslet packets. The local crosslets have to be correlated with the local crosslets and
+with each of the S_lba - S_pn remote crosslet packets. The correlation with the local crosslets
+is a square matrix that yields X_sq = S_pn * S_pn = 144 visibilities. For the local-local square
+correlator cell the efficiency is (S_pn * (S_pn+1)) / 2 / X_sq = 54%, but for the N/2 other
+local-remote square correlator cells the efficiency is 100 %. With N = 16 PN for LBA there are
+N/2 = 8 remote crosslet packets. Hence together with the local crosslet visibilities this yields
+X_pn = (floor(N/2) + 1) * X_sq = (8 + 1) * 144 = 1296 visibilities per PN. In total the subband
+correlator calculates N * X_pn = 16 * 1296 = 20736 visibilities. There are
+S_lba * (S_lba + 1)/2 = 192 * 193 / 2 = 18528 unique visibilities. The difference 20736 - 18528
+- 2208 is due to that:
+
+. for any N the N * S_pn*(S_pn-1)/2 = 16 * 12*11/2 = 1056 local-local visibilities are calculated
+ twice
+. for N is even floor(N/2) * S_pn*S_pn = 16/2 * 12*12 = 1152 local-remote visibilities are
+ calculated twice. For N is odd the local-remote visibilities are only calculated once.
+
+and to check 1056 + 1152 = 2208 indeed.
+
+
+
+Number of multipliers per crosslet:
+The subband correlator needs to finished within one subband period, so within N_fft = 1024 clock
+cycles. The X_pn = 1296 visibililies per PN can be caluculated using one complex multiplier if
+the complex multiplier runs at 1296 / 1024 * 200 M > 253 MHz. For an oversampled filterbank with
+R_os <= 1.28 this requires 324 MHz, which is too much. All X_pn = 1296 can be calculated using
+two complex multipliers running at > 161 MHz. However another option is to use one pultiplier
+per X_sq = 144 visibilities, so one complex multiplier per correlator cell and N/2 + 1 = 9
+correlator cells in parallel. The FPGA has sufficient multipliers to support this scheme and the
+spare capacity of each correlator cell can be used to support a subband correlator with more
+than 1 subband per integration interval, so N_crosslets > 1.
+
+Design decision:
+ Use 1 + N/2 parallel correlator cells, for the local-local visibilities and for the local-
+ remote visibilities for each remote source.
+
What is the crosslet packet size?
-With S_pn = 12 signal inputs per PN and one crosslet per signal input there are 12 crosslets per packet. A crosslet is
-a W_crosslet = 16 bit complex value, so 12 * 4 = 48 octets payload, so the effective packet size is 40 + 48 = 88 octets.
-The relative packet overhead for single crosslet payloads is 40 / 88 = 45 %.
-
-There are f_sub = 195312.5 subbands per s, and the packets have to travel N/2 hops. This yields a packet load of
-packet size * f_sub * N/2 = (88 * 8b) * 195312.5 * 16 / 2 = 1.1 Gbps. The data load of only the payload data is
-payload size * f_sub * N/2 = (48 * 8b) * 195312.5 * 16 / 2 = 0.6 Gbps. Hence the small packet size causes a large
-packet overhead, but is still acceptable, since it fits on a single 10G link of the ring.
-
-Calculate one or multiple crosslets:
-With small payloads the 10G link could fit about 10/1.1 ~= 8 different crosslets. With larger payloads the 10G link
-could fit about 10 / 0.6 = 16 crosslets. The advantage of using small payloads is that adding more crosslets can be done
-by instantiating the same single crosslets XC multiple times. However the small packets do have to travel sequentially
-via the same 10G link, so there needs to be a multiplexer after that the local ETH frames have been made. The advantage of
-using larger payloads is that they can be made by putting the extra crosslets in the same payload. With 16 crosslets
-the payload size is 16 * 48 = 768 and the effective packet size is 40 + 768 = 808 octets. The relative packet overhead for
-multi crosslet payloads is 40 / 808 ~= 5 %. The packet load for multi crosslet payloads is (808 * 8b) * 195312.5 * 16 / 2 =
-10.1 Gbps, so this will just not fit on a 10GbE link, but 15 crosslets would.
-
-At 200 MHz for the critically sampled subbands, a X_pn correlator cell can correlate N_fft / X_sq = 1024 / 144 = 7
-different crosslets frequencies. With N = 16 for LBA there need to be N/2 + 1 = 9 of these X_pn correlator cells in
-parallel. One X_pn correlates the local-local crosslets and the other N/2 X_pn correlates the local-remote crosslets.
-These 9 X_pn in parallel can correlate up to 7 crosslets. The link can transport 15 crosslets, so 18 X_pn in parallel
-could correlate 14 different crosslets to make better use of the link capacity.
-
-One X_pn takes one complex multiplier. For one crosslet using N/2+1 = 9 X_pn is a waste of resources, but still
-acceptable and providing a clear design.
+With S_pn = 12 signal inputs per PN and one crosslet per signal input there are 12 crosslets per
+packet. A crosslet is a W_crosslet = 16 bit complex value, so P_payload = 12 * 4 = 48 octets
+payload, so the effective packet size is P_packet = P_overhead + P_payload = 60 + 48 = 108 octets.
+The relative packet overhead for single crosslet payloads is P_overhead / P_packet = 60 / 108 =
+55 %. Note that P_overhead_dp + P_payload = 20 + 48 = 68 octets still meets the minimum Ethernet
+payload size requirement of 46 octets.
+
+Maximum number of crosslets per lane:
+There are f_sub = 195312.5 subbands per s, and the packets have to travel N/2 hops. This yields
+a packet load of P_packet * f_sub * N/2 = (108 * 8b) * 195312.5 * 16 / 2 = 1.35 Gbps. The data
+load of only the payload data is P_payload * f_sub * N/2 = (48 * 8b) * 195312.5 * 16 / 2 =
+0.6 Gbps. Hence the small packet size causes a large packet overhead, but is still acceptable,
+since it is < L_lane = 7.8125 Gbps, so it fits on a single 10G lane of the ring.
+Multiple local crosslets could be transported via seperate packets, a lane can then fit about
+7.8125 / 1.35 ~= 5 different crosslets. Packing the local crosslets into a single payload
+reduces the packet overhead. The maximum number of crosslets per packet follows from
+(P_overhead + x * P_payload * 8b) * f_sub * N/2 < L_lane. For N = 16 this yields x ~=
+(7.8125 Gbps / (16/2) / 195312.5 - 60) / (48 * 8b) = 12. With x = 12 crosslets the payload size
+is 12 * 48 = 576 and the effective packet size is P_packet = 60 + 576 = 636 octets. The relative
+packet overhead for multi crosslet payloads is P_overhead / P_packet = 60 / 636 ~= 9.4%. The
+packet load for multi crosslet payloads is (636 * 8b) * 195312.5 * 16/2 = 7.95 Gbps >
+L_lane = 7.8125 Gbps, so this just does not fit on a 10GbE lane, due to the still significant
+packet overhead. Using x = 11 instead of x = 12 crosslets per packet yields a total crosslet
+packet load per lane of ((60 + 11 * 48) * 8b) * 195312.5 * 16/2 = 7.35 Gbps, which does fit on
+a lane.
+
+Design decision:
+ Pack local crosslets into a single payload if N_crosslets > 1, because then the relative packet
+ overhead is much reduced to support transporting more crosslets per lane (11 instead of 5).
+
+Maximum number of crosslets per correlator cell:
+An X_pn correlator cell can correlate N_clk / X_sq = 1024 / 144 = 7 different crosslets frequencies.
+With N = 16 for LBA, there need to be N/2 + 1 = 9 of these X_pn correlator cells in parallel. One
+X_pn correlates the local-local crosslets and the other N/2 = 8 X_pn correlate the local-remote
+crosslets. These 9 X_pn in parallel can correlate up to 7 different crosslets. The link can
+transport maximum 11 crosslets. Hence the processing capacity of 9 X_pn is less than the IO
+capacity of one 10GbE lane, therefore 9 X_pn in parallel can correlate 7 different crosslets.
+The crosslet data rate on a lane is then ((60 + 7 * 48) * 8b) * 195312.5 * 16/2 = 4.95 Gbps, so a
+utilization of 4.95 / 7.8125 = 63 %. Another set of 9 X_pn could be used to correlate the remaining
+11 - 7 = 4 crosslets that can be transported via that lane. However, if more than N_crosslet = 7
+crosslets need to be correlated in parallel per integration interval, then it is easier to allocate
+an extra lane and to instantiate an extra set of 9 X_pn to correlate 14 crosslets in parallel in
+total.
+
+One X_pn takes one complex multiplier. For N_crosslets = 1 crosslet per integration interval using
+1 + N/2 = 9 X_pn uses only 144 / 1024 = 14% of the processing resources. However this is acceptable
+because:
+- the FPGA has sufficient multipliers
+- it provides a clear design
+- the spare capacity can be used to process more crosslets per integration interval
+
+Design decision:
+ Use 1 + N/2 = 9 parallel correlator cells to correlate N_crosslets = 1 crosslet, or upto 7
+ crosslets in parallel, per integration interval.
+
Send more than one time slot per packet?
-To reduce the relative packet overhead for single crosslet XC it is an option to put multiple time slots per payload.
-This is considered to complicating.
-
- PN0 PN1 PN2 PN3 PN1
-t
-0: L00 L11 L22 L33 L44 <-- For example two time slots per packet
- R44 R00 R11 R22 R33
- R33 R44 R00 R11 R22
-
-2:
-
-What if a node fails?
-The next N/2 nodes will then miss packets. The order of the packets is not affected, because on each node it will
-be the last one or more packets that are missed. There will be no correlations for the missed packets, but the
-correlation should continue if the next time slot the node starts again. A packet count per packet source at each
-node will reveal missed packets and thus also the number of integrations that happened in the final visibilities.
-If no packets are missed then the packet count is 195312.5 per integration interval on every PN for every packet
-source PN.
-
- PN0 PN1 PN2 PN3 PN1
-t
-0: L0 . L2 L3 L4 <-- PN1 fails, so next N/2 nodes will miss packets
- R4 . . R2 R3
- R3 . . . R2
- 00 . 22 33 44
- 04 . . 32 43
- 03 . . . 42
-
-
+To reduce the relative packet overhead for single crosslet XC it is an option to put multiple
+time slots per payload. Design decision: This is considered to complicated.
+
+
What if a packet gets lost?
-If a packet gets lots then it can cause a gap in the packet order, so the next packet must not be mistaken as
-the lost packet. Therefore the packets must have a time slot number and a source number, such that the XST in
-each node will use it for the correct visibilities.
+The local crosslets cannot get lost, but remote packets may get lost. For transit crosslet packets
+a lost packet remains lost, because it cannot be replaced. For the subband correlator at this
+node the lost remote packets can be replaced by filler data, because the BSN aligner can use the
+local input as reference to detect lost packets. The BSN aligner will replace lost remote packets
+with filler packets that are flagged. The crosslets in the filler packets contain zero data, so in
+the correlator they do not contribute to the visibilities. Each X_pn correlator cell operates on
+crosslets from another source. Therefore each X_pn correlator cell has to maintain a count of the
+number of valid N_valid and of the number of flagged N_flagged crosslets per integration interval.
+The N_valid can be used to weight the visibility relative to the expected number of N_int
+crosslets. The N_flagged is used for monitoring. For every integration interval N_int = N_valid
++ N_flagged should be true, by design of the BSN aligner.
- PN0 PN1 PN2 PN3 PN1
-t
-0: L0 L1 L2 L3 L4
- R4 . R1 R2 R3 <-- L0 from PN0 gets lost at PN1
- R3 R4 . R1 R2
-Packet order is guarantueed?
-At the start of every time slot the local L# packet is send first. After that each node passes on the packets that
-it receives. Therefore the packets arrive in order with packet from closest node first and from furtherst node
-last. If a packet gets lost then there will be a gap, but the order is still preserved.
What if T_sq > T_hop latency on ring?
What if T_sub > N/2 * T_hop latency on ring?
@@ -538,63 +700,90 @@ A04. After that the correlator can continue with B00 and then B07 when it arrive
packet input also needs a buffer, to store B7 in case the correlation of B00 is still busy.
- PN0 PN1 PN2 PN3 PN4 PN5 PN6 PN7
-t
-0: L0
- R7
- R6
- R5
- R4
-
-0: A0
- A7
-1: B0
- A6
- B7
-2: C0
- A5
- A4
- B6
- C7
-3: D0
- B5
- B4
- C6
- D7
-4: E0
- C5
- C4
- D6
- E7
-5: F0
- D5
- D4
- E6
- F4
- E5
- E4
-
- A00
- 07
- 06 <-- queue local B0 in FIFO, because first finish time slot A for A6,5,4
- 05 <-- queue remote B7 in FIFO, because first finish time slot A for A5,4
- 04
- B00
- 07
- 06 <-- queue local C0 in FIFO, because first finish time slot B for B6,5,4
- 05 <-- queue remote C7 in FIFO, because first finish time slot B for A5,4
- 04
-
-If remote packets get lost then the local FIFO will run full, this can then be used to flush
-the FIFOs and restart the alignment. The flush time should be long enough, such that it will
-cause that all PN in the ring will restart. However it is important that all PN restart at
-the same time or using the same time slot. This can be achieved by restarting at the sync
-(so once per second) or by restarting at every time slot in case the previous time slot did
-not receive any remote packet, which indicates that the source node was still flushing its
-FIFOs.
+XC ring transport:
+The crosslet packets have to travel accross N/2 hops along the ring. At each node all remote
+crosslet packets are decoded and stored-and-forwarded to be able to validate the ETH CRC, the DP
+CRC and the BSN. Each node inserts its local crosslet packet onto the ring and removes the
+most distant remote packet from the ring. The other remote crosslet packet are passed on.
+For the remote packets that are passed on the payload can remain packed. For the local crosslet
+packets the payload needs to be repacked from 2 * 16b crosslets to 64b packed data. With
+N_crosslets = 1 crosslet per integration interval the P_packet = 108 octets or 14 64b words.
+The packed remote and local crosslets payloads can then be multiplexed and then encoded.
+The muliplexer that inserts the local crosslet packet uses a round robin scheme, so that the
+local crosslet packet can be inserted as soon as there is a gap between the remote packets.
+Therefore assume the multiplexer may cause an extra latency t_mux of one packet duration at
+one node, but not at all nodes. The Tx repacking of the local crosslets causes gaps in the 64b
+data, because r = 200/156.25 * 32/64 = 0.64 < 1. Therefore the clock domain crossing Tx FIFO
+needs to use a fill FIFO. The Tx FIFO will first need to be filled by about (1-r) * P_packet =
+(1 - 0.64) * 14 = 6 64b words, before the Tx can start to ensure that the packet is transmitted
+without gaps. The travel latency t_travel per hop can be expressed in DP clock cycles at 200 MHz:
+
+- t_pipe + t_prop ~= 0.2 us, or 40 clock cycles.
+- t_store ~= 14 / 156.25M = 0.09 us, or 18 clock cycles
+- t_fill ~= 6 / 156.25M = 0.038 us, or 8 clock cycles.
+
+Hence t_travel = 40 + 18 + 8 = 66 clock cycles. Assume t_mux is equal to t_store at one node and
+0 at the N/2-1 other nodes. The total latency along the ring for the most distant remote packet
+is then about N/2 * travel + t_mux = 16/2 * 66 + 18 = 546 clock cycles, so less then N_clk = 1024.
+
+The XC dispatcher does:
+- repack the remote crosslets from 64b data to 2 * 16b crosslets
+- demultiplex the crosslets from the N/2 different sources
+- align the local crosslets input with the N/2 remote inputs.
+- output the local-local crosslets and the N/2 local-remote crosslets to the 1 + N/2 correlator
+ cells
+
+XC BSN aligner input buffer size:
+The maximum input latency is less than one block period T_sub, so the size of the input buffer
+in the BSN aligner only needs be 2 blocks. While one block free for new blocks, the other
+aligned block is being output to the correlator cells. This yields an input buffer size of K = 2
+blocks, so K * S_pn * N_complex * W_subband = 2 * 12 * 2 * 16 = 768 bit, which takes one M20k
+block RAM. The BSN aligner for the crosslet ring dispatcher has 1 + N/2 inputs, so it will use
+9 * 1 = 9 M20k block RAMs. Note that these BSN aligner input buffers are also large enough to
+fit N_crosslet = 7, because 7 * 768 = 5376 bit also fits in one M20k block RAM.
+
+If the BSN aligners allows direct memory access to its input buffers then the X_sq square
+correlator cell can read the crosslets from the BSN aligner in arbitrary order and multiple
+times.
+
+X_sq correlator cell:
+The X_sq correlator cell has two input streams. One input stream delivers the crosslet from
+S_pn = 12 signal inputs on one PN and the other input stream delivers the crosslet from
+S_pn = 12 signal inputs on the same PN (for local-local visibilities) or another PN (for the
+local-remote visibilities). In total the X_sq calculates X_sq = S_pn * S_pn = 12*12 = 144
+visibilities. The crosslets are delivered sequentially using a double for loop, so for each
+crosslet i in range(S_pn) on one input and for each crosslet j in range(S_pn) on the other
+input calculate the product and intergrate the visibility. This calculation sequence requires
+that crosslets can be addressed multiple times. For N_crosslets = 1 the X_sq correlator cell
+only correlates the first S_pn = 12 crosslets that are delivered on its two inputs. For
+N_crosslets > 1 the X_sq continues correlating the next S_pn = 12 crosslets that are delivered
+on its two inputs. Hence N_crosslets > 1 merely adds another for loop level to the X_sq, that
+loops for k in range(N_crosslets). The visibilities are calculated in order:
+ k, i, j
+ 0, 0, 0
+ 0, 0, 1
+ . . .
+ 0, 0,11
+ 0, 1, 0
+ 0, 1, 1
+ . . .
+ 0, 1,11
+ . . .
+ . . .
+ 0,11, 0
+ 0,11, 1
+ . . .
+ 0,11,11
+ 1, 0, 0
+ etc.
+
Support for other (shorter) integration period T_int_x?
- Longer T_int as multiple of 1 s can be supported outside SDP
+- Longer T_int can be supported within SDP by:
+ . Using BSN scheduler
+ . Reduces M&C data rate
+ . Should still fit in number of bit of visibility
- Shorter T_int < 1 s (PPS):
. Using BSN scheduler
. increases M&C data rate
@@ -609,14 +798,76 @@ How can it be scaled to more than one crosslet per XST?
*******************************************************************************
* Subband offload for AARTFAAC
*******************************************************************************
-Current AARTFAAC can offload S_sub_so = 36 subbands for S = 96 signal inputs (SI) in W_subband_so = 16 bit mode,
-so a bandwidth of 36 * 1953125.5 Hz = 7.03 MHz. This corresponds to a load of S_sub_so * S * f_sub * N_complex *
-W_subband_so = 36 * 96 * 195312.5 * 2 * 16 = 21.6 Gbps. The 8 bit subband mode does not work in RSP, but would
-be sufficient for AARTFAAC. Therefore assume W_subband_so = 8 bit for LOFAR 2.0. For LOFAR 2.0 the number of LBA
-doubles to S_lba = 192, so assume S = 192. The load from one 8 bit subband from all 192 signal inputs is
-S * f_sub * N_complex * W_subband_so = 192 * 195312.5 * 2 * 8 = 0.6 Gbps for R_os = 1 and 0.75 Gbps for maximum
-expected R_os = 1.25 of an oversampled filterbank. Per 10GbE output link this then yields maximum of 10G / 0.6G
-= 16.6 subbands for R_os = 1 and 10G / 0.75G = 13.3 subbands for R_os = 1.25. The 10GbE requires some spare
+
+Assumptions for AARTFAAC2.0:
+
+- S = 96 signal inputs
+- W_subband_so = 8 bit
+- S_sub_so = 64 subbands, so 12.5 MHz subband bandwidth
+- group subbands from all S = 96 inputs in a packet
+- similar subband output format as in ASTRON_RP_1403_UDP_SDO ICD
+
+LOFAR1 uses the outer LBA for about 80 % of the time and the inner LBA for 20 % of the time. This
+is because at lower frequencies the mutual coupling of LBA in the inner region becomes more
+significant, which then reduces the sensitivity of the inner LBA. The mutual coupling increases
+and the sensitivity decreases because for nearby LBA the wavelength >~ the distance between LBA.
+
+Assumptions for Station.SDP:
+- Any S = 96 out of S_lba = 192 can be selected for offload
+- The number subbands per lane is independent of set the same for R_os = 1 and R_os = 1.28. This
+ implies that the utilization of the lanes for R_os = 1 is about a factor 1.28 less.
+
+Select S = 96 from S_lba = 192 signal inputs
+AARTFAAC uses the dual pol antennas, so the signal inputs (SI) have to be selected per pair of X
+and Y polarization. The N = 48 antennas can be selected from the N_lba = 96 antennas in different
+either at the offload node or at each PN:
+- Transport all SI to the offload node and select there
+- Select SI per PN and only transport the selected SI to the offload node
+The first schemeThe selection can be programmable or fixed.
+
+
+First collect all S_lba = 192 signal inputs at the offload node, and then make an arbitrary
+ selection or a fixed selection. The disadvantage is that this doubles the load on the ring.
+- Select at each PN and transport only First collect all S_lba = 192 signal inputs at the offload node, and then make an arbitrary
+ selection or a fixed selection.
+
+Use ring transport scheme 1 or scheme2a:
+- With scheme 1 the selection of S out of S_lba can be made per PN, as the payload is passed along
+ and each node can insert none, all or a subset of its S_pn at the allocated subband index in the
+ payload. With scheme 2a the selection of S will be done at the offload node, so all PN then send
+ all their S_pn inputs via the ring. This doubles the load on the ring.
+- With scheme 2a each node only has to pass on the remote packets, but at the offload node it
+ needs an N input BSN aligner, an N input to one output subband selection to get the offload
+ payload. With scheme 1 the first node initiates the offload payload and then each node has to
+ insert the local subbands at the correct index. This requires only a two input BSN aligner.
+- If one hop fails in scheme 1 then there is no offload. If one hop fails in scheme 2a then there
+ is still offload from subsequent hops.
+
+
+
+Current AARTFAAC1 can offload S_sub_so = 32 subbands for S = 96 signal inputs (SI) in W_subband_so
+= 16 bit mode. On the RSP - Uniboard interface there are 9 subbands per lane, so S_sub_so = 36 in
+total, but on the UniBoard - UDP interface to the GPU correlator only 8 subbands, so 32 in total
+are output. The AARTFAAC1 output load is S_sub_so * S * f_sub * N_complex * W_subband_so =
+32 * 96 * 195312.5 * 2 * 16 = 19.2 Gbps. Due to a bug in probably the RSP firmware, W_subband_so
+= 8 bit mode cannot be supported, but for LOFAR2.0 it can. Hence for the same output load as
+AARTFAAC1, AARTFAAC2.0 can offload S_sub_so = 64 subbands, which corresponds to a bandwidth of
+64 * 195312.5 Hz = 12.5 MHz.
+
+For LOFAR 2.0 the number of LBA doubles to S_lba = 192, but AARTFAAC2.0 assumes that still S = 96
+will offload subbands. Assume that the S = 96 signal inputs can be selected from the S_lba = 192
+available signal inputs at the Station output. Therefore internally in the Station SDP the
+subbands from all S_lba are passed on via ring to an the output node in SDP. For the LBA the ring
+in SDP connects N = S_lbs / S_pn = 192 / 12 = 16 nodes, so N-1 hops. Assume all subbands are send
+in one direction along the ring. The subband data load on the last hop is then
+(N-1)/N * 2 * 19.2G = 15/16 * 2 * 19.2G = 36.0 Gbps, excluding packet overhead. Given a lane
+load capacity of L_lane = 7.8125 Gbps, this implies that the subband offload requires at least
+ceil(36.0 / 7.8125) = ceil(4.6) = 5 lanes.
+
+The load on the from one W_subband_so = 8 bit subband is L_sub_so = S_lba * f_sub * N_complex *
+W_subband_so = 192 * 195312.5 * 2 * 8 = 0.6 Gbps. Per 10GbE lane this then yields maximum of
+L_lane / L_sub_so = 7.8125G / 0.6G = 33.3 subbands for
+R_os = 1 and 10G / 0.75G = 13.3 subbands for R_os = 1.25. The 10GbE requires some spare
capacity, so therefore assume S_sub_so = 12 subbands / 10GbE link will just fit for R_os <= 1.25, provided that
the packet overhead is < (13.3-12)/12 ~= 10 %. Hence with one 4 * 10GbE QSFP port at the final PN it is possible
to offload 4 * 12 = 48 subbands or 9.375 MHz bandwidth with S_lba = 192 signal paths and W_subband_so = 8 bit.
@@ -624,8 +875,6 @@ The ring can be used to transport the subbands to some single destination PN tha
the 4 x 10GbE ports or 40GbE port on the QSFP. The destination PN could also do subband reordering to group
subbands per S_lba = 192 inputs.
-Remark: On the RSP - Uniboard interface there are 9 subbands per lane, so S_sub_so = 36 in total, but on the
-UniBoard - UDP interface to the GPU correlator only 8 subbands, so 32 in total are output.
The subbands are gathered at the output node via the ring. Using the ring avoids the need to use a 10GbE switch.
Such a switch would need > 16 + 16 ports to support LBA + international HBA and some output ports. If the data
@@ -664,7 +913,8 @@ to the rsp_terminal function on UniBoard1 for AARTFAAC. Scheme is specific to th
work if the subband data is send to the end node via a switch (or via URI like with RSP).
With scheme 2a the ring could be used in both directions, but this does not improve the capacity of the
-ring. With scheme 1 the packets travel 1+2+3+...+(16-1) = 120 hops. With scheme 2a the packets travel
+ring. With scheme 2a in one direction the packets travel 1+2+3+...+(16-1) = 120 hops. With scheme 2a in
+both directions the packets travel
1+2+3+4+5+6+7+8 = 36 hops left and 1+2+3+4+5+6+7 = 28 hops right, so total 64 hops. For the transport load
on the ring as a whole scheme 2 is a factor 102/64 = 1.875 more efficient. However at the end node both
schemes still have transfer the same load of 15 packets. Therefore at the end node the load for both
@@ -684,7 +934,7 @@ Suppose 8 of these can be allocated to subband offload, then the ring can supppo
Design decision:
- Gather subbands at output node (instead of having a dedicated offload port at each node)
-- Gather the subbands via the ring (to avoid the need for a 10GbE switch wit about 40 ports)
+- Gather the subbands via the ring (to avoid the need for a 10GbE switch with about 40 ports)
- Reorder the subbands to have all subbands from signal inputs in one payload (to ease input stage of user application)
- Use scheme 2a and in both directions (to reduce the number of hops and latency)
diff --git a/applications/lofar2/doc/prestudy/station2_sdp_timing.txt b/applications/lofar2/doc/prestudy/station2_sdp_timing.txt
index ac488b6e9b194cde7a6d910d3e0060e1ba0ac694..060a82f7731524a05d4f8fbeb6e8e0cc5c0bdf3e 100644
--- a/applications/lofar2/doc/prestudy/station2_sdp_timing.txt
+++ b/applications/lofar2/doc/prestudy/station2_sdp_timing.txt
@@ -2,42 +2,43 @@
* Fixed Station BSN grid and the PPS grid
*******************************************************************************
-The Station needs an external trigger to align all ADCs in the RCU2S and all FPGA procesing nodes in the SDP.
-For this trigger a pulse from the pulse per second (PPS) is used. The PPS is aliged to the top of second of the
-UTC time of day (ToD). The PPS is a hardware trigger that is available within the entire SDP at sample clock
-cycle accuracy. Thanks to the Timing Distributor (TD) the PPS trigger is also available as hardware trigger in
-all Stations. Thanks to the TD the PPS is aligned to UTC ToD, and the ToD is available to the Telescope Manager
-(TM) in LOFAR2.0 and to Station Control in each Station. The TM controls, via Station Control, which PPS pulse
-is used to start SDP. The PPS is identified by a Seconds Sequence Number (SSN) that counts PPS since a certain
+The Station needs an external trigger to align all ADCs in the RCU2S and all FPGA procesing nodes
+in the SDP. For this trigger a pulse from the pulse per second (PPS) is used. The PPS is aliged to
+the top of second of the UTC time of day (ToD). The PPS is a hardware trigger that is available
+within the entire SDP at sample clock cycle accuracy. Thanks to the Timing Distributor (TD) the
+PPS trigger is also available as hardware trigger in all Stations. Thanks to the TD the PPS is
+aligned to UTC ToD, and the ToD is available to the Telescope Manager (TM) in LOFAR2.0 and to
+Station Control in each Station. The TM controls, via Station Control, which PPS pulse is used to
+start SDP. The PPS is identified by a Seconds Sequence Number (SSN) that counts PPS since a certain
date in the past, e.g. t_epoch = 1 jan 1970, but some other fixed date is possible too.
-The SDP processes the data in blocks of ADC samples that are identified by a Station block sequence number
-(BSN). The Station BSN time grid should be fixed, so independent of when the data processing starts. Therefore
-the Station BSN counts blocks since the same t_epoch as the SSN, so the t_epoch defines the common reference
-moment in history for the Station BSN grid and for the PPS grid. The PPS grid does not necessarily always
-coincide with the Station BSN grid. The BSN period determines whether the Station BSN can start exactly at an
-PPS or not.
+The SDP processes the data in blocks of ADC samples that are identified by a Station block sequence
+number (BSN). The Station BSN time grid should be fixed, so independent of when the data processing
+starts. Therefore the Station BSN counts blocks since the same t_epoch as the SSN, so the t_epoch
+defines the common reference moment in history for the Station BSN grid and for the PPS grid. The
+PPS grid does not necessarily always coincide with the Station BSN grid. The BSN period determines
+whether the Station BSN can start exactly at an PPS or not.
The processing of the ADC inputs in SDP is done by multiple FPGAs in parallel. Each FPGA has a BSN source that
creates the Station BSN grid. The BSN source is the wall clock of the FPGA. To be able to start the data
processing at any PPS it is necessary that the BSN source can start at a programmable fraction of a BSN period
after the PPS. In this way processing of one Station ADC signal input can be restarted at any PPS (with zero
-phase offset to the other signal input) and an entire Station can be restarted at any PPS (with zero phase
+phase offset to the other signal input) and an entire Station can be restarted at any PPS (with zero phase
offset to the other Stations). The BSN source ensures that the BSN timing is always on the fixed Station
BSN time grid. The initial BSN and the offset fraction of a BSN period need to be provided to SDP via the
M&C interface by Station Control. Both Station Control and SDP know the PPS grid. Station Control also knows
UTC and with that information Station Control can program and initialize the BSN source in the FPGAs to start
-counting data blocks at the next PPS.
+counting data blocks at the next PPS.
The sample frequency f_adc = 200 MHz is an integer number of Hz and locked to the PPS, therefore the PPS grid
always coincides with the ADC sample period T_adc = 1/f_adc = 5 ns grid. The Station BSN block period is an
integer number of N_blk sample periods T_adc. The Station BSN period is set by the subband rate of the subband
-polyphase filterbank (PFB), so the Station BSN period is equal to the subband period is T_sub.
-The input to the subband filterbank is the real signal from the ADC. For both the critically sampled PFB and
+polyphase filterbank (PFB), so the Station BSN period is equal to the subband period is T_sub.
+The input to the subband filterbank is the real signal from the ADC. For both the critically sampled PFB and
the oversampled PFB the data block size of the input data is N_blk = N_FFT = 1024 ADC samples, however for the
oversampled PFB the blocks overlap by a factor R_os. Hence for the critically sampled PFB the BSN period is
T_sub = N_blk = 1024 [T_adc] and for the oversampled PFB the BSN period is T_sub = N_blk / R_os = 864
-[T_adc], in case R_os = 32/27. At the output of the subband filterbank a data block contains
+[T_adc], in case R_os = 32/27. At the output of the subband filterbank a data block contains
N_sub = N_FFT / N_complex = 512 complex subband samples that all correspond to the same time instant as
defined by the Station BSN. Each subband sample represents another frequency.
@@ -50,17 +51,17 @@ of 0:N_blk-1 sample periods. The BSN source starts at a PPS with an initial Stat
and a BSN offset fraction of:
BSN offset fraction = mod(SSN * 1 s, T_sub) / T_adc = mod(SSN * f_adc, N_blk)
-
+
to make sure that the BSN grid is always relative to t_epoch, independent of at which PPS the BSN source was
started. The Station BSN increments after every block. The time ToD_BSN at the BSN grid is:
ToD_BSN = t_epoch + Station BSN * T_sub
-
+
Note:
- The BSN offset fraction could also be compensated for by delaying the sample data in the ADC signal input
buffers at the input of SDP. Delaying the data does compensate for phase differences in the subband
- data, but does not compensate for the offset in the BSN grid. The BSN alignment buffers between signal
+ data, but does not compensate for the offset in the BSN grid. The BSN alignment buffers between signal
inputs from different FPGAs then still need to compensate for this BSN offset fraction. Hence delaying the
data is an indirect and incomplete solution, and therefore it is not used.
- In LOFAR1 the Station BSN is divided in a 32 bit seconds sequence number (SSN) that counts PPS intervals and
@@ -80,7 +81,7 @@ and any M&C upon the data, because:
- It is not necessary to facilitate using an offset 0 < T_sub_o < T_sub to start the BSN grid at an integer
number of T_adc after t_epoch, because the BSN grid is sufficiently fine.
-- It is not necessary to represent fine group delays of digital filters or analogue electronics and
+- It is not necessary to represent fine group delays of digital filters or analogue electronics and
cables in the BSN, because these delays are all accounted for after calibration.
. Course group delays and cable delay differences can be compensated for in steps to T_adc via the signal
input buffer of every ADC input in SDP.
@@ -106,7 +107,7 @@ In LOFAR2 the timestamp should be independent of:
- using 200 MHz sample rate or 160 MHz sample rate,
- using critically sampled subband filterbank or oversampled subband filterbank
-
+
If T_sub was fixed then T_sub could be used as timestamp resolution (like in APERTIF). However T_sub depends
on the type of subband filterbank with a resolution of T_adc. If T_adc was fixed then T_adc could be used
as timestamp resolution. However T_adc depends on the sample clock rate. Therefore the timestamp resolution
@@ -118,11 +119,11 @@ of 0.2 ns such that they are:
* integer values, and
* independent of the sample period.
-
+
The actual timestamp in fractional seconds of 0.2 ns follows from:
timestamp = Station BSN * T_sub_i * 0.2 [ns].
-
+
The BSN and T_sub_i can be specified as:
- single 64 bit integer timestamp value of BSN * T_sub_i [0.2 ns]
@@ -131,7 +132,7 @@ The BSN and T_sub_i can be specified as:
To cover 116 years for a BSN with smallest T_sub = 4000 ns for R_os = 32/25 = 1.28 requires:
log2( 116 * (365.25 * 24 * 3600 / 4000e-9) ) = 49.7, so 50 bits
-
+
Therefore allocate 64b in a packet header to send the BSN information. The BSN and timestamp are direcly
related via T_sub_i, but the advantage of providing the BSN separately is that it increments by 1 for
each block period T_sub, so it can be used as block index.
@@ -155,12 +156,12 @@ of the data in a Station. However counting blocks is not sufficient to maintain
The assumptions are:
- data is transported and processed in blocks,
-- partial blocks cannot occur.
+- partial blocks cannot occur.
- the data flow can only stop or continue at block boundaries.
To recover from gaps in the data flow the BSN can be transported along with every data block.
For the external FPGA interfaces one or more data blocks get packed into the payload and the BSN is then
-transported via the header. The BSN in the header corresponds to the first data block in the payload, the
+transported via the header. The BSN in the header corresponds to the first data block in the payload, the
position of a data block in the payload defines the offset to this BSN.
For data transport within the FPGA it is costly from a resource point of view to tranport the 64 bit BSN
@@ -191,10 +192,10 @@ For the blocks between sync pulses the Station BSN is incremented with every blo
BSN needs to be preserved during the sync interval, then lost or discarded blocks must be replaced by filler
blocks. Whether only the BSN at the data sync is relevant, or whether also the BSN of subsequent data blocks is
needed depends on the function. For the statistics (AST, SST, BST, XST) the BSN at the data sync is sufficient to
-mark the timing of integration results. For these integration results the number of data blocks within the
+mark the timing of integration results. For these integration results the number of data blocks within the
integration interval is relevant to know how many blocks contributed (and thus also how many blocks were lost).
However for the integration result it is not relevant which blocks got lost, because the statistics do not have
-to keep accurated time centroid information. It is sufficient to use the BSN at data sync to timestamp the
+to keep accurated time centroid information. It is sufficient to use the BSN at data sync to timestamp the
integration results, as if all blocks contributed. As another example, for the beamformer it is important to
be able to recreate the BSN at the data sync and all subsequent data blocks, because the beamformer must weight
and sum the input beamlets that coincide in time. Similar for the beamformer output to CEP and for the subband
@@ -253,7 +254,7 @@ because it means that Stations should start at an even sync interval when the PP
to ensure that all stations remain aligned. Starting only at even PPS ensures that LOFAR1 uses a BSN grid
that is fixed to t_epoch = 1970. For an oversampled subband filterbank the PPS grid and BSN grid
coincide every q-th PPS, where R_os = p/q, so then a Station should only start every q-th PPS.
-In APERTIF the sync interval was chosen to be an integer number of fine channel periods T_chan =
+In APERTIF the sync interval was chosen to be an integer number of fine channel periods T_chan =
N_Chan * T_sub, which resulted in 12500 T_chan and 800000 T_sub or a period of 1.024 s. This 1.024 s is used
as unit integration period of the correlator in APERTIF. A sync interval of 1 s would have resulted in
781250 T_sub and 12207.03125 T_chan. The APERTIF sync interval of 1.024 s is akward too, because it differs
@@ -262,7 +263,7 @@ grid coincide, which is once every 125 s, because 128/125 = 1.024.
LOFAR1 and APERTIF show that in general application periods do not integer fit with the 1 s PPS grid. For
integration periods the only two options are to either use another integration interval (like 1.024 s in
APERTIF) or to accept that the number of samples per integration interval can differs by one (like 195313 or
-195312 in LOFAR1).
+195312 in LOFAR1).
Both LOFAR1 and APERTIF cannot start at any PPS without affecting the BSN grid. This needs to be solved for
LOFAR2.0. Like in LOFAR1, for LOFAR2.0 the PPS grid and BSN grid are fixed to t_epoch = 1970. However,
instead of waiting until the BSN grid and PPS grid coincide, the BSN source in
@@ -339,14 +340,14 @@ In Station SDP the BSN serves two purposes;
- the entire BSN provides wall clock time on the BSN grid and is thus linked to UTC,
- the difference in BSN is used to time align input streams
-In Station SDP each FPGA has a local BSN source and a local stream that carries the data from its local ADC
+In Station SDP each FPGA has a local BSN source and a local stream that carries the data from its local ADC
signal inputs. The BSN aligner needs to align the local stream with the remote streams that are received
from the other FPGA via the ring. The maximum BSN latency on the ring depends on the number of FPGAs in the
ring. Suppose each FPGA introduces a latency of at least one packet, because it applies store and forward on
packets, and less than two packets. Furthermroe assume that on the ring each packet contains one data block.
The maximum number of hops between the first FPGA on the ring and the final FPGA is N_FPGA-1. For the LBA
ring N_FPGA = 16. Hence the maximum BSN latency that can occur within
-SDP is < (N_FPGA-1) * 2 < 32 block periods. Hence the maximum BSN difference between the local input and a
+SDP is < (N_FPGA-1) * 2 < 32 block periods. Hence the maximum BSN difference between the local input and a
remote input of the BSN aligner is < 32. Therefore to align the input streams the BSN aligner only has to
compare the log2(32) = 5 LSbits of the BSN of all input streams. This implies that for the BSN aligner it
would be sufficient to only transport these bits in the packet header, however it is convenient and not too
@@ -371,6 +372,28 @@ Note:
+Key ideas:
+- Use Ethernet CRC and DP CRC to ensure detection of packet errors and to ensure error free blocks
+ within FPGA firmware
+- Within SDP firmware the BSN at sync can be obtained from the local BSN source and subsequent
+ BSN can be derived by counting blocks:
+ . Use filler blocks to replace lost packets, to maintain BSN count within FPGA firmware
+ . Use local BSN source in FPGA and pass on sync within SDP firmware to know the BSN in the firmware.
+
+
+ RCU2 Subband Ring
+ PFB
+
+ data data
+ data ------> BSN --------> Move, -------> Packet
+ PPSH ------> source sync DSP sync encoding
+ BSN .........> BSN ring
+
+ Ring BF, XC
+ data data data
+ Packet --------> Validate --> Validate --> BSN --------> Move, --------> Packet
+ decoding sync CRC BSN aligner sync DSP sync encoding
+ ring BSN .......................................................> BSN output
@@ -386,9 +409,7 @@ Design decisions:
but in simulation it can be much less.
- Use central UTC timestamp at PPS initialized by M&C and incremented by SDP firmware for the SSN
per FPGA.
-- Use 32 bit SSN to fit UTC in seconds for 136 years since 1970
-- Use local BSN that counts data blocks within a sync interval, so it restarts at 0 at the internal sync
-- Within SDP transport the sync and the local BSN. The sync is transported via the MSbit of the local BSN.
- At the sync transport the 31 bit SSN instead of local BSN 0, but only for monitoring purposes.
-- Derive 64 bit UTC timestamp in units of T_sub in SDP firmware and use this for data output to CEP
+- Use 64 bit continuous BSN that counts subband periods since 1970
+- Within SDP transport the sync and the BSN. The sync is transported via the MSbit of the BSN.
+
diff --git a/applications/lofar2/doc/prestudy/station2_to_do_erko.txt b/applications/lofar2/doc/prestudy/station2_to_do_erko.txt
index ee6be7b14dec0f294d9b9243871504190607d49b..b7862111dffe12b5d73d5ce0a8953f36b3789a82 100755
--- a/applications/lofar2/doc/prestudy/station2_to_do_erko.txt
+++ b/applications/lofar2/doc/prestudy/station2_to_do_erko.txt
@@ -182,15 +182,16 @@ git remote remove <remote name> # remove a remote repo
*******************************************************************************
Open issues:
- Central HDL_IO_FILE_SIM_DIR = build/sim --> Project local sim dir
-- avs_eth_coe.vhd per tool version? Because copying avs_eth_coe_<buildset>_hw.tcl to $HDL_BUILD_DIR copies the
- last <buildset>, using more than one buildset at a time gices conflicts.
+- avs_eth_coe.vhd per tool version? Because copying avs_eth_coe_<buildset>_hw.tcl to $HDL_BUILD_DIR
+ copies the last <buildset>, using more than one buildset at a time gices conflicts.
*******************************************************************************
* To do:
*******************************************************************************
-- Check that the Expert users (MB, SJW, MN), Maintainers (HM) and Local users are happy with the design decisions
+- Check that the Expert users (MB, SJW, MN), Maintainers (HM) and Local users are happy with the
+ design decisions
- H6 M&C loads section
- H3 Functions mapping
- H3/4 Timing (1s default, PPS, event message)
@@ -225,7 +226,7 @@ Open issues:
- Update RadioHDL docs
- Write RadioHDL article
- Write HDL RL=0 article - desp_hdl_design_article.txt
-
+- XST : SNR = 1 per visibility for 10000 samples, brigthtest sourcre log 19.5 --> 4.5 dB --> T_int = 1 s is ok.
diff --git a/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg b/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
index 2c87641ca55b5a52ce9c4437f4849274ac674de3..567a97eff3cac97ff165a74a897ea77ec4fa7e11 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
@@ -7,7 +7,7 @@ hdl_lib_technology = ip_stratixiv
synth_files =
# Commented unb1_bn_capture.vhd and SOPC because only the node is reused.
# The SOPC causes a simulation error if it not there, because it is instantiated as an entity
- #$HDL_BUILD_DIR/unb1/quartus/unb1_bn_capture/sopc_unb1_bn_capture.vhd
+ #$RADIOHDL_BUILD_DIR/unb1/quartus/unb1_bn_capture/sopc_unb1_bn_capture.vhd
src/vhdl/unb1_bn_capture_pkg.vhd
src/vhdl/unb1_bn_capture_input.vhd
src/vhdl/node_unb1_bn_capture.vhd
@@ -41,7 +41,7 @@ quartus_qsf_files =
quartus_tcl_files =
quartus/unb1_bn_capture_pins.tcl
-quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/unb1_bn_capture/sopc_unb1_bn_capture.qip
+quartus_qip_files = $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_bn_capture/sopc_unb1_bn_capture.qip
quartus_sdc_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg b/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
index 9368e22ad325e4676b993d61512b0b9fd1f7b785..db644b06b44f6bcd17363e2e983e7fc2f36e9148 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
synth_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn_terminal_bg.vhd
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn_terminal_bg.vhd
src/vhdl/node_unb1_bn_terminal_bg.vhd
src/vhdl/unb1_bn_terminal_bg.vhd
@@ -31,7 +31,7 @@ quartus_qsf_files =
quartus_tcl_files =
quartus/unb1_bn_terminal_bg_pins.tcl
-quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn_terminal_bg.qip
+quartus_qip_files = $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn_terminal_bg.qip
quartus_sdc_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
diff --git a/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
index 89321855be5b9591595b7b3c57d742d82ba8f64f..05d368e3ebc99d39a4bf6b963926fffe32ddb6ce 100644
--- a/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_technology = ip_stratixiv
hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_800_master
synth_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.vhd
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.vhd
src/vhdl/node_unb1_ddr3.vhd
src/vhdl/mmm_unb1_ddr3.vhd
src/vhdl/unb1_ddr3.vhd
@@ -31,7 +31,7 @@ quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_qip_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.qip
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.qip
quartus_tcl_files =
quartus/unb1_ddr3_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
index 5274dbde5038d22a985445aa564845bc71fbf204..8d92055e78e0a50b1ff6eb8e4c7463199d13ae1b 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_technology = ip_stratixiv
hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_800_master
synth_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.vhd
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.vhd
../../src/vhdl/node_unb1_ddr3_reorder.vhd
../../src/vhdl/mmm_unb1_ddr3_reorder.vhd
../../src/vhdl/unb1_ddr3_reorder.vhd
@@ -42,7 +42,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+ $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
$RADIOHDL_WORK/build/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.qip
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
index a9fe01c6998deaad4a2dae2b42b3fbc42d3e04fe..a995636301fc5c0a3f4b3bf534d98e5ec25d8fbc 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_technology = ip_stratixiv
hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
synth_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.vhd
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.vhd
../../src/vhdl/node_unb1_ddr3_reorder.vhd
../../src/vhdl/mmm_unb1_ddr3_reorder.vhd
../../src/vhdl/unb1_ddr3_reorder.vhd
@@ -42,7 +42,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+ $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
$RADIOHDL_WORK/build/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.qip
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
index 3deda821337e0d7909ffb96b8dc5c75c6f716e43..3c859fd55b86d0a317c5c1fcbe9d3dbec58e4b1b 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_technology = ip_stratixiv
hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_800_master
synth_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.vhd
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.vhd
src/vhdl/mmm_unb1_ddr3_transpose.vhd
src/vhdl/unb1_ddr3_transpose.vhd
@@ -38,8 +38,8 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.qip
- $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.qip
+ $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
nios2_app_userflags = -DCOMPILE_FOR_SOPC
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg b/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
index 908c0f97085a4bdaa5d9fb02a1ce8d20162e681d..449b3d56363644be28435e243a124b71a3851b3e 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
synth_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_fn_terminal_db/sopc_unb1_fn_terminal_db.vhd
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_fn_terminal_db/sopc_unb1_fn_terminal_db.vhd
src/vhdl/mmm_unb1_fn_terminal_db.vhd
src/vhdl/unb1_fn_terminal_db.vhd
@@ -30,7 +30,7 @@ quartus_tcl_files =
quartus/unb1_fn_terminal_db_pins.tcl
quartus_qip_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_fn_terminal_db/sopc_unb1_fn_terminal_db.qip
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_fn_terminal_db/sopc_unb1_fn_terminal_db.qip
nios2_app_userflags = -DCOMPILE_FOR_SOPC
diff --git a/boards/uniboard1/designs/unb1_heater/hdllib.cfg b/boards/uniboard1/designs/unb1_heater/hdllib.cfg
index 3124faa9b5ec78cd53c1007ea48847f895d0d4ee..b142a97e96336039816c7864f34c156d0c395d34 100644
--- a/boards/uniboard1/designs/unb1_heater/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_heater/hdllib.cfg
@@ -35,7 +35,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_heater/qsys_unb1_heater/synthesis/qsys_unb1_heater.qip
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_heater/qsys_unb1_heater/synthesis/qsys_unb1_heater.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_minimal/doc/sopc-to-qsys.txt b/boards/uniboard1/designs/unb1_minimal/doc/sopc-to-qsys.txt
index 7e1166a1613c72d24e1511912ce527632e674545..883ec70f72c66a37c07d1692f961fe8e4417ae53 100644
--- a/boards/uniboard1/designs/unb1_minimal/doc/sopc-to-qsys.txt
+++ b/boards/uniboard1/designs/unb1_minimal/doc/sopc-to-qsys.txt
@@ -37,7 +37,7 @@ run: rm -rf ~/svn/UniBoard_FP7/RadioHDL/trunk/build/*
../../quartus/qsys_unb1_minimal.qsys .
quartus_qip_files =
- $HDL_BUILD_DIR/quartus/unb1_minimal/qsys_unb1_minimal/synthesis/qsys_unb1_minimal.qip
+ $RADIOHDL_BUILD_DIR/quartus/unb1_minimal/qsys_unb1_minimal/synthesis/qsys_unb1_minimal.qip
11. For future compilations the file qsys_unb1_minimal.qsys
(after SOPC->QSYS it is this file: ~/RadioHDL/trunk/build/quartus/unb1_minimal/sopc_unb1_minimal.qsys)
diff --git a/boards/uniboard1/designs/unb1_minimal/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/hdllib.cfg
index f78ab28d3cb8808fe0e41c5887748c3b6deec7ab..83c59ab9e86d6957a7803866bc9f0a9caddf590b 100644
--- a/boards/uniboard1/designs/unb1_minimal/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
synth_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_minimal_sopc/sopc_unb1_minimal.vhd
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_minimal_sopc/sopc_unb1_minimal.vhd
src/vhdl/qsys_unb1_minimal_pkg.vhd
src/vhdl/mmm_unb1_minimal.vhd
src/vhdl/unb1_minimal.vhd
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg
index deb47a3d479505985aeda879aa9429b3f4affa6e..13fa7738f7019913ee5fa4b8f3ef809b8acf8f70 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg
@@ -32,7 +32,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_minimal_mm_arbiter/qsys_unb1_minimal_mm_arbiter/synthesis/qsys_unb1_minimal_mm_arbiter.qip
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_minimal_mm_arbiter/qsys_unb1_minimal_mm_arbiter/synthesis/qsys_unb1_minimal_mm_arbiter.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg
index fe15d426ddfcafe3c9476aa1a7fbee75533c0bee..0cb052797c19454015e07816390d3709c3ad9125 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg
@@ -35,7 +35,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_minimal_qsys/qsys_unb1_minimal/synthesis/qsys_unb1_minimal.qip
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_minimal_qsys/qsys_unb1_minimal/synthesis/qsys_unb1_minimal.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg
index c338c16de20ea62f1a58bd30c10ea1106194e8a4..ba9098f82fc57660fba7e660a29cf2b050b0ac74 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg
@@ -34,7 +34,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal/synthesis/qsys_wo_pll_unb1_minimal.qip
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal/synthesis/qsys_wo_pll_unb1_minimal.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg
index 9bc3748356d2625dae7d81a1463fbd4ea622a099..872744005aab2a2fbfdaa602f407c791f7ab6d81 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg
@@ -32,7 +32,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_minimal_sopc/sopc_unb1_minimal.qip
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_minimal_sopc/sopc_unb1_minimal.qip
nios2_app_userflags = -DCOMPILE_FOR_SOPC
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.fpga.yaml b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.fpga.yaml
index d6ee3b63770c2411d856bd2c111f507784a6a7e5..c9db53eee21d5d95387444fe9e17a93af102899d 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.fpga.yaml
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.fpga.yaml
@@ -9,64 +9,42 @@ fpga_description: |
"unb1_minimal system for sopc"
peripherals:
- - peripheral_name: rom_system_info
- subsystem_name : ''
+ - peripheral_name: unb1_board/system
slave_port_names:
- - rom_system_info
- parameters:
- - { name: lock_base_address, value: 0x1000 }
-
- - peripheral_name: reg_system_info
-
- subsystem_name : ''
+ - pio_system_info
+ - peripheral_name: unb1_board/rom_system
slave_port_names:
- - pio_system_info
- parameters:
- - { name: lock_base_address, value: 0x0 }
-
- - peripheral_name: ctrl_unb1_board
- subsystem_name : ''
+ - rom_system_info
+ - peripheral_name: unb1_board/ctrl
slave_port_names:
- - pio_wdi
-
- - peripheral_name: unb1_board_wdi_reg
- subsystem_name : ''
+ - pio_wdi
+ - peripheral_name: unb1_board/wdi
slave_port_names:
- - reg_wdi
-
- - peripheral_name: eth1g
- subsystem_name : ''
+ - reg_wdi
+ - peripheral_name: eth/eth1g
slave_port_names:
- - avs_eth_0_mms_tse
- - avs_eth_0_mms_reg
- - avs_eth_0_mms_ram
-
- - peripheral_name: ppsh
- subsystem_name : ''
+ - avs_eth_0_tse
+ - avs_eth_0_reg
+ - avs_eth_0_ram
+ - peripheral_name: ppsh/ppsh
slave_port_names:
- - pio_pps
-
- - peripheral_name: epcs_reg
- subsystem_name : ''
+ - pio_pps
+ - peripheral_name: epcs/epcs
slave_port_names:
- - reg_epcs
- - reg_mmdp_ctrl
- - reg_mmdp_data
- - reg_dpmm_ctrl
- - reg_dpmm_data
- parameters:
+ - reg_epcs
+ - reg_dpmm_ctrl
+ - reg_dpmm_data
+ - reg_mmdp_ctrl
+ - reg_mmdp_data
+ parameter_overrides:
- { name : g_sim_flash_model, value: FALSE }
-
- - peripheral_name: remu_reg
- subsystem_name : ''
+ - peripheral_name: remu/remu
slave_port_names:
- - reg_remu
-
- - peripheral_name: unb1_board_sens_reg
- subsystem_name : ''
+ - reg_remu
+ - peripheral_name: unb1_board/sens
slave_port_names:
- - reg_unb_sens
- parameters:
+ - reg_unb_sens
+ parameter_overrides:
- { name : g_sim, value: FALSE }
- { name : g_clk_freq, value: 125E6 }
- { name : g_temp_high, value: 85 }
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
index f7db8733bd9c89611f906dfd740d56ecf1524ef2..0179234f75cf6f9636149ecf3334e126abf1e5d2 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
synth_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.v
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.v
src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
src/vhdl/node_unb1_terminal_bg_mesh_db.vhd
src/vhdl/unb1_terminal_bg_mesh_db.vhd
@@ -33,7 +33,7 @@ quartus_tcl_files =
quartus/unb1_terminal_bg_mesh_db_pins.tcl
quartus_qip_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.qip
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.qip
quartus_sdc_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
diff --git a/boards/uniboard1/designs/unb1_test/doc/README b/boards/uniboard1/designs/unb1_test/doc/README
index e2fdce714481f03d9ec2e3d12e35af559ed25dd8..9939ae7eeb01e10d89cb2d4e8f644b991e6eb1d0 100644
--- a/boards/uniboard1/designs/unb1_test/doc/README
+++ b/boards/uniboard1/designs/unb1_test/doc/README
@@ -121,7 +121,7 @@ The 2nd tcl file can be created with Quartus. Here are the steps:
- generate the IP's by running: $RADIOHDL_WORK/libraries/technology/ip_stratixiv/generate-all-ip.sh
- Start synthesis in the Quartus GUI. Only the Analysis step!!
- Then in Quartus click: Tools/TclScripts.
- Open the Tcl file: $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0_pin_assignments.tcl
+ Open the Tcl file: $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0_pin_assignments.tcl
Click Run.
- Then Continue synthesis with Fitter, or restart with Analysis.
- Copy the generated build/unb1_test_ddr_MB_I_II.qsf file to ./designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/quartus/unb1_test_ddr_MB_I_II_pins_constraints.tcl
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
index 6cd3f1ca727cd5d7e10a62b620790d008150b61c..cd2f29bacfc8c8cb2c18b66b74074c865ca33dca 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
@@ -35,7 +35,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_test_10GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_10GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg
index 6a8245325ddcec9eb168109d0b005e22817e41a4..78d24bed859fe4c9ea2a3e876cc0430f885c0fc5 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg
@@ -35,7 +35,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_test_10GbE_tx_only/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_10GbE_tx_only/qsys_unb1_test/synthesis/qsys_unb1_test.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg
index b1a6665e016758d1b7601d358415d06df72768bb..aca536d5a71877e379626af55c4ed1fd76df1160 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg
@@ -35,7 +35,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_test_1GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_1GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
index 9c83f47a8dd7256d547aaa95a00b8bc5b9a38fb8..1640cf177a84738ed038c0dd10f9740d4ed5fd6c 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
@@ -40,9 +40,9 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_test_all/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
- #$HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_all/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+ $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+ #$RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
index 14de6969547a38e650fe61774ee632b2e747c5c6..64c9950b5d56a1dd6efba9ba7e6bed4281667c3c 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
@@ -40,9 +40,9 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
- #$HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+ $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+ #$RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg
index 64451014bed47872dd3176a43c4662a0b2dc3fcd..45d53b348e9277fc93173ca4a042858dc4abde73 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg
@@ -41,8 +41,8 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+ $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg
index 48f3e6132c2271b31a7f22854a61ca3f39dbfe6c..e6ab3a6e1e53b21e04aec1a6e9a7174d5fef4f69 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg
@@ -40,8 +40,8 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+ $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg
index 87fbbf48a8a68f94e071d36b8d90e392ab569ec5..c686e3dc316267ab5b53890ceccfae883da4e143 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg
@@ -40,8 +40,8 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+ $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
index 92dd925a6646d7477110ba86703149522eaa8ccb..a82fc8400e3c133a771a001a9fb094a7ea87c32f 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
@@ -40,8 +40,8 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+ $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
index ffb6a7e81a155d9b9c578d7bed411c916d28acf2..02712a8aa2a01190b75c7ac80886cbcb30bea360 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
@@ -40,8 +40,8 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+ $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
index 76ca23e4b7d50df2e4aca15005d2b06a73f53d97..e299f486007a5d3f5b81d89048b2e2f43e4a8e83 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
@@ -39,8 +39,8 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+ $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
index 5e10bf15e3c51ad17bf3c4ebfd9ca25b5ae84c84..2fdbe5db8cf17a85abf711380108686fdff7d491 100644
--- a/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
synth_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_tr_10GbE/qsys_unb1_tr_10GbE/synthesis/qsys_unb1_tr_10GbE.v
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_tr_10GbE/qsys_unb1_tr_10GbE/synthesis/qsys_unb1_tr_10GbE.v
src/vhdl/mmm_unb1_tr_10GbE.vhd
src/vhdl/unb1_tr_10GbE.vhd
@@ -36,7 +36,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_tr_10GbE/qsys_unb1_tr_10GbE/synthesis/qsys_unb1_tr_10GbE.qip
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_tr_10GbE/qsys_unb1_tr_10GbE/synthesis/qsys_unb1_tr_10GbE.qip
quartus_sdc_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
diff --git a/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml b/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml
index 1dc9ae0ba5d39c6614431d04a5b0a2bbab1ebd83..eb6ec2e24c49510c75a88a64aa6432fbab490f5d 100644
--- a/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml
+++ b/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml
@@ -5,98 +5,81 @@ schema_type : peripheral
hdl_library_name : unb1_board
hdl_library_description: " This is the description for the unb1_board package "
+# <peripheral_group>_<peripheral_name>_<slave_name>_<slave_type>
+
peripherals:
- -
- peripheral_name: rom_system_info
+ - peripheral_name: rom_system
slave_ports:
- -
# rom_system_info
- slave_prefix : WORK
- slave_name : ROM_SYSTEM_INFO
- slave_postfix: REG
+ - slave_name : info
slave_type : REG
fields:
- -
- field_name : field_rom_info
- access_mode : RO
- address_offset: 0x0
- number_of_fields: 1024
- field_description: |
- "address place for rom_system_info"
+ - - field_name : info
+ access_mode : RO
+ address_offset: 0x0
+ number_of_fields: 1024
+ field_description: |
+ "address place for rom_system_info"
slave_description: " rom_info "
peripheral_description: |
" settings for rom_system_info register "
- -
- peripheral_name: reg_system_info
+
+ - peripheral_name: system
slave_ports:
- -
# reg_system_info
- slave_prefix : WORK
- slave_name : REG_SYSTEM_INFO
- slave_postfix: REG
+ - slave_name : info
slave_type : REG
fields:
- -
- field_name : field_reg_info
- access_mode : RO
- address_offset: 0x0
- number_of_fields: 31
- field_description: |
- "address place for reg_system_info"
+ - - field_name : info
+ access_mode : RO
+ address_offset: 0x0
+ number_of_fields: 32
+ field_description: |
+ "address place for reg_system_info"
slave_description: " reg_info "
peripheral_description: |
" settings for reg_system_info register "
# peripheral, unb1_board_wdi_reg
- -
- peripheral_name: ctrl_unb1_board
+ - peripheral_name: ctrl
slave_ports:
- -
- # actual hdl name: unb1_board_wdi_reg
- slave_prefix : UNB1_BOARD
- slave_name : PIO_WDI
- slave_postfix: REG
+ # actual hdl name: unb1_board_wdi_reg
+ - slave_name : pio_wdi
slave_type : REG
fields:
- -
- field_name : nios_reset
- access_mode : WO
- address_offset : 0x0
- number_of_fields: 4
- field_description: " Reset done by nios "
+ - - field_name : nios_reset
+ width : 32
+ access_mode : WO
+ address_offset : 0x0
+ number_of_fields: 1
+ field_description: " Reset done by nios "
slave_description: "Reset register, for nios "
peripheral_description: " "
# peripheral, unb1_board_wdi_reg
- -
- peripheral_name: unb1_board_wdi_reg
+ - peripheral_name: wdi
slave_ports:
- -
- # actual hdl name: unb1_board_wdi_reg
- slave_prefix : UNB1_BOARD
- slave_name : WDI
- slave_postfix: REG
+ # actual hdl name: unb1_board_wdi_reg
+ - slave_name : wdi
slave_type : REG
fields:
- -
- field_name : reset_word
- access_mode : WO
- address_offset: 0x0
- field_description: " Only the value 0xB007FAC7 'Boot factory' will result in a reset "
-
+ - - field_name : reset_word
+ access_mode : WO
+ address_offset: 0x0
+ field_description: " Only the value 0xB007FAC7 'Boot factory' will result in a reset "
+
slave_description: "Reset register, if the right value is provided the factory image will be reloaded "
peripheral_description: " "
# periheral, unb1_board_sens
- -
- peripheral_name: unb1_board_sens_reg
+ - peripheral_name: sens
parameters:
- { name: g_sim, value: FALSE }
@@ -104,41 +87,35 @@ peripherals:
- { name: g_temp_high, value: 85 }
slave_ports:
- -
- # actual hdl name: reg_unb1_sens
- slave_prefix : UNB1_BOARD
- slave_name : SENS
- slave_postfix: REG
+ # actual hdl name: reg_unb1_sens
+ - slave_name : sens
slave_type : REG
fields:
- -
- field_name : sens_data
- width : 8
- access_mode : RO
- address_offset: 0x0
- number_of_fields: 4
- field_description: |
- " data array with sens data
- 0x0 = fpga temperature in degrees (two's complement)
- 0x1 = eth_temp temperature in degrees (two's complement)
- 0x2 = hot_swap_v_sens
- 0x3 = hot_swap_v_source"
-
- -
- field_name : sens_err
- width : 1
- access_mode : RO
- address_offset: 0x4
- radix : unsigned
- field_description: ""
+ - - field_name : sens_data
+ width : 8
+ access_mode : RO
+ address_offset: 0x0
+ number_of_fields: 4
+ field_description: |
+ " data array with sens data
+ 0x0 = fpga temperature in degrees (two's complement)
+ 0x1 = eth_temp temperature in degrees (two's complement)
+ 0x2 = hot_swap_v_sens
+ 0x3 = hot_swap_v_source"
+
+ - - field_name : sens_err
+ width : 1
+ access_mode : RO
+ address_offset: 0x10
+ radix : unsigned
+ field_description: ""
- -
- field_name : temp_high
- width : 7
- address_offset: 0x5
- reset_value : g_temp_high
- software_value: g_temp_high
- field_description: ""
+ - - field_name : temp_high
+ width : 7
+ address_offset: 0x14
+ reset_value : g_temp_high
+ software_value: g_temp_high
+ field_description: ""
slave_description: " "
diff --git a/boards/uniboard2/designs/unb2_minimal/hdllib.cfg b/boards/uniboard2/designs/unb2_minimal/hdllib.cfg
index baf6be9c0fda52ee72fe1e7846fd3228eb915c80..93e521fbb0eb01f56f60c93e98316de8c28a1e8c 100644
--- a/boards/uniboard2/designs/unb2_minimal/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_minimal/hdllib.cfg
@@ -34,7 +34,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb2/quartus/unb2_minimal/qsys_unb2_minimal/synthesis/qsys_unb2_minimal.qip
+ $RADIOHDL_BUILD_DIR/unb2/quartus/unb2_minimal/qsys_unb2_minimal/synthesis/qsys_unb2_minimal.qip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
index 11d333fa4a8db05cc7fb60edf295302958d89ec6..94a1d7a4b5dc81519f691645119e391a112bd0a6 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
@@ -56,7 +56,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb2/quartus/unb2_test_10GbE/qsys_unb2_test/synthesis/qsys_unb2_test.qip
+ $RADIOHDL_BUILD_DIR/unb2/quartus/unb2_test_10GbE/qsys_unb2_test/synthesis/qsys_unb2_test.qip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
index 29426ebaefb735a48310cc43360a7cd29c7fba0f..71f2e12e3d263d1c5694968f434eae78e10aaec4 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
@@ -35,7 +35,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb2/quartus/unb2_test_1GbE/qsys_unb2_test/synthesis/qsys_unb2_test.qip
+ $RADIOHDL_BUILD_DIR/unb2/quartus/unb2_test_1GbE/qsys_unb2_test/synthesis/qsys_unb2_test.qip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
index 49cb72afe5e583f8097524505ed2cb450f1c78fd..980805831d7e154500d89e17e353eca603cb1ff6 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
@@ -61,7 +61,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb2/quartus/unb2_test_all/qsys_unb2_test/synthesis/qsys_unb2_test.qip
+ $RADIOHDL_BUILD_DIR/unb2/quartus/unb2_test_all/qsys_unb2_test/synthesis/qsys_unb2_test.qip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
index 32d7e2b66d0d2947e519ff5b7a56a9aff8f834f3..0e60dc6cc014f1f1c2b984b2e25f322851d903a0 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
@@ -36,7 +36,7 @@ quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
quartus_qip_files =
- $HDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_I/qsys_unb2_test/synthesis/qsys_unb2_test.qip
+ $RADIOHDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_I/qsys_unb2_test/synthesis/qsys_unb2_test.qip
quartus_tcl_files =
quartus/unb2_test_ddr_MB_I_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
index e7f73d38757f87d359b30281b3212b11ac8f9a33..2d80edfff0b5a8c85243997e0a3afb648702ba4f 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
@@ -36,7 +36,7 @@ quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
quartus_qip_files =
- $HDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_II/qsys_unb2_test/synthesis/qsys_unb2_test.qip
+ $RADIOHDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_II/qsys_unb2_test/synthesis/qsys_unb2_test.qip
quartus_tcl_files =
quartus/unb2_test_ddr_MB_II_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
index 4c2b30eb68315146bf192916426ea47681cfaced..69ccd15818216ce41350817cb15f3085964681e2 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
@@ -36,7 +36,7 @@ quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
quartus_qip_files =
- $HDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_I_II/qsys_unb2_test/synthesis/qsys_unb2_test.qip
+ $RADIOHDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_I_II/qsys_unb2_test/synthesis/qsys_unb2_test.qip
quartus_tcl_files =
quartus/unb2_test_ddr_MB_I_II_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg b/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg
index 93adc2818af06c42526e4a54afdf0765fa6c4239..606ea20f76bfe81095761ae13c27bce1653b5027 100644
--- a/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg
@@ -34,7 +34,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb2a/quartus/unb2a_heater/qsys_unb2a_heater/synthesis/qsys_unb2a_heater.qip
+ $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_heater/qsys_unb2a_heater/synthesis/qsys_unb2a_heater.qip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg b/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg
index 5fdd289221b68399510cec10cc970efa064c89b8..d06919a710843ba166221d78b5ce75b37da04d48 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg
@@ -34,7 +34,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb2a/quartus/unb2a_minimal/qsys_unb2a_minimal/synthesis/qsys_unb2a_minimal.qip
+ $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_minimal/qsys_unb2a_minimal/synthesis/qsys_unb2a_minimal.qip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
index 8529b7eb5db2adf22b31c8623beaa068165f4d88..22976e6d86bea2e9b8fe53ef5d166601ae00d822 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
@@ -59,7 +59,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb2a/quartus/unb2a_test_10GbE/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
+ $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_test_10GbE/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
index 22de500f6e73eafba43ccdf186250ea7cccbb503..2baa5dd51a0ad479ea5cc15519f5bd702740f8e3 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
@@ -35,7 +35,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb2a/quartus/unb2a_test_1GbE/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
+ $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_test_1GbE/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
index bc11b4b0367248efe478d2a0c0adc26b74332445..c0fe8620de3c10a9e101470d6829d8d73ed8aff2 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
@@ -62,7 +62,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb2a/quartus/unb2a_test_all/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
+ $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_test_all/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
index 79cbeb53282b4d69aaa07577b49feb5a095ce93b..5886fa177c2ae9fa67c24c3f81e271a094f9a3cc 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
@@ -37,7 +37,7 @@ quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
quartus_qip_files =
- $HDL_BUILD_DIR/unb2a/quartus/unb2a_test_ddr_MB_I/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
+ $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_test_ddr_MB_I/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
quartus_tcl_files =
quartus/unb2a_test_ddr_MB_I_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
index ff9a3d4b7a62ce2410a18bfc89d680a43f717bbd..e15377b23d0e850669dfedb634769c2ab1640e00 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
@@ -37,7 +37,7 @@ quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
quartus_qip_files =
- $HDL_BUILD_DIR/unb2a/quartus/unb2a_test_ddr_MB_II/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
+ $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_test_ddr_MB_II/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
quartus_tcl_files =
quartus/unb2a_test_ddr_MB_II_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
index 2b8b063d7e0a47e390f5ff875de6dda4b745a0ef..fd9199ad99711573ad4fd40353e70e67f06ec4ff 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
@@ -37,7 +37,7 @@ quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
quartus_qip_files =
- $HDL_BUILD_DIR/unb2a/quartus/unb2a_test_ddr_MB_I_II/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
+ $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_test_ddr_MB_I_II/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
quartus_tcl_files =
quartus/unb2a_test_ddr_MB_I_II_pins.tcl
diff --git a/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg b/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg
index cad8b1c16ab141d979202f288102f8b79ebb9e16..9d8ad666907f428c808f9f26c63ddfb733b227c9 100644
--- a/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg
@@ -34,31 +34,31 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/qsys_unb2b_heater/qsys_unb2b_heater.qip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/qsys_unb2b_heater/qsys_unb2b_heater.qip
quartus_ip_files =
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_avs_eth_0.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_clk_0.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_cpu_0.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_jtag_uart_0.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_onchip_memory2_0.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_pio_pps.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_pio_system_info.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_pio_wdi.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_dpmm_ctrl.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_dpmm_data.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_epcs.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_fpga_temp_sens.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_fpga_voltage_sens.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_heater.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_mmdp_ctrl.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_mmdp_data.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_remu.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_unb_pmbus.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_unb_sens.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_wdi.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_rom_system_info.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_timer_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_avs_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_clk_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_cpu_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_jtag_uart_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_onchip_memory2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_pio_pps.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_pio_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_pio_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_dpmm_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_dpmm_data.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_epcs.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_fpga_temp_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_fpga_voltage_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_heater.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_mmdp_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_remu.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_unb_pmbus.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_unb_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_rom_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2b/designs/unb2b_jesd/hdllib.cfg b/boards/uniboard2b/designs/unb2b_jesd/hdllib.cfg
index dc01f1470182e33f393473bf917dc96820c9928c..72f15b0a7355071c4a5a74cf6d1de598c7acb6b3 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_jesd/hdllib.cfg
@@ -34,6 +34,6 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_jesd/qsys_unb2b_jesd/qsys_unb2b_jesd.qip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_jesd/qsys_unb2b_jesd/qsys_unb2b_jesd.qip
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/hdllib.cfg b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/hdllib.cfg
index a357b0ac5c8ffa6ef1463cbd2ebe4368caff8858..de64e7f039857c34c7c167c537c039e51f63e04c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/hdllib.cfg
@@ -31,6 +31,6 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_jesd_node0/qsys_unb2b_jesd/qsys_unb2b_jesd.qip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_jesd_node0/qsys_unb2b_jesd/qsys_unb2b_jesd.qip
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/hdllib.cfg b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/hdllib.cfg
index d4b0c462fc557de1074c6a6147c62b7b61267b45..324205ffa195e1ea2ed9d019b1b02b9e267c5834 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/hdllib.cfg
@@ -31,6 +31,6 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_jesd_node3/qsys_unb2b_jesd/qsys_unb2b_jesd.qip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_jesd_node3/qsys_unb2b_jesd/qsys_unb2b_jesd.qip
diff --git a/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg b/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
index c14007d56250625c914f10559a915a752fbea450..d5eb95c53e926a6f7869e38d3a9cab1ed7b510a4 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
@@ -34,30 +34,30 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/qsys_unb2b_minimal/qsys_unb2b_minimal.qip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/qsys_unb2b_minimal/qsys_unb2b_minimal.qip
quartus_ip_files =
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info.ip
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg
index 02c44bf134a4b7bef4135f0391c3b9bb8699f00b..cdaa8c7e78ccaf4d769d221ef8e076539d9866b4 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg
@@ -60,7 +60,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_10GbE/qsys_unb2b_test/qsys_unb2b_test.qip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_10GbE/qsys_unb2b_test/qsys_unb2b_test.qip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_heater/hdllib.cfg b/boards/uniboard2c/designs/unb2c_heater/hdllib.cfg
index 385dbb59a6925d92e91c658378d1c501adf4af57..50492e0e239604b017999e3119e2f17d79d94b47 100644
--- a/boards/uniboard2c/designs/unb2c_heater/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_heater/hdllib.cfg
@@ -34,31 +34,31 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/qsys_unb2c_heater/qsys_unb2c_heater.qip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/qsys_unb2c_heater/qsys_unb2c_heater.qip
quartus_ip_files =
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_avs_eth_0.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_clk_0.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_cpu_0.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_jtag_uart_0.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_onchip_memory2_0.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_pio_pps.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_pio_system_info.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_pio_wdi.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_dpmm_ctrl.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_dpmm_data.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_epcs.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_fpga_temp_sens.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_fpga_voltage_sens.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_heater.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_mmdp_ctrl.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_mmdp_data.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_remu.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_unb_pmbus.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_unb_sens.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_wdi.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_rom_system_info.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_timer_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_avs_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_clk_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_cpu_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_jtag_uart_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_onchip_memory2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_pio_pps.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_pio_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_pio_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_dpmm_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_dpmm_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_epcs.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_fpga_temp_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_fpga_voltage_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_heater.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_mmdp_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_remu.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_unb_pmbus.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_unb_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_rom_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_jesd/hdllib.cfg b/boards/uniboard2c/designs/unb2c_jesd/hdllib.cfg
index 74dd04a7b4c72bce1921dac14bf648ecf7da05e4..9165660bb7cad98c6d59a3d8f6560d8c565dc522 100644
--- a/boards/uniboard2c/designs/unb2c_jesd/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_jesd/hdllib.cfg
@@ -35,6 +35,6 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_jesd/qsys_unb2c_jesd/qsys_unb2c_jesd.qip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_jesd/qsys_unb2c_jesd/qsys_unb2c_jesd.qip
diff --git a/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node0/hdllib.cfg b/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node0/hdllib.cfg
index e580c1600a3dc583d8c5cebea32f2a9b3dfe9c2b..0030745ae318921676899b75bec3251c883b4a94 100644
--- a/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node0/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node0/hdllib.cfg
@@ -31,6 +31,6 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_jesd_node0/qsys_unb2c_jesd/qsys_unb2c_jesd.qip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_jesd_node0/qsys_unb2c_jesd/qsys_unb2c_jesd.qip
diff --git a/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node3/hdllib.cfg b/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node3/hdllib.cfg
index 7a59e62d82807f96856aeb647449f417d9ade20e..b797e647cf1f405ec799d10f20a398cf28986c54 100644
--- a/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node3/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node3/hdllib.cfg
@@ -31,6 +31,6 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_jesd_node3/qsys_unb2c_jesd/qsys_unb2c_jesd.qip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_jesd_node3/qsys_unb2c_jesd/qsys_unb2c_jesd.qip
diff --git a/boards/uniboard2c/designs/unb2c_minimal/hdllib.cfg b/boards/uniboard2c/designs/unb2c_minimal/hdllib.cfg
index 56e214f2466ed59c77fd93296955e7e8b0818829..b41f722c594cb055c2f8b2ac85db2eb965fcb60f 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_minimal/hdllib.cfg
@@ -34,30 +34,30 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/qsys_unb2c_minimal/qsys_unb2c_minimal.qip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/qsys_unb2c_minimal/qsys_unb2c_minimal.qip
quartus_ip_files =
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_avs_eth_0.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_clk_0.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_cpu_0.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_jtag_uart_0.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_onchip_memory2_0.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_pps.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_system_info.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_wdi.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_ctrl.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_data.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_epcs.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_temp_sens.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_voltage_sens.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_ctrl.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_data.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_remu.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_unb_pmbus.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_unb_sens.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_wdi.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_rom_system_info.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_timer_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_avs_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_clk_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_cpu_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_jtag_uart_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_onchip_memory2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_pps.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_epcs.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_temp_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_voltage_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_remu.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_unb_pmbus.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_unb_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_rom_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/hdllib.cfg
index 8b9161b9ace74ec8dc1a3a679fe44ca10f45f289..c604d6b3dec82e2fea0e877145b7499aff6e016d 100644
--- a/boards/uniboard2c/designs/unb2c_test/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/hdllib.cfg
@@ -37,63 +37,63 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/qsys_unb2c_test/qsys_unb2c_test.qip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/qsys_unb2c_test/qsys_unb2c_test.qip
quartus_ip_files =
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_avs_eth_0.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_avs_eth_1.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_cpu_0.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_1gbe.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_1gbe.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_1GbE.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_1gbe.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_1gbe.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_1gbe.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_1gbe.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_ip_arria10_e1sg_phy_10gbase_r_24.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_unb_pmbus.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_unb_sens.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/reg_10gbase_r_24.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_avs_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_avs_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_cpu_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_1GbE.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_ip_arria10_e1sg_phy_10gbase_r_24.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_unb_pmbus.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_unb_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/reg_10gbase_r_24.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg
index 57a240cbb1d5412bdd38aa9dba1830827c0e1fd2..62374dd103db70c4ec4d020305b77f4d5451e46c 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg
@@ -57,62 +57,62 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/qsys_unb2c_test/qsys_unb2c_test.qip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/qsys_unb2c_test/qsys_unb2c_test.qip
quartus_ip_files =
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_avs_eth_0.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_avs_eth_1.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_clk_0.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_cpu_0.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_jtag_uart_0.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_onchip_memory2_0.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_pio_pps.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_pio_system_info.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_pio_wdi.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_bg_10gbe.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_bg_1gbe.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_data_buffer_1gbe.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_bsn_monitor_1GbE.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_bg_10gbe.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_bg_1gbe.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_data_buffer_1gbe.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_rx_seq_1gbe.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_tx_seq_1gbe.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_dpmm_ctrl.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_dpmm_data.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_epcs.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_eth10g_back0.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_eth10g_back1.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_fpga_temp_sens.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_fpga_voltage_sens.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_io_ddr_MB_I.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_io_ddr_MB_II.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_ip_arria10_e1sg_phy_10gbase_r_24.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_mmdp_ctrl.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_mmdp_data.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_remu.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_tr_10GbE_back0.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_tr_10GbE_back1.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_unb_pmbus.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_unb_sens.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_wdi.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_rom_system_info.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_timer_0.ip
- $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/reg_10gbase_r_24.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_avs_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_avs_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_clk_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_cpu_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_jtag_uart_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_onchip_memory2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_pio_pps.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_pio_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_pio_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_bg_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_bg_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_data_buffer_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_bsn_monitor_1GbE.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_bg_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_bg_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_data_buffer_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_rx_seq_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_tx_seq_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_dpmm_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_dpmm_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_epcs.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_eth10g_back0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_eth10g_back1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_fpga_temp_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_fpga_voltage_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_io_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_io_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_ip_arria10_e1sg_phy_10gbase_r_24.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_mmdp_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_remu.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_tr_10GbE_back0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_tr_10GbE_back1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_unb_pmbus.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_unb_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_rom_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_timer_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/reg_10gbase_r_24.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/init_hdl.sh b/init_hdl.sh
index 42eeaaab84b5baf6d436e9612c7e9033a8fe730e..8dfeb67292e7e6c6ddd95e950575a31ab534ffc3 100644
--- a/init_hdl.sh
+++ b/init_hdl.sh
@@ -34,29 +34,42 @@ if [[ "$_" == "${0}" ]]; then
exit
fi
+#
+if [ -z "${ALTERA_DIR}" ]; then
+ echo "== environ variable 'ALTERA_DIR' not set. =="
+ echo "should be in your .bashrc file."
+ echo "if it is your .bashrc file but not active run bash in your terminal"
+ exit
+fi
# Figure out where this script is located and set environment variables accordingly
export RADIOHDL_WORK="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
-# setup paths to build and config dir if not already defined by the user.
-export HDL_BUILD_DIR=${HDL_BUILD_DIR:-${RADIOHDL_WORK}/build}
echo "HDL environment will be setup for" $RADIOHDL_WORK
+# setup paths to build and config dir if not already defined by the user.
+export ARGS_WORK=${RADIOHDL_WORK}
+export RADIOHDL_BUILD_DIR=${RADIOHDL_WORK}/build
+
# modelsim uses this sim dir for testing
-export HDL_IOFILE_SIM_DIR=${HDL_IOFILE_SIM_DIR:-${HDL_BUILD_DIR}/sim}
-if ! [[ -e HDL_IOFILE_SIM_DIR ]]; then
+export HDL_IOFILE_SIM_DIR=${RADIOHDL_BUILD_DIR}/sim
+if [[ ! -d "${HDL_IOFILE_SIM_DIR}" ]]; then
echo "make sim dir"
- mkdir ${HDL_BUILD_DIR}/sim
+ mkdir "${HDL_IOFILE_SIM_DIR}"
+fi
+# if sim dir not empty, remove all files and dirs
+if [ ! -z "$(ls -A ${HDL_IOFILE_SIM_DIR})" ]; then
+ echo "clear sim dir"
+ rm -r ${HDL_IOFILE_SIM_DIR}/*
fi
-rm -r ${HDL_BUILD_DIR}/sim/*
# copy git user_componets.ipx into Altera dir's
for altera_dir in ${ALTERA_DIR}/*; do
- if [[ -d ${altera_dir} ]] && [[ ! -h ${altera_dir} ]]; then
+ if [[ -d "${altera_dir}" ]] && [[ ! -h "${altera_dir}" ]]; then
echo "copy git hdl_user_components.ipx to ${altera_dir}/ip/altera/user_components.ipx"
cp ${RADIOHDL_WORK}/hdl_user_components.ipx $altera_dir/ip/altera/user_components.ipx
fi
done
-if [ -z "${RADIOHDL_GEAR}" ]; then
- . ../radiohdl/init_radiohdl.sh
-fi
+# source also radiohdl and args tools
+. ../radiohdl/init_radiohdl.sh
+. ../args/init_args.sh
diff --git a/libraries/base/diag/diag.peripheral.yaml b/libraries/base/diag/diag.peripheral.yaml
index 65d1b28189256ecc88e25db0154d238a8e09225d..139d78141f26d08793d8f00ae1eeff6bdd4ab2eb 100644
--- a/libraries/base/diag/diag.peripheral.yaml
+++ b/libraries/base/diag/diag.peripheral.yaml
@@ -7,7 +7,7 @@ hdl_library_description: " This is the description for the bf package "
peripherals:
-
- peripheral_name: diag_block_gen
+ peripheral_name: block_gen
parameters:
- { name: g_nof_streams, value: 1 }
@@ -15,80 +15,73 @@ peripherals:
- { name: g_buf_addr_w , value: 7 }
slave_ports:
- -
# actual hdl name: reg_diag_bg
- slave_prefix : DIAG
- slave_name : BG
- slave_postfix: REG
+ - slave_name : ctrl
slave_type : REG
fields:
- -
- field_name : Enable
- width : 2
- address_offset: 0x0
- field_description: |
- "Bit 0: enable the block generator Bit 1: enable the blok generator on PPS"
- -
- field_name : Samples_per_packet
- width : 16
- address_offset: 0x1
- reset_value : 256
- field_description: |
- "This REG specifies the number samples in a packet"
- -
- field_name : Blocks_per_sync
- width : 16
- address_offset: 0x2
- reset_value : 781250
- field_description: |
- "This REG specifies the number of packets in a sync period"
- -
- field_name : Gapsize
- width : 16
- address_offset: 0x3
- reset_value : 80
- field_description: |
- "This REG specifies the gap in number of clock cycles between two consecutive packets"
- -
- field_name : Mem_low_address
- width : 8
- address_offset: 0x4
- field_description: |
- "This REG specifies the starting address for reading from the waveform memory"
- -
- field_name : Mem_high_address
- width : 8
- address_offset: 0x5
- field_description: |
- "This REG specifies the last address to be read when from the waveform memory"
- -
- field_name : BSN_init_low
- address_offset: 0x6
- field_description: |
- "This REG specifies the lower(LSB) 32 bits [31:0] of the initialization BSN"
- -
- field_name : BSN_init_high
- address_offset: 0x7
- field_description: |
- "This REG specifies the higher(MSB) 32 bits [63:32] of the initialization BSN"
- -
+ - - field_name : Enable
+ width : 2
+ address_offset: 0x0
+ field_description: |
+ "Bit 0: enable the block generator Bit 1: enable the blok generator on PPS"
+
+ - - field_name : Samples_per_packet
+ width : 16
+ address_offset: 0x4
+ reset_value : 256
+ field_description: |
+ "This REG specifies the number samples in a packet"
+
+ - - field_name : Blocks_per_sync
+ width : 16
+ address_offset: 0x8
+ reset_value : 781250
+ field_description: |
+ "This REG specifies the number of packets in a sync period"
+
+ - - field_name : Gapsize
+ width : 16
+ address_offset: 0xc
+ reset_value : 80
+ field_description: |
+ "This REG specifies the gap in number of clock cycles between two consecutive packets"
+
+ - - field_name : Mem_low_address
+ width : 8
+ address_offset: 0x10
+ field_description: |
+ "This REG specifies the starting address for reading from the waveform memory"
+
+ - - field_name : Mem_high_address
+ width : 8
+ address_offset: 0x14
+ field_description: |
+ "This REG specifies the last address to be read when from the waveform memory"
+
+ - - field_name : BSN_init_low
+ address_offset: 0x18
+ field_description: |
+ "This REG specifies the lower(LSB) 32 bits [31:0] of the initialization BSN"
+
+ - - field_name : BSN_init_high
+ address_offset: 0x1c
+ field_description: |
+ "This REG specifies the higher(MSB) 32 bits [63:32] of the initialization BSN"
+
# actual hdl name: ram_diag_bg
- slave_prefix : DIAG
- slave_name : BG
- slave_postfix: RAM
+ - slave_name : wave_data
number_of_slaves: g_nof_streams
slave_type : RAM
fields:
- -
- field_name: diag_bg
- width: g_buf_dat_w
- number_of_fields: 2**g_buf_addr_w
- field_description : |
- "Contains the Waveform data for the data-streams to be send"
+ - - field_name: diag_bg
+ width: g_buf_dat_w
+ number_of_fields: 2**g_buf_addr_w
+ field_description : |
+ "Contains the Waveform data for the data-streams to be send"
peripheral_description: |
"Block generator"
- -
- peripheral_name: diag_data_buffer
+
+ - peripheral_name: data_buffer
parameters:
- { name: g_nof_streams , value: 1 }
@@ -96,60 +89,52 @@ peripherals:
- { name: g_buf_nof_data, value: 1024 }
slave_ports:
- -
# actual hdl name: reg_diag_data_buffer
- slave_prefix : DIAG
- slave_name : DATA_BUFFER
- slave_postfix: REG
+ - slave_name : status
slave_type : REG
fields:
- -
- field_name : Sync_cnt
- access_mode : RO
- address_offset: 0x0
- field_description: |
- "Sync_cnt contains the nof times the buffer (ST) has received a sync pulse since the last MM read
- (cleared when the last data word from the buffer is read)"
- -
- field_name : Word_cnt
- access_mode : RO
- address_offset: 0x1
- field_description: |
- "Word_cnt indicates the number of word currently (ST) written in the buffer. Cleared on (ST) re-write of buffer."
- -
- field_name : Valid_cnt_arm_ena
- address_offset: 0x2
- field_description: |
- "Valid_cnt contains the number of valid cycles since the last sync pulse. Cleared on every sync pulse.
- Arm_enable: Write to this REG to arm the system.
- After the system is armed the next syn pulse will trigger the acquisition of data."
- -
- field_name : Reg_sync_delay
- address_offset: 0x3
- field_description: |
- "Reg_sync_delay contains the number of valid cycles to delay/wait after an armed-syncpulse,
- before the data is written to the databuffer."
- -
- field_name : Version
- access_mode : RO
- address_offset: 0x7
- field_description: |
- "Version contains the version number of the databuffer peripheral."
+ - - field_name : Sync_cnt
+ access_mode : RO
+ address_offset: 0x0
+ field_description: |
+ "Sync_cnt contains the nof times the buffer (ST) has received a sync pulse since the last MM read
+ (cleared when the last data word from the buffer is read)"
+
+ - - field_name : Word_cnt
+ access_mode : RO
+ address_offset: 0x4
+ field_description: |
+ "Word_cnt indicates the number of word currently (ST) written in the buffer. Cleared on (ST) re-write of buffer."
+
+ - - field_name : Valid_cnt_arm_ena
+ address_offset: 0x8
+ field_description: |
+ "Valid_cnt contains the number of valid cycles since the last sync pulse. Cleared on every sync pulse.
+ Arm_enable: Write to this REG to arm the system.
+ After the system is armed the next syn pulse will trigger the acquisition of data."
+
+ - - field_name : Reg_sync_delay
+ address_offset: 0xc
+ field_description: |
+ "Reg_sync_delay contains the number of valid cycles to delay/wait after an armed-syncpulse,
+ before the data is written to the databuffer."
+
+ - - field_name : Version
+ access_mode : RO
+ address_offset: 0x1c
+ field_description: |
+ "Version contains the version number of the databuffer peripheral."
slave_description: ""
- -
# actual hdl name: ram_diag_data_buffer
- slave_prefix : DIAG
- slave_name : DATA_BUFFER
- slave_postfix: RAM
+ - slave_name : data
number_of_slaves: g_nof_streams
slave_type : RAM
fields:
- -
- field_name : ram
- width : g_data_w
- number_of_fields: g_buf_nof_data
- field_description: |
- "Contains the data that is being captured."
+ - - field_name : ram
+ width : g_data_w
+ number_of_fields: g_buf_nof_data
+ field_description: |
+ "Contains the data that is being captured."
slave_description: ""
peripheral_description: |
diff --git a/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg b/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg
index 0ac4f1ca44488f9f88f660c43fc7e67482662d23..cca9e1d6c59f63fdec3a256a14aac90d4d87515c 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg
+++ b/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
synth_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_dp_offload/sopc_unb1_dp_offload.vhd
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_dp_offload/sopc_unb1_dp_offload.vhd
src/vhdl/mmm_unb1_dp_offload.vhd
src/vhdl/unb1_dp_offload.vhd
@@ -35,7 +35,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_dp_offload/sopc_unb1_dp_offload.qip
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_dp_offload/sopc_unb1_dp_offload.qip
nios2_app_userflags = -DCOMPILE_FOR_SOPC
diff --git a/libraries/base/dp/dp.peripheral.yaml b/libraries/base/dp/dp.peripheral.yaml
index 1c6e7a3bb2e6fcde98cd871db2aad69062201d07..f015f5fcdb514a42c55bcf8e8bcd8ac4c0c5956d 100644
--- a/libraries/base/dp/dp.peripheral.yaml
+++ b/libraries/base/dp/dp.peripheral.yaml
@@ -6,64 +6,54 @@ hdl_library_name : dp
hdl_library_description: " This is the description for the dp package "
peripherals:
- -
- peripheral_name: dp_bsn_align
+ - peripheral_name: bsn
parameters:
- { name: g_nof_input, value : 2 }
slave_ports:
- -
# actual hdl name: reg_dp_bsn_align
- slave_prefix : DP
- slave_name : BSN_ALIGN
- slave_postfix: REG
+ - slave_name : ALIGN
number_of_slaves: g_nof_input
slave_type : REG
fields:
- -
- field_name : Enable
- width : 1
- address_offset : 0x0
- field_description: |
- "Input enable register for input 0. If set to 0 the input is discarded from alignment.
- If set to 1 the corresopnding input is taken into account."
+ - - field_name : Enable
+ width : 1
+ address_offset : 0x0
+ field_description: |
+ "Input enable register for input 0. If set to 0 the input is discarded from alignment.
+ If set to 1 the corresopnding input is taken into account."
slave_discription: " "
-
+
peripheral_description: "This is the BSN aligner"
-
- -
- peripheral_name: dp_fifo_fill
+
+ - peripheral_name: fifo
parameters:
- { name : g_nof_streams, value: 3 }
slave_ports:
- -
# actual hdl name: reg_dp_fifo_fill
- slave_prefix : DP
- slave_name : FIFO_FILL
- slave_postfix: REG
+ - slave_name : fill_status
number_of_slaves: g_nof_streams
slave_type : REG
fields:
- -
- field_name : fifo_used_words
- access_mode : RO
- address_offset : 0x0
- field_description: "Register reflects the currently used nof words on the fifo."
- -
- field_name : fifo_status
- width : 2
- access_mode : RO
- address_offset : 0x1
- field_description: "Bit 0: fifo_read_empty Bit 1: fifo_wr_full."
- -
- field_name : max_fifo_used_words
- access_mode : RO
- address_offset : 0x2
- field_description: |
- "Register contains the maximum number of words that have been in the fifo.
+ - - field_name : fifo_used_words
+ access_mode : RO
+ address_offset : 0x0
+ field_description: "Register reflects the currently used nof words on the fifo."
+
+ - - field_name : fifo_status
+ width : 2
+ access_mode : RO
+ address_offset : 0x4
+ field_description: "Bit 0: fifo_read_empty Bit 1: fifo_wr_full."
+
+ - - field_name : max_fifo_used_words
+ access_mode : RO
+ address_offset : 0x8
+ field_description: |
+ "Register contains the maximum number of words that have been in the fifo.
Will be cleared after it has been read."
slave_discription: ""
-
+
peripheral_description: "This is the MM slave version of the dp_fifo_fill component."
diff --git a/libraries/dsp/bf/bf.peripheral.yaml b/libraries/dsp/bf/bf.peripheral.yaml
index b4359c3404086da5bf4daf68dd0b665f57608799..85987668999582e19448a14b902807b067f9e30e 100644
--- a/libraries/dsp/bf/bf.peripheral.yaml
+++ b/libraries/dsp/bf/bf.peripheral.yaml
@@ -6,7 +6,7 @@ hdl_library_name : bf
hdl_library_description: " This is the description for the bf package "
peripherals:
- - peripheral_name: bf_unit
+ - peripheral_name: bf
parameters:
- { name: g_bf.in_weights_w , value: 16 }
@@ -17,76 +17,61 @@ peripherals:
- { name: c_nof_signal_paths_per_stream, value: g_bf.nof_signal_paths / g_bf.nof_input_streams }
slave_ports:
- -
# ram_bf_weights
- slave_prefix : BF
- slave_name : WEIGHTS
- slave_postfix: RAM
+ - slave_name : WEIGHTS
number_of_slaves: g_bf.nof_weights
slave_type: RAM
fields:
- -
- field_name : bf_weights
- width : g_bf.in_weights_w * c_nof_complex
+ - - field_name : bf_weights
+ width : g_bf.in_weights_w * c_nof_complex
- number_of_fields: g_bf.nof_signal_paths
- field_description: |
- "Contains the weights.
- The real and the imaginary parts are concatenated: W_real in Lower part. W_imag in Higher part."
+ number_of_fields: g_bf.nof_signal_paths
+ field_description: |
+ "Contains the weights.
+ The real and the imaginary parts are concatenated: W_real in Lower part. W_imag in Higher part."
slave_discription: >
" "
-
- -
+
# ram_ss_ss_wide
- slave_prefix : BF
- slave_name : SS_SS_WIDE
- slave_postfix: RAM
+ - slave_name : SS_SS_WIDE
number_of_slaves: g_bf.nof_weights
slave_type: RAM
fields:
- -
- field_name : ss_ss_wide
- width : 32
- number_of_fields: g_bf.nof_subbands * g_bf.nof_input_streams * c_nof_signal_paths_per_stream # 16*4=64, nof_input_streams*nof_signal_paths_per_stream
- field_description: |
- "Contains the addresses to select from the stored subbands."
+ - - field_name : ss_ss_wide
+ width : 32
+ number_of_fields: g_bf.nof_subbands * g_bf.nof_input_streams * c_nof_signal_paths_per_stream # 16*4=64, nof_input_streams*nof_signal_paths_per_stream
+ field_description: |
+ "Contains the addresses to select from the stored subbands."
slave_discription: >
" "
- -
# ram_st_sst_bf
- slave_prefix : BF
- slave_name : ST_SST
- slave_postfix: RAM
+ - slave_name : ST_SST
number_of_slaves: g_bf.nof_weights
slave_type: RAM
fields:
- -
- field_name : st_sst_bf
- width : 56
- number_of_fields: 512
- access_mode : RO
- field_description: |
- "Contains the weights.
- The real and the imaginary parts are concatenated: W_real in Lower part. W_imag in Higher part."
+ - - field_name : st_sst_bf
+ width : 56
+ number_of_fields: 512
+ access_mode : RO
+ field_description: |
+ "Contains the weights.
+ The real and the imaginary parts are concatenated: W_real in Lower part. W_imag in Higher part."
slave_discription: >
+ " "
- -
# reg_st_sst_bf
- slave_prefix : BF
- slave_name : ST_SST
- slave_postfix: REG
+ - slave_name : treshold
number_of_slaves: 1
slave_type: REG
fields:
- -
- field_name : treshold
- address_offset: 0x0
- field_description : |
- "When the treshold register is set to 0 the statistics will be auto-correlations.
- In case the treshold register is set to a non-zero value, it allows to create a sample & hold function
- for the a-input of the multiplier.
- The a-input of the multiplier is updated every treshold clockcycle. Thereby cross statistics can be created."
+ - - field_name : treshold
+ address_offset: 0x0
+ field_description : |
+ "When the treshold register is set to 0 the statistics will be auto-correlations.
+ In case the treshold register is set to a non-zero value, it allows to create a sample & hold function
+ for the a-input of the multiplier.
+ The a-input of the multiplier is updated every treshold clockcycle. Thereby cross statistics can be created."
slave_discription: >
" "
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg b/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg
index 53b8ab7f7fbe2086c666d0c3b531de8fce09c795..e424ea9d5ff2530cbdd61574854fe100f054329f 100644
--- a/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
synth_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_fn_bf/sopc_unb1_fn_bf.vhd
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_fn_bf/sopc_unb1_fn_bf.vhd
src/vhdl/mmm_unb1_fn_bf.vhd
src/vhdl/node_unb1_fn_bf.vhd
src/vhdl/unb1_fn_bf.vhd
@@ -31,7 +31,7 @@ quartus_tcl_files =
quartus/unb1_fn_bf_pins.tcl
quartus_qip_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_fn_bf/sopc_unb1_fn_bf.qip
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_fn_bf/sopc_unb1_fn_bf.qip
nios2_app_userflags = -DCOMPILE_FOR_SOPC
diff --git a/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg b/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg
index 8850bc6d00096625d5260686a5d31d045338a5bf..04101e79bec296013ae70c6fb821b98e4a5babff 100644
--- a/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg
+++ b/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
synth_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_correlator/qsys_unb1_correlator/synthesis/qsys_unb1_correlator.v
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_correlator/qsys_unb1_correlator/synthesis/qsys_unb1_correlator.v
src/vhdl/mmm_unb1_correlator.vhd
src/vhdl/unb1_correlator.vhd
@@ -31,7 +31,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/unb1/quartus/unb1_correlator/qsys_unb1_correlator/synthesis/qsys_unb1_correlator.qip
+ $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_correlator/qsys_unb1_correlator/synthesis/qsys_unb1_correlator.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/libraries/dsp/fringe_stop/fringe_stop.peripheral.yaml b/libraries/dsp/fringe_stop/fringe_stop.peripheral.yaml
index a48573c686828c7ff18e53b0a8e3c6cd8e66bab1..04e707fbea28f020d5a47173567f77811cad3291 100644
--- a/libraries/dsp/fringe_stop/fringe_stop.peripheral.yaml
+++ b/libraries/dsp/fringe_stop/fringe_stop.peripheral.yaml
@@ -6,8 +6,7 @@ hdl_library_name : fringe_stop
hdl_library_description: " This is the description for the finge_stop library "
peripherals:
- -
- peripheral_name: fringe_stop_unit
+ - peripheral_name: fringe_stop
parameters:
- { name: g_nof_channels, value: 256 }
@@ -15,34 +14,26 @@ peripherals:
- { name: g_fs_step_w , value: 17 }
slave_ports:
- -
# actual hdl name: ram_fringe_stop_step
- slave_prefix : FRINGE_STOP
- slave_name : STEP
- slave_postfix: RAM
+ - slave_name : STEP
slave_type : RAM
fields:
- -
- field_name : fringe_stop_step
- width: g_fs_step_w
- number_of_fields: g_nof_channels
- field_description: |
- "Contains the step size for all nof_channels channels."
+ - - field_name : fringe_stop_step
+ width: g_fs_step_w
+ number_of_fields: g_nof_channels
+ field_description: |
+ "Contains the step size for all nof_channels channels."
slave_discription: " "
- -
# actual hdl name: fringe_stop_offset
- slave_prefix : FRINGE_STOP
- slave_name : OFFSET
- slave_postfix: RAM
+ - slave_name : STOP_OFFSET
slave_type : RAM
fields:
- -
- field_name: fringe_stop_offset
- width: g_fs_offset_w
- number_of_fields: g_nof_channels
- field_description: |
- "Contains the offset for all nof_channels channels."
+ - - field_name: fringe_stop_offset
+ width: g_fs_offset_w
+ number_of_fields: g_nof_channels
+ field_description: |
+ "Contains the offset for all nof_channels channels."
slave_discription: " "
peripheral_description: |
diff --git a/libraries/io/ddr3/hdllib.cfg b/libraries/io/ddr3/hdllib.cfg
index 6b8dd8ebd11710ed5df9e7d90a190639bd2cfc45..970529be4267e1d121cd77c32cbca7ff8485c82c 100644
--- a/libraries/io/ddr3/hdllib.cfg
+++ b/libraries/io/ddr3/hdllib.cfg
@@ -28,9 +28,9 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
- $HDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_AC_ROM.hex .
- $HDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_inst_ROM.hex .
- $HDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_sequencer_mem.hex .
+ $RADIOHDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_AC_ROM.hex .
+ $RADIOHDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_inst_ROM.hex .
+ $RADIOHDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_sequencer_mem.hex .
modelsim_compile_ip_files =
$RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd b/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
index a45392e234e98478c7c185e2fdab4c8b6252cb18..aaca3d6c3c297d021b996ec3ac83b6c7d366c6be 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
@@ -121,7 +121,7 @@ PACKAGE ddr3_pkg IS
CONSTANT c_ddr3_seq : t_ddr3_seq := (64, 1, 16, 4, 0, 5);
- -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.v
+ -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.v
COMPONENT ip_stratixiv_ddr3_uphy_4g_800_master IS
PORT (
pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk
@@ -173,7 +173,7 @@ PACKAGE ddr3_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.v
+ -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.v
-- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
COMPONENT ip_stratixiv_ddr3_uphy_4g_800_slave IS
PORT (
diff --git a/libraries/io/epcs/epcs.peripheral.yaml b/libraries/io/epcs/epcs.peripheral.yaml
index 50045e05a6e1c132f0ab60ce0cc503ef82c2288f..f569cf6840f74fd0be8c15685287715a519a2f7f 100644
--- a/libraries/io/epcs/epcs.peripheral.yaml
+++ b/libraries/io/epcs/epcs.peripheral.yaml
@@ -9,118 +9,93 @@ peripherals:
# epcs_reg
-
- peripheral_name: epcs_reg
+ peripheral_name: epcs
parameters:
- {name: "g_sim_flash_model", value: TRUE}
slave_ports:
- -
# actual hdl name: epcs_reg
- slave_prefix : EPCS
- slave_name : EPCS
- slave_postfix: REG
+ - slave_name : EPCS
slave_type : REG
fields:
- -
- field_name : addr
- width : 24
- access_mode : WO
- address_offset: 0x0
- field_description: " address to write to or read from "
+ - - field_name : addr
+ width : 24
+ access_mode : WO
+ address_offset: 0x0
+ field_description: " address to write to or read from "
- -
- field_name : rden
- width : 1
- access_mode : WO
- address_offset: 0x1
- field_description: " Read enable bit "
+ - - field_name : rden
+ width : 1
+ access_mode : WO
+ address_offset: 0x4
+ field_description: " Read enable bit "
- -
- field_name : read_bit
- width : 1
- access_mode : WO
- side_effect : PW
- address_offset: 0x2
- field_description: " Read bit "
+ - - field_name : read_bit
+ width : 1
+ access_mode : WO
+ side_effect : PW
+ address_offset: 0x8
+ field_description: " Read bit "
- -
- field_name : write_bit
- width : 1
- access_mode : WO
- side_effect : PW
- address_offset: 0x3
- field_description: " Write bit "
+ - - field_name : write_bit
+ width : 1
+ access_mode : WO
+ side_effect : PW
+ address_offset: 0xc
+ field_description: " Write bit "
- -
- field_name : sector_erase
- width : 1
- access_mode : WO
- address_offset: 0x4
- field_description: " Sector erase bit "
+ - - field_name : sector_erase
+ width : 1
+ access_mode : WO
+ address_offset: 0x10
+ field_description: " Sector erase bit "
- -
- field_name : busy
- width : 1
- access_mode : RO
- address_offset: 0x5
- field_description: " busy "
+ - - field_name : busy
+ width : 1
+ access_mode : RO
+ address_offset: 0x14
+ field_description: " busy "
slave_description: " Read and write access to flash "
# actual hdl name: mms_dp_fifo_to_mm
- -
- slave_prefix : EPCS
- slave_name : DPMM_CTRL
- slave_postfix: REG
+ - slave_name : DPMM_CTRL
slave_type : REG
fields:
- -
- field_name : ctrl
- width : 32
- access_mode : RW
- address_offset: 0x0
- field_description: " "
+ - - field_name : ctrl
+ width : 32
+ access_mode : RW
+ address_offset: 0x0
+ field_description: " "
- -
- slave_prefix : EPCS
- slave_name : DPMM_DATA
- slave_postfix: REG
+ - slave_name : DPMM_DATA
slave_type : REG
fields:
- -
- field_name : data
- width : 32
- access_mode : RW
- address_offset: 0x0
- field_description: " "
+ - - field_name : data
+ width : 32
+ access_mode : RW
+ address_offset: 0x0
+ field_description: " "
# actual hdl name: mms_dp_fifo_from_mm
- -
- slave_prefix : EPCS
- slave_name : MMDP_CTRL
- slave_postfix: REG
+ - slave_name : MMDP_CTRL
slave_type : REG
fields:
- -
- field_name : ctrl
- width : 32
- access_mode : RW
- address_offset: 0x0
- field_description: " "
+ - - field_name : ctrl
+ width : 32
+ access_mode : RW
+ address_offset: 0x0
+ field_description: " "
- -
- slave_prefix : EPCS
- slave_name : MMDP_DATA
- slave_postfix: REG
+ - slave_name : MMDP_DATA
slave_type : REG
fields:
- -
- field_name : data
- width : 32
- access_mode : RW
- address_offset: 0x0
- field_description: " "
+ - - field_name : data
+ width : 32
+ access_mode : RW
+ address_offset: 0x0
+ field_description: " "
peripheral_description: |
"wi Bits SE R/W Name Default Description |REG_EPCS|
diff --git a/libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg b/libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg
index c8bef4e2c3ba35ac5dcd190f8a40047279d5ff7e..a090ba6f04d48dfe58337b270c1ba2f97924e5e1 100644
--- a/libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg
+++ b/libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg
@@ -26,7 +26,7 @@ quartus_qsf_files =
quartus_tcl_files =
quartus/unb1_eth_10g_pins.tcl
-quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/unb1_eth_10g/qsys_unb1_eth_10g/synthesis/qsys_unb1_eth_10g.qip
+quartus_qip_files = $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_eth_10g/qsys_unb1_eth_10g/synthesis/qsys_unb1_eth_10g.qip
quartus_sdc_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
diff --git a/libraries/io/eth/eth.peripheral.yaml b/libraries/io/eth/eth.peripheral.yaml
index f8a30232682a1caec7d26f287072ff4602e6d50d..52cdc9dc3d091fa3c8f4088069adf61a7c81bc7f 100644
--- a/libraries/io/eth/eth.peripheral.yaml
+++ b/libraries/io/eth/eth.peripheral.yaml
@@ -15,47 +15,36 @@ peripherals:
#g_ETH_PHY : "LVDS"
slave_ports:
- -
- # actual hdl name: reg_tse
- slave_prefix : ETH
- slave_name : TSE
- slave_postfix: REG
+ # actual hdl name: reg_tse
+ - slave_name : TSE
slave_type : REG
fields:
- -
- field_name : status
- access_mode : RO
- address_offset : 0x0
- number_of_fields: 1024
- field_description: |
- " reg tse "
- slave_description: ""
- -
- # actual hdl name: reg
- slave_prefix : ETH
- slave_name : REG
- slave_postfix: REG
- slave_type : REG
+ - - field_name : status
+ access_mode : RO
+ address_offset : 0x0
+ number_of_fields: 1024
+ field_description: "reg tse"
+ slave_description: " "
+
+ # actual hdl name: reg
+ - slave_name : ETH
+ slave_type : REG
fields:
- -
- field_name : status
- access_mode : RO
- address_offset : 0x0
- number_of_fields: 11
- field_description: " reg registers "
+ - - field_name : status
+ access_mode : RO
+ address_offset : 0x0
+ number_of_fields: 12
+ field_description: "reg registers"
slave_description: " "
- -
- # actual hdl name: ram
- slave_prefix : ETH
- slave_name : RAM
- slave_postfix: RAM
+
+ # actual hdl name: ram
+ - slave_name : ETH
slave_type : RAM
fields:
- -
- field_name : ram
- number_of_fields: c_eth_ram_nof_words
- field_description: |
- "Contains the Waveform data for the data-streams to be send"
+ - - field_name : ram
+ number_of_fields: c_eth_ram_nof_words
+ field_description: |
+ "Contains the Waveform data for the data-streams to be send"
slave_description: " "
peripheral_description: |
diff --git a/libraries/io/eth/hdllib.cfg b/libraries/io/eth/hdllib.cfg
index a9c17c9c3bbbf81bc2fed71ffd2886dce1691fe7..5c3fb5fb6901a606b031a2c9f80e7f44f51ffc10 100644
--- a/libraries/io/eth/hdllib.cfg
+++ b/libraries/io/eth/hdllib.cfg
@@ -45,10 +45,10 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
- #src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $HDL_BUILD_DIR/<buildset_name>/avs2_eth_coe_hw.tcl
+ #src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $RADIOHDL_BUILD_DIR/<buildset_name>/avs2_eth_coe_hw.tcl
src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
[quartus_project_file]
quartus_copy_files =
- #src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $HDL_BUILD_DIR/<buildset_name>/avs2_eth_coe_hw.tcl
+ #src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $RADIOHDL_BUILD_DIR/<buildset_name>/avs2_eth_coe_hw.tcl
src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
\ No newline at end of file
diff --git a/libraries/io/ppsh/ppsh.peripheral.yaml b/libraries/io/ppsh/ppsh.peripheral.yaml
index b9b71e89d669190ec79128165c4c5e501c1d89d0..c6af948356d4b093cc19e9d5eace4ccf7571eb51 100644
--- a/libraries/io/ppsh/ppsh.peripheral.yaml
+++ b/libraries/io/ppsh/ppsh.peripheral.yaml
@@ -13,22 +13,18 @@ peripherals:
- { name: g_st_clk_freq, value: 200 * 10**6 }
slave_ports:
- -
# actual hdl name: reg_ppsh
- slave_prefix : PPSH
- slave_name : PPSH
- slave_postfix: REG
+ - slave_name : PPSH
slave_type : REG
fields:
- -
- field_name : status
- access_mode : RO
- address_offset: 0x0
- field_description: " ppsh status "
- -
- field_name : control
- address_offset: 0x1
- field_description: " ppsh control "
+ - - field_name : status
+ access_mode : RO
+ address_offset: 0x0
+ field_description: " ppsh status "
+
+ - - field_name : control
+ address_offset: 0x4
+ field_description: " ppsh control "
slave_discription: " "
peripheral_description: |
diff --git a/libraries/io/remu/remu.peripheral.yaml b/libraries/io/remu/remu.peripheral.yaml
index 51d26382f1fc9515204307ed5da0da66692d1dab..34bcce2aab6ba0d5eab44eefc655261965f4e288 100644
--- a/libraries/io/remu/remu.peripheral.yaml
+++ b/libraries/io/remu/remu.peripheral.yaml
@@ -8,71 +8,60 @@ hdl_library_description: " This is the description for the remu package "
peripherals:
# peripheral, remu_reg
- -
- peripheral_name: remu_reg
+ - peripheral_name: remu
parameters:
- { name: g_data_w, value: 24 }
slave_ports:
- -
# actual hdl name: reg_remu
- slave_prefix : WORK
- slave_name : REMU
- slave_postfix: REG
+ - slave_name : REMU
slave_type : REG
fields:
- -
- field_name : reconfigure_key
- width : c_word_w
- access_mode : WO
- address_offset: 0x0
- field_description: " reconfigure key for safety "
+ - - field_name : reconfigure_key
+ width : c_word_w
+ access_mode : WO
+ address_offset: 0x0
+ field_description: " reconfigure key for safety "
- -
- field_name : param
- width : 3
- access_mode : WO
- address_offset: 0x1
- radix : unsigned
- field_description: " "
+ - - field_name : param
+ width : 3
+ access_mode : WO
+ address_offset: 0x4
+ radix : unsigned
+ field_description: " "
- -
- field_name : read_param
- width : 1
- access_mode : WO
- side_effect : PW
- address_offset: 0x2
- field_description: " read_param "
+ - - field_name : read_param
+ width : 1
+ access_mode : WO
+ side_effect : PW
+ address_offset: 0x8
+ field_description: " read_param "
- -
- field_name : write_param
- width : 1
- access_mode : WO
- side_effect : PW
- address_offset: 0x3
- field_description: " write_param "
+ - - field_name : write_param
+ width : 1
+ access_mode : WO
+ side_effect : PW
+ address_offset: 0xc
+ field_description: " write_param "
- -
- field_name : data_out
- width : g_data_w
- access_mode : RO
- address_offset: 0x4
- field_description: " data_out "
+ - - field_name : data_out
+ width : g_data_w
+ access_mode : RO
+ address_offset: 0x10
+ field_description: " data_out "
- -
- field_name : data_in
- width : g_data_w
- access_mode : WO
- address_offset: 0x5
- field_description: " data_in "
+ - - field_name : data_in
+ width : g_data_w
+ access_mode : WO
+ address_offset: 0x14
+ field_description: " data_in "
- -
- field_name : busy
- width : 1
- access_mode : RO
- address_offset: 0x6
- field_description: " busy "
+ - - field_name : busy
+ width : 1
+ access_mode : RO
+ address_offset: 0x18
+ field_description: " busy "
slave_description: " Remote Upgrade "
diff --git a/libraries/technology/ddr/tech_ddr_component_pkg.vhd b/libraries/technology/ddr/tech_ddr_component_pkg.vhd
index 011b01a5c1ddf503099ccd1ad3faf9d610c260c8..2284612023138e43eac50447b5d0bf100d3c70f5 100644
--- a/libraries/technology/ddr/tech_ddr_component_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_component_pkg.vhd
@@ -31,7 +31,7 @@ PACKAGE tech_ddr_component_pkg IS
-- ip_stratixiv
------------------------------------------------------------------------------
- -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.v
+ -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.v
COMPONENT ip_stratixiv_ddr3_uphy_4g_800_master IS
PORT (
pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk
@@ -83,7 +83,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.v
+ -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.v
-- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
COMPONENT ip_stratixiv_ddr3_uphy_4g_800_slave IS
PORT (
@@ -134,7 +134,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.v
+ -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.v
COMPONENT ip_stratixiv_ddr3_uphy_4g_single_rank_800_master IS
PORT (
pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk
@@ -186,7 +186,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
+ -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
-- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
COMPONENT ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave IS
PORT (
@@ -237,7 +237,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.v
+ -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.v
COMPONENT ip_stratixiv_ddr3_uphy_16g_dual_rank_800 IS
PORT (
pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk
@@ -293,7 +293,7 @@ PACKAGE tech_ddr_component_pkg IS
-- ip_arria10
------------------------------------------------------------------------------
- -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_ddr4_4g_1600.vhd
+ -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_ddr4_4g_1600.vhd
COMPONENT ip_arria10_ddr4_4g_1600 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -331,7 +331,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_ddr4_4g_2000.vhd
+ -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_ddr4_4g_2000.vhd
COMPONENT ip_arria10_ddr4_4g_2000 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -373,7 +373,7 @@ PACKAGE tech_ddr_component_pkg IS
-- ip_arria10_e3sge3
------------------------------------------------------------------------------
- -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e3sge3_ddr4_4g_1600.vhd
+ -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_e3sge3_ddr4_4g_1600.vhd
COMPONENT ip_arria10_e3sge3_ddr4_4g_1600 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -449,7 +449,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e3sge3_ddr4_4g_2000.vhd
+ -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_e3sge3_ddr4_4g_2000.vhd
COMPONENT ip_arria10_e3sge3_ddr4_4g_2000 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -491,7 +491,7 @@ PACKAGE tech_ddr_component_pkg IS
-- ip_arria10_e1sg
------------------------------------------------------------------------------
- -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e1sg_ddr4_4g_1600.vhd
+ -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_ddr4_4g_1600.vhd
COMPONENT ip_arria10_e1sg_ddr4_4g_1600 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -567,7 +567,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e1sg_ddr4_4g_2000.vhd
+ -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_ddr4_4g_2000.vhd
COMPONENT ip_arria10_e1sg_ddr4_4g_2000 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
diff --git a/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd b/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
index e0b73443cc0be208405596661a9760e4b338ea98..ebbb325b5f1d9bcd5e6c1e9d2a636582b02596b6 100644
--- a/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
@@ -32,7 +32,7 @@ PACKAGE tech_ddr_mem_model_component_pkg IS
------------------------------------------------------------------------------
-- Manually derived VHDL entity from Verilog module alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en.sv in:
- -- $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master_example_design/simulation/vhdl/submodules/
+ -- $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master_example_design/simulation/vhdl/submodules/
COMPONENT alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en IS
GENERIC (
diff --git a/libraries/technology/hdllib.cfg b/libraries/technology/hdllib.cfg
index 02e4adb554aec475da941a60d7c76bd2fd9e58b9..09ec26b81ae0122136ebdc626accce7595a535c4 100644
--- a/libraries/technology/hdllib.cfg
+++ b/libraries/technology/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_technology =
synth_files =
technology_pkg.vhd
- $HDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
+ $RADIOHDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
test_bench_files =
@@ -16,10 +16,10 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
- technology_select_pkg_<buildset_name>.vhd $HDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
+ technology_select_pkg_<buildset_name>.vhd $RADIOHDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
[quartus_project_file]
quartus_copy_files =
- technology_select_pkg_<buildset_name>.vhd $HDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
+ technology_select_pkg_<buildset_name>.vhd $RADIOHDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
diff --git a/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl b/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
index 5e5795ffacb7327cc1fb4ee1c912613d8e7685ea..44f305f0b19f6ef32390f5eeb7759da1d56089b6 100644
--- a/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
index 43acb41dbef0fb27a4faaabf1a7ba7b8f4b8cab6..55e6320c95cadb8c1e631eb0410f1f2a1e1a8c01 100644
--- a/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/ddio/compile_ip.tcl b/libraries/technology/ip_arria10/ddio/compile_ip.tcl
index 64aba5490a1ac644abeabe6b9924bdfe195d15fa..ea28f210cf233f23315cc1a15bb5e51d5a893a41 100644
--- a/libraries/technology/ip_arria10/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddio/compile_ip.tcl
@@ -26,7 +26,7 @@ set IPMODEL "SIM";
if {$IPMODEL=="PHY"} {
# This file is based on Qsys-generated file msim_setup.tcl.
- set IP_DIR "$env(HDL_BUILD_DIR)/"
+ set IP_DIR "$env(RADIOHDL_BUILD_DIR)/"
#vlib ./work/ ;# Assume library work already exists
vmap ip_arria10_ddio_in_1_altera_gpio_core_150 ./work/
diff --git a/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl b/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
index 92b736708c5f397f2669fcabf33f23930c10c4fb..3e5f93390f573a7c8bd58ac855451a4e7b25d748 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
index fca54fa81397d5fe2fed6c83f43174c445ec9dc3..b83177faa5b1cb8f7914cb1aa5a44381e85bac22 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl b/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
index ec106dc119f0b937632a4dc67aff6a1c8d679b91..fb90cea0b32e3e6c69cbfa4a139c5aedb996f4ba 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl b/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl
index e0de434cf68a2b36abac305aa1295db9bf676ed6..0126c5c44fc2f14013aa65c8faba90359ffef766 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl b/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
index 748f3779e18a424294a431e7b32a6f6b27d11bf9..297be0f53261b7a31f47ff06a12584e606729f1c 100644
--- a/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl b/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl
index dca56d5c3c797d693a1497ee635df4ba72270577..7987c4b82e1ccf4ae922a03fb5720433a2e5a129 100644
--- a/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
index 7ad84ee07bff1ab5473c734fc53609797e73dec8..32237451dc2c302dfa68b638e5fb4c47de711e66 100644
--- a/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
vmap ip_arria10_asmi_parallel_altera_asmi_parallel_150 ./work/
diff --git a/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
index 46836c839335b0c1a9a26c7f65d7bd45452a9657..bd002e349294ad0e46ca0d6166e1e395cb9f5213 100644
--- a/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
vmap ip_arria10_remote_update_altera_remote_update_core_150 ./work/
vmap ip_arria10_remote_update_altera_remote_update_150 ./work/
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
index 80a62c66728cbf85d97b24a84daed153673028b7..851350a43c6ceabe3919511133fe33ecbaa440b8 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
index 8d2f641fcc8860bd127d95f956d2d36c11d49292..48d30f0d8919ce779bf57581ade5ba02a20a5242 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
index 1865ab2bb04acaf84406cb094a18d831a8c38a89..a8883cc13242d13d7bc792f260482f06265a8b70 100644
--- a/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
@@ -26,8 +26,8 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
-set IP_TBDIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_TBDIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
index 4a0011ee35ba95992d898a467858dea8cbbdcf18..6a1b1dd972a06c768520590e73255fa3830b7b84 100644
--- a/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
@@ -9,7 +9,7 @@ synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
- #$HDL_BUILD_DIR/sim/ip_arria10_mac_10g_tb.vhd
+ #$RADIOHDL_BUILD_DIR/sim/ip_arria10_mac_10g_tb.vhd
[modelsim_project_file]
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
index 05fdc5ebb71331a4d596bfed14fbfb75e1abe958..794ca94e334b853ceac9fcdbd9c00627f740e324 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
index 4df7738bdcbbb9259a5ad46048c80e97ed3fa5b6..f40fb259020f09cd98abb04e913637bf5dcc2099 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
index 5ef95c261f33071aa5333527bd61316d970b3c45..182a93de25363bf55ff70897678dabe73007b3e8 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
index 4df2e0bdecb96b8ef473082f28af7a7b09c5bf41..740989b1157c49f8004d0af278671c8d27f7e628 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
index 53e06e4de13144c7d5f04c48b2a3668b4b0b3ab3..2cf8040b19ec0dd8b4cbc9453bec69898deaa865 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
index ca650eea03c441dd28c7d1db95fe5858d2e1b2b9..e66921e0b330ede9a74a01ad878abc7446256f22 100644
--- a/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
index 88558ac77859eb3864cb9657e3f8c21539db39b1..9a1b5855e11f4642ceeaf023fb66cd9a8e04fb01 100644
--- a/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
index 65f55bd48db30500ebe48bf5dc93e019d032d020..58312af4c266a64f2cd82253ff649fd40604440c 100644
--- a/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
index 20e438b4c19e1e7c1aca450ab6bc3e439f4c0d49..d31c8671a798c3899e189cbc4f0d354d1543cd3f 100644
--- a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
index e24b47eab8f26f11b277087e52befb7ed06a3160..6404a59d660ea18074ae67b68286650006d74aa0 100644
--- a/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
index 0ca0862832784bf6d305b2a30503b0e76fd964ee..950a6849abb5d59accb772d44b93e8a962de330c 100644
--- a/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
index ede7525a7c82aea577cfeb7fb9f0a8aba1d026b8..0b48cda572c2a91c92702b6908cd6530a72d1d3a 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
index 7e487453a1f8d57295d9203d6868e04cc2895739..0b9fd32f8156d0df118951b96bc7c0681f8740de 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
index 4b2d7cd58b179c78354392060a21f5d418fd7e4f..a98ab3b9500f226f4dadf17ce07fd14fe87ca004 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
index 2adc9e61a6b8385bc9d5604eeaa9ec630c71e2ef..8f4d76ddf3b165426aa469b62198d437460441a8 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
index 89dc59e26a28cf196eee9369a1512982901dc64f..a4a6db128f22937079b2c51574d5f89130519edf 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
index 97a8f992de1d36397fcd1fb8d80bbec7c3e8806a..3f4f14a00e3d83e3c7df35ee5d745895e54b6f4e 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
@@ -26,7 +26,7 @@
# - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
# - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
index a9062836f7bbd80f60938f94448f21f763016b54..a22e115699c0346b81882fc18f14b319b1de139f 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
@@ -26,7 +26,7 @@
# - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
# - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
index 03e7c495f2853b87e59a0b396d86a7b86da4b0db..fd90e1ac9c90092e50f26c10a30467166ed8cad4 100644
--- a/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/compile_ip.tcl
index d2c1cac94d7a915467598e00158b226912f78133..ffa123ac217c86efde7d6de9ab386fa0714560c8 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_mac_10g/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_mac_10g/sim"
vmap alt_em10g32_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/hdllib.cfg
index 0f16ed2ea08563b84db2c26831acc2ee8ce5c4ea..62619e221dc75d4ca1d7cb15e2757190ce02eba6 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/hdllib.cfg
@@ -9,7 +9,7 @@ synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
- #$HDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
+ #$RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
[modelsim_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/compile_ip.tcl
index 48b8eadb18ffe222be00011f1a9d45c2e88cd8a9..564cbf1d9c3f4b62d7fadea5308fa980386646df 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap alt_mem_if_jtag_master_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/compile_ip.tcl
index 0fdc6a880e087a7f252a0ffa7071d286d0bdc84f..b8ff2a3d814ebf9bb58af5ffc17637361cd6eae9 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_clkbuf_global/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_clkbuf_global/sim"
vmap altclkctrl_180 ./work/
vcom "$IP_DIR/../altclkctrl_180/sim/ip_arria10_e1sg_clkbuf_global_altclkctrl_180_uuznxiq.vhd" -work altclkctrl_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/compile_ip.tcl
index d6b2ba13b801ab542ffb812499cd045bcd976b4a..e1847b95f20bbae0aeccb8b696cbc90929c3e893 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/compile_ip.tcl
@@ -29,7 +29,7 @@
vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_asmi_parallel/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_asmi_parallel/sim"
vmap altera_asmi_parallel_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/compile_ip.tcl
index af0c7159fd9aeb9898dd708d829011e65639f3e7..eafa959867e1a4c01ae8e165643abd814f48bbb5 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vmap altera_avalon_mm_bridge_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/compile_ip.tcl
index edf94714dd03299d19c6edb8b7e661399c6246a8..25d72fb06ab3e3840de87530222a59396bf54d70 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/compile_ip.tcl
@@ -30,16 +30,16 @@
#
vmap altera_avalon_onchip_memory2_180 ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/compile_ip.tcl
index db85d837ed13d5ed34522941592c314fd4cd9a4c..f9b6566b8737158a23387418ddcfaa01f06b9103 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap altera_avalon_packets_to_master_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/compile_ip.tcl
index ee66c060b0e7e1ca395e7dae50698d29a8bd7cdb..3f67e1b1cea65400bf28774c3e96a3d3fdffc38c 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap altera_avalon_sc_fifo_180 ./work/
vlog "$IP_DIR/../altera_avalon_sc_fifo_180/sim/altera_avalon_sc_fifo.v" -work altera_avalon_sc_fifo_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/compile_ip.tcl
index 1a6e4e1ee4bb0e5a2c60a0180f457e2140ab51eb..a2defb493fec5579e0e6139e52298a412daade71 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap altera_avalon_st_bytes_to_packets_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/compile_ip.tcl
index 5399369f80dc9e53407739de92814c1c9cc6cd84..fa3ff32e9a3eae243226670d61ef1034926bd801 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap altera_avalon_st_packets_to_bytes_180 ./work/
vlog "$IP_DIR/../altera_avalon_st_packets_to_bytes_180/sim/altera_avalon_st_packets_to_bytes.v" -work altera_avalon_st_packets_to_bytes_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/compile_ip.tcl
index 543fd5e973a9516aa61464633a21b1da9a5850c9..b28e1dcf6539c2b979be8c152b2efbc473553b95 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/compile_ip.tcl
@@ -29,42 +29,42 @@
#vlib ./work/ ;# Assume library work already exist
#
vmap altera_emif_180 ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vlog "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_180_dzobyri.v" -work altera_emif_180
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000sim"
vlog "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_180_lwknerq.v" -work altera_emif_180
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vlog "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_180_ebfu2ha.v" -work altera_emif_180
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vlog "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_180_nz3mdxa.v" -work altera_emif_180
vmap altera_emif_arch_nf_180 ./work/
# ddr4_4g_1600
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y_io_aux.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y.sv" -work altera_emif_arch_nf_180
# ddr4_4g_2000
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy_io_aux.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy.sv" -work altera_emif_arch_nf_180
# ddr4_8g_1600
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_spx5pgi_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_spx5pgi_io_aux.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_spx5pgi.sv" -work altera_emif_arch_nf_180
# ddr4_8g_2400
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i_io_aux.sv" -work altera_emif_arch_nf_180
@@ -110,52 +110,52 @@ set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_d
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/io_12_lane__nf5es_abphy.sv" -work altera_emif_arch_nf_180
vmap altera_emif_cal_slave_nf_180 ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_cal_slave_nf_180_efslyyq.v" -work altera_emif_cal_slave_nf_180
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_cal_slave_nf_180_efslyyq.v" -work altera_emif_cal_slave_nf_180
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_cal_slave_nf_180_efslyyq.v" -work altera_emif_cal_slave_nf_180
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_cal_slave_nf_180_efslyyq.v" -work altera_emif_cal_slave_nf_180
vmap altera_reset_controller_180 ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vlog "$IP_DIR/../altera_reset_controller_180/sim/mentor/altera_reset_controller.v" -work altera_reset_controller_180
vlog "$IP_DIR/../altera_reset_controller_180/sim/mentor/altera_reset_synchronizer.v" -work altera_reset_controller_180
vmap altera_mm_interconnect_180 ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_ibrpcbq.vhd" -work altera_mm_interconnect_180
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_mtvmp4i.vhd" -work altera_mm_interconnect_180
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
vmap altera_avalon_onchip_memory2_180 ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
vmap altera_avalon_mm_bridge_180 ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vlog "$IP_DIR/../altera_avalon_mm_bridge_180/sim/altera_avalon_mm_bridge.v" -work altera_avalon_mm_bridge_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/compile_ip.tcl
index 15a326cec8dafbcca19edd4ae0e243717e06c3b6..64ca0f6eeadf453a5e77a3f6d7e01e05987ffac8 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/compile_ip.tcl
@@ -30,28 +30,28 @@
vmap altera_emif_arch_nf_180 ./work/
# ddr4_4g_1600
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y_io_aux.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y.sv" -work altera_emif_arch_nf_180
# ddr4_4g_2000
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy_io_aux.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy.sv" -work altera_emif_arch_nf_180
# ddr4_8g_1600
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_spx5pgi_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_spx5pgi_io_aux.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_spx5pgi.sv" -work altera_emif_arch_nf_180
# ddr4_8g_2400
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i_io_aux.sv" -work altera_emif_arch_nf_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/hdllib.cfg
index b999c7f23026b67692ab403e47a1226f16a93b93..6a6fb2b5794a0f12129400737b18c42dc5fb34c1 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/hdllib.cfg
@@ -9,7 +9,7 @@ synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
- #$HDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
+ #$RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
[modelsim_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/compile_ip.tcl
index 385052319b67e2009b1716c5e17db4df155d65a6..096a6b31306261ef5d5bca80a5ac8ebdc7d9972c 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/compile_ip.tcl
@@ -30,16 +30,16 @@
#
vmap altera_emif_cal_slave_nf_180 ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_cal_slave_nf_180_efslyyq.v" -work altera_emif_cal_slave_nf_180
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_cal_slave_nf_180_efslyyq.v" -work altera_emif_cal_slave_nf_180
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_cal_slave_nf_180_efslyyq.v" -work altera_emif_cal_slave_nf_180
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_cal_slave_nf_180_efslyyq.v" -work altera_emif_cal_slave_nf_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/compile_ip.tcl
index a5c3c36590b3094a82f565e9245dee42e7ecbd76..cff47b359f6891ed690a27c43d6451c3d446f064 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/compile_ip.tcl
@@ -31,10 +31,10 @@
vmap altera_eth_tse_180 ./work/
# tse_sgmii_gx
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
vcom "$IP_DIR/../altera_eth_tse_180/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_180_dm7dxyq.vhd" -work altera_eth_tse_180
# tse_sgmii_lvds
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
vcom "$IP_DIR/../altera_eth_tse_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_180_zsww75y.vhd" -work altera_eth_tse_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/compile_ip.tcl
index ebfe3676cb19cb08a431b9203e96a6590c0d6bfe..9f48b1b749250a738f695bb7ce7bc2c69f59118d 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/compile_ip.tcl
@@ -28,6 +28,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
vmap altera_eth_tse_avalon_arbiter_180 ./work/
vlog "$IP_DIR/../altera_eth_tse_avalon_arbiter_180/sim/mentor/altera_eth_tse_avalon_arbiter.v" -work altera_eth_tse_avalon_arbiter_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/compile_ip.tcl
index 358035beda539eb04f5474b0b081a44f89b8bf16..7253272d7084058511d59a5d0af08740a7b5bc40 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
vmap altera_eth_tse_mac_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/compile_ip.tcl
index 7bb7d7873ed59c1df6cc54ff92de5c988dd65190..325af551d7de32b53e49add90339e834acc14c18 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
vmap altera_eth_tse_nf_lvds_terminator_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/compile_ip.tcl
index 01f18f57979d83e0f571442af961ae5312ee8a2a..15cf56df5c4669ec66a27e29622bdb5898b2b7bc 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
vmap altera_eth_tse_nf_phyip_terminator_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/compile_ip.tcl
index 5f0cbdfbe7f9ec6e8e393ea20b8a4590cd96e6ea..490a07462d595096e527514d0faac94024bbd17b 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
vmap altera_eth_tse_pcs_pma_nf_lvds_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/compile_ip.tcl
index c5d8719befd1072ee3d2bd73432fe5b382afa189..55ca36b48bc56676a2f54a39c67217684a57ad27 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
vmap altera_eth_tse_pcs_pma_nf_phyip_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl
index 7d2db270093e09c09dc540b0c577063d6cc9a345..c55c9c297abf87133483b340a561c94f3edeeed9 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl
@@ -30,12 +30,12 @@
vmap altera_iopll_180 ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk25/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk25/sim"
vlog "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_pll_clk25_altera_iopll_180_fp6fpla.vo" -work altera_iopll_180
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk125/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk125/sim"
vlog "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_pll_clk125_altera_iopll_180_abkdtja.vo" -work altera_iopll_180
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk200/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk200/sim"
vlog "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_pll_clk200_altera_iopll_180_qkytlfy.vo" -work altera_iopll_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/compile_ip.tcl
index 8a6590e8bfa054ded07453f84d72a7fb3b49ad07..1edfa6f5a67aad9f9c735fd62445047dea10d33c 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap altera_ip_col_if_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/compile_ip.tcl
index 7855db26f8e5a63f80266935f967b88efec513a8..74c891aeba6bf0dd16b62025009fe212598b2216 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap altera_jtag_dc_streaming_180 ./work/
vlog "$IP_DIR/../altera_jtag_dc_streaming_180/sim/altera_avalon_st_jtag_interface.v" -work altera_jtag_dc_streaming_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/compile_ip.tcl
index 0638a7a9520818a6dc10f6621e4bd549eee72d7a..27e323677c47e105f8741a7bb15a1a7ad2d90f2b 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/compile_ip.tcl
@@ -27,7 +27,7 @@
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
vmap altera_lvds_180 ./work/
vcom "$IP_DIR/../altera_lvds_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_180_og2byry.vhd" -work altera_lvds_180
vcom "$IP_DIR/../altera_lvds_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_180_zfbfxeq.vhd" -work altera_lvds_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/compile_ip.tcl
index 763b27886008cbbb58ceef4c7af44f8475861e43..c349496c4228765340b65ce927357d1c8bc0e4b9 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/compile_ip.tcl
@@ -27,7 +27,7 @@
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
vmap altera_lvds_core20_180 ./work/
vlog -sv "$IP_DIR/../altera_lvds_core20_180/sim/altera_lvds_core20.sv" -work altera_lvds_core20_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/compile_ip.tcl
index 80bd106da1914b57491732edf57ce30133229073..d94285a791912268da4ba249b191284fcff83aa5 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
#
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vmap altera_merlin_master_translator_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/compile_ip.tcl
index abeccdc26435224da3598c2864522aa281d814b5..5556de9e14d841053e4568950bfa4c549a6a8395 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
#
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vmap altera_merlin_slave_translator_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/compile_ip.tcl
index 260516ca230f890a50041bc00838d86108f880ff..2b1c5214731b4c8bbb98b4887fe4705a3dcf24b0 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/compile_ip.tcl
@@ -30,16 +30,16 @@
#
vmap altera_mm_interconnect_180 ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_ibrpcbq.vhd" -work altera_mm_interconnect_180
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_mtvmp4i.vhd" -work altera_mm_interconnect_180
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/compile_ip.tcl
index 4923e9411fd1cb74b2162c30701fad84431b389b..d884da7788a187319b1370e4c7af6e946d9feca8 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_remote_update/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_remote_update/sim"
vmap altera_remote_update_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/compile_ip.tcl
index 27a2935517fe106c7374ae001c78310471dcb8ea..3f761c4a642e4aaf370045f295053240950688e9 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_remote_update/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_remote_update/sim"
vmap altera_remote_update_core_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/compile_ip.tcl
index 56f7ad4cbbda4691a6b9506ad554fb48c9be9d4b..072c34aed34eda1c0bd9b4e1883a46904e422a28 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
#
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vmap altera_reset_controller_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/compile_ip.tcl
index abf16a6330d3a5ff6fe320552e9448b3621d882f..0a291e94b1ffa4e695a43cd793fa1cf539edfab9 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/sim"
vmap altera_common_sv_packages ./work/
vmap altera_xcvr_atx_pll_a10_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/compile_ip.tcl
index 278e32120b0b7699dc9134174091aababe1f8232..16078458ea96afd0cb2f880fd0ee92ce1ad0688c 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/sim"
vmap altera_xcvr_fpll_a10_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl
index 55ea004c209d891beb081b060bb31ce7764c2f02..5c4256f75c2c011ebceced00007eb7acb7b27d6b 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl
@@ -32,7 +32,7 @@ vmap altera_xcvr_native_a10_180 ./work/
vmap altera_common_sv_packages ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/sim"
# common dependencies
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
@@ -68,31 +68,31 @@ set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_p
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_y6b7ffi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# phy_10gbase_r_24
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_180_mhfwvwa.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_mhfwvwa.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# phy_10gbase_r_12
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_180_fs3onwi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_fs3onwi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# phy_10gbase_r_4
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_180_d2amdia.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_d2amdia.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# phy_10gbase_r_3
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_180_skxmbpy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_skxmbpy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# phy_10gbase_r
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_180_nbxifma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_nbxifma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# tse_sgmii_gx
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_xcvr_native_a10_180_k23srea.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_k23srea.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/compile_ip.tcl
index 687d9bf2eb56786c3ce70397b91a7cc46b65b486..c99889b4826946bc97e0ef6eda25f2e85b688849 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/sim"
vmap altera_xcvr_reset_control_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/compile_ip.tcl
index 79d78a02f240dca1c415e8d0655f644126eb3838..d1c2e5c5d8fb7766f9ccff03c03eb0f1f805d928 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap channel_adapter_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/compile_ip.tcl
index dd0ebe9a6983d3c418dc741ba141c5c6e0a65899..de74d47a27b7611fd6c31a50270f4365e6272498 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap timing_adapter_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
index 3d395b250cfca9e836d1b0c2b0e1ad56f47e5551..73fa9937b39cc9564aa048bfcfa3f8c1d74cd0b3 100644
--- a/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_clkbuf_global/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_clkbuf_global/sim"
vcom "$IP_DIR/ip_arria10_e1sg_clkbuf_global.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
index e4bf3a3d8940c34b163531350cf77e5c6402bdb5..322c95752d30393b5c846493dbd185c391a9840d 100644
--- a/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_clkbuf_global/ip_arria10_e1sg_clkbuf_global.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_clkbuf_global/ip_arria10_e1sg_clkbuf_global.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
index cf358c071bf54f072d98f0b63121a4f689d0a5ec..bf653f2f16a62adc67568a085aed6b01011333d3 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult/sim"
vmap altmult_complex_180 ./work/
vlog "$IP_DIR/../altmult_complex_180/synth/ip_arria10_e1sg_complex_mult_altmult_complex_180_nkpx3mi.v" -work altmult_complex_180
#vlog "$IP_DIR/ip_arria10_e1sg_complex_mult_bb.v"
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
index b261fdd280e2ea5bcfc866dfa8b35250bcb56ffe..2cb2598b2ff1d9391f1789b1a6255fc6bd739319 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_complex_mult/ip_arria10_e1sg_complex_mult.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_complex_mult/ip_arria10_e1sg_complex_mult.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
index b36839e7c83697574b720f848e19297be32b82d3..5e3fcefa5ebb64853c8ee2693f32028036218fc7 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
@@ -34,7 +34,7 @@ set IPMODEL "SIM";
if {$IPMODEL=="PHY"} {
# OUTDATED AND NOT USED!!
# This file is based on Qsys-generated file msim_setup.tcl.
- set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddio_in_1/sim"
+ set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddio_in_1/sim"
#vlib ./work/ ;# Assume library work already exists
vmap ip_arria10_ddio_in_1_altera_gpio_core_180 ./work/
@@ -46,7 +46,7 @@ if {$IPMODEL=="PHY"} {
vcom "$IP_DIR/ip_arria10_ddio_in_1.vhd"
- set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddio_out_1/sim"
+ set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddio_out_1/sim"
#vlib ./work/ ;# Assume library work already exists
vmap ip_arria10_ddio_out_1_altera_gpio_core_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
index 049a6ef228e39ed326022ff1f0d3a95b892dd12f..6fdd643351675e042111525e1af727a64e93267e 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
@@ -18,8 +18,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddio_in_1/ip_arria10_e1sg_ddio_in_1.qip
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddio_out_1/ip_arria10_e1sg_ddio_out_1.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddio_in_1/ip_arria10_e1sg_ddio_in_1.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddio_out_1/ip_arria10_e1sg_ddio_out_1.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
index 45e98a1c47c1cdb750252cbc8127c4b8c522e99b..7b57f32c77761658d8555f5a962322a97d802a08 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_4g_1600.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
index f881b77a856ecf14cdd998a97aeb7f399009c6a1..807580094ddcfb2df77f38e645971cf32c47594a 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
index bb05a34afe0f020702ca784f11baa36adb2ed9a8..c6034f2bd565ec0f957a3fcce1d75dd18d786a8b 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/ip_arria10_e1sg_ddr4_4g_1600.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/ip_arria10_e1sg_ddr4_4g_1600.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
index 1650d44f51fa3f3044d92b4f95ef255c00257cbf..2b8a534222f35b96791c2559589a67326042e0fd 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_4g_2000.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
index 1394d1d34b471707e8a33267468f54f99bd6207a..d5f9fe639bda2c4810f83a2e88296a4425dd190b 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
index 8b021c649079174643f4865f00e51914a5d9c997..a22ea2e96a16c47ff1d501631aaa9a10d8346d67 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/ip_arria10_e1sg_ddr4_4g_2000.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/ip_arria10_e1sg_ddr4_4g_2000.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
index 2cfbbd059dcf6e3019c3a096a5a80134b437337d..fbbcfe7aac13c0e04a0262d21120cd98db2afbcc 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_8g_1600.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
index 63035b8e07cf7d4c2fab84dd72af2a901f992a48..14517ed7157af9b78e7146196bb7a59e7df8e75b 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
index d7825e3efccb1b18a4fbc75e91125692ee7ddfd1..bff7f43f6487d547b5ba08de983cc04b19c503ef 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/ip_arria10_e1sg_ddr4_8g_1600.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/ip_arria10_e1sg_ddr4_8g_1600.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
index 2638a04129dcefb3efba4a0a34592ae7cba6381d..6655a839f81d14880840d7b9b039a945e1d917ed 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_8g_2400.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
index e1a1ada8b9df39c2a88790b9e7c2107a134d0cdf..104e49f90dbec112dc4a55c4ee227a1317926633 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
index 35a821a428baccf96d358096efd150f4fe3a0099..b203d90d95a6e4a324cdc2b1380fc5af116b6dce 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
index a708e8034288473042353c0399da5b1e911d2580..a4c21a5083b10e01b62e4451a94e5766422c8b79 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
@@ -29,7 +29,7 @@
vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_asmi_parallel/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_asmi_parallel/sim"
vcom "$IP_DIR/ip_arria10_e1sg_asmi_parallel.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
index cb20b751c9200f10605bc6a094fcf85c1741da75..802d7bc9b687d0c6d345be36d44179dff86f293f 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_asmi_parallel/ip_arria10_e1sg_asmi_parallel.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_asmi_parallel/ip_arria10_e1sg_asmi_parallel.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
index 1f003afd9b87762c816f1489a7b13e2a25cbca59..d721b04349295f70c6feb364690f5fa363d657e3 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_remote_update/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_remote_update/sim"
vcom "$IP_DIR/ip_arria10_e1sg_remote_update.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
index 88fb5e8af9c9b49f57f739f9f1582b281ca95fa2..64c28833bdbc85573cfff07c1d63f99545b94319 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_remote_update/ip_arria10_e1sg_remote_update.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_remote_update/ip_arria10_e1sg_remote_update.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
index f93c3aa93962977cf4ee463ef6f74334ac921081..1c55491d25b7e57b72491e61b9262f450aa97709 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_fractional_pll_clk125/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_fractional_pll_clk125/sim"
vcom "$IP_DIR/ip_arria10_e1sg_fractional_pll_clk125.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
index 0c3631101ad1539dbe263e445c8b1fcd5246f675..9ad42d42523220226ea426fbdd7e07e353e7fe58 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_fractional_pll_clk125/ip_arria10_e1sg_fractional_pll_clk125.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_fractional_pll_clk125/ip_arria10_e1sg_fractional_pll_clk125.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
index 7d453434694e4580eae0dce1ddcac777a90d8d72..d62136904bc45e1c2a440bd325bc8bcf125a8bf0 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_fractional_pll_clk200/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_fractional_pll_clk200/sim"
vcom "$IP_DIR/ip_arria10_e1sg_fractional_pll_clk200.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
index aecf94dba75fa49f6bfd0abaa96016f08bcea4d1..28bf7f6a7871285ce62baa8d8848b319ce4a19aa 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_fractional_pll_clk200/ip_arria10_e1sg_fractional_pll_clk200.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_fractional_pll_clk200/ip_arria10_e1sg_fractional_pll_clk200.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
index 1c211f6ce77eab1736f2cdb2293dc4304b866453..86cfa6cac3c69e353b5a784aca3cf3bd6a80312b 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_mac_10g/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_mac_10g/sim"
vcom "$IP_DIR/ip_arria10_e1sg_mac_10g.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
index 8baf093d8acfa333d161d9bb74c5255017caa205..508bbebf1f01513b700caab82607c0759bd84917 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
@@ -9,7 +9,7 @@ synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
- #$HDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
+ #$RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
[modelsim_project_file]
@@ -19,7 +19,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_mac_10g/ip_arria10_e1sg_mac_10g.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_mac_10g/ip_arria10_e1sg_mac_10g.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
index 8d098b26ceb1370b059ca79aa43962b836ce3e2e..82202caa753d96f5ef579124ae82e43b3d062924 100644
--- a/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_mult_add4/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_mult_add4/sim"
vmap ip_arria10_e1sg_mult_add4 ./work/
vmap altera_mult_add_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
index ea8fcb393b6adc0ff7a367cbc523904718395e74..0aca429ea06daa64dbeee3b3526c124b987b3c21 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
index 4914557dcbf6e8011aaaabd48f793397caf55446..9af7dc8bc851932be599d09748e903f5a873853a 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/ip_arria10_e1sg_phy_10gbase_r.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/ip_arria10_e1sg_phy_10gbase_r.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
index 2736172286780eef136f59560c695e36175ecae3..4aa3d0288ed14c3bce53ac2a3c11d3913d7e008b 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_12.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
index ba97097939ca4de7b4a7a139c604614f9f2b37eb..0d284db59b6114f7e109e7eb08c3ff3ec0d00d57 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/ip_arria10_e1sg_phy_10gbase_r_12.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/ip_arria10_e1sg_phy_10gbase_r_12.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
index 94616624b526848a0e4b0c8717d4689323dc6a03..fa35c21f357b100a23edbea6db7b1bcf373465c3 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_24.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
index 6a653bed8e598ff98f9d053f348709a2ff126639..f46a87107adc6133923eabbaaff96cd4b6239de7 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/ip_arria10_e1sg_phy_10gbase_r_24.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/ip_arria10_e1sg_phy_10gbase_r_24.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
index 3a060c4715c7aba668425aa5038bd97499e30e4f..81251469c69078e91f865c2c074261af7a3a9c51 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_3.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
index f63bb14398415de260495a90bd9aa70900ea1aed..bae65c01609d3ae0bf94ac6bceb8de6dfa71c83b 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/ip_arria10_e1sg_phy_10gbase_r_3.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/ip_arria10_e1sg_phy_10gbase_r_3.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
index 31257d769e70a8d1dd370da0c2fa8117d34d8af6..e52b7142990360c4c48a38be38c05d0e0d1da9a6 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_4.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
index 615c1c48fa0d844ea7845145659dfdf8ca3b48e1..05e6b863a664e8947477ad9bf568462b647b486d 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/ip_arria10_e1sg_phy_10gbase_r_4.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/ip_arria10_e1sg_phy_10gbase_r_4.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
index 1343afc3b59a5e9269152b2004812ae90625603b..555bdfed731f97884e1219dd24461a6d0819c5d0 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_48.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
index 39e0cd631e72644f1d203e6246b3e77b332265e8..ea4dd7440b6c716e40eb8d91e646aa46a2a11fec 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/ip_arria10_e1sg_phy_10gbase_r_48.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/ip_arria10_e1sg_phy_10gbase_r_48.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
index d18342e3f5b6c088b1bf6e2fd5d7c3c7c8052276..f6712cdd63d903940460fe8a517e0d37b48f0ff0 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk125/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk125/sim"
vcom "$IP_DIR/ip_arria10_e1sg_pll_clk125.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
index 1770bb5f7782fc68ff8f718df218d3203306034a..5bb0972c0c04b8179ff312a03df21d2736016582 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_clk125/ip_arria10_e1sg_pll_clk125.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_clk125/ip_arria10_e1sg_pll_clk125.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
index edfbbf4c076bd1b13d4585581613c7852b6f8a5c..f7f3cec7ac4e866c30234a7afc26b74bdb89557b 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
@@ -29,5 +29,5 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk200/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk200/sim"
vcom "$IP_DIR/ip_arria10_e1sg_pll_clk200.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
index be6b835b4b71ca53fe0866975eafc68a02e34b81..d745852618bbeee287e3b2689f96251f8d822716 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_clk200/ip_arria10_e1sg_pll_clk200.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_clk200/ip_arria10_e1sg_pll_clk200.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
index 40eb599bd5eeca7d2b25ad20a2ecbd476ff9b671..710e0dcc0043d4ed1605d5433ba0a1d176171d15 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk25/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk25/sim"
vcom "$IP_DIR/ip_arria10_e1sg_pll_clk25.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
index d270a6265bc624ef99883794931b78f88e83bd5b..c06945b319b0a50b94941c2d38e3bb90993fbbae 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_clk25/ip_arria10_e1sg_pll_clk25.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_clk25/ip_arria10_e1sg_pll_clk25.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
index 054104dc07c3b24b524a7788406455f2a9fb01f3..27231003981fb24e6f906b909c4bbb1aca3d5839 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/sim"
vcom "$IP_DIR/ip_arria10_e1sg_pll_xgmii_mac_clocks.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
index 141472385b783d24ddbaeec56d95475194a95e27..fb2761f88131214772cd9868a54bcd1b000deb87 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/ip_arria10_e1sg_pll_xgmii_mac_clocks.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/ip_arria10_e1sg_pll_xgmii_mac_clocks.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
index f8fb076632d1d86a5d74b02e2955fba283668de2..77ca49010cf8cdb964e013ae3a0260553f0b0a6e 100644
--- a/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_temp_sense/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_temp_sense/sim"
vmap altera_temp_sense_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
index dc7c730a2a04dd8aeceebf329166991f094349d7..71ad52e9e476160785b73d430afb8c6854a29d31 100644
--- a/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
@@ -16,7 +16,7 @@ test_bench_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_temp_sense/ip_arria10_e1sg_temp_sense.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_temp_sense/ip_arria10_e1sg_temp_sense.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
index e62b1ca32fe1b8a4193c2430560173f2a1683a2b..fcb30bbd9025a5c32590682c384e5a89cd0d75b8 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_pll_10g.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
index dd46f8828c49145ff271bd4e5b14337efc84f590..30c1dbc1e5e3c7ae96ab91f8dfee2fc24cb3d439 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/ip_arria10_e1sg_transceiver_pll_10g.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/ip_arria10_e1sg_transceiver_pll_10g.qip
[generate_ip_libs]
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
index 11105df2aa676cf5ba385c58df0d9d1baaf61c13..076177e1677f824bd02fea3cd99eee0e0b69df54 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_1.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
index 845503837a5dfe9426d87ab1bb73b5b783452931..42274baf396d77d0428e286103dfd6f66c02f127 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/ip_arria10_e1sg_transceiver_reset_controller_1.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/ip_arria10_e1sg_transceiver_reset_controller_1.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
index a708530bf8c518ffe2fde52eb1429107c1e0e8bc..aba40145fdc83925800ffb409387d493c517079d 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_12/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_12/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_12.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
index 773136b36096cea98d84092d774e3d25c1db2664..ae5ebcdb13bbf401b52c605b3d643e8222956c5d 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_12/ip_arria10_e1sg_transceiver_reset_controller_12.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_12/ip_arria10_e1sg_transceiver_reset_controller_12.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
index 87293d4a5f12876019d2b7d5d54a5d096f152139..70970628ba950e5063873ceefa755e70f4060e9b 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_24/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_24/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_24.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
index 701ee178494a83be2a135ec4af244aacdfcae21e..6e0d258dfbf6de1499e5e57ab45b86111ad2ad31 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_24/ip_arria10_e1sg_transceiver_reset_controller_24.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_24/ip_arria10_e1sg_transceiver_reset_controller_24.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
index a1f71285b5e64a3f00788fa4c6b41d89ff31c8bb..64f9f0b300fa79d4a20ef439e8b5ddd23d70d403 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_3/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_3/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_3.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
index cd49f3f7c3dd6915594bd1429e64fc2644586c81..8a9a5c4f5f71d953174b78c3422b507622e4d9b6 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
index d8cfa66c847d5e9da0d6eb5ed42b1ed9796760f3..f939d89ec657fa800c5cd20c6dcaaa3a8bd750d9 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_4/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_4/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_4.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
index 665debaad2883da7b3bdea3b76a9e8fdf91a87d6..6871a530371cefb160aaf96111960e1869182062 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_4/ip_arria10_e1sg_transceiver_reset_controller_4.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_4/ip_arria10_e1sg_transceiver_reset_controller_4.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
index cf074f0e1289216d80eb041de92b8aa70362d851..6450d4dd24dbb605c5b4bf3e2c3fcd7e06cac3f8 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_48/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_48/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_48.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
index 50f05c573ab1ddd8830edecdb15ff1edaeaf32e1..f24fde1a35d33190f400bbe21ef804f02a4f91b0 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_48/ip_arria10_e1sg_transceiver_reset_controller_48.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_48/ip_arria10_e1sg_transceiver_reset_controller_48.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
index 33ff4e89d52bf16f33c80575ded3d2fa8b12e1ca..f195da292399416ce68ae5dd5610297ddcc43e21 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
vcom "$IP_DIR/ip_arria10_e1sg_tse_sgmii_gx.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
index 407be614316506e93eb94c72fc9431b08a1adbea..6b6ad07b4ca2a22bbe83e592a3873fc0466af76b 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/ip_arria10_e1sg_tse_sgmii_gx.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/ip_arria10_e1sg_tse_sgmii_gx.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
index bb52a542f9bafa95f952930ec469aad1dd88f17f..3b2fffc3b6b66c1c07faa9935a77768f3bf02ce4 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
vcom "$IP_DIR/ip_arria10_e1sg_tse_sgmii_lvds.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
index f4641c545e4a779fd590c6e3a595b3222c5af0cb..0496ed8bd15cfc12b6dddc52c61f9b8fca70456e 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
@@ -18,7 +18,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/ip_arria10_e1sg_tse_sgmii_lvds.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/ip_arria10_e1sg_tse_sgmii_lvds.qip
[generate_ip_libs]
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
index 0d545f56085d38f564ecf515fb55d4b47b39aab2..1be59a86e78fdeefbe27c6b3750c369389304f73 100644
--- a/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_voltage_sense/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_voltage_sense/sim"
vmap ip_arria10_e1sg_voltage_sense ./work/
vmap altera_voltage_sensor_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
index 31f2ef1a72c10398288456b6229f87847570601a..a6cb5882e899f8467809c7c9057056237266fd4c 100644
--- a/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
@@ -17,7 +17,7 @@ test_bench_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_voltage_sense/ip_arria10_e1sg_voltage_sense.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_voltage_sense/ip_arria10_e1sg_voltage_sense.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
index 7ae5ccdb0110507c116a5516c53b54a7644de291..bf8cd80c93a7860a1697ac526a57157b151b6842 100644
--- a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
index 57832897c9e03dacb771638be58eac6e5f950b5e..9d3d77809588700d590519cd1596b2ab44add79d 100644
--- a/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
index aa2dd948bc10c19bcbf6eca5f43b580cc89e8c57..bf52569332beb12035486d9477909efde4f0d22e 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
@@ -26,7 +26,7 @@ set IPMODEL "SIM";
if {$IPMODEL=="PHY"} {
# This file is based on Qsys-generated file msim_setup.tcl.
- set IP_DIR "$env(HDL_BUILD_DIR)/"
+ set IP_DIR "$env(RADIOHDL_BUILD_DIR)/"
#vlib ./work/ ;# Assume library work already exists
vmap ip_arria10_e3sge3_ddio_in_1_altera_gpio_core_151 ./work/
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
index f9daedf909c3374e88c54a2db2a5788038997cdf..e62b5e5b0ec2ca57c94a7ab5b9d13a8a9f993b0c 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
index 960d695d93ac14ac14d9fca19cb02da3dde50874..ffac688997df0844310121f869edb099a0f7b893 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
index 4958df3351a1a1f8f3802460d8e7f0321d2f2917..5af54448735656b71c72ba70c8ea9abda0030c03 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl
index 9ee3836145e3eeae78859b7d60f8325a0d8d0848..c7dc9753f6703576382161215eaf38894884de9b 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
index f1b453f200164d5d78459ead9a893ce00b1db24e..9235dd757d1c734c7100d95ab966a22837ab6b6d 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
index 04c2a8b4be31e4d5f5ef249a650466322d8b90f7..50bcddb253056ba6151939404cb7a8087772998d 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
index ce6a73617cf8953e1e92e06aed99720360d50beb..6ab71a395bb7b1e3e7d06d446983253e205c110e 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl
index aae9b7d9c164ae06e67a2c7f461da36003ebce98..7017bd16807f790d696cdf8165fb677c09c390bc 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
index dca4f15724202af79962351ed84c4c74b7e698ff..bdfa521c2e6ecc238bbde399fb49198e91421278 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
vmap ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151 ./work/
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
index 74015b629d77fa5bb93635d791d424e2c431c3e4..3ce459025cc583a84317805d0d834f9a99f92364 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
vmap ip_arria10_e3sge3_remote_update_altera_remote_update_core_151 ./work/
vmap ip_arria10_e3sge3_remote_update_altera_remote_update_151 ./work/
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
index 7e094e9376d12c2d669bd1f866df2cc8e050d012..644fcc2174cfdc4be4fb1a61a7a39c99ff51f2bd 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
index c0daa81c16aead7d28d9c9c4a02a89d671be52e7..c74c2287408f1056c710ee8f3f4919c6b978c3ae 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
index 5567b55fb3ecb22e5b70bf65468cff275cf57dd2..652e8572667600fc7ffe8d9af75e567441a6835e 100644
--- a/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
@@ -26,8 +26,8 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
-set IP_TBDIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_TBDIR "$env(RADIOHDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg
index 1388ee04dd3a148a41a25eb40a1a8bdbcc28a33b..2395b80019ba2a23b3ad696cc19a94fe3f2e5310 100644
--- a/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg
@@ -9,7 +9,7 @@ synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
- #$HDL_BUILD_DIR/sim/ip_arria10_e3sge3_mac_10g_tb.vhd
+ #$RADIOHDL_BUILD_DIR/sim/ip_arria10_e3sge3_mac_10g_tb.vhd
[modelsim_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl
index 9f2c5442d710666ca8ab4049d336979fdafc104c..f4812de719ae2432daf1b2136321bbf4c5c830af 100644
--- a/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
index e27cf86d7f2e8c9c5aff9ebccdeb94f396559222..bac46a302542d23df2b48e95b334e174592073bb 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
index 4d2d833dae507da920d09319c4b44fda9d976d05..845c5bc4dc96a15673a1beae9442e550c2ce0461 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
index 26ba984cb5036540586ece8045005736f2841a36..52b235c6fcc56d01e23f600b679f612c623e2a13 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
index 76743709b4c09aebff7c4cdf62d95de2aa1f831b..a1a50b1517e457f5de611dfafda1d454f0098099 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
index f80ddb5a8f5ef750d79362407a6fa7c6a1f50805..55c73ea9afa9b28c71305785104bf7c394b6fbfc 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
index cdad30ae363b2c7919319f57edf6f9ae3c05282e..0f450fb1fb2068e521e2419cf34ac571b826bce8 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
index 1e38e5900f4698bdf951883342899bdf381249e4..4596b44c787b38044a3ce96587702fc3ea42c746 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
index fed8a5ff9a11c0fb8a76aa9943bfdec3ab112af2..6b08a6749e9ad8aec693df93ea7fd05f06ae8475 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
index 10417d22caf3d49fad2250b27a92af6e1c837bd4..b165f8ec1162f64706d063d64920cf8eb4111265 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
index 350a3674c84ac54768168ceb712b6ff2a8ddb292..5453478c58970fb5e877ab1e2b8a7c492aa9725d 100644
--- a/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
index e16ab1bb84c6316da9dfc49018ba573bc2b95a77..fb2a92dad8ae293a93969f9f5aed73cdcbe2d9b9 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
index 824d03bc0cb687920db589d5f8ea78d4f8560d98..54b0b19176acc00bc244f13a55b8f1df88066d77 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
index b674c73aa85fa7158f0b197728d48ec5b4e03671..ad26deea9322f9d42db7aa499771b957a181fabe 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
index d9cbccb13916af9d956f2cfd4599dffd5adb1e36..a1afcf294250b25a461c3a81bb59f97dd6d38eb3 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
index f2d0fa88e704a22ac8413b19035bcbfa706dfabd..fb291b27e4d4d9f54eb8a0c5e6e3635510b451f8 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
index 84ad7eb84803cc22e84de6f2107d5db4a3761297..41414481897ae78573b47195fa70475fdca94790 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
index 216ad6395efaab77b402e3772713ca874f202a96..124ced04c46847a261fd34787276c34cc47f597a 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
@@ -26,7 +26,7 @@
# - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
# - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
index add9457301889430396ec523be3c6a3948e1ff19..f6ae1988b3bb03f0f934553df7c61505a06a108e 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
@@ -26,7 +26,7 @@
# - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
# - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
index 090df9c5c970cda1729a1d4f14a1ad3d2b96691d..2e88d7082a8dee592125afd2206cf5ae9f94e951 100644
--- a/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
index 59ee3539ca85a400014442074aca2f02d6ba97e3..aa484a4ee70ee2594db2f55febaeaaf99cc3d3ba 100644
--- a/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
@@ -24,7 +24,7 @@
# Get the memory model fro the uphy_4g_* from the ip_stratixiv_ddr3_uphy_4g_800_master example design
#set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_example_design"
-set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_example_design
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_example_design
# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
index 0cba85661da782f1018dac1256b37ce01128a5e7..0cd94954d84f08aaaa3e6f3d4fa7413a56eb60cc 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
index c62e33e6542d97c0afd5710ed102b21c46b996fb..d73de176a4e4528412132468a9617fd9acf0ba43 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
index 0130afea23dfba3cd3857bdb6b6ce45204bc2f89..182467d01b17a56aeea08094f341d59925e91b01 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
index aae001963a1666ede237e7d4a4f3879f8747cab9..f3f0232211be40a411b8f9051d31dcbc5a580d31 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
index 100507af6ac9d66860d3515cce14de9b0d6d6018..b248f5b52c5effb708991a84367db7047b3c3a13 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl
index 96244d1526a14cce781676867953c8e7a7a4b5e3..16afa271530c6722b7ded9fa3a890288ece0e45e 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
index 84678948ceb14c7d67f200944ea17387669da202..3941d3de8cca0ca760403391bd31e6056403d596 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
index 6a06571581b76225f3950e55aad925a7bb8b8a8c..0e72fc7b5348808fb86070e500f3b80681c38022 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
index ca5ef73e8666aba7af7ecc6b4bb7a8088ae62929..59118cab74016c69aff32a1edb2d96647ed21cce 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
index 755278c8493e3aee82e075c5c9c660581ef38ef7..3f69d05466561abe71d506c79a3d6952a6be20b0 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl b/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
index 8133ccc7f4a321a55c1e08d79c23843be17a72b9..1a23512475600b3c92c9993885b2f546701c009a 100644
--- a/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
@@ -24,7 +24,7 @@
# file msim_setup.tcl.
# tr_xaui is the first module I did this for.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_mac_10g_sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_mac_10g_sim"
#vlib ./work/ ;# Assume library work already exists
#vmap work ./work/
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
index 3318814203f8331a9e088a57d8fec68ae9cc9284..72ba6432812883235936295c64978558c0268fe9 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
@@ -27,7 +27,7 @@
# correct compile order).
# EK: The model files in phy_xaui_0_sim/ are suitable for all hard xaui IP variants.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_phy_xaui_0_sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_phy_xaui_0_sim"
#vlib ./work/ ;# EK: Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
index 7e223040ac5a77da850fcf76c456371f295e9dbd..fb8eca101ffc7543a7edc6b661298de98dd06531 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
+++ b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
@@ -27,7 +27,7 @@
# correct compile order). Bonus of this is also that there will be no errors
# when making all_mod without having run the XAUI megawizard first.
-set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_phy_xaui_soft_sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_phy_xaui_soft_sim"
#vlib ./work/ ;# EK: Assume library work already exists
diff --git a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
index fccd070a5056e9397d604d567d9f6ccb20e1d5a3..f88b2836c2344b2f226f9206d77fe4a5600ef8a1 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
@@ -52,7 +52,7 @@ PACKAGE tech_mac_10g_component_pkg IS
-- ip_stratixiv
------------------------------------------------------------------------------
- -- Copied from entity $HDL_BUILD_DIR/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g.vhd
+ -- Copied from entity $RADIOHDL_BUILD_DIR/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g.vhd
COMPONENT ip_stratixiv_mac_10g IS
PORT (
csr_clk_clk : in std_logic := '0'; -- csr_clk.clk
diff --git a/libraries/technology/tse/tech_tse_component_pkg.vhd b/libraries/technology/tse/tech_tse_component_pkg.vhd
index 456d59f72b2b42d0e402caedd7bb3a4fc091f0fe..64cac8c994213b141addda3a35238437cc8be30b 100644
--- a/libraries/technology/tse/tech_tse_component_pkg.vhd
+++ b/libraries/technology/tse/tech_tse_component_pkg.vhd
@@ -147,7 +147,7 @@ PACKAGE tech_tse_component_pkg IS
-- ip_arria10
------------------------------------------------------------------------------
- -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_tse_sgmii_lvds.vhd
+ -- Copied from $RADIOHDL_BUILD_DIR/sim/ip_arria10_tse_sgmii_lvds.vhd
COMPONENT ip_arria10_tse_sgmii_lvds IS
PORT (
clk : in std_logic := '0'; -- control_port_clock_connection.clk
@@ -198,7 +198,7 @@ PACKAGE tech_tse_component_pkg IS
END COMPONENT;
- -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_tse_sgmii_gx.vhd
+ -- Copied from $RADIOHDL_BUILD_DIR/sim/ip_arria10_tse_sgmii_gx.vhd
COMPONENT ip_arria10_tse_sgmii_gx IS
PORT (
clk : in std_logic := '0'; -- control_port_clock_connection.clk
@@ -265,7 +265,7 @@ PACKAGE tech_tse_component_pkg IS
-- ip_arria10_e3sge3
------------------------------------------------------------------------------
- -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_e3sge3_tse_sgmii_lvds.vhd
+ -- Copied from $RADIOHDL_BUILD_DIR/sim/ip_arria10_e3sge3_tse_sgmii_lvds.vhd
COMPONENT ip_arria10_e3sge3_tse_sgmii_lvds IS
PORT (
reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata
@@ -316,7 +316,7 @@ PACKAGE tech_tse_component_pkg IS
END COMPONENT;
- -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_e3sge3_tse_sgmii_gx.vhd
+ -- Copied from $RADIOHDL_BUILD_DIR/sim/ip_arria10_e3sge3_tse_sgmii_gx.vhd
COMPONENT ip_arria10_e3sge3_tse_sgmii_gx IS
PORT (
reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata
@@ -383,7 +383,7 @@ PACKAGE tech_tse_component_pkg IS
-- ip_arria10_e1sg
------------------------------------------------------------------------------
- -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_e1sg_tse_sgmii_lvds.vhd
+ -- Copied from $RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_tse_sgmii_lvds.vhd
COMPONENT ip_arria10_e1sg_tse_sgmii_lvds IS
PORT (
reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata
@@ -434,7 +434,7 @@ PACKAGE tech_tse_component_pkg IS
END COMPONENT;
- -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_e1sg_tse_sgmii_gx.vhd
+ -- Copied from $RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_tse_sgmii_gx.vhd
COMPONENT ip_arria10_e1sg_tse_sgmii_gx IS
PORT (
reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata