diff --git a/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd b/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd
index 48582e511cd6bb16e2680656752fb4300d059edb..f7d1470165032b9bf1c118c0bd4e9b9e6d89519c 100644
--- a/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd
+++ b/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd
@@ -153,7 +153,7 @@ BEGIN
 
       sleep => '0',                     -- 1-bit input: sleep signal to enable the dynamic power saving feature.
 
-      wea => STD_LOGIC_VECTOR(wren),    -- WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
+      wea(0) => wren,    -- WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
                                         -- for port A input data port dina. 1 bit wide when word-wide writes
                                         -- are used. In byte-wide write configurations, each bit controls the
                                         -- writing one byte of dina to address addra. For example, to
diff --git a/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_crw_crw.vhd b/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_crw_crw.vhd
index e043b25315958aa66347a2965c48149daf31f881..9da5f346647856128fd3c91fc58ef79466e4323c 100644
--- a/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_crw_crw.vhd
+++ b/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_crw_crw.vhd
@@ -163,14 +163,14 @@ BEGIN
                                         -- by parameter READ_RESET_VALUE_B.
 
       sleep => '0',                     -- 1-bit input: sleep signal to enable the dynamic power saving feature.
-      wea => STD_LOGIC_VECTOR(wren_a),                       -- WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
+      wea(0) => wren_a,                       -- WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
                                         -- for port A input data port dina. 1 bit wide when word-wide writes
                                         -- are used. In byte-wide write configurations, each bit controls the
                                         -- writing one byte of dina to address addra. For example, to
                                         -- synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
                                         -- is 32, wea would be 4'b0010.
 
-      web => STD_LOGIC_VECTOR(wren_a)                        -- WRITE_DATA_WIDTH_B/BYTE_WRITE_WIDTH_B-bit input: Write enable vector
+      web(0) => wren_a                        -- WRITE_DATA_WIDTH_B/BYTE_WRITE_WIDTH_B-bit input: Write enable vector
                                         -- for port B input data port dinb. 1 bit wide when word-wide writes
                                         -- are used. In byte-wide write configurations, each bit controls the
                                         -- writing one byte of dinb to address addrb. For example, to