From 3ed294cf8061c110f2f9dcf6c1cf20ae0c86e298 Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Tue, 18 Apr 2023 16:47:19 +0200
Subject: [PATCH] corrected syntax
---
.../technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd | 2 +-
.../ip_ultrascale/ram/ip_ultrascale_ram_crw_crw.vhd | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd b/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd
index 48582e511c..f7d1470165 100644
--- a/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd
+++ b/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd
@@ -153,7 +153,7 @@ BEGIN
sleep => '0', -- 1-bit input: sleep signal to enable the dynamic power saving feature.
- wea => STD_LOGIC_VECTOR(wren), -- WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
+ wea(0) => wren, -- WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
-- for port A input data port dina. 1 bit wide when word-wide writes
-- are used. In byte-wide write configurations, each bit controls the
-- writing one byte of dina to address addra. For example, to
diff --git a/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_crw_crw.vhd b/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_crw_crw.vhd
index e043b25315..9da5f34664 100644
--- a/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_crw_crw.vhd
+++ b/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_crw_crw.vhd
@@ -163,14 +163,14 @@ BEGIN
-- by parameter READ_RESET_VALUE_B.
sleep => '0', -- 1-bit input: sleep signal to enable the dynamic power saving feature.
- wea => STD_LOGIC_VECTOR(wren_a), -- WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
+ wea(0) => wren_a, -- WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
-- for port A input data port dina. 1 bit wide when word-wide writes
-- are used. In byte-wide write configurations, each bit controls the
-- writing one byte of dina to address addra. For example, to
-- synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
-- is 32, wea would be 4'b0010.
- web => STD_LOGIC_VECTOR(wren_a) -- WRITE_DATA_WIDTH_B/BYTE_WRITE_WIDTH_B-bit input: Write enable vector
+ web(0) => wren_a -- WRITE_DATA_WIDTH_B/BYTE_WRITE_WIDTH_B-bit input: Write enable vector
-- for port B input data port dinb. 1 bit wide when word-wide writes
-- are used. In byte-wide write configurations, each bit controls the
-- writing one byte of dinb to address addrb. For example, to
--
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