add key to hdllib.cfg

libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_fractional_pll_clk200.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_fractional_pll_clk200.qsys
+

libraries/technology/ip_arria10/mac_10g/hdllib.cfg

@@ -20,3 +20,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_mac_10g.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_mac_10g.qsys
+

libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_phy_10gbase_r.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_phy_10gbase_r.qsys
+

libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_phy_10gbase_r_12.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_phy_10gbase_r_12.qsys
+

libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_phy_10gbase_r_24.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_phy_10gbase_r_24.qsys
+

libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_phy_10gbase_r_4.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_phy_10gbase_r_4.qsys
+

libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_phy_10gbase_r_48.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_phy_10gbase_r_48.qsys
+

libraries/technology/ip_arria10/pll_clk125/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_pll_clk125.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_pll_clk125.qsys
+

libraries/technology/ip_arria10/pll_clk200/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_pll_clk200.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_pll_clk200.qsys
+

libraries/technology/ip_arria10/pll_clk25/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_pll_clk25.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_pll_clk25.qsys
+

libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_pll_xgmii_mac_clocks.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_pll_xgmii_mac_clocks.qsys
+

libraries/technology/ip_arria10/ram/hdllib.cfg

@@ -22,3 +22,11 @@ test_bench_files =
 
 [quartus_project_file]
 
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_ram_crwk_crw.qsys
+    ip_arria10_ram_crw_crw.qsys
+    ip_arria10_ram_cr_cw.qsys
+    ip_arria10_ram_r_w.qsys
+

libraries/technology/ip_arria10/temp_sense/hdllib.cfg

@@ -16,3 +16,8 @@ test_bench_files =
 
 [quartus_project_file]
 quartus_qip_files = generated/ip_arria10_temp_sense.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_temp_sense.qsys
+

libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_transceiver_pll_10g.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_transceiver_pll_10g.qsys
+

libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_transceiver_reset_controller_1.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_transceiver_reset_controller_1.qsys
+

libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_transceiver_reset_controller_12.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_transceiver_reset_controller_12.qsys
+

libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_transceiver_reset_controller_24.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_transceiver_reset_controller_24.qsys
+

libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_transceiver_reset_controller_4.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_transceiver_reset_controller_4.qsys
+

libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_transceiver_reset_controller_48.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_transceiver_reset_controller_48.qsys
+

libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg

@@ -18,3 +18,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_tse_sgmii_gx.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_tse_sgmii_gx.qsys
+