From 3bcb65e2ee8645a3f6a1b9cd866215fbe93871a3 Mon Sep 17 00:00:00 2001
From: donker <donker@astron.nl>
Date: Tue, 1 Oct 2019 10:19:38 +0200
Subject: [PATCH] add key to hdllib.cfg
---
boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg | 3 +++
.../uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg | 3 +++
boards/uniboard1/designs/unb1_ddr3/hdllib.cfg | 3 +++
.../revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg | 3 +++
.../unb1_ddr3_reorder_single_rank/hdllib.cfg | 3 +++
.../uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg | 2 ++
.../uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg | 3 +++
boards/uniboard1/designs/unb1_heater/hdllib.cfg | 3 +++
.../revisions/unb1_minimal_mm_arbiter/hdllib.cfg | 3 +++
.../revisions/unb1_minimal_qsys/hdllib.cfg | 2 ++
.../revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg | 3 +++
.../revisions/unb1_minimal_sopc/hdllib.cfg | 2 ++
.../designs/unb1_terminal_bg_mesh_db/hdllib.cfg | 3 +++
.../unb1_test/revisions/unb1_test_10GbE/hdllib.cfg | 3 +++
.../revisions/unb1_test_10GbE_tx_only/hdllib.cfg | 3 +++
.../unb1_test/revisions/unb1_test_1GbE/hdllib.cfg | 3 +++
.../unb1_test/revisions/unb1_test_all/hdllib.cfg | 3 +++
.../unb1_test/revisions/unb1_test_ddr/hdllib.cfg | 3 +++
.../revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg | 3 +++
.../revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg | 3 +++
.../revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg | 3 +++
.../unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg | 2 ++
.../revisions/unb1_test_ddr_MB_II/hdllib.cfg | 2 ++
.../revisions/unb1_test_ddr_MB_I_II/hdllib.cfg | 2 ++
boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg | 3 +++
boards/uniboard2/designs/unb2_led/hdllib.cfg | 3 +++
boards/uniboard2/designs/unb2_minimal/hdllib.cfg | 3 +++
.../unb2_test/revisions/unb2_test_10GbE/hdllib.cfg | 3 +++
.../unb2_test/revisions/unb2_test_1GbE/hdllib.cfg | 3 +++
.../unb2_test/revisions/unb2_test_all/hdllib.cfg | 3 +++
.../unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg | 2 ++
.../revisions/unb2_test_ddr_MB_II/hdllib.cfg | 2 ++
.../revisions/unb2_test_ddr_MB_I_II/hdllib.cfg | 2 ++
boards/uniboard2a/designs/unb2a_heater/hdllib.cfg | 2 ++
boards/uniboard2a/designs/unb2a_led/hdllib.cfg | 2 ++
boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg | 2 ++
.../unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg | 3 +++
.../unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg | 3 +++
.../unb2a_test/revisions/unb2a_test_all/hdllib.cfg | 3 +++
.../revisions/unb2a_test_ddr_MB_I/hdllib.cfg | 2 ++
.../revisions/unb2a_test_ddr_MB_II/hdllib.cfg | 2 ++
.../revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg | 2 ++
boards/uniboard2b/designs/unb2b_heater/hdllib.cfg | 2 ++
boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg | 3 +--
.../unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg | 3 +++
libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg | 3 +++
libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg | 3 +++
.../dsp/correlator/designs/unb1_correlator/hdllib.cfg | 3 +++
libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg | 3 +++
libraries/io/tr_xaui/hdllib.cfg | 2 +-
.../technology/ip_arria10/clkbuf_global/hdllib.cfg | 5 +++++
.../technology/ip_arria10/complex_mult/hdllib.cfg | 5 +++++
libraries/technology/ip_arria10/ddio/hdllib.cfg | 6 ++++++
.../technology/ip_arria10/ddr4_4g_1600/hdllib.cfg | 5 +++++
.../technology/ip_arria10/ddr4_4g_2000/hdllib.cfg | 4 ++++
.../technology/ip_arria10/ddr4_8g_2400/hdllib.cfg | 5 +++++
libraries/technology/ip_arria10/fifo/hdllib.cfg | 7 +++++++
.../ip_arria10/flash/asmi_parallel/hdllib.cfg | 5 +++++
.../ip_arria10/flash/remote_update/hdllib.cfg | 5 +++++
.../ip_arria10/fractional_pll_clk125/hdllib.cfg | 5 +++++
.../ip_arria10/fractional_pll_clk200/hdllib.cfg | 5 +++++
libraries/technology/ip_arria10/mac_10g/hdllib.cfg | 5 +++++
.../technology/ip_arria10/phy_10gbase_r/hdllib.cfg | 5 +++++
.../technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg | 5 +++++
.../technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg | 5 +++++
.../technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg | 5 +++++
.../technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg | 5 +++++
libraries/technology/ip_arria10/pll_clk125/hdllib.cfg | 5 +++++
libraries/technology/ip_arria10/pll_clk200/hdllib.cfg | 5 +++++
libraries/technology/ip_arria10/pll_clk25/hdllib.cfg | 5 +++++
.../ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg | 5 +++++
libraries/technology/ip_arria10/ram/hdllib.cfg | 8 ++++++++
libraries/technology/ip_arria10/temp_sense/hdllib.cfg | 5 +++++
.../ip_arria10/transceiver_pll_10g/hdllib.cfg | 5 +++++
.../transceiver_reset_controller_1/hdllib.cfg | 5 +++++
.../transceiver_reset_controller_12/hdllib.cfg | 5 +++++
.../transceiver_reset_controller_24/hdllib.cfg | 5 +++++
.../transceiver_reset_controller_4/hdllib.cfg | 5 +++++
.../transceiver_reset_controller_48/hdllib.cfg | 5 +++++
.../technology/ip_arria10/tse_sgmii_gx/hdllib.cfg | 5 +++++
.../technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg | 5 +++++
.../technology/ip_arria10/voltage_sense/hdllib.cfg | 5 +++++
.../ip_arria10_e1sg/clkbuf_global/hdllib.cfg | 5 +++++
.../ip_arria10_e1sg/complex_mult/hdllib.cfg | 5 +++++
libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg | 6 ++++++
.../ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg | 5 +++++
.../ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg | 5 +++++
.../ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg | 5 +++++
.../ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg | 5 +++++
libraries/technology/ip_arria10_e1sg/fifo/hdllib.cfg | 7 +++++++
.../ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg | 5 +++++
.../ip_arria10_e1sg/flash/remote_update/hdllib.cfg | 5 +++++
.../ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg | 5 +++++
.../ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg | 5 +++++
.../technology/ip_arria10_e1sg/mac_10g/hdllib.cfg | 5 +++++
.../technology/ip_arria10_e1sg/mult_add4/hdllib.cfg | 5 +++++
.../ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg | 5 +++++
.../ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg | 5 +++++
.../ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg | 5 +++++
.../ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg | 5 +++++
.../ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg | 5 +++++
.../technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg | 5 +++++
.../technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg | 5 +++++
.../technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg | 5 +++++
.../ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg | 5 +++++
libraries/technology/ip_arria10_e1sg/ram/hdllib.cfg | 8 ++++++++
.../technology/ip_arria10_e1sg/temp_sense/hdllib.cfg | 5 +++++
.../ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg | 5 +++++
.../transceiver_reset_controller_1/hdllib.cfg | 5 +++++
.../transceiver_reset_controller_12/hdllib.cfg | 5 +++++
.../transceiver_reset_controller_24/hdllib.cfg | 5 +++++
.../transceiver_reset_controller_4/hdllib.cfg | 5 +++++
.../transceiver_reset_controller_48/hdllib.cfg | 5 +++++
.../ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg | 5 +++++
.../ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg | 5 +++++
.../ip_arria10_e1sg/voltage_sense/hdllib.cfg | 5 +++++
.../ip_arria10_e3sge3/clkbuf_global/hdllib.cfg | 5 +++++
.../ip_arria10_e3sge3/complex_mult/hdllib.cfg | 5 +++++
.../technology/ip_arria10_e3sge3/ddio/hdllib.cfg | 6 ++++++
.../ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg | 5 +++++
.../ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg | 5 +++++
.../ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg | 5 +++++
.../ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg | 5 +++++
.../technology/ip_arria10_e3sge3/fifo/hdllib.cfg | 7 +++++++
.../ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg | 5 +++++
.../ip_arria10_e3sge3/flash/remote_update/hdllib.cfg | 5 +++++
.../fractional_pll_clk125/hdllib.cfg | 5 +++++
.../fractional_pll_clk200/hdllib.cfg | 5 +++++
.../technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg | 5 +++++
.../technology/ip_arria10_e3sge3/mult_add4/hdllib.cfg | 5 +++++
.../ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg | 5 +++++
.../ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg | 5 +++++
.../ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg | 5 +++++
.../ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg | 5 +++++
.../ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg | 5 +++++
.../ip_arria10_e3sge3/pll_clk125/hdllib.cfg | 5 +++++
.../ip_arria10_e3sge3/pll_clk200/hdllib.cfg | 5 +++++
.../technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg | 5 +++++
.../ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg | 5 +++++
libraries/technology/ip_arria10_e3sge3/ram/hdllib.cfg | 8 ++++++++
.../ip_arria10_e3sge3/temp_sense/hdllib.cfg | 5 +++++
.../ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg | 5 +++++
.../transceiver_reset_controller_1/hdllib.cfg | 5 +++++
.../transceiver_reset_controller_12/hdllib.cfg | 5 +++++
.../transceiver_reset_controller_24/hdllib.cfg | 5 +++++
.../transceiver_reset_controller_4/hdllib.cfg | 5 +++++
.../transceiver_reset_controller_48/hdllib.cfg | 5 +++++
.../ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg | 5 +++++
.../ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg | 5 +++++
.../ip_arria10_e3sge3/voltage_sense/hdllib.cfg | 5 +++++
.../technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg | 11 +++++++++++
.../ddr3_uphy_16g_dual_rank_800/hdllib.cfg | 5 +++++
.../ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg | 5 +++++
.../ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg | 5 +++++
.../ddr3_uphy_4g_single_rank_800_master/hdllib.cfg | 5 +++++
.../ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg | 5 +++++
libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg | 5 +++++
.../ip_stratixiv_phy_xaui_0.vhd | 2 +-
.../ip_stratixiv_phy_xaui_0_sim/mentor/msim_setup.tcl | 2 +-
.../ip_stratixiv_phy_xaui_soft.vhd | 2 +-
.../mentor/msim_setup.tcl | 2 +-
libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg | 10 +++++++++-
162 files changed, 701 insertions(+), 8 deletions(-)
diff --git a/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg b/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
index e970f79671..6886ae203a 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
@@ -47,3 +47,6 @@ quartus_sdc_files =
+
+nios2_app_userflags = -DCOMPILE_FOR_SOPC
+
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg b/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
index e927886e07..39f2b4fad8 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
@@ -34,3 +34,6 @@ quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn
quartus_sdc_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+
+nios2_app_userflags = -DCOMPILE_FOR_SOPC
+
diff --git a/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
index d3453f987c..6ac2788584 100644
--- a/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
@@ -38,3 +38,6 @@ quartus_tcl_files =
quartus_sdc_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+
+nios2_app_userflags = -DCOMPILE_FOR_SOPC
+
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
index 4bded51236..e9680ed83e 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
@@ -45,3 +45,6 @@ quartus_qip_files =
$RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
$RADIOHDL_WORK/build/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.qip
+
+nios2_app_userflags = -DCOMPILE_FOR_SOPC
+
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
index d9e3a8cd86..4e1e86e84b 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
@@ -45,3 +45,6 @@ quartus_qip_files =
$RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
$RADIOHDL_WORK/build/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.qip
+
+nios2_app_userflags = -DCOMPILE_FOR_SOPC
+
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
index 6c541b4951..a11a44ecae 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
@@ -38,3 +38,5 @@ quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.qip
$RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+nios2_app_userflags = -DCOMPILE_FOR_SOPC
+
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg b/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
index d956258b51..6dcd96169c 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
@@ -31,3 +31,6 @@ quartus_tcl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_fn_terminal_db/sopc_unb1_fn_terminal_db.qip
+
+nios2_app_userflags = -DCOMPILE_FOR_SOPC
+
diff --git a/boards/uniboard1/designs/unb1_heater/hdllib.cfg b/boards/uniboard1/designs/unb1_heater/hdllib.cfg
index 84640d28b1..0a1fcb2605 100644
--- a/boards/uniboard1/designs/unb1_heater/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_heater/hdllib.cfg
@@ -36,3 +36,6 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_heater/qsys_unb1_heater/synthesis/qsys_unb1_heater.qip
+
+nios2_app_userflags = -DCOMPILE_FOR_QSYS
+
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg
index 46135b9788..deb47a3d47 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg
@@ -34,3 +34,6 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_minimal_mm_arbiter/qsys_unb1_minimal_mm_arbiter/synthesis/qsys_unb1_minimal_mm_arbiter.qip
+
+nios2_app_userflags = -DCOMPILE_FOR_QSYS
+
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg
index 30e64fde99..fe15d426dd 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg
@@ -37,3 +37,5 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_minimal_qsys/qsys_unb1_minimal/synthesis/qsys_unb1_minimal.qip
+nios2_app_userflags = -DCOMPILE_FOR_QSYS
+
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg
index 8feddd68dc..c338c16de2 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg
@@ -35,3 +35,6 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal/synthesis/qsys_wo_pll_unb1_minimal.qip
+
+nios2_app_userflags = -DCOMPILE_FOR_QSYS
+
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg
index 2724f918e6..9bc3748356 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg
@@ -34,3 +34,5 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_minimal_sopc/sopc_unb1_minimal.qip
+nios2_app_userflags = -DCOMPILE_FOR_SOPC
+
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
index f34d0b341d..57bf8b965b 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
@@ -34,3 +34,6 @@ quartus_qip_files =
quartus_sdc_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+
+nios2_app_userflags = -DCOMPILE_FOR_QSYS
+
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
index 790c2fcb41..6cd3f1ca72 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
@@ -37,3 +37,6 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_10GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+
+nios2_app_userflags = -DCOMPILE_FOR_QSYS
+
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg
index fc2febb454..6a8245325d 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg
@@ -37,3 +37,6 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_10GbE_tx_only/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+
+nios2_app_userflags = -DCOMPILE_FOR_QSYS
+
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg
index 78f41d558f..b1a6665e01 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg
@@ -37,3 +37,6 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_1GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+
+nios2_app_userflags = -DCOMPILE_FOR_QSYS
+
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
index f5dcccf80c..67096db24e 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
@@ -44,3 +44,6 @@ quartus_qip_files =
$RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
#$RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
+
+nios2_app_userflags = -DCOMPILE_FOR_QSYS
+
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
index 8363cba5b7..b45e077994 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
@@ -44,3 +44,6 @@ quartus_qip_files =
$RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
#$RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
+
+nios2_app_userflags = -DCOMPILE_FOR_QSYS
+
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg
index f768ee780f..984c18f3c3 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg
@@ -44,3 +44,6 @@ quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
+
+nios2_app_userflags = -DCOMPILE_FOR_QSYS
+
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg
index 131abe1162..0f81d33534 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg
@@ -43,3 +43,6 @@ quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
+
+nios2_app_userflags = -DCOMPILE_FOR_QSYS
+
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg
index 3c9364d69e..a3dc5f59d0 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg
@@ -43,3 +43,6 @@ quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
+
+nios2_app_userflags = -DCOMPILE_FOR_QSYS
+
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
index 2f10f4fbe8..3c0d599d00 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
@@ -43,3 +43,5 @@ quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+nios2_app_userflags = -DCOMPILE_FOR_QSYS
+
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
index 7fe0acbd0a..2141317b49 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
@@ -43,3 +43,5 @@ quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+nios2_app_userflags = -DCOMPILE_FOR_QSYS
+
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
index b0b65d1327..fc8059c27d 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
@@ -42,3 +42,5 @@ quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+nios2_app_userflags = -DCOMPILE_FOR_QSYS
+
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
index 0e0b26f797..16d1b7fe34 100644
--- a/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
@@ -38,3 +38,6 @@ quartus_qip_files =
quartus_sdc_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+
+nios2_app_userflags = -DCOMPILE_FOR_QSYS
+
diff --git a/boards/uniboard2/designs/unb2_led/hdllib.cfg b/boards/uniboard2/designs/unb2_led/hdllib.cfg
index 31c102a23c..5ee94b1931 100644
--- a/boards/uniboard2/designs/unb2_led/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_led/hdllib.cfg
@@ -32,3 +32,6 @@ quartus_vhdl_files =
quartus_qip_files =
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
+
diff --git a/boards/uniboard2/designs/unb2_minimal/hdllib.cfg b/boards/uniboard2/designs/unb2_minimal/hdllib.cfg
index 3c8171266d..baf6be9c0f 100644
--- a/boards/uniboard2/designs/unb2_minimal/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_minimal/hdllib.cfg
@@ -36,3 +36,6 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb2/quartus/unb2_minimal/qsys_unb2_minimal/synthesis/qsys_unb2_minimal.qip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
+
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
index 2835bf9b43..11d333fa4a 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
@@ -57,3 +57,6 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb2/quartus/unb2_test_10GbE/qsys_unb2_test/synthesis/qsys_unb2_test.qip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
+
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
index a5ce4f51a9..29426ebaef 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
@@ -36,3 +36,6 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb2/quartus/unb2_test_1GbE/qsys_unb2_test/synthesis/qsys_unb2_test.qip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
+
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
index 00625f07eb..49cb72afe5 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
@@ -62,3 +62,6 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb2/quartus/unb2_test_all/qsys_unb2_test/synthesis/qsys_unb2_test.qip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
+
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
index 67f20d9e4f..32d7e2b66d 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
@@ -44,3 +44,5 @@ quartus_tcl_files =
quartus_sdc_files =
$RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
+
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
index 34036c3461..e7f73d3875 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
@@ -44,3 +44,5 @@ quartus_tcl_files =
quartus_sdc_files =
$RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
+
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
index a42629b841..4c2b30eb68 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
@@ -44,3 +44,5 @@ quartus_tcl_files =
quartus_sdc_files =
$RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
+
diff --git a/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg b/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg
index 2c8fffa256..93adc2818a 100644
--- a/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg
@@ -36,3 +36,5 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb2a/quartus/unb2a_heater/qsys_unb2a_heater/synthesis/qsys_unb2a_heater.qip
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
+
diff --git a/boards/uniboard2a/designs/unb2a_led/hdllib.cfg b/boards/uniboard2a/designs/unb2a_led/hdllib.cfg
index 9060d3ba02..9d75b890c2 100644
--- a/boards/uniboard2a/designs/unb2a_led/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_led/hdllib.cfg
@@ -32,3 +32,5 @@ quartus_vhdl_files =
quartus_qip_files =
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
+
diff --git a/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg b/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg
index c569e3b684..5fdd289221 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg
@@ -36,3 +36,5 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb2a/quartus/unb2a_minimal/qsys_unb2a_minimal/synthesis/qsys_unb2a_minimal.qip
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
+
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
index f9c0677edd..8529b7eb5d 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
@@ -60,3 +60,6 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb2a/quartus/unb2a_test_10GbE/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
+
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
index cbc5c0292e..22de500f6e 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
@@ -36,3 +36,6 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb2a/quartus/unb2a_test_1GbE/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
+
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
index 68466090d0..bc11b4b036 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
@@ -63,3 +63,6 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb2a/quartus/unb2a_test_all/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
+
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
index a7a4643277..79cbeb5328 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
@@ -45,3 +45,5 @@ quartus_tcl_files =
quartus_sdc_files =
$RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
+
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
index 4030938bac..ff9a3d4b7a 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
@@ -45,3 +45,5 @@ quartus_tcl_files =
quartus_sdc_files =
$RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
+
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
index 8b25ef236f..2b8b063d7e 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
@@ -45,3 +45,5 @@ quartus_tcl_files =
quartus_sdc_files =
$RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
+
diff --git a/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg b/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg
index 73def4af46..7910f1251a 100644
--- a/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg
@@ -36,3 +36,5 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/qsys_unb2b_heater/qsys_unb2b_heater.qip
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
+
diff --git a/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg b/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
index 213b715445..2c45357259 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
@@ -37,6 +37,5 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/qsys_unb2b_minimal/qsys_unb2b_minimal.qip
-nios2_app_userflags =
- "use=gen2"
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg
index 8d7faee81b..02c44bf134 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg
@@ -61,3 +61,6 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb2b/quartus/unb2b_test_10GbE/qsys_unb2b_test/qsys_unb2b_test.qip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
+
diff --git a/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg b/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg
index 94b17e0841..0ac4f1ca44 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg
+++ b/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg
@@ -36,3 +36,6 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_dp_offload/sopc_unb1_dp_offload.qip
+
+nios2_app_userflags = -DCOMPILE_FOR_SOPC
+
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg b/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg
index b7626df359..53b8ab7f7f 100644
--- a/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg
@@ -33,3 +33,6 @@ quartus_tcl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_fn_bf/sopc_unb1_fn_bf.qip
+
+nios2_app_userflags = -DCOMPILE_FOR_SOPC
+
diff --git a/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg b/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg
index be1afe4a89..8850bc6d00 100644
--- a/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg
+++ b/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg
@@ -32,3 +32,6 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_correlator/qsys_unb1_correlator/synthesis/qsys_unb1_correlator.qip
+
+nios2_app_userflags = -DCOMPILE_FOR_QSYS
+
diff --git a/libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg b/libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg
index 062af006fc..c8bef4e2c3 100644
--- a/libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg
+++ b/libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg
@@ -30,3 +30,6 @@ quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/unb1_eth_10g/qsys_unb1_eth_10g/s
quartus_sdc_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+
+nios2_app_userflags = -DCOMPILE_FOR_QSYS
+
diff --git a/libraries/io/tr_xaui/hdllib.cfg b/libraries/io/tr_xaui/hdllib.cfg
index a74d5202f3..a09ac0f8d4 100644
--- a/libraries/io/tr_xaui/hdllib.cfg
+++ b/libraries/io/tr_xaui/hdllib.cfg
@@ -2,7 +2,7 @@ hdl_lib_name = tr_xaui
hdl_library_clause_name = tr_xaui_lib
hdl_lib_uses_synth = common dp mdio diagnostics tech_xaui
hdl_lib_uses_sim =
-hdl_lib_technology = ip_stratixiv
+hdl_lib_technology =
synth_files =
src/vhdl/tr_xaui_deframer.vhd
diff --git a/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg
index e38e606ee6..d3d850ad78 100644
--- a/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_clkbuf_global.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_clkbuf_global.qsys
+
diff --git a/libraries/technology/ip_arria10/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10/complex_mult/hdllib.cfg
index 09e6c2196d..b61b700ebc 100644
--- a/libraries/technology/ip_arria10/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10/complex_mult/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_complex_mult.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_complex_mult.qsys
+
diff --git a/libraries/technology/ip_arria10/ddio/hdllib.cfg b/libraries/technology/ip_arria10/ddio/hdllib.cfg
index b3a726e9aa..cdf478319d 100644
--- a/libraries/technology/ip_arria10/ddio/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddio/hdllib.cfg
@@ -20,3 +20,9 @@ modelsim_compile_ip_files =
quartus_qip_files =
generated/ip_arria10_ddio_in_1.qip
generated/ip_arria10_ddio_out_1.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_ddio_in_1.qsys
+ ip_arria10_ddio_out_1.qsys
+
diff --git a/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg b/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg
index bf24013508..cd9ab6a0c9 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_ddr4_4g_1600.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_ddr4_4g_1600.qsys
+
diff --git a/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg b/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg
index 6b605ee02f..cf1a8b5f46 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg
@@ -17,3 +17,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_ddr4_4g_2000.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_ddr4_4g_2000.qsys
diff --git a/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg
index 7272be213a..9883e05153 100644
--- a/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_ddr4_8g_2400.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_ddr4_8g_2400.qsys
+
diff --git a/libraries/technology/ip_arria10/fifo/hdllib.cfg b/libraries/technology/ip_arria10/fifo/hdllib.cfg
index 12198c4f1c..07f06f5923 100644
--- a/libraries/technology/ip_arria10/fifo/hdllib.cfg
+++ b/libraries/technology/ip_arria10/fifo/hdllib.cfg
@@ -17,3 +17,10 @@ test_bench_files =
[quartus_project_file]
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_fifo_sc.qsys
+ ip_arria10_fifo_dc.qsys
+ ip_arria10_fifo_dc_mixed_widths.qsys
+
diff --git a/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg
index b07ad14a43..fada8c8e47 100644
--- a/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_asmi_parallel.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_asmi_parallel.qsys
+
diff --git a/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg
index 732cd7b072..464e3bdf68 100644
--- a/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_remote_update.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_remote_update.qsys
+
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg
index 825eb56fb4..71d929e9ed 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_fractional_pll_clk125.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_fractional_pll_clk125.qsys
+
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg
index 4b8ecae748..6b6b3cef3a 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_fractional_pll_clk200.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_fractional_pll_clk200.qsys
+
diff --git a/libraries/technology/ip_arria10/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
index fe9d8cfe4c..bd87b3444a 100644
--- a/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
@@ -20,3 +20,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_mac_10g.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_mac_10g.qsys
+
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
index 1d90fe04e6..b4fc8605ca 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_phy_10gbase_r.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_phy_10gbase_r.qsys
+
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg
index 52f291e044..52866d7080 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_phy_10gbase_r_12.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_phy_10gbase_r_12.qsys
+
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
index f203933b41..0c22bfef18 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_phy_10gbase_r_24.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_phy_10gbase_r_24.qsys
+
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg
index 84ed2d979e..9066174d78 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_phy_10gbase_r_4.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_phy_10gbase_r_4.qsys
+
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg
index 23b996d5d1..3372c4933b 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_phy_10gbase_r_48.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_phy_10gbase_r_48.qsys
+
diff --git a/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg
index ba0c574b95..716dc23633 100644
--- a/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_pll_clk125.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_pll_clk125.qsys
+
diff --git a/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg
index 876299925e..a2cceba6b3 100644
--- a/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_pll_clk200.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_pll_clk200.qsys
+
diff --git a/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg
index 85ec82a965..9254e79292 100644
--- a/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_pll_clk25.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_pll_clk25.qsys
+
diff --git a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg
index 7fe81748c9..e868b714af 100644
--- a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_pll_xgmii_mac_clocks.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_pll_xgmii_mac_clocks.qsys
+
diff --git a/libraries/technology/ip_arria10/ram/hdllib.cfg b/libraries/technology/ip_arria10/ram/hdllib.cfg
index c955318716..4b56555b04 100644
--- a/libraries/technology/ip_arria10/ram/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ram/hdllib.cfg
@@ -22,3 +22,11 @@ test_bench_files =
[quartus_project_file]
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_ram_crwk_crw.qsys
+ ip_arria10_ram_crw_crw.qsys
+ ip_arria10_ram_cr_cw.qsys
+ ip_arria10_ram_r_w.qsys
+
diff --git a/libraries/technology/ip_arria10/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10/temp_sense/hdllib.cfg
index 0d4162d734..743b54a4f8 100644
--- a/libraries/technology/ip_arria10/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10/temp_sense/hdllib.cfg
@@ -16,3 +16,8 @@ test_bench_files =
[quartus_project_file]
quartus_qip_files = generated/ip_arria10_temp_sense.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_temp_sense.qsys
+
diff --git a/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
index 75dcfa5eca..be5fa19d53 100644
--- a/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_transceiver_pll_10g.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_transceiver_pll_10g.qsys
+
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
index 11f7683e31..64be140c28 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_transceiver_reset_controller_1.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_transceiver_reset_controller_1.qsys
+
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg
index c6a5d3b797..f5aa17bd77 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_transceiver_reset_controller_12.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_transceiver_reset_controller_12.qsys
+
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
index 490fa6c30d..f9d08597da 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_transceiver_reset_controller_24.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_transceiver_reset_controller_24.qsys
+
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg
index d24b6726af..7e5fb7f0d3 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_transceiver_reset_controller_4.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_transceiver_reset_controller_4.qsys
+
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg
index 58e0413fd0..a519b5da8e 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_transceiver_reset_controller_48.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_transceiver_reset_controller_48.qsys
+
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
index 26d59ecf13..76550d695f 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
@@ -18,3 +18,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_tse_sgmii_gx.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_tse_sgmii_gx.qsys
+
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
index 694b6c70f6..f840e7826f 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
@@ -19,3 +19,8 @@ modelsim_compile_ip_files =
quartus_qip_files =
generated/ip_arria10_tse_sgmii_lvds.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_tse_sgmii_lvds.qsys
+
diff --git a/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg
index a2e3ec5155..72730345ec 100644
--- a/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg
@@ -17,3 +17,8 @@ test_bench_files =
[quartus_project_file]
quartus_qip_files = generated/ip_arria10_voltage_sense.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_voltage_sense.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
index 7504ddb609..23561d7520 100644
--- a/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_clkbuf_global.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_clkbuf_global.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
index 02a6d4874a..90d4a43e52 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_complex_mult.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_complex_mult.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
index 8fd1e669ff..4b67f37fb8 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
@@ -20,3 +20,9 @@ modelsim_compile_ip_files =
quartus_qip_files =
generated/ip_arria10_e1sg_ddio_in_1.qip
generated/ip_arria10_e1sg_ddio_out_1.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_ddio_in_1.qsys
+ ip_arria10_e1sg_ddio_out_1.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
index 9fa46dcfab..b85f1affbd 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_ddr4_4g_1600.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_ddr4_4g_1600.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
index 695d6e9a6b..df3280dd87 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_ddr4_4g_2000.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_ddr4_4g_2000.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
index fb991b3967..8ae4f5fe24 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
@@ -18,3 +18,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_ddr4_8g_1600.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_ddr4_8g_1600.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
index ceea1ea066..1e627f46a2 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_ddr4_8g_2400.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_ddr4_8g_2400.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/fifo/hdllib.cfg
index 6bbc027dd8..a44f90faa8 100644
--- a/libraries/technology/ip_arria10_e1sg/fifo/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/fifo/hdllib.cfg
@@ -17,3 +17,10 @@ test_bench_files =
[quartus_project_file]
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_fifo_sc.qsys
+ ip_arria10_e1sg_fifo_dc.qsys
+ ip_arria10_e1sg_fifo_dc_mixed_widths.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
index 05b50ddd82..5759286524 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_asmi_parallel.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_asmi_parallel.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
index 9db01d2cbd..d976bfc1df 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_remote_update.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_remote_update.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
index f4a814161a..0c531649bf 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_fractional_pll_clk125.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_fractional_pll_clk125.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
index 1a6b0a376b..abb39ab8e3 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_fractional_pll_clk200.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_fractional_pll_clk200.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
index 8b45746380..cd1823f27a 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
@@ -20,3 +20,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_mac_10g.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_mac_10g.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/mult_add4/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/mult_add4/hdllib.cfg
index 762c5bdef3..a08133a9e1 100644
--- a/libraries/technology/ip_arria10_e1sg/mult_add4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/mult_add4/hdllib.cfg
@@ -14,3 +14,8 @@ test_bench_files =
[quartus_project_file]
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_mult_add4.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
index d35beb3b4e..0741afe109 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_phy_10gbase_r.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_phy_10gbase_r.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
index 29adb1d9b8..a96e9f38fa 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_phy_10gbase_r_12.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_phy_10gbase_r_12.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
index 4bd7fc021e..73089d379c 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_phy_10gbase_r_24.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_phy_10gbase_r_24.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
index 89b33cab67..d9b2caffc6 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_phy_10gbase_r_4.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_phy_10gbase_r_4.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
index 8876a23c01..2f81d5c56d 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_phy_10gbase_r_48.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_phy_10gbase_r_48.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
index 5d46c79cf0..fba621f4cc 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_pll_clk125.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_pll_clk125.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
index f931e60738..64f374ea39 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_pll_clk200.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_pll_clk200.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
index 776f7257d6..0b0445e87b 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_pll_clk25.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_pll_clk25.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
index 9bbc02a2ca..828c1daaa8 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_pll_xgmii_mac_clocks.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_pll_xgmii_mac_clocks.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/ram/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ram/hdllib.cfg
index 11a6f46151..84cf6b8216 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ram/hdllib.cfg
@@ -22,3 +22,11 @@ test_bench_files =
[quartus_project_file]
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_ram_crwk_crw.qsys
+ ip_arria10_e1sg_ram_crw_crw.qsys
+ ip_arria10_e1sg_ram_cr_cw.qsys
+ ip_arria10_e1sg_ram_r_w.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
index 0d72950c53..802957ffee 100644
--- a/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
@@ -16,3 +16,8 @@ test_bench_files =
[quartus_project_file]
quartus_qip_files = generated/ip_arria10_e1sg_temp_sense.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_temp_sense.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
index 08c2ac709b..2ccd57aa2c 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_transceiver_pll_10g.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_transceiver_pll_10g.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
index 66e3ff86ed..c166e3b4b0 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_transceiver_reset_controller_1.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_transceiver_reset_controller_1.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
index 23934188a7..47ed49c37e 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_transceiver_reset_controller_12.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_transceiver_reset_controller_12.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
index f71b8b1bd4..6db0558222 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_transceiver_reset_controller_24.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_transceiver_reset_controller_24.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
index 49ae906062..43c1644820 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_transceiver_reset_controller_4.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_transceiver_reset_controller_4.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
index 51f03a221a..a886607f47 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_transceiver_reset_controller_48.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_transceiver_reset_controller_48.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
index abfacc5cb9..b0c2a4a140 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
@@ -18,3 +18,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_tse_sgmii_gx.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_tse_sgmii_gx.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
index 9a67954387..148454de1b 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
@@ -20,3 +20,8 @@ modelsim_compile_ip_files =
quartus_qip_files =
generated/ip_arria10_e1sg_tse_sgmii_lvds.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_tse_sgmii_lvds.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
index 58a16e4119..e1c54d182a 100644
--- a/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
@@ -17,3 +17,8 @@ test_bench_files =
[quartus_project_file]
quartus_qip_files = generated/ip_arria10_e1sg_voltage_sense.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_voltage_sense.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg
index 0c279c1749..66d47d1ae3 100644
--- a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_clkbuf_global.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_clkbuf_global.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg
index 66eec32570..28ead31eed 100644
--- a/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_complex_mult.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_complex_mult.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg
index ffdcf8e0d8..d053102ed7 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg
@@ -20,3 +20,9 @@ modelsim_compile_ip_files =
quartus_qip_files =
generated/ip_arria10_e3sge3_ddio_in_1.qip
generated/ip_arria10_e3sge3_ddio_out_1.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_ddio_in_1.qsys
+ ip_arria10_e3sge3_ddio_out_1.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg
index 7de6d9cc7e..20a085ab64 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_ddr4_4g_1600.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_ddr4_4g_1600.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg
index 5b8927482c..c23aafef03 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_ddr4_4g_2000.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_ddr4_4g_2000.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg
index a90e81ff44..29715012a3 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_ddr4_8g_1600.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_ddr4_8g_1600.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg
index 91a0f97472..a433ee5522 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_ddr4_8g_2400.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_ddr4_8g_2400.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/fifo/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/fifo/hdllib.cfg
index 779ccfcef2..feab22041e 100644
--- a/libraries/technology/ip_arria10_e3sge3/fifo/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/fifo/hdllib.cfg
@@ -17,3 +17,10 @@ test_bench_files =
[quartus_project_file]
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_fifo_sc.qsys
+ ip_arria10_e3sge3_fifo_dc.qsys
+ ip_arria10_e3sge3_fifo_dc_mixed_widths.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg
index 0ceeddd60a..08a9862f73 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_asmi_parallel.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_asmi_parallel.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg
index 4bf49a5928..ee60d547c8 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_remote_update.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_remote_update.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg
index 86e2ac2c1a..70f593d6bb 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_fractional_pll_clk125.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_fractional_pll_clk125.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg
index dc5a2ead34..f150a9eff0 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_fractional_pll_clk200.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_fractional_pll_clk200.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg
index 98c627b440..9d03c8de48 100644
--- a/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg
@@ -20,3 +20,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_mac_10g.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_mac_10g.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/mult_add4/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/mult_add4/hdllib.cfg
index ca89bcac69..49f1f40515 100644
--- a/libraries/technology/ip_arria10_e3sge3/mult_add4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/mult_add4/hdllib.cfg
@@ -14,3 +14,8 @@ test_bench_files =
[quartus_project_file]
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_mult_add4.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg
index ef62134dae..d6999a29ee 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_phy_10gbase_r.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_phy_10gbase_r.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg
index 7f282e1841..2c483639f5 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_phy_10gbase_r_12.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_phy_10gbase_r_12.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg
index c71586e637..5c2b3e6e59 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_phy_10gbase_r_24.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_phy_10gbase_r_24.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg
index fa9eb57875..94e1849d1e 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_phy_10gbase_r_4.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_phy_10gbase_r_4.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg
index a9a4f25f2a..4ea8a12229 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_phy_10gbase_r_48.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_phy_10gbase_r_48.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg
index 4744956c34..3e61b19f5b 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_pll_clk125.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_pll_clk125.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg
index bbf989101b..736f98fb0c 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_pll_clk200.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_pll_clk200.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg
index faa8018251..7ddd6210a7 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_pll_clk25.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_pll_clk25.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg
index 8ffd2a8b64..3241762cfd 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_pll_xgmii_mac_clocks.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_pll_xgmii_mac_clocks.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ram/hdllib.cfg
index 993b503c63..5042710d8b 100644
--- a/libraries/technology/ip_arria10_e3sge3/ram/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ram/hdllib.cfg
@@ -22,3 +22,11 @@ test_bench_files =
[quartus_project_file]
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_ram_crwk_crw.qsys
+ ip_arria10_e3sge3_ram_crw_crw.qsys
+ ip_arria10_e3sge3_ram_cr_cw.qsys
+ ip_arria10_e3sge3_ram_r_w.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg
index eb2f310663..04b2dc9836 100644
--- a/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg
@@ -16,3 +16,8 @@ test_bench_files =
[quartus_project_file]
quartus_qip_files = generated/ip_arria10_e3sge3_temp_sense.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_temp_sense.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg
index 351187d243..d128486395 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_transceiver_pll_10g.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_transceiver_pll_10g.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg
index fd0ff98f51..df77648d5b 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_transceiver_reset_controller_1.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_transceiver_reset_controller_1.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg
index 6d8544bec1..1174e7891a 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_transceiver_reset_controller_12.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_transceiver_reset_controller_12.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg
index 3104cabeda..5568315590 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_transceiver_reset_controller_24.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_transceiver_reset_controller_24.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg
index 4c9fed6698..e5bb6bb856 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_transceiver_reset_controller_4.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_transceiver_reset_controller_4.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg
index 86b474c736..9185b8febc 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_transceiver_reset_controller_48.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_transceiver_reset_controller_48.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg
index df60de6e51..a2022287b2 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg
@@ -18,3 +18,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_tse_sgmii_gx.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_tse_sgmii_gx.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg
index 8c175111ce..5665f5db4c 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg
@@ -19,3 +19,8 @@ modelsim_compile_ip_files =
quartus_qip_files =
generated/ip_arria10_e3sge3_tse_sgmii_lvds.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_tse_sgmii_lvds.qsys
+
diff --git a/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg
index b6529dfd36..63946dd01b 100644
--- a/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg
@@ -17,3 +17,8 @@ test_bench_files =
[quartus_project_file]
quartus_qip_files = generated/ip_arria10_e3sge3_voltage_sense.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e3sge3_voltage_sense.qsys
+
diff --git a/libraries/technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg
index 6e6d7706b8..be91a1fd6b 100644
--- a/libraries/technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg
@@ -15,3 +15,14 @@ modelsim_compile_ip_files =
[quartus_project_file]
+
+
+[generate_ip_libs]
+qmegawiz_ip_files =
+ ip_stratixiv_ddr3_uphy_4g_800_master.v
+quartus_sh_ip_files =
+ generate_sim_vhdl_example_design.tcl
+quartus_sh_ip_srcdir =
+ ../qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_example_design/simulation
+
+#cd ../ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_example_design/simulation
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg
index 1b5ee24b7e..31f0359c75 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg
@@ -18,3 +18,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
+
+[generate_ip_libs]
+qmegawiz_ip_files =
+ ip_stratixiv_ddr3_uphy_16g_dual_rank_800.v
+
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg
index 9644bb62bc..0d39d81f1f 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg
@@ -18,3 +18,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+
+[generate_ip_libs]
+qmegawiz_ip_files =
+ ip_stratixiv_ddr3_uphy_4g_800_master.v
+
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg
index f56145e6a6..46a856b9a0 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg
@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
+
+[generate_ip_libs]
+qmegawiz_ip_files =
+ ip_stratixiv_ddr3_uphy_4g_800_slave.v
+
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg
index 1f4f9200a4..c28bd93dd1 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg
@@ -18,3 +18,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+
+[generate_ip_libs]
+qmegawiz_ip_files =
+ ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.v
+
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg
index bf801765f0..6f9285a234 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg
@@ -18,3 +18,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.qip
+
+[generate_ip_libs]
+qmegawiz_ip_files =
+ ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg b/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg
index 0863274168..da20f4a1a8 100644
--- a/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg
@@ -26,3 +26,8 @@ quartus_sdc_files =
quartus_qip_files =
generated/ip_stratixiv_mac_10g.qip
+
+[generate_ip_libs]
+qmegawiz_ip_files =
+ ip_stratixiv_mac_10g.vhd
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/ip_stratixiv_phy_xaui_0.vhd b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/ip_stratixiv_phy_xaui_0.vhd
index f0bda1c332..6eaa8362bf 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/ip_stratixiv_phy_xaui_0.vhd
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/ip_stratixiv_phy_xaui_0.vhd
@@ -1,6 +1,6 @@
-- ip_stratixiv_phy_xaui_0.vhd
--- Generated using ACDS version 11.1sp2 259 at 2016.05.17.15:40:35
+-- Generated using ACDS version 11.1sp2 259 at 2019.09.24.11:22:17
library IEEE;
use IEEE.std_logic_1164.all;
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/mentor/msim_setup.tcl b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/mentor/msim_setup.tcl
index 6016835230..05cf8ec7e2 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/mentor/msim_setup.tcl
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/mentor/msim_setup.tcl
@@ -1,5 +1,5 @@
-# (C) 2001-2016 Altera Corporation. All rights reserved.
+# (C) 2001-2019 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/ip_stratixiv_phy_xaui_soft.vhd b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/ip_stratixiv_phy_xaui_soft.vhd
index f9ee88a0be..ba85a5ee9e 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/ip_stratixiv_phy_xaui_soft.vhd
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/ip_stratixiv_phy_xaui_soft.vhd
@@ -1,6 +1,6 @@
-- ip_stratixiv_phy_xaui_soft.vhd
--- Generated using ACDS version 11.1sp2 259 at 2016.05.17.15:41:14
+-- Generated using ACDS version 11.1sp2 259 at 2019.09.24.11:22:44
library IEEE;
use IEEE.std_logic_1164.all;
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/mentor/msim_setup.tcl b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/mentor/msim_setup.tcl
index 2d65d2485f..047e62db29 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/mentor/msim_setup.tcl
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/mentor/msim_setup.tcl
@@ -1,5 +1,5 @@
-# (C) 2001-2016 Altera Corporation. All rights reserved.
+# (C) 2001-2019 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg b/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg
index 260a93b452..8f8916bf66 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg
@@ -34,4 +34,12 @@ quartus_sdc_files =
quartus_qip_files =
generated/ip_stratixiv_phy_xaui_0.qip
- ip_stratixiv_phy_xaui_soft.qip
\ No newline at end of file
+ ip_stratixiv_phy_xaui_soft.qip
+
+[generate_ip_libs]
+qmegawiz_ip_files =
+ ip_stratixiv_phy_xaui_0.vhd
+ ip_stratixiv_phy_xaui_1.vhd
+ ip_stratixiv_phy_xaui_2.vhd
+ ip_stratixiv_phy_xaui_soft.vhd
+
--
GitLab