RTSD-181: Removed assert and recover assignment clock_b.

libraries/technology/memory/tech_memory_ram_crw_crw.vhd

@@ -58,7 +58,7 @@ entity tech_memory_ram_crw_crw is
     address_a : in std_logic_vector(g_adr_w - 1 downto 0);
     address_b : in std_logic_vector(g_adr_w - 1 downto 0);
     clock_a   : in std_logic  := '1';
-    clock_b   : in std_logic  := '1';
+    clock_b   : in std_logic;
     data_a    : in std_logic_vector(g_dat_w - 1 downto 0);
     data_b    : in std_logic_vector(g_dat_w - 1 downto 0);
     enable_a  : in std_logic  := '1';
@@ -110,10 +110,6 @@ begin
     port map (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
   end generate;
 
-  assert not(g_technology = c_tech_agi027_xxxx and clock_a /= clock_b) 
-    report "tech_memory_ram_crw_crw, utilizing ip_agi027_xxxx_ram_rw_rw : only supports one clock domain (use clock_b)"
-    severity FAILURE;
-
   gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
     u0 : ip_agi027_xxxx_ram_rw_rw
     generic map (false, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)