From 05cae2cf0d7080211c32554bde67b44387d20e6e Mon Sep 17 00:00:00 2001
From: David Brouwer <dbrouwer@astron.nl>
Date: Thu, 18 Jan 2024 11:43:46 +0100
Subject: [PATCH] RTSD-181: Removed assert and recover assignment clock_b.
---
libraries/technology/memory/tech_memory_ram_crw_crw.vhd | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
index 2bcc8bcca8..d27c85e4a8 100644
--- a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
@@ -58,7 +58,7 @@ entity tech_memory_ram_crw_crw is
address_a : in std_logic_vector(g_adr_w - 1 downto 0);
address_b : in std_logic_vector(g_adr_w - 1 downto 0);
clock_a : in std_logic := '1';
- clock_b : in std_logic := '1';
+ clock_b : in std_logic;
data_a : in std_logic_vector(g_dat_w - 1 downto 0);
data_b : in std_logic_vector(g_dat_w - 1 downto 0);
enable_a : in std_logic := '1';
@@ -110,10 +110,6 @@ begin
port map (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
end generate;
- assert not(g_technology = c_tech_agi027_xxxx and clock_a /= clock_b)
- report "tech_memory_ram_crw_crw, utilizing ip_agi027_xxxx_ram_rw_rw : only supports one clock domain (use clock_b)"
- severity FAILURE;
-
gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
u0 : ip_agi027_xxxx_ram_rw_rw
generic map (false, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
--
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