Skip to content
GitLab
Explore
Sign in
Primary navigation
Search or go to…
Project
H
HDL
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Iterations
Wiki
Requirements
Jira
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Locked files
Build
Pipelines
Jobs
Pipeline schedules
Test cases
Artifacts
Deploy
Releases
Container registry
Model registry
Operate
Environments
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Code review analytics
Issue analytics
Insights
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
RTSD
HDL
Commits
052e6d0e
Commit
052e6d0e
authored
3 years ago
by
Job van Wee
Browse files
Options
Downloads
Plain Diff
Merge branch '
L2SDP-644
' into
L2SDP-657
parents
f1b0a7c8
945b0d39
Branches
Branches containing commit
No related tags found
1 merge request
!215
Resolve L2SDP-660
Changes
1
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_pack.vhd
+2
-2
2 additions, 2 deletions
...ions/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_pack.vhd
with
2 additions
and
2 deletions
applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_pack.vhd
+
2
−
2
View file @
052e6d0e
...
...
@@ -50,7 +50,7 @@ ARCHITECTURE tb OF tb_ddrctrl_pack IS
CONSTANT
c_out_data_w
:
NATURAL
:
=
g_nof_streams
*
g_data_w
;
-- output data with, 168
FUNCTION
c_testv_init
RETURN
STD_LOGIC_VECTOR
IS
VARIABLE
temp
:
STD_LOGIC_VECTOR
(
c_out_data_w
-1
DOWNTO
0
);
VARIABLE
temp
:
STD_LOGIC_VECTOR
(
c_out_data_w
-1
DOWNTO
0
);
BEGIN
FOR
I
IN
0
TO
g_nof_streams
-1
LOOP
temp
(
g_data_w
*
(
I
+
1
)
-1
DOWNTO
g_data_w
*
I
)
:
=
TO_UVEC
(
I
,
g_data_w
);
...
...
@@ -78,7 +78,7 @@ BEGIN
-- Start the testbench.
tb_end
<=
'0'
;
WAIT
UNTIL
rising_edge
(
clk
);
-- align to rising edge
WAIT
UNTIL
rising_edge
(
clk
);
-- align to rising edge
WAIT
FOR
c_clk_period
*
2
;
...
...
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment