Ready for review.

applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_pack.vhd

@@ -50,7 +50,7 @@ ARCHITECTURE tb OF tb_ddrctrl_pack IS
   CONSTANT  c_out_data_w      : NATURAL                                     := g_nof_streams * g_data_w;          -- output data with, 168
 
   FUNCTION c_testv_init RETURN STD_LOGIC_VECTOR IS
-    VARIABLE temp : STD_LOGIC_VECTOR(c_out_data_w-1 DOWNTO 0);
+    VARIABLE temp             : STD_LOGIC_VECTOR(c_out_data_w-1 DOWNTO 0);
   BEGIN
     FOR I IN 0 TO g_nof_streams-1 LOOP
       temp(g_data_w*(I+1)-1 DOWNTO g_data_w*I) := TO_UVEC(I, g_data_w);
@@ -78,7 +78,7 @@ BEGIN
 
     -- Start the testbench.
     tb_end            <= '0';
-    WAIT UNTIL rising_edge(clk);  -- align to rising edge
+    WAIT UNTIL rising_edge(clk);                                                                                  -- align to rising edge
     WAIT FOR c_clk_period*2;