finishing tb, almost ready for review.

applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_repack.vhd

@@ -35,61 +35,89 @@ USE common_lib.common_pkg.ALL;
 ENTITY tb_ddrctrl_repack IS
   GENERIC (
 
-    g_tech_ddr                : t_c_tech_ddr                            := c_tech_ddr4_8g_1600m;
-    g_in_data_w	              : NATURAL                                 := 168
+    g_tech_ddr                : t_c_tech_ddr                                           := c_tech_ddr4_8g_1600m;                    -- type of memory
+    g_in_data_w	              : NATURAL                                                := 168;                                     -- input data vector with
+    g_sim_lengt               : NATURAL                                                := 32                                       -- amount of times there wil be input data for ddrctrl_repack in this testbench
 
   );
 END tb_ddrctrl_repack;
 
 ARCHITECTURE tb OF tb_ddrctrl_repack IS
 
-  CONSTANT  c_clk_freq        : NATURAL                                 := 200;     -- MHz
-  CONSTANT  c_clk_period      : TIME                                    := (10**6 / c_clk_freq) * 1 ps;
-  CONSTANT  c_out_data_w      : NATURAL                                 := func_tech_ddr_ctlr_data_w( g_tech_ddr ); --576
+  CONSTANT  c_clk_freq        : NATURAL                                                := 200;                                     -- clock freqency in MHz
+  CONSTANT  c_clk_period      : TIME                                                   := (10**6 / c_clk_freq) * 1 ps;             -- clock period, 5 ns
+  CONSTANT  c_out_data_w      : NATURAL                                                := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- output data vector with, 576
 
 
-  SIGNAL    tb_end            : STD_LOGIC                               := '0';
+  FUNCTION  c_total_vector_init RETURN STD_LOGIC_VECTOR IS
+    VARIABLE temp             : STD_LOGIC_VECTOR(g_in_data_w*g_sim_lengt-1 DOWNTO 0);
+  BEGIN
+    FOR I IN 0 TO g_sim_lengt-1 LOOP
+      temp(g_in_data_w*(I+1)-1 DOWNTO g_in_data_w*I) := TO_UVEC(I, g_in_data_w);
+    END LOOP;
+    RETURN temp;
+  END FUNCTION c_total_vector_init;
+  CONSTANT  c_total_vector    : STD_LOGIC_VECTOR(g_in_data_w*g_sim_lengt-1 DOWNTO 0)   := c_total_vector_init;                     -- vector witch contains all input data vectors to make it easy to fill ctr_vector
+
 
-  SIGNAL    clk               : STD_LOGIC                               := '1';
-  SIGNAL    in_data           : STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0):= (OTHERS => '0');
+  SIGNAL    total_vector_cnt  : NATURAL                                                := 0;                                       -- signal to keep track of how many times there has been checked if there is the correct output
 
-  SIGNAL    out_of            : NATURAL                                 := 0;
-  SIGNAL    out_sosi          : t_dp_sosi                               := c_dp_sosi_init;
+  SIGNAL    tb_end            : STD_LOGIC                                              := '0';                                     -- signal to turn the testbench off
+
+  SIGNAL    clk               : STD_LOGIC                                              := '1';                                     -- clock signal
+  SIGNAL    in_data           : STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0)               := (OTHERS => '0');                         -- input data signal for ddrctrl_repack
+
+  SIGNAL    out_of            : NATURAL                                                := 0;                                       -- output signal from ddrctrl_repack to determen how high the overflow is
+  SIGNAL    out_sosi          : t_dp_sosi                                              := c_dp_sosi_init;                          -- output data signal form ddrctrl_repack
 
 BEGIN
 
-  clk                 <= NOT clk OR tb_end AFTER c_clk_period/2;
+  clk                 <= NOT clk OR tb_end AFTER c_clk_period/2;                                                                   -- genereting clock signal
 
   p_mm : PROCESS
   BEGIN
 
+
+    -- Start the testbench.
     tb_end            <= '0';
+    WAIT UNTIL rising_edge(clk);                                                                                                   -- align to rising edge
+    WAIT UNTIL out_of /= 0;                                                                                                        -- wait for out_of /= 0 to align to ddrctrl_repack properly 
+    WAIT UNTIL out_of = 0;                                                                                                         -- align to ddrctrl_repack 
 
-    WAIT UNTIL rising_edge(clk);  -- align to rising edge
-    WAIT FOR c_clk_period*30;
-    WAIT UNTIL out_of = 0;       -- align to ddrctrl_repack 
 
-    change_in_data : FOR I IN 0 TO 32 LOOP
+    -- Filling the input vector g_sim_lengt amount of times.
+    make_in_data : FOR I IN 0 TO g_sim_lengt-1 LOOP
       --ASSERT FALSE REPORT "I = " & NATURAL'image(I) SEVERITY NOTE;
       in_data(g_in_data_w-1 DOWNTO 0) <= TO_UVEC(I, g_in_data_w);
       WAIT FOR c_clk_period*1;
     END LOOP;
 
-    WAIT FOR c_clk_period*5;
 
+    -- Stop the testbench.
+    WAIT FOR c_clk_period*5;
     tb_end <= '1';
 
     WAIT;
   END PROCESS;
 
+
+  -- Verification by checking if the input vectors are correctly put into the output vector.
   p_verify : PROCESS
   BEGIN
-    WAIT UNTIL rising_edge(out_sosi.valid);
+
+ 
+    WAIT UNTIL rising_edge(clk);                                                                                                   -- align to rising edge
+    WAIT UNTIL out_of /= 0;                                                                                                        -- wait for out_of /= 0 to align to ddrctrl_repack properly 
+    WAIT UNTIL out_of = 0;                                                                                                         -- align to ddrctrl_repack 
+    WAIT FOR c_clk_period*1;                                                                                                       -- first outputdata is empty
+
     IF rising_edge(out_sosi.valid) THEN
-        ASSERT out_sosi.data(c_out_data_w -1 DOWNTO 0) = iets REPORT "Data does not match, I = " SEVERITY NOTE;
+        ASSERT out_sosi.data(c_out_data_w -1 DOWNTO 0) = c_total_vector(c_out_data_w*(total_vector_cnt+1)-1 DOWNTO c_out_data_w*total_vector_cnt) REPORT "Data does not match, total_vector_cnt = " & NATURAL'image(total_vector_cnt)  SEVERITY NOTE;
+        total_vector_cnt <= total_vector_cnt + 1;
     END IF;
   END PROCESS;
 
+
   u_ddrctrl_repack : ENTITY work.ddrctrl_repack
   GENERIC MAP (
     g_tech_ddr        => g_tech_ddr,