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Commit f3ca9837 authored by Jan David Mol's avatar Jan David Mol
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L2SS-358: Added MAC address of dts-lcu:eno2

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CDB/Darkrai_ConfigDb.json
+ 32
− 32
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...@@ -109,22 +109,22 @@ ...@@ -109,22 +109,22 @@
"5.0" "5.0"
], ],
"FPGA_sst_offload_hdr_eth_destination_mac_RW_default": [ "FPGA_sst_offload_hdr_eth_destination_mac_RW_default": [
"6c:2b:59:97:be:dd", "0c:c4:7a:c0:30:f1",
"6c:2b:59:97:be:dd", "0c:c4:7a:c0:30:f1",
"6c:2b:59:97:be:dd", "0c:c4:7a:c0:30:f1",
"6c:2b:59:97:be:dd", "0c:c4:7a:c0:30:f1",
"6c:2b:59:97:be:dd", "0c:c4:7a:c0:30:f1",
"6c:2b:59:97:be:dd", "0c:c4:7a:c0:30:f1",
"6c:2b:59:97:be:dd", "0c:c4:7a:c0:30:f1",
"6c:2b:59:97:be:dd", "0c:c4:7a:c0:30:f1",
"6c:2b:59:97:be:dd", "0c:c4:7a:c0:30:f1",
"6c:2b:59:97:be:dd", "0c:c4:7a:c0:30:f1",
"6c:2b:59:97:be:dd", "0c:c4:7a:c0:30:f1",
"6c:2b:59:97:be:dd", "0c:c4:7a:c0:30:f1",
"6c:2b:59:97:be:dd", "0c:c4:7a:c0:30:f1",
"6c:2b:59:97:be:dd", "0c:c4:7a:c0:30:f1",
"6c:2b:59:97:be:dd", "0c:c4:7a:c0:30:f1",
"6c:2b:59:97:be:dd" "0c:c4:7a:c0:30:f1"
], ],
"FPGA_sst_offload_hdr_ip_destination_address_RW_default": [ "FPGA_sst_offload_hdr_ip_destination_address_RW_default": [
"10.99.250.250", "10.99.250.250",
...@@ -164,22 +164,22 @@ ...@@ -164,22 +164,22 @@
"5.0" "5.0"
], ],
"FPGA_xst_offload_hdr_eth_destination_mac_RW_default": [ "FPGA_xst_offload_hdr_eth_destination_mac_RW_default": [
"6c:2b:59:97:be:dd", "0c:c4:7a:c0:30:f1",
"6c:2b:59:97:be:dd", "0c:c4:7a:c0:30:f1",
"6c:2b:59:97:be:dd", "0c:c4:7a:c0:30:f1",
"6c:2b:59:97:be:dd", "0c:c4:7a:c0:30:f1",
"6c:2b:59:97:be:dd", "0c:c4:7a:c0:30:f1",
"6c:2b:59:97:be:dd", "0c:c4:7a:c0:30:f1",
"6c:2b:59:97:be:dd", "0c:c4:7a:c0:30:f1",
"6c:2b:59:97:be:dd", "0c:c4:7a:c0:30:f1",
"6c:2b:59:97:be:dd", "0c:c4:7a:c0:30:f1",
"6c:2b:59:97:be:dd", "0c:c4:7a:c0:30:f1",
"6c:2b:59:97:be:dd", "0c:c4:7a:c0:30:f1",
"6c:2b:59:97:be:dd", "0c:c4:7a:c0:30:f1",
"6c:2b:59:97:be:dd", "0c:c4:7a:c0:30:f1",
"6c:2b:59:97:be:dd", "0c:c4:7a:c0:30:f1",
"6c:2b:59:97:be:dd", "0c:c4:7a:c0:30:f1",
"6c:2b:59:97:be:dd" "0c:c4:7a:c0:30:f1"
], ],
"FPGA_xst_offload_hdr_ip_destination_address_RW_default": [ "FPGA_xst_offload_hdr_ip_destination_address_RW_default": [
"10.99.250.250", "10.99.250.250",
......
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