From f3ca9837b4c69ddadfa34961b56c3c33122b69ff Mon Sep 17 00:00:00 2001
From: Jan David Mol <mol@astron.nl>
Date: Mon, 11 Oct 2021 15:24:45 +0200
Subject: [PATCH] L2SS-358: Added MAC address of dts-lcu:eno2
---
CDB/Darkrai_ConfigDb.json | 64 +++++++++++++++++++--------------------
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git a/CDB/Darkrai_ConfigDb.json b/CDB/Darkrai_ConfigDb.json
index e4327e5e4..401351c0d 100644
--- a/CDB/Darkrai_ConfigDb.json
+++ b/CDB/Darkrai_ConfigDb.json
@@ -109,22 +109,22 @@
"5.0"
],
"FPGA_sst_offload_hdr_eth_destination_mac_RW_default": [
- "6c:2b:59:97:be:dd",
- "6c:2b:59:97:be:dd",
- "6c:2b:59:97:be:dd",
- "6c:2b:59:97:be:dd",
- "6c:2b:59:97:be:dd",
- "6c:2b:59:97:be:dd",
- "6c:2b:59:97:be:dd",
- "6c:2b:59:97:be:dd",
- "6c:2b:59:97:be:dd",
- "6c:2b:59:97:be:dd",
- "6c:2b:59:97:be:dd",
- "6c:2b:59:97:be:dd",
- "6c:2b:59:97:be:dd",
- "6c:2b:59:97:be:dd",
- "6c:2b:59:97:be:dd",
- "6c:2b:59:97:be:dd"
+ "0c:c4:7a:c0:30:f1",
+ "0c:c4:7a:c0:30:f1",
+ "0c:c4:7a:c0:30:f1",
+ "0c:c4:7a:c0:30:f1",
+ "0c:c4:7a:c0:30:f1",
+ "0c:c4:7a:c0:30:f1",
+ "0c:c4:7a:c0:30:f1",
+ "0c:c4:7a:c0:30:f1",
+ "0c:c4:7a:c0:30:f1",
+ "0c:c4:7a:c0:30:f1",
+ "0c:c4:7a:c0:30:f1",
+ "0c:c4:7a:c0:30:f1",
+ "0c:c4:7a:c0:30:f1",
+ "0c:c4:7a:c0:30:f1",
+ "0c:c4:7a:c0:30:f1",
+ "0c:c4:7a:c0:30:f1"
],
"FPGA_sst_offload_hdr_ip_destination_address_RW_default": [
"10.99.250.250",
@@ -164,22 +164,22 @@
"5.0"
],
"FPGA_xst_offload_hdr_eth_destination_mac_RW_default": [
- "6c:2b:59:97:be:dd",
- "6c:2b:59:97:be:dd",
- "6c:2b:59:97:be:dd",
- "6c:2b:59:97:be:dd",
- "6c:2b:59:97:be:dd",
- "6c:2b:59:97:be:dd",
- "6c:2b:59:97:be:dd",
- "6c:2b:59:97:be:dd",
- "6c:2b:59:97:be:dd",
- "6c:2b:59:97:be:dd",
- "6c:2b:59:97:be:dd",
- "6c:2b:59:97:be:dd",
- "6c:2b:59:97:be:dd",
- "6c:2b:59:97:be:dd",
- "6c:2b:59:97:be:dd",
- "6c:2b:59:97:be:dd"
+ "0c:c4:7a:c0:30:f1",
+ "0c:c4:7a:c0:30:f1",
+ "0c:c4:7a:c0:30:f1",
+ "0c:c4:7a:c0:30:f1",
+ "0c:c4:7a:c0:30:f1",
+ "0c:c4:7a:c0:30:f1",
+ "0c:c4:7a:c0:30:f1",
+ "0c:c4:7a:c0:30:f1",
+ "0c:c4:7a:c0:30:f1",
+ "0c:c4:7a:c0:30:f1",
+ "0c:c4:7a:c0:30:f1",
+ "0c:c4:7a:c0:30:f1",
+ "0c:c4:7a:c0:30:f1",
+ "0c:c4:7a:c0:30:f1",
+ "0c:c4:7a:c0:30:f1",
+ "0c:c4:7a:c0:30:f1"
],
"FPGA_xst_offload_hdr_ip_destination_address_RW_default": [
"10.99.250.250",
--
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