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RTSD
HDL
Commits
88f1cb7b4f203435e5be8001f8667ef0f7c31a6b
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Branches
4
L2SDP-LIFT
L2SDP-1113
master
default
protected
HPR-158
4 results
hdl
libraries
technology
ddr
sim_ddr.vhd
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authors
Daniel van der Schuur
schuur
Eric Kooistra
kooistra
Gijs Schoonderbeek
schoonderbeek
Pieter Donker
donker
Steven van der Vlugt
vlugt
5 authors
Dec 14, 2017
Added debug signals for view in Wave window.
· 88f1cb7b
Eric Kooistra
authored
7 years ago
88f1cb7b
Jun 13, 2017
Fixed DDR simulation model.
· a2f529f6
Eric Kooistra
authored
8 years ago
a2f529f6
Corrected sim_ddr model, tb_io_ddr now passes with g_sim_model = true.
· 57034f10
Eric Kooistra
authored
8 years ago
57034f10
Jun 12, 2015
Moved DDR sim model to sim_ddr.vhd.
· 201f8808
Eric Kooistra
authored
10 years ago
201f8808
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Eric Kooistra authored
Eric Kooistra authored
Eric Kooistra authored
Eric Kooistra authored