Commits · 848a1d38852a4ba2bb685eb55cd67b2081f2f59c · RTSD / HDL · GitLab

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Aug 16, 2023
- RTSD-82 : add indent fix from vsg · 848a1d38
  Pieter Donker authored 1 year ago
  
  848a1d38
Jun 14, 2023
- RTSD-93 , master with all style fixes · de83af40
  Pieter Donker authored 2 years ago
  
  de83af40
Apr 18, 2023
- updated tech lib to support ultrascale ram IPs · 56102f69
  Reinier van der Walle authored 2 years ago
  
  56102f69
Apr 11, 2023
- initial commit of ported Block RAM · 32c433b0
  Reinier van der Walle authored 2 years ago
  
  32c433b0
Jan 17, 2020
- New IP version e2sg for unb2c using Arria 10AX115U3F45E2SG · f5e8c817
  Jonathan Hargreaves authored 5 years ago
  
  f5e8c817
Feb 15, 2017
- Modify technology wrappers to include unb2b FPGA Arria 10 version e1sg · e50aab24
  Jonathan Hargreaves authored 8 years ago
  
  e50aab24
Jan 21, 2016
- added the wrappers for ip_arria10_e3sge3 · ed3020b3
  Kenneth Hiemstra authored 9 years ago
  
  ed3020b3
Oct 27, 2014
- Added Arria10 RAM IP from ip_arria10_ram library to the tech_memory library. · 7f5fe56b
  Eric Kooistra authored 10 years ago
  
  7f5fe56b
Jun 13, 2014
- Added component ip_arria10_ram_crw_crw. · 8613c9c1
  Eric Kooistra authored 11 years ago
  
  8613c9c1
Jun 05, 2014
- Rename ip_altera_mf into ip_stratixiv. · 2173d7f2
  Eric Kooistra authored 11 years ago
  
  2173d7f2
May 28, 2014
- Renamed altera_mf prefix into using ip_altera_mf prefix. By using extra 'ip_'... · 4870f6cc
  Eric Kooistra authored 11 years ago
  4870f6cc
May 27, 2014
- Added purpose comment. · 5065c153
  Eric Kooistra authored 11 years ago
  
  5065c153
- Renamed memory_* into tech_memory_*, to more clearly show that the components... · de3d10ca
  Eric Kooistra authored 11 years ago
  de3d10ca
- Ported common RAM, ROM components from... · 901887ef
  Eric Kooistra authored 11 years ago
  901887ef