Commits · 3870acad047ea1775815460d58fc4e1234738c2f · RTSD / HDL · GitLab

Snippets Groups Projects

"SAS/TMSS/frontend/git@git.astron.nl:ro/lofar.git" did not exist on "90f76b7387b9e0eecf4c2f6c3770ebe1975d7c21"

Dec 19, 2014
- Defined c_ctrl_address_w and c_ctlr_data_w. Corrected soft_reset_n<='1'. Renamed record fields. · 3870acad
  Eric Kooistra authored 10 years ago
  
  3870acad
Dec 18, 2014
- Moved ddr3/ VHDL files to ddr/. · 6d479748
  Eric Kooistra authored 10 years ago
  
  6d479748
- Rename g_ddr into g_tech_ddr · bb69952f
  Eric Kooistra authored 10 years ago
  
  bb69952f
- Gather all DDR parameters in one t_c_tech_ddr record · 3c8fc0e5
  Eric Kooistra authored 10 years ago
  
  3c8fc0e5
Dec 17, 2014
- Added DDR3 IP technology wrapper for straticiv using UniPhy. · 880633c0
  Eric Kooistra authored 10 years ago
  
  880633c0