Commits · 37b92e7f2bb44e1f6490ede0a19aac3fcff83d1d · RTSD / HDL

Jan 08, 2015
- Pass on local_init_done from IP via ctlr_miso.done instead of via separate signal ctlr_init_done. · 37b92e7f
  Eric Kooistra authored 10 years ago
  
  37b92e7f
- Define t_mem_ctlr_mosi/miso in common_mem_pkg, to use that instead of the... · b559785d
  Eric Kooistra authored 10 years ago
  
  Define t_mem_ctlr_mosi/miso in common_mem_pkg, to use that instead of the records defined in tech_ddr_pkg. Also remove t_tech_ddr_addr record because it is not needed.
  b559785d
Jan 05, 2015
- Rename ctrl into ctlr. · d61c490e
  Eric Kooistra authored 10 years ago
  
  d61c490e
Dec 22, 2014
- Rename ctrl into ctlr. · 8d6b8949
  Eric Kooistra authored 10 years ago
  
  8d6b8949
Dec 19, 2014
- Defined c_ctrl_address_w and c_ctlr_data_w. Corrected soft_reset_n<='1'. Renamed record fields. · 3870acad
  Eric Kooistra authored 10 years ago
  
  3870acad
Dec 18, 2014
- Moved ddr3/ VHDL files to ddr/. · 6d479748
  Eric Kooistra authored 10 years ago
  
  6d479748
- Rename g_ddr into g_tech_ddr · bb69952f
  Eric Kooistra authored 10 years ago
  
  bb69952f
- Gather all DDR parameters in one t_c_tech_ddr record · 3c8fc0e5
  Eric Kooistra authored 10 years ago
  
  3c8fc0e5
Dec 17, 2014
- Added DDR3 IP technology wrapper for straticiv using UniPhy. · 880633c0
  Eric Kooistra authored 10 years ago
  
  880633c0