Expanded description

applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd

@@ -24,6 +24,12 @@
 -- Description:
 -- . This core consists of two dual clock fifos and glue logic to be used between 
 --   the OpenCL kernel IO channel and dp MM interface to board qsys.
+-- . After a MM write request the waitrequest is immediatly pulled low due to the
+--   fifo being ready.
+-- . After a MM read request the waitrequest is kept high until valid data has 
+--   been received back from the OpenCL kernel through the dual clock fifo. Due 
+--   to the latency of both dual clock fifos, a read request takes at least 14
+--   mm clock cycles (excluding OpenCL kernel process time).
 -- . Details:
 --   . This core was developed for use on the Uniboard2b.
 --   . The implementation of the MM data mapped onto the IO channel is shown below.