From ff42e407ba37bea84011863a9b86b2a52217b417 Mon Sep 17 00:00:00 2001 From: Reinier van der Walle <walle@astron.nl> Date: Tue, 8 Dec 2020 15:15:26 +0100 Subject: [PATCH] Expanded description --- applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd b/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd index e8dd9ac102..ef0bd7d32f 100644 --- a/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd +++ b/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd @@ -24,6 +24,12 @@ -- Description: -- . This core consists of two dual clock fifos and glue logic to be used between -- the OpenCL kernel IO channel and dp MM interface to board qsys. +-- . After a MM write request the waitrequest is immediatly pulled low due to the +-- fifo being ready. +-- . After a MM read request the waitrequest is kept high until valid data has +-- been received back from the OpenCL kernel through the dual clock fifo. Due +-- to the latency of both dual clock fifos, a read request takes at least 14 +-- mm clock cycles (excluding OpenCL kernel process time). -- . Details: -- . This core was developed for use on the Uniboard2b. -- . The implementation of the MM data mapped onto the IO channel is shown below. -- GitLab