Corrected missing signals in sensitivity list.

libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd

@@ -248,7 +248,7 @@ BEGIN
   END GENERATE;
     
   -- Determine the output info and output ctrl using snk_in and r.reg_sosi
-  p_state : PROCESS(r, enable, in_sosi)
+  p_state : PROCESS(r, enable, in_sosi, snk_in)
   BEGIN
     nxt_r <= r;
 

libraries/io/aduh/src/vhdl/lvdsh_dd_phs4.vhd

@@ -771,7 +771,7 @@ BEGIN
   -- Monitor the dp_clk phase alignment
   ------------------------------------------------------------------------------
   
-  p_out_status : PROCESS(r_dp, dp_in_clk_stable, dp_in_clk_detected, fifo_rdusedw)
+  p_out_status : PROCESS(dp_fifo_fill_stable, dp_phs_stable, wb_roundtrip_stable, dp_in_clk_stable, dp_in_clk_detected, fifo_rdusedw, r_dp)
   BEGIN
     -- Debug monitor status
     i_out_status               <= (OTHERS=>'0');