From fcf2c00af59cb31e5ba4b149363991ce9a243349 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Thu, 23 Nov 2017 15:28:58 +0000
Subject: [PATCH] Corrected missing signals in sensitivity list.
---
libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd | 2 +-
libraries/io/aduh/src/vhdl/lvdsh_dd_phs4.vhd | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd b/libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd
index 66538e01ea..f7fb6266ed 100644
--- a/libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd
@@ -248,7 +248,7 @@ BEGIN
END GENERATE;
-- Determine the output info and output ctrl using snk_in and r.reg_sosi
- p_state : PROCESS(r, enable, in_sosi)
+ p_state : PROCESS(r, enable, in_sosi, snk_in)
BEGIN
nxt_r <= r;
diff --git a/libraries/io/aduh/src/vhdl/lvdsh_dd_phs4.vhd b/libraries/io/aduh/src/vhdl/lvdsh_dd_phs4.vhd
index 55886d081c..2769d06c96 100644
--- a/libraries/io/aduh/src/vhdl/lvdsh_dd_phs4.vhd
+++ b/libraries/io/aduh/src/vhdl/lvdsh_dd_phs4.vhd
@@ -771,7 +771,7 @@ BEGIN
-- Monitor the dp_clk phase alignment
------------------------------------------------------------------------------
- p_out_status : PROCESS(r_dp, dp_in_clk_stable, dp_in_clk_detected, fifo_rdusedw)
+ p_out_status : PROCESS(dp_fifo_fill_stable, dp_phs_stable, wb_roundtrip_stable, dp_in_clk_stable, dp_in_clk_detected, fifo_rdusedw, r_dp)
BEGIN
-- Debug monitor status
i_out_status <= (OTHERS=>'0');
--
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