Skip to content
GitLab
Explore
Sign in
Register
Primary navigation
Search or go to…
Project
H
HDL
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Iterations
Wiki
Requirements
Jira
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Locked files
Build
Pipelines
Jobs
Pipeline schedules
Test cases
Artifacts
Deploy
Releases
Container registry
Model registry
Operate
Environments
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Code review analytics
Issue analytics
Insights
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
GitLab community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
RTSD
HDL
Commits
fa59516e
Commit
fa59516e
authored
10 years ago
by
Eric Kooistra
Browse files
Options
Downloads
Patches
Plain Diff
Use tx_clk_arr.
parent
2f63a0ef
Branches
Branches containing commit
No related tags found
No related merge requests found
Changes
1
Show whitespace changes
Inline
Side-by-side
Showing
1 changed file
libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
+17
-12
17 additions, 12 deletions
libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
with
17 additions
and
12 deletions
libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
+
17
−
12
View file @
fa59516e
...
@@ -111,8 +111,9 @@ ARCHITECTURE str OF tr_10GbE IS
...
@@ -111,8 +111,9 @@ ARCHITECTURE str OF tr_10GbE IS
CONSTANT
c_fifo_margin
:
NATURAL
:
=
g_pkt_len
;
CONSTANT
c_fifo_margin
:
NATURAL
:
=
g_pkt_len
;
SIGNAL
tx_clk
:
STD_LOGIC
;
SIGNAL
tr_clk
:
STD_LOGIC
;
SIGNAL
tx_rst
:
STD_LOGIC
;
SIGNAL
tr_rst
:
STD_LOGIC
;
SIGNAL
tx_clk_arr
:
STD_LOGIC_VECTOR
(
g_nof_macs
-1
DOWNTO
0
);
SIGNAL
tx_rst_arr
:
STD_LOGIC_VECTOR
(
g_nof_macs
-1
DOWNTO
0
);
SIGNAL
tx_rst_arr
:
STD_LOGIC_VECTOR
(
g_nof_macs
-1
DOWNTO
0
);
SIGNAL
rx_clk_arr
:
STD_LOGIC_VECTOR
(
g_nof_macs
-1
DOWNTO
0
);
SIGNAL
rx_clk_arr
:
STD_LOGIC_VECTOR
(
g_nof_macs
-1
DOWNTO
0
);
...
@@ -157,8 +158,11 @@ BEGIN
...
@@ -157,8 +158,11 @@ BEGIN
-- Clocks and reset
-- Clocks and reset
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
tx_clk
<=
tr_clk_156
;
-- tx_clk_arr = tr_clk_156 = tr_clk
tx_rst
<=
tr_rst_156
;
tr_clk
<=
tr_clk_156
;
tr_rst
<=
tr_rst_156
;
tx_clk_arr
<=
(
OTHERS
=>
tr_clk_156
);
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- TX FIFO: dp_clk -> tx_clk
-- TX FIFO: dp_clk -> tx_clk
...
@@ -174,7 +178,7 @@ BEGIN
...
@@ -174,7 +178,7 @@ BEGIN
wr_rst
=>
dp_rst
,
wr_rst
=>
dp_rst
,
wr_clk
=>
dp_clk
,
wr_clk
=>
dp_clk
,
rd_rst
=>
tx_rst_arr
(
i
),
rd_rst
=>
tx_rst_arr
(
i
),
rd_clk
=>
tx_clk
,
rd_clk
=>
tx_clk
_arr
(
i
)
,
snk_out
=>
snk_out_arr
(
i
),
snk_out
=>
snk_out_arr
(
i
),
snk_in
=>
snk_in_arr
(
i
),
snk_in
=>
snk_in_arr
(
i
),
...
@@ -198,7 +202,7 @@ BEGIN
...
@@ -198,7 +202,7 @@ BEGIN
)
)
PORT
MAP
(
PORT
MAP
(
rst
=>
tx_rst_arr
(
i
),
rst
=>
tx_rst_arr
(
i
),
clk
=>
tx_clk
,
clk
=>
tx_clk
_arr
(
i
)
,
snk_out
=>
dp_fifo_dc_tx_src_in_arr
(
i
),
snk_out
=>
dp_fifo_dc_tx_src_in_arr
(
i
),
snk_in
=>
dp_fifo_dc_tx_src_out_arr
(
i
),
snk_in
=>
dp_fifo_dc_tx_src_out_arr
(
i
),
...
@@ -218,7 +222,7 @@ BEGIN
...
@@ -218,7 +222,7 @@ BEGIN
dp_fifo_dc_rx_snk_in_arr
<=
dp_fifo_fill_tx_src_out_arr
;
dp_fifo_dc_rx_snk_in_arr
<=
dp_fifo_fill_tx_src_out_arr
;
rx_rst_arr
<=
tx_rst_arr
;
rx_rst_arr
<=
tx_rst_arr
;
rx_clk_arr
<=
(
OTHERS
=>
tx_clk
)
;
rx_clk_arr
<=
tx_clk
_arr
;
END
GENERATE
;
END
GENERATE
;
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
...
@@ -248,7 +252,7 @@ BEGIN
...
@@ -248,7 +252,7 @@ BEGIN
csr_miso
=>
reg_mac_miso_arr
(
i
),
csr_miso
=>
reg_mac_miso_arr
(
i
),
-- ST
-- ST
tx_clk_156
=>
tx_clk
,
-- 156.25 MHz local reference
tx_clk_156
=>
tx_clk
_arr
(
i
),
-- 156.25 MHz local reference
tx_rst
=>
tx_rst_arr
(
i
),
tx_rst
=>
tx_rst_arr
(
i
),
tx_snk_in
=>
mac_10g_snk_in_arr
(
i
),
-- 64 bit data
tx_snk_in
=>
mac_10g_snk_in_arr
(
i
),
-- 64 bit data
tx_snk_out
=>
mac_10g_snk_out_arr
(
i
),
tx_snk_out
=>
mac_10g_snk_out_arr
(
i
),
...
@@ -292,8 +296,8 @@ BEGIN
...
@@ -292,8 +296,8 @@ BEGIN
)
)
PORT
MAP
(
PORT
MAP
(
-- Transceiver PLL reference clock
-- Transceiver PLL reference clock
tr_clk
=>
t
x
_clk
,
-- = tr_clk_156
tr_clk
=>
t
r
_clk
,
-- = tr_clk_156
= tx_clk_arr
tr_rst
=>
t
x
_rst
,
-- = tr_rst_156
tr_rst
=>
t
r
_rst
,
-- = tr_rst_156
-- Calibration & reconfig clock
-- Calibration & reconfig clock
cal_rec_clk
=>
cal_rec_clk
,
cal_rec_clk
=>
cal_rec_clk
,
...
@@ -303,11 +307,12 @@ BEGIN
...
@@ -303,11 +307,12 @@ BEGIN
mm_rst
=>
mm_rst
,
mm_rst
=>
mm_rst
,
-- Streaming TX interfaces
-- Streaming TX interfaces
tx_clk
=>
tx_clk
,
tx_clk
_arr
=>
tx_clk
_arr
,
tx_rst_arr
=>
tx_rst_arr
,
tx_rst_arr
=>
tx_rst_arr
,
-- Streaming RX interfaces
-- Streaming RX interfaces
rx_clk_arr
=>
rx_clk_arr
,
rx_clk_arr_out
=>
rx_clk_arr
,
rx_clk_arr_in
=>
rx_clk_arr
,
rx_rst_arr
=>
rx_rst_arr
,
rx_rst_arr
=>
rx_rst_arr
,
-- Direct XGMII interface
-- Direct XGMII interface
...
...
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment