From fa59516e9ce32280f728c7fc33dc511448bdd537 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Fri, 5 Dec 2014 09:13:27 +0000
Subject: [PATCH] Use tx_clk_arr.
---
libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd | 29 ++++++++++++---------
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
index b622e9867d..fb9412af4d 100644
--- a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
+++ b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
@@ -111,8 +111,9 @@ ARCHITECTURE str OF tr_10GbE IS
CONSTANT c_fifo_margin : NATURAL := g_pkt_len;
- SIGNAL tx_clk : STD_LOGIC;
- SIGNAL tx_rst : STD_LOGIC;
+ SIGNAL tr_clk : STD_LOGIC;
+ SIGNAL tr_rst : STD_LOGIC;
+ SIGNAL tx_clk_arr : STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
SIGNAL tx_rst_arr : STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
SIGNAL rx_clk_arr : STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
@@ -157,9 +158,12 @@ BEGIN
-- Clocks and reset
---------------------------------------------------------------------------------------
- tx_clk <= tr_clk_156;
- tx_rst <= tr_rst_156;
+ -- tx_clk_arr = tr_clk_156 = tr_clk
+ tr_clk <= tr_clk_156;
+ tr_rst <= tr_rst_156;
+ tx_clk_arr <= (OTHERS=>tr_clk_156);
+
---------------------------------------------------------------------------------------
-- TX FIFO: dp_clk -> tx_clk
---------------------------------------------------------------------------------------
@@ -174,7 +178,7 @@ BEGIN
wr_rst => dp_rst,
wr_clk => dp_clk,
rd_rst => tx_rst_arr(i),
- rd_clk => tx_clk,
+ rd_clk => tx_clk_arr(i),
snk_out => snk_out_arr(i),
snk_in => snk_in_arr(i),
@@ -198,7 +202,7 @@ BEGIN
)
PORT MAP (
rst => tx_rst_arr(i),
- clk => tx_clk,
+ clk => tx_clk_arr(i),
snk_out => dp_fifo_dc_tx_src_in_arr(i),
snk_in => dp_fifo_dc_tx_src_out_arr(i),
@@ -218,7 +222,7 @@ BEGIN
dp_fifo_dc_rx_snk_in_arr <= dp_fifo_fill_tx_src_out_arr;
rx_rst_arr <= tx_rst_arr;
- rx_clk_arr <= (OTHERS=>tx_clk);
+ rx_clk_arr <= tx_clk_arr;
END GENERATE;
---------------------------------------------------------------------------------------
@@ -248,7 +252,7 @@ BEGIN
csr_miso => reg_mac_miso_arr(i),
-- ST
- tx_clk_156 => tx_clk, -- 156.25 MHz local reference
+ tx_clk_156 => tx_clk_arr(i), -- 156.25 MHz local reference
tx_rst => tx_rst_arr(i),
tx_snk_in => mac_10g_snk_in_arr(i), -- 64 bit data
tx_snk_out => mac_10g_snk_out_arr(i),
@@ -292,8 +296,8 @@ BEGIN
)
PORT MAP (
-- Transceiver PLL reference clock
- tr_clk => tx_clk, -- = tr_clk_156
- tr_rst => tx_rst, -- = tr_rst_156
+ tr_clk => tr_clk, -- = tr_clk_156 = tx_clk_arr
+ tr_rst => tr_rst, -- = tr_rst_156
-- Calibration & reconfig clock
cal_rec_clk => cal_rec_clk,
@@ -303,11 +307,12 @@ BEGIN
mm_rst => mm_rst,
-- Streaming TX interfaces
- tx_clk => tx_clk,
+ tx_clk_arr => tx_clk_arr,
tx_rst_arr => tx_rst_arr,
-- Streaming RX interfaces
- rx_clk_arr => rx_clk_arr,
+ rx_clk_arr_out => rx_clk_arr,
+ rx_clk_arr_in => rx_clk_arr,
rx_rst_arr => rx_rst_arr,
-- Direct XGMII interface
--
GitLab