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Commit 2f63a0ef authored by Eric Kooistra's avatar Eric Kooistra
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Added *_ready_arr ports and output txc_rx_channelaligned_arr in tx clock... 

Added *_ready_arr ports and output txc_rx_channelaligned_arr in tx clock domain. Defined rx_clk_arr_out/in to avoid delta-delay.
parent 07ed1746
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libraries/io/tr_xaui/src/vhdl/mms_tr_xaui.vhd
+ 13
− 16
View file @ 2f63a0ef
...@@ -57,13 +57,14 @@ ENTITY mms_tr_xaui IS ...@@ -57,13 +57,14 @@ ENTITY mms_tr_xaui IS
mdio_miso_arr : OUT t_mem_miso_arr(g_nof_xaui-1 DOWNTO 0); mdio_miso_arr : OUT t_mem_miso_arr(g_nof_xaui-1 DOWNTO 0);
-- Streaming TX interfaces -- Streaming TX interfaces
tx_clk : IN STD_LOGIC; -- 156.25 MHz, externally connect tr_clk also to tx_clk tx_clk_arr : IN STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); -- 156.25 MHz, externally connect tr_clk to tx_clk_arr or connect rx_clk_arr to tx_clk_arr
tx_rst_arr : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); tx_rst_arr : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
tx_sosi_arr : IN t_dp_sosi_arr(g_nof_xaui-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst); tx_sosi_arr : IN t_dp_sosi_arr(g_nof_xaui-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst);
tx_siso_arr : OUT t_dp_siso_arr(g_nof_xaui-1 DOWNTO 0); tx_siso_arr : OUT t_dp_siso_arr(g_nof_xaui-1 DOWNTO 0);
-- Streaming RX interfaces -- Streaming RX interfaces
rx_clk_arr : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); rx_clk_arr_out : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); -- recovered clock per XAUI
rx_clk_arr_in : IN STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); -- externally connect to rx_clk_arr_out to avoid clock delta-delay
rx_rst_arr : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); rx_rst_arr : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
rx_sosi_arr : OUT t_dp_sosi_arr(g_nof_xaui-1 DOWNTO 0); rx_sosi_arr : OUT t_dp_sosi_arr(g_nof_xaui-1 DOWNTO 0);
rx_siso_arr : IN t_dp_siso_arr(g_nof_xaui-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rst); rx_siso_arr : IN t_dp_siso_arr(g_nof_xaui-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rst);
...@@ -93,9 +94,7 @@ ARCHITECTURE wrap OF mms_tr_xaui IS ...@@ -93,9 +94,7 @@ ARCHITECTURE wrap OF mms_tr_xaui IS
TYPE t_select_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_nof_select_w-1 DOWNTO 0); TYPE t_select_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_nof_select_w-1 DOWNTO 0);
SIGNAL tx_clk_arr : STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
SIGNAL i_tx_rst_arr : STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); SIGNAL i_tx_rst_arr : STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
SIGNAL i_rx_clk_arr : STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
SIGNAL i_rx_rst_arr : STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); SIGNAL i_rx_rst_arr : STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
SIGNAL diagnostics_rx_sosi_arr : t_dp_sosi_arr(g_nof_xaui-1 DOWNTO 0); SIGNAL diagnostics_rx_sosi_arr : t_dp_sosi_arr(g_nof_xaui-1 DOWNTO 0);
...@@ -127,10 +126,7 @@ ARCHITECTURE wrap OF mms_tr_xaui IS ...@@ -127,10 +126,7 @@ ARCHITECTURE wrap OF mms_tr_xaui IS
BEGIN BEGIN
tx_clk_arr <= (OTHERS=>tx_clk);
tx_rst_arr <= i_tx_rst_arr; tx_rst_arr <= i_tx_rst_arr;
rx_clk_arr <= i_rx_clk_arr;
rx_rst_arr <= i_rx_rst_arr; rx_rst_arr <= i_rx_rst_arr;
u_tr_xaui: ENTITY work.tr_xaui u_tr_xaui: ENTITY work.tr_xaui
...@@ -155,12 +151,13 @@ BEGIN ...@@ -155,12 +151,13 @@ BEGIN
mdio_miso_arr => mdio_miso_arr, mdio_miso_arr => mdio_miso_arr,
--Parallel data --Parallel data
tx_clk => tx_clk, tx_clk_arr => tx_clk_arr,
tx_rst_arr => i_tx_rst_arr, tx_rst_arr => i_tx_rst_arr,
tx_sosi_arr => mux_out_sosi_arr, tx_sosi_arr => mux_out_sosi_arr,
tx_siso_arr => mux_out_siso_arr, tx_siso_arr => mux_out_siso_arr,
rx_clk_arr => i_rx_clk_arr, rx_clk_arr_out => rx_clk_arr_out,
rx_clk_arr_in => rx_clk_arr_in,
rx_rst_arr => i_rx_rst_arr, rx_rst_arr => i_rx_rst_arr,
rx_sosi_arr => demux_in_sosi_arr, rx_sosi_arr => demux_in_sosi_arr,
rx_siso_arr => demux_in_siso_arr, rx_siso_arr => demux_in_siso_arr,
...@@ -190,7 +187,7 @@ BEGIN ...@@ -190,7 +187,7 @@ BEGIN
src_clk => tx_clk_arr, src_clk => tx_clk_arr,
snk_rst => i_rx_rst_arr, snk_rst => i_rx_rst_arr,
snk_clk => i_rx_clk_arr, snk_clk => rx_clk_arr_in,
mm_mosi => diagnostics_mosi, mm_mosi => diagnostics_mosi,
mm_miso => diagnostics_miso, mm_miso => diagnostics_miso,
...@@ -241,7 +238,7 @@ BEGIN ...@@ -241,7 +238,7 @@ BEGIN
) )
PORT MAP ( PORT MAP (
rst => i_tx_rst_arr(i), rst => i_tx_rst_arr(i),
clk => tx_clk, clk => tx_clk_arr(i),
sel_ctrl => TO_UINT(mux_select_arr(i)), sel_ctrl => TO_UINT(mux_select_arr(i)),
...@@ -253,11 +250,11 @@ BEGIN ...@@ -253,11 +250,11 @@ BEGIN
src_out => mux_out_sosi_arr(i) src_out => mux_out_sosi_arr(i)
); );
p_tx_clk : PROCESS(i_tx_rst_arr, tx_clk) p_tx_clk : PROCESS(i_tx_rst_arr, tx_clk_arr)
BEGIN BEGIN
IF i_tx_rst_arr(i)='1' THEN IF i_tx_rst_arr(i)='1' THEN
mux_select_arr(i) <= (OTHERS=>'0'); mux_select_arr(i) <= (OTHERS=>'0');
ELSIF rising_edge(tx_clk) THEN ELSIF rising_edge(tx_clk_arr(i)) THEN
mux_select_arr(i) <= nxt_mux_select_arr(i); mux_select_arr(i) <= nxt_mux_select_arr(i);
END IF; END IF;
END PROCESS; END PROCESS;
...@@ -272,7 +269,7 @@ BEGIN ...@@ -272,7 +269,7 @@ BEGIN
) )
PORT MAP ( PORT MAP (
rst => i_rx_rst_arr(i), rst => i_rx_rst_arr(i),
clk => i_rx_clk_arr(i), clk => rx_clk_arr_in(i),
sel_ctrl => TO_UINT(demux_select_arr(i)), sel_ctrl => TO_UINT(demux_select_arr(i)),
...@@ -284,11 +281,11 @@ BEGIN ...@@ -284,11 +281,11 @@ BEGIN
src_out_arr => demux_out_sosi_2arr(i) src_out_arr => demux_out_sosi_2arr(i)
); );
p_rx_clk_arr : PROCESS(i_rx_rst_arr, i_rx_clk_arr) p_rx_clk_arr : PROCESS(i_rx_rst_arr, rx_clk_arr_in)
BEGIN BEGIN
IF i_rx_rst_arr(i)='1' THEN IF i_rx_rst_arr(i)='1' THEN
demux_select_arr(i) <= (OTHERS=>'0'); demux_select_arr(i) <= (OTHERS=>'0');
ELSIF rising_edge(i_rx_clk_arr(i)) THEN ELSIF rising_edge(rx_clk_arr_in(i)) THEN
demux_select_arr(i) <= nxt_demux_select_arr(i); demux_select_arr(i) <= nxt_demux_select_arr(i);
END IF; END IF;
END PROCESS; END PROCESS;
......
libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd
+ 42
− 35
View file @ 2f63a0ef
...@@ -60,13 +60,14 @@ ENTITY tr_xaui IS ...@@ -60,13 +60,14 @@ ENTITY tr_xaui IS
mdio_miso_arr : OUT t_mem_miso_arr(g_nof_xaui-1 DOWNTO 0); mdio_miso_arr : OUT t_mem_miso_arr(g_nof_xaui-1 DOWNTO 0);
-- Streaming TX interfaces -- Streaming TX interfaces
tx_clk : IN STD_LOGIC; -- 156.25 MHz, externally connect tr_clk also to tx_clk tx_clk_arr : IN STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); -- 156.25 MHz, externally connect tr_clk to tx_clk_arr or connect rx_clk_arr to tx_clk_arr
tx_rst_arr : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); -- tx_rst release depends on XAUI ready tx_rst_arr : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); -- tx_rst release depends on XAUI ready
tx_sosi_arr : IN t_dp_sosi_arr(g_nof_xaui-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst); tx_sosi_arr : IN t_dp_sosi_arr(g_nof_xaui-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst);
tx_siso_arr : OUT t_dp_siso_arr(g_nof_xaui-1 DOWNTO 0); tx_siso_arr : OUT t_dp_siso_arr(g_nof_xaui-1 DOWNTO 0);
-- Streaming RX interfaces -- Streaming RX interfaces
rx_clk_arr : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); -- recovered clock per XAUI rx_clk_arr_out : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); -- recovered clock per XAUI
rx_clk_arr_in : IN STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); -- externally connect to rx_clk_arr_out to avoid clock delta-delay
rx_rst_arr : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); rx_rst_arr : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
rx_sosi_arr : OUT t_dp_sosi_arr(g_nof_xaui-1 DOWNTO 0); rx_sosi_arr : OUT t_dp_sosi_arr(g_nof_xaui-1 DOWNTO 0);
rx_siso_arr : IN t_dp_siso_arr(g_nof_xaui-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rst); rx_siso_arr : IN t_dp_siso_arr(g_nof_xaui-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rst);
...@@ -91,7 +92,6 @@ END tr_xaui; ...@@ -91,7 +92,6 @@ END tr_xaui;
ARCHITECTURE str OF tr_xaui IS ARCHITECTURE str OF tr_xaui IS
SIGNAL i_tx_rst_arr : STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); SIGNAL i_tx_rst_arr : STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
SIGNAL i_rx_clk_arr : STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
SIGNAL i_rx_rst_arr : STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); SIGNAL i_rx_rst_arr : STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
--XGMII data and control combined: --XGMII data and control combined:
...@@ -106,7 +106,9 @@ ARCHITECTURE str OF tr_xaui IS ...@@ -106,7 +106,9 @@ ARCHITECTURE str OF tr_xaui IS
SIGNAL xgmii_tx_d_arr : t_xgmii_d_arr(g_nof_xaui-1 DOWNTO 0); SIGNAL xgmii_tx_d_arr : t_xgmii_d_arr(g_nof_xaui-1 DOWNTO 0);
SIGNAL xgmii_rx_d_arr : t_xgmii_d_arr(g_nof_xaui-1 DOWNTO 0); SIGNAL xgmii_rx_d_arr : t_xgmii_d_arr(g_nof_xaui-1 DOWNTO 0);
SIGNAL a_rx_channelaligned_arr : STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); SIGNAL txc_tx_ready_arr : STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
SIGNAL rxc_rx_ready_arr : STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
SIGNAL txc_rx_channelaligned_arr : STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
SIGNAL txc_rx_channelaligned_dly_arr : STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); SIGNAL txc_rx_channelaligned_dly_arr : STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
SIGNAL tx_framer_siso_arr : t_dp_siso_arr(g_nof_xaui-1 DOWNTO 0); SIGNAL tx_framer_siso_arr : t_dp_siso_arr(g_nof_xaui-1 DOWNTO 0);
...@@ -115,12 +117,15 @@ ARCHITECTURE str OF tr_xaui IS ...@@ -115,12 +117,15 @@ ARCHITECTURE str OF tr_xaui IS
BEGIN BEGIN
tx_rst_arr <= i_tx_rst_arr; tx_rst_arr <= i_tx_rst_arr;
rx_clk_arr <= i_rx_clk_arr;
rx_rst_arr <= i_rx_rst_arr; rx_rst_arr <= i_rx_rst_arr;
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- XAUI PHY -- XAUI PHY
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
i_tx_rst_arr <= NOT txc_tx_ready_arr;
i_rx_rst_arr <= NOT rxc_rx_ready_arr;
gen_phy: IF g_sim = FALSE OR g_sim_level = 0 GENERATE gen_phy: IF g_sim = FALSE OR g_sim_level = 0 GENERATE
-- Altera's IP -- Altera's IP
u_tech_xaui : ENTITY tech_xaui_lib.tech_xaui u_tech_xaui : ENTITY tech_xaui_lib.tech_xaui
...@@ -139,18 +144,19 @@ BEGIN ...@@ -139,18 +144,19 @@ BEGIN
xaui_mosi => xaui_mosi, xaui_mosi => xaui_mosi,
xaui_miso => xaui_miso, xaui_miso => xaui_miso,
tx_clk => tx_clk, tx_clk_arr => tx_clk_arr,
tx_rst_arr => i_tx_rst_arr, rx_clk_arr_out => rx_clk_arr_out,
rx_clk_arr => i_rx_clk_arr, rx_clk_arr_in => rx_clk_arr_in,
rx_rst_arr => i_rx_rst_arr,
a_rx_channelaligned_arr => a_rx_channelaligned_arr, txc_tx_ready_arr => txc_tx_ready_arr,
rxc_rx_ready_arr => rxc_rx_ready_arr,
txc_rx_channelaligned_arr => txc_rx_channelaligned_arr,
xgmii_tx_dc_arr => xgmii_tx_dc_in_arr, xgmii_tx_dc_arr => xgmii_tx_dc_in_arr,
xgmii_rx_dc_arr => xgmii_rx_dc_out_arr, xgmii_rx_dc_arr => xgmii_rx_dc_out_arr,
xaui_rx_arr => xaui_rx_arr, xaui_tx_arr => xaui_tx_arr,
xaui_tx_arr => xaui_tx_arr xaui_rx_arr => xaui_rx_arr
); );
END GENERATE; END GENERATE;
...@@ -164,18 +170,19 @@ BEGIN ...@@ -164,18 +170,19 @@ BEGIN
tr_clk => tr_clk, tr_clk => tr_clk,
tr_rst => tr_rst, tr_rst => tr_rst,
tx_clk => tx_clk, tx_clk_arr => tx_clk_arr,
tx_rst_arr => i_tx_rst_arr, rx_clk_arr_out => rx_clk_arr_out,
rx_clk_arr => i_rx_clk_arr, rx_clk_arr_in => rx_clk_arr_in,
rx_rst_arr => i_rx_rst_arr,
a_rx_channelaligned_arr => a_rx_channelaligned_arr, txc_tx_ready_arr => txc_tx_ready_arr,
rxc_rx_ready_arr => rxc_rx_ready_arr,
txc_rx_channelaligned_arr => txc_rx_channelaligned_arr,
xgmii_tx_dc_arr => xgmii_tx_dc_in_arr, xgmii_tx_dc_arr => xgmii_tx_dc_in_arr,
xgmii_rx_dc_arr => xgmii_rx_dc_out_arr, xgmii_rx_dc_arr => xgmii_rx_dc_out_arr,
xaui_rx_arr => xaui_rx_arr, xaui_tx_arr => xaui_tx_arr,
xaui_tx_arr => xaui_tx_arr xaui_rx_arr => xaui_rx_arr
); );
END GENERATE; END GENERATE;
...@@ -202,7 +209,7 @@ BEGIN ...@@ -202,7 +209,7 @@ BEGIN
) )
PORT MAP ( PORT MAP (
tx_rst => i_tx_rst_arr(i), tx_rst => i_tx_rst_arr(i),
tx_clk => tx_clk, tx_clk => tx_clk_arr(i),
snk_out => tx_framer_siso_arr(i), snk_out => tx_framer_siso_arr(i),
snk_in => tx_framer_sosi_arr(i), snk_in => tx_framer_sosi_arr(i),
...@@ -214,7 +221,7 @@ BEGIN ...@@ -214,7 +221,7 @@ BEGIN
u_rx_deframer : ENTITY work.tr_xaui_deframer u_rx_deframer : ENTITY work.tr_xaui_deframer
PORT MAP ( PORT MAP (
rx_rst => i_rx_rst_arr(i), rx_rst => i_rx_rst_arr(i),
rx_clk => i_rx_clk_arr(i), rx_clk => rx_clk_arr_in(i),
xgmii_rx_d => xgmii_rx_d_arr(i), xgmii_rx_d => xgmii_rx_d_arr(i),
xgmii_rx_c => xgmii_rx_c_arr(i), xgmii_rx_c => xgmii_rx_c_arr(i),
...@@ -228,9 +235,9 @@ BEGIN ...@@ -228,9 +235,9 @@ BEGIN
) )
PORT MAP( PORT MAP(
tx_rst => i_tx_rst_arr(i), tx_rst => i_tx_rst_arr(i),
tx_clk => tx_clk, tx_clk => tx_clk_arr(i),
a_rx_channelaligned => a_rx_channelaligned_arr(i), a_rx_channelaligned => txc_rx_channelaligned_arr(i),
txc_rx_channelaligned_dly => txc_rx_channelaligned_dly_arr(i) txc_rx_channelaligned_dly => txc_rx_channelaligned_dly_arr(i)
); );
END GENERATE; -- g_nof_xaui END GENERATE; -- g_nof_xaui
......
libraries/io/tr_xaui/tb/vhdl/sim_xaui.vhd
+ 23
− 33
View file @ 2f63a0ef
...@@ -34,12 +34,14 @@ ENTITY sim_xaui IS ...@@ -34,12 +34,14 @@ ENTITY sim_xaui IS
tr_clk : IN STD_LOGIC; -- 156.25 MHz tr_clk : IN STD_LOGIC; -- 156.25 MHz
tr_rst : IN STD_LOGIC; tr_rst : IN STD_LOGIC;
tx_clk : IN STD_LOGIC; -- 156.25 MHz, tx_clk = tr_clk, externally connect tr_clk also to tx_clk tx_clk_arr : IN STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); -- 156.25 MHz, externally connect tr_clk to tx_clk_arr or connect rx_clk_arr to tx_clk_arr
tx_rst_arr : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); rx_clk_arr_out : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); -- recovered clock per XAUI, rx_clk_arr = tx_clk_arr in this model
rx_clk_arr : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); -- rx_clk_arr = tx_clk in this model rx_clk_arr_in : IN STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); -- externally connect to rx_clk_arr_out to avoid clock delta-delay
rx_rst_arr : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
a_rx_channelaligned_arr : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); txc_tx_ready_arr : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
rxc_rx_ready_arr : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
txc_rx_channelaligned_arr : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
xgmii_tx_dc_arr : IN t_xgmii_dc_arr(g_nof_xaui-1 DOWNTO 0); xgmii_tx_dc_arr : IN t_xgmii_dc_arr(g_nof_xaui-1 DOWNTO 0);
xgmii_rx_dc_arr : OUT t_xgmii_dc_arr(g_nof_xaui-1 DOWNTO 0); xgmii_rx_dc_arr : OUT t_xgmii_dc_arr(g_nof_xaui-1 DOWNTO 0);
...@@ -56,12 +58,6 @@ ARCHITECTURE wrap OF sim_xaui IS ...@@ -56,12 +58,6 @@ ARCHITECTURE wrap OF sim_xaui IS
CONSTANT c_xaui_serdes_ctrl_w : NATURAL := c_xaui_serdes_data_w/c_byte_w; CONSTANT c_xaui_serdes_ctrl_w : NATURAL := c_xaui_serdes_data_w/c_byte_w;
CONSTANT c_xaui_serdes_line_rate : NATURAL := 3125; CONSTANT c_xaui_serdes_line_rate : NATURAL := 3125;
-- Phy ready
SIGNAL txc_tx_ready_arr : STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
SIGNAL i_rx_clk_arr : STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
SIGNAL rxc_rx_ready_arr : STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
-- XGMII control bits (one for each XGMII lane): -- XGMII control bits (one for each XGMII lane):
SIGNAL xgmii_tx_c_arr : t_xgmii_c_arr(g_nof_xaui-1 DOWNTO 0); SIGNAL xgmii_tx_c_arr : t_xgmii_c_arr(g_nof_xaui-1 DOWNTO 0);
SIGNAL xgmii_rx_c_arr : t_xgmii_c_arr(g_nof_xaui-1 DOWNTO 0); SIGNAL xgmii_rx_c_arr : t_xgmii_c_arr(g_nof_xaui-1 DOWNTO 0);
...@@ -72,7 +68,8 @@ ARCHITECTURE wrap OF sim_xaui IS ...@@ -72,7 +68,8 @@ ARCHITECTURE wrap OF sim_xaui IS
BEGIN BEGIN
rx_clk_arr <= i_rx_clk_arr; -- Model rx_clk = tx_clk = tr_clk
rx_clk_arr_out <= tx_clk_arr;
gen_nof_xaui : FOR i IN g_nof_xaui-1 DOWNTO 0 GENERATE gen_nof_xaui : FOR i IN g_nof_xaui-1 DOWNTO 0 GENERATE
...@@ -82,47 +79,40 @@ BEGIN ...@@ -82,47 +79,40 @@ BEGIN
xgmii_rx_dc_arr(i) <= func_xgmii_dc(xgmii_rx_d_arr(i), xgmii_rx_c_arr(i)); xgmii_rx_dc_arr(i) <= func_xgmii_dc(xgmii_rx_d_arr(i), xgmii_rx_c_arr(i));
-- Model rx_clk = tx_clk = tr_clk -- Model tx_ready
i_rx_clk_arr(i) <= tx_clk;
-- Release tx resets when tx_ready
u_areset_tx_rdy : ENTITY common_lib.common_areset u_areset_tx_rdy : ENTITY common_lib.common_areset
GENERIC MAP( GENERIC MAP(
g_rst_level => '0', g_rst_level => '0',
g_delay_len => 40 g_delay_len => 40
) )
PORT MAP( PORT MAP(
clk => tx_clk, clk => tx_clk_arr(i),
in_rst => '0', in_rst => '0',
out_rst => txc_tx_ready_arr(i) out_rst => txc_tx_ready_arr(i)
); );
tx_rst_arr(i) <= NOT txc_tx_ready_arr(i); -- Model rx_ready
-- Release rx resets when rx_ready
u_areset_rx_rdy : ENTITY common_lib.common_areset u_areset_rx_rdy : ENTITY common_lib.common_areset
GENERIC MAP( GENERIC MAP(
g_rst_level => '0', g_rst_level => '0',
g_delay_len => 80 g_delay_len => 80
) )
PORT MAP( PORT MAP(
clk => i_rx_clk_arr(i), clk => rx_clk_arr_in(i),
in_rst => '0', in_rst => '0',
out_rst => rxc_rx_ready_arr(i) out_rst => rxc_rx_ready_arr(i)
); );
rx_rst_arr(i) <= NOT rxc_rx_ready_arr(i); -- Model rx_channelaligned
-- Signal Rx aligned after rx_ready
u_areset_rx_channelaligned : ENTITY common_lib.common_areset u_areset_rx_channelaligned : ENTITY common_lib.common_areset
GENERIC MAP( GENERIC MAP(
g_rst_level => '0', g_rst_level => '0',
g_delay_len => 120 g_delay_len => 120
) )
PORT MAP( PORT MAP(
clk => i_rx_clk_arr(i), clk => tx_clk_arr(i),
in_rst => '0', in_rst => '0',
out_rst => a_rx_channelaligned_arr(i) out_rst => txc_rx_channelaligned_arr(i)
); );
gen_serdes: FOR j IN c_nof_xaui_lanes-1 DOWNTO 0 GENERATE gen_serdes: FOR j IN c_nof_xaui_lanes-1 DOWNTO 0 GENERATE
......
libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui.vhd
+ 11
− 7
View file @ 2f63a0ef
...@@ -50,15 +50,17 @@ ARCHITECTURE str of tb_tr_xaui IS ...@@ -50,15 +50,17 @@ ARCHITECTURE str of tb_tr_xaui IS
CONSTANT c_sim : BOOLEAN := TRUE; -- tr_xaui_align_dly has time delay ~ 1 sec, so not suitable for simulation CONSTANT c_sim : BOOLEAN := TRUE; -- tr_xaui_align_dly has time delay ~ 1 sec, so not suitable for simulation
CONSTANT c_nof_streams : NATURAL := 1;
CONSTANT c_xgmii_data_w : NATURAL := 64;
CONSTANT c_nof_lanes : NATURAL := 4;
CONSTANT tr_clk_period : TIME := 6.4 ns; -- 156.25 MHz CONSTANT tr_clk_period : TIME := 6.4 ns; -- 156.25 MHz
CONSTANT tx_clk_period : TIME := 6.4 ns; -- 156.25 MHz CONSTANT tx_clk_period : TIME := 6.4 ns; -- 156.25 MHz
CONSTANT mm_clk_period : TIME := 25 ns; -- 40 MHz CONSTANT mm_clk_period : TIME := 25 ns; -- 40 MHz
CONSTANT cal_rec_clk_period : TIME := 25 ns; -- 40 MHz CONSTANT cal_rec_clk_period : TIME := 25 ns; -- 40 MHz
CONSTANT phy_delay : TIME := sel_a_b(g_sim_level>0, tr_clk_period*1, 1 ns); -- the sim_xaui only works without unit PHY delays
CONSTANT c_nof_streams : NATURAL := 1;
CONSTANT c_xgmii_data_w : NATURAL := 64;
CONSTANT c_nof_lanes : NATURAL := 4;
SIGNAL tr_clk : STD_LOGIC := '1'; SIGNAL tr_clk : STD_LOGIC := '1';
SIGNAL tr_rst : STD_LOGIC; SIGNAL tr_rst : STD_LOGIC;
...@@ -95,6 +97,7 @@ BEGIN ...@@ -95,6 +97,7 @@ BEGIN
-- Duration -- Duration
p_tb_end : PROCESS p_tb_end : PROCESS
BEGIN BEGIN
tb_end <= '0';
WAIT FOR 7 us; WAIT FOR 7 us;
-- Stop the simulation -- Stop the simulation
...@@ -125,7 +128,7 @@ BEGIN ...@@ -125,7 +128,7 @@ BEGIN
END PROCESS; END PROCESS;
-- Loopback: -- Loopback:
xaui_rx_arr <= xaui_tx_arr; xaui_rx_arr <= TRANSPORT xaui_tx_arr AFTER phy_delay;
u_tr_xaui: ENTITY WORK.tr_xaui u_tr_xaui: ENTITY WORK.tr_xaui
GENERIC MAP ( GENERIC MAP (
...@@ -144,12 +147,13 @@ BEGIN ...@@ -144,12 +147,13 @@ BEGIN
mm_rst => mm_rst, mm_rst => mm_rst,
--Parallel data --Parallel data
tx_clk => tx_clk, tx_clk_arr(0) => tx_clk,
tx_rst_arr(0) => tx_rst, tx_rst_arr(0) => tx_rst,
tx_sosi_arr => tx_sosi_arr, tx_sosi_arr => tx_sosi_arr,
tx_siso_arr => tx_siso_arr, tx_siso_arr => tx_siso_arr,
rx_clk_arr(0) => rx_clk, rx_clk_arr_out(0) => rx_clk,
rx_clk_arr_in(0) => rx_clk,
rx_rst_arr(0) => rx_rst, rx_rst_arr(0) => rx_rst,
rx_sosi_arr => rx_sosi_arr, rx_sosi_arr => rx_sosi_arr,
rx_siso_arr => rx_siso_arr, rx_siso_arr => rx_siso_arr,
......
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