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Commit f8616185 authored by Eric Kooistra's avatar Eric Kooistra
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Added verification of TO_UVEC() and TO_UINT() for REALs.

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libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd
+ 45
− 13
View file @ f8616185
...@@ -38,7 +38,8 @@ ...@@ -38,7 +38,8 @@
-- [1] https://support.astron.nl/confluence/display/L2M/L3+SDP+Decision%3A+Definition+of+fixed+point+numbers -- [1] https://support.astron.nl/confluence/display/L2M/L3+SDP+Decision%3A+Definition+of+fixed+point+numbers
-- --
-- Usage: -- Usage:
-- > as 5, observe signals with radix decimal -- > as 5, observe signed signals with radix decimal, and observe unsigned
-- signals with radix unsigend.
-- > run -all -- > run -all
LIBRARY IEEE; LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_1164.ALL;
...@@ -64,7 +65,9 @@ ARCHITECTURE tb OF tb_common_to_sreal IS ...@@ -64,7 +65,9 @@ ARCHITECTURE tb OF tb_common_to_sreal IS
SIGNAL a_real : REAL := 0.0; SIGNAL a_real : REAL := 0.0;
SIGNAL a_sint : INTEGER := 0; SIGNAL a_sint : INTEGER := 0;
SIGNAL a_slv : STD_LOGIC_VECTOR(c_width-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL a_uint : NATURAL := 0;
SIGNAL a_slv : STD_LOGIC_VECTOR(c_width-1 DOWNTO 0) := (OTHERS => '0'); -- signed slv
SIGNAL a_ulv : STD_LOGIC_VECTOR(c_width-1 DOWNTO 0) := (OTHERS => '0'); -- unsigned slv
SIGNAL dbg_resolution_w : INTEGER := 0; SIGNAL dbg_resolution_w : INTEGER := 0;
SIGNAL dbg_resolution : REAL := 0.0; SIGNAL dbg_resolution : REAL := 0.0;
...@@ -103,10 +106,18 @@ BEGIN ...@@ -103,10 +106,18 @@ BEGIN
a_real <= v_real; a_real <= v_real;
a_sint <= TO_SINT(v_real, c_width, R); a_sint <= TO_SINT(v_real, c_width, R);
a_slv <= TO_SVEC(v_real, c_width, R); a_slv <= TO_SVEC(v_real, c_width, R);
IF I >= 0 THEN
a_uint <= TO_UINT(v_real, c_width, R);
a_ulv <= TO_UVEC(v_real, c_width, R);
END IF;
WAIT UNTIL rising_edge(clk); WAIT UNTIL rising_edge(clk);
-- Verify -- Verify
ASSERT a_sint = I REPORT "Wrong REAL to INTEGER conversion for I = " & INTEGER'IMAGE(I) SEVERITY ERROR; ASSERT a_sint = I REPORT "Wrong REAL to INTEGER conversion for I = " & INTEGER'IMAGE(I) SEVERITY ERROR;
ASSERT a_slv = v_slv REPORT "Wrong REAL to SLV conversion for I = " & INTEGER'IMAGE(I) SEVERITY ERROR; ASSERT a_slv = v_slv REPORT "Wrong REAL to SLV conversion for I = " & INTEGER'IMAGE(I) SEVERITY ERROR;
IF I >= 0 THEN
ASSERT a_uint = I REPORT "Wrong REAL to NATURAL conversion for I = " & NATURAL'IMAGE(I) SEVERITY ERROR;
ASSERT a_ulv = v_slv REPORT "Wrong REAL to unsigned SLV conversion for I = " & NATURAL'IMAGE(I) SEVERITY ERROR;
END IF;
END LOOP; END LOOP;
proc_wait_some_cycles(clk, 10); proc_wait_some_cycles(clk, 10);
END LOOP; END LOOP;
...@@ -123,30 +134,47 @@ BEGIN ...@@ -123,30 +134,47 @@ BEGIN
v_real := -7.49; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); v_real := -7.49; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
v_real := -6.51; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); v_real := -6.51; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
v_real := -6.49; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); v_real := -6.49; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
v_real := 6.49; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); v_real := 6.49; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0);
v_real := 6.51; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
v_real := 7.49; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); v_real := 6.51; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0);
v_real := 7.51; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
v_real := 7.49; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0);
a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
v_real := 7.51; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0);
a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
proc_wait_some_cycles(clk, 5); proc_wait_some_cycles(clk, 5);
-- . Just overflow with 4 bit integers for -16.5 : +15.5 -- . Just overflow with 4 bit integers for -16.5 : +15.5
v_real := -15.5; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); v_real := -15.5; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
v_real := 15.5; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); v_real := 15.5; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0);
a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
proc_wait_some_cycles(clk, 5); proc_wait_some_cycles(clk, 5);
-- . Negative clip to 0 for unsigned
v_real := -3.0; a_real <= v_real; a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
ASSERT a_uint = 0 REPORT "Unexpected TO_UINT(< 0) : " & INTEGER'IMAGE(a_uint) & " /= 0" SEVERITY ERROR;
ASSERT TO_UINT(a_ulv) = 0 REPORT "Unexpected TO_UVEC(< 0) : " & INTEGER'IMAGE(TO_UINT(a_ulv)) & " /= 0" SEVERITY ERROR;
proc_wait_some_cycles(clk, 5);
-- . Large overflow with 4 bit integers for << -16.5 : >> +15.5 -- . Large overflow with 4 bit integers for << -16.5 : >> +15.5
v_real := -68.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
v_real := -58.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
v_real := -48.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
v_real := -38.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
v_real := -28.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
v_real := -18.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); v_real := -18.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
v_real := 18.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); v_real := 18.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
v_real := -28.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
v_real := 28.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); v_real := 28.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
v_real := -38.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
v_real := 38.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); v_real := 38.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
v_real := -48.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
v_real := 48.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); v_real := 48.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
v_real := -58.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
v_real := 58.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); v_real := 58.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
v_real := -68.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
v_real := 68.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); v_real := 68.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
proc_wait_some_cycles(clk, 10); proc_wait_some_cycles(clk, 10);
tb_end <= '1'; tb_end <= '1';
...@@ -154,6 +182,10 @@ BEGIN ...@@ -154,6 +182,10 @@ BEGIN
END PROCESS; END PROCESS;
-- TO_SINT() and TO_SVEC() must always yield same result -- TO_SINT() and TO_SVEC() must always yield same result
ASSERT a_sint = TO_SINT(a_slv) REPORT "Unexpected difference between TO_SINT() and TO_SVEC() :" & INTEGER'IMAGE(a_sint) & " /= " & INTEGER'IMAGE(TO_SINT(a_slv)); ASSERT a_sint = TO_SINT(a_slv) REPORT "Unexpected difference between TO_SINT() and TO_SVEC() :" &
INTEGER'IMAGE(a_sint) & " /= " & INTEGER'IMAGE(TO_SINT(a_slv)) SEVERITY ERROR;
-- TO_UINT() and TO_UVEC() must always yield same result
ASSERT a_uint = TO_UINT(a_ulv) REPORT "Unexpected difference between TO_UINT() and TO_UVEC() :" &
INTEGER'IMAGE(a_uint) & " /= " & INTEGER'IMAGE(TO_SINT(a_ulv)) SEVERITY ERROR;
END tb; END tb;
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