Initialize a_sint = 0 to avoid assert error at 0 ps.

libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd

@@ -63,7 +63,7 @@ ARCHITECTURE tb OF tb_common_to_sreal IS
   SIGNAL rst              : STD_LOGIC := '1';
 
   SIGNAL a_real           : REAL := 0.0;
-  SIGNAL a_sint           : INTEGER;
+  SIGNAL a_sint           : INTEGER := 0;
   SIGNAL a_slv            : STD_LOGIC_VECTOR(c_width-1 DOWNTO 0) := (OTHERS => '0');
   SIGNAL dbg_resolution_w : INTEGER := 0;
   SIGNAL dbg_resolution   : REAL := 0.0;